drm: update radeon to 1.25 add r200 vertex program support
[linux-2.6-block.git] / drivers / char / drm / mga_warp.c
CommitLineData
1da177e4
LT
1/* mga_warp.c -- Matrox G200/G400 WARP engine management -*- linux-c -*-
2 * Created: Thu Jan 11 21:29:32 2001 by gareth@valinux.com
3 *
4 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Gareth Hughes <gareth@valinux.com>
28 */
29
30#include "drmP.h"
31#include "drm.h"
32#include "mga_drm.h"
33#include "mga_drv.h"
34#include "mga_ucode.h"
35
b5e89ed5 36#define MGA_WARP_CODE_ALIGN 256 /* in bytes */
1da177e4
LT
37
38#define WARP_UCODE_SIZE( which ) \
39 ((sizeof(which) / MGA_WARP_CODE_ALIGN + 1) * MGA_WARP_CODE_ALIGN)
40
41#define WARP_UCODE_INSTALL( which, where ) \
42do { \
43 DRM_DEBUG( " pcbase = 0x%08lx vcbase = %p\n", pcbase, vcbase );\
44 dev_priv->warp_pipe_phys[where] = pcbase; \
45 memcpy( vcbase, which, sizeof(which) ); \
46 pcbase += WARP_UCODE_SIZE( which ); \
47 vcbase += WARP_UCODE_SIZE( which ); \
48} while (0)
49
6795c985 50static const unsigned int mga_warp_g400_microcode_size =
b5e89ed5
DA
51 (WARP_UCODE_SIZE(warp_g400_tgz) +
52 WARP_UCODE_SIZE(warp_g400_tgza) +
53 WARP_UCODE_SIZE(warp_g400_tgzaf) +
54 WARP_UCODE_SIZE(warp_g400_tgzf) +
55 WARP_UCODE_SIZE(warp_g400_tgzs) +
56 WARP_UCODE_SIZE(warp_g400_tgzsa) +
57 WARP_UCODE_SIZE(warp_g400_tgzsaf) +
58 WARP_UCODE_SIZE(warp_g400_tgzsf) +
59 WARP_UCODE_SIZE(warp_g400_t2gz) +
60 WARP_UCODE_SIZE(warp_g400_t2gza) +
61 WARP_UCODE_SIZE(warp_g400_t2gzaf) +
62 WARP_UCODE_SIZE(warp_g400_t2gzf) +
63 WARP_UCODE_SIZE(warp_g400_t2gzs) +
64 WARP_UCODE_SIZE(warp_g400_t2gzsa) +
65 WARP_UCODE_SIZE(warp_g400_t2gzsaf) + WARP_UCODE_SIZE(warp_g400_t2gzsf));
6795c985
DA
66
67static const unsigned int mga_warp_g200_microcode_size =
b5e89ed5
DA
68 (WARP_UCODE_SIZE(warp_g200_tgz) +
69 WARP_UCODE_SIZE(warp_g200_tgza) +
70 WARP_UCODE_SIZE(warp_g200_tgzaf) +
71 WARP_UCODE_SIZE(warp_g200_tgzf) +
72 WARP_UCODE_SIZE(warp_g200_tgzs) +
73 WARP_UCODE_SIZE(warp_g200_tgzsa) +
74 WARP_UCODE_SIZE(warp_g200_tgzsaf) + WARP_UCODE_SIZE(warp_g200_tgzsf));
6795c985
DA
75
76unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv)
1da177e4 77{
6795c985
DA
78 switch (dev_priv->chipset) {
79 case MGA_CARD_TYPE_G400:
80 case MGA_CARD_TYPE_G550:
81 return PAGE_ALIGN(mga_warp_g400_microcode_size);
82 case MGA_CARD_TYPE_G200:
83 return PAGE_ALIGN(mga_warp_g200_microcode_size);
84 default:
85 return 0;
86 }
1da177e4
LT
87}
88
b5e89ed5 89static int mga_warp_install_g400_microcode(drm_mga_private_t * dev_priv)
1da177e4
LT
90{
91 unsigned char *vcbase = dev_priv->warp->handle;
92 unsigned long pcbase = dev_priv->warp->offset;
1da177e4 93
b5e89ed5
DA
94 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
95
96 WARP_UCODE_INSTALL(warp_g400_tgz, MGA_WARP_TGZ);
97 WARP_UCODE_INSTALL(warp_g400_tgzf, MGA_WARP_TGZF);
98 WARP_UCODE_INSTALL(warp_g400_tgza, MGA_WARP_TGZA);
99 WARP_UCODE_INSTALL(warp_g400_tgzaf, MGA_WARP_TGZAF);
100 WARP_UCODE_INSTALL(warp_g400_tgzs, MGA_WARP_TGZS);
101 WARP_UCODE_INSTALL(warp_g400_tgzsf, MGA_WARP_TGZSF);
102 WARP_UCODE_INSTALL(warp_g400_tgzsa, MGA_WARP_TGZSA);
103 WARP_UCODE_INSTALL(warp_g400_tgzsaf, MGA_WARP_TGZSAF);
104
105 WARP_UCODE_INSTALL(warp_g400_t2gz, MGA_WARP_T2GZ);
106 WARP_UCODE_INSTALL(warp_g400_t2gzf, MGA_WARP_T2GZF);
107 WARP_UCODE_INSTALL(warp_g400_t2gza, MGA_WARP_T2GZA);
108 WARP_UCODE_INSTALL(warp_g400_t2gzaf, MGA_WARP_T2GZAF);
109 WARP_UCODE_INSTALL(warp_g400_t2gzs, MGA_WARP_T2GZS);
110 WARP_UCODE_INSTALL(warp_g400_t2gzsf, MGA_WARP_T2GZSF);
111 WARP_UCODE_INSTALL(warp_g400_t2gzsa, MGA_WARP_T2GZSA);
112 WARP_UCODE_INSTALL(warp_g400_t2gzsaf, MGA_WARP_T2GZSAF);
1da177e4
LT
113
114 return 0;
115}
116
b5e89ed5 117static int mga_warp_install_g200_microcode(drm_mga_private_t * dev_priv)
1da177e4
LT
118{
119 unsigned char *vcbase = dev_priv->warp->handle;
120 unsigned long pcbase = dev_priv->warp->offset;
1da177e4 121
6795c985 122 memset(dev_priv->warp_pipe_phys, 0, sizeof(dev_priv->warp_pipe_phys));
1da177e4 123
6795c985
DA
124 WARP_UCODE_INSTALL(warp_g200_tgz, MGA_WARP_TGZ);
125 WARP_UCODE_INSTALL(warp_g200_tgzf, MGA_WARP_TGZF);
126 WARP_UCODE_INSTALL(warp_g200_tgza, MGA_WARP_TGZA);
127 WARP_UCODE_INSTALL(warp_g200_tgzaf, MGA_WARP_TGZAF);
128 WARP_UCODE_INSTALL(warp_g200_tgzs, MGA_WARP_TGZS);
129 WARP_UCODE_INSTALL(warp_g200_tgzsf, MGA_WARP_TGZSF);
130 WARP_UCODE_INSTALL(warp_g200_tgzsa, MGA_WARP_TGZSA);
131 WARP_UCODE_INSTALL(warp_g200_tgzsaf, MGA_WARP_TGZSAF);
1da177e4
LT
132
133 return 0;
134}
135
b5e89ed5 136int mga_warp_install_microcode(drm_mga_private_t * dev_priv)
1da177e4 137{
6795c985
DA
138 const unsigned int size = mga_warp_microcode_size(dev_priv);
139
140 DRM_DEBUG("MGA ucode size = %d bytes\n", size);
141 if (size > dev_priv->warp->size) {
142 DRM_ERROR("microcode too large! (%u > %lu)\n",
143 size, dev_priv->warp->size);
144 return DRM_ERR(ENOMEM);
145 }
146
147 switch (dev_priv->chipset) {
1da177e4 148 case MGA_CARD_TYPE_G400:
6795c985
DA
149 case MGA_CARD_TYPE_G550:
150 return mga_warp_install_g400_microcode(dev_priv);
1da177e4 151 case MGA_CARD_TYPE_G200:
b5e89ed5 152 return mga_warp_install_g200_microcode(dev_priv);
1da177e4
LT
153 default:
154 return DRM_ERR(EINVAL);
155 }
156}
157
158#define WMISC_EXPECTED (MGA_WUCODECACHE_ENABLE | MGA_WMASTER_ENABLE)
159
b5e89ed5 160int mga_warp_init(drm_mga_private_t * dev_priv)
1da177e4
LT
161{
162 u32 wmisc;
163
164 /* FIXME: Get rid of these damned magic numbers...
165 */
b5e89ed5 166 switch (dev_priv->chipset) {
1da177e4 167 case MGA_CARD_TYPE_G400:
6795c985
DA
168 case MGA_CARD_TYPE_G550:
169 MGA_WRITE(MGA_WIADDR2, MGA_WMODE_SUSPEND);
170 MGA_WRITE(MGA_WGETMSB, 0x00000E00);
171 MGA_WRITE(MGA_WVRTXSZ, 0x00001807);
172 MGA_WRITE(MGA_WACCEPTSEQ, 0x18000000);
1da177e4
LT
173 break;
174 case MGA_CARD_TYPE_G200:
b5e89ed5
DA
175 MGA_WRITE(MGA_WIADDR, MGA_WMODE_SUSPEND);
176 MGA_WRITE(MGA_WGETMSB, 0x1606);
177 MGA_WRITE(MGA_WVRTXSZ, 7);
1da177e4
LT
178 break;
179 default:
180 return DRM_ERR(EINVAL);
181 }
182
b5e89ed5
DA
183 MGA_WRITE(MGA_WMISC, (MGA_WUCODECACHE_ENABLE |
184 MGA_WMASTER_ENABLE | MGA_WCACHEFLUSH_ENABLE));
185 wmisc = MGA_READ(MGA_WMISC);
186 if (wmisc != WMISC_EXPECTED) {
187 DRM_ERROR("WARP engine config failed! 0x%x != 0x%x\n",
188 wmisc, WMISC_EXPECTED);
1da177e4
LT
189 return DRM_ERR(EINVAL);
190 }
191
192 return 0;
193}