Commit | Line | Data |
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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
33 | /* General customization: | |
34 | */ | |
35 | ||
36 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
37 | ||
38 | #define DRIVER_NAME "i915" | |
39 | #define DRIVER_DESC "Intel Graphics" | |
de227f5f | 40 | #define DRIVER_DATE "20060119" |
1da177e4 LT |
41 | |
42 | /* Interface history: | |
43 | * | |
44 | * 1.1: Original. | |
0d6aa60b DA |
45 | * 1.2: Add Power Management |
46 | * 1.3: Add vblank support | |
de227f5f | 47 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 48 | * 1.5: Add vblank pipe configuration |
2228ed67 MCA |
49 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
50 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
51 | */ |
52 | #define DRIVER_MAJOR 1 | |
2228ed67 | 53 | #define DRIVER_MINOR 6 |
1da177e4 LT |
54 | #define DRIVER_PATCHLEVEL 0 |
55 | ||
1da177e4 LT |
56 | typedef struct _drm_i915_ring_buffer { |
57 | int tail_mask; | |
58 | unsigned long Start; | |
59 | unsigned long End; | |
60 | unsigned long Size; | |
61 | u8 *virtual_start; | |
62 | int head; | |
63 | int tail; | |
64 | int space; | |
65 | drm_local_map_t map; | |
66 | } drm_i915_ring_buffer_t; | |
67 | ||
68 | struct mem_block { | |
69 | struct mem_block *next; | |
70 | struct mem_block *prev; | |
71 | int start; | |
72 | int size; | |
6c340eac | 73 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
74 | }; |
75 | ||
a6b54f3f MCA |
76 | typedef struct _drm_i915_vbl_swap { |
77 | struct list_head head; | |
78 | drm_drawable_t drw_id; | |
ac741ab7 | 79 | unsigned int plane; |
a6b54f3f | 80 | unsigned int sequence; |
ac741ab7 | 81 | int flip; |
a6b54f3f MCA |
82 | } drm_i915_vbl_swap_t; |
83 | ||
1da177e4 LT |
84 | typedef struct drm_i915_private { |
85 | drm_local_map_t *sarea; | |
86 | drm_local_map_t *mmio_map; | |
87 | ||
88 | drm_i915_sarea_t *sarea_priv; | |
89 | drm_i915_ring_buffer_t ring; | |
90 | ||
9c8da5eb | 91 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 92 | void *hw_status_page; |
1da177e4 | 93 | dma_addr_t dma_status_page; |
ac741ab7 | 94 | uint32_t counter; |
dc7a9319 WZ |
95 | unsigned int status_gfx_addr; |
96 | drm_local_map_t hws_map; | |
1da177e4 | 97 | |
a6b54f3f | 98 | unsigned int cpp; |
1da177e4 LT |
99 | int back_offset; |
100 | int front_offset; | |
101 | int current_page; | |
102 | int page_flipping; | |
103 | int use_mi_batchbuffer_start; | |
104 | ||
105 | wait_queue_head_t irq_queue; | |
106 | atomic_t irq_received; | |
ac741ab7 | 107 | atomic_t irq_emited; |
1da177e4 LT |
108 | |
109 | int tex_lru_log_granularity; | |
110 | int allow_batchbuffer; | |
111 | struct mem_block *agp_heap; | |
0d6aa60b | 112 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 113 | int vblank_pipe; |
ac741ab7 JB |
114 | spinlock_t user_irq_lock; |
115 | int user_irq_refcount; | |
116 | int fence_irq_on; | |
117 | uint32_t irq_enable_reg; | |
118 | int irq_enabled; | |
a6b54f3f MCA |
119 | |
120 | spinlock_t swaps_lock; | |
121 | drm_i915_vbl_swap_t vbl_swaps; | |
122 | unsigned int swaps_pending; | |
ba8bbcf6 JB |
123 | |
124 | /* Register state */ | |
125 | u8 saveLBB; | |
126 | u32 saveDSPACNTR; | |
127 | u32 saveDSPBCNTR; | |
128 | u32 savePIPEACONF; | |
129 | u32 savePIPEBCONF; | |
130 | u32 savePIPEASRC; | |
131 | u32 savePIPEBSRC; | |
132 | u32 saveFPA0; | |
133 | u32 saveFPA1; | |
134 | u32 saveDPLL_A; | |
135 | u32 saveDPLL_A_MD; | |
136 | u32 saveHTOTAL_A; | |
137 | u32 saveHBLANK_A; | |
138 | u32 saveHSYNC_A; | |
139 | u32 saveVTOTAL_A; | |
140 | u32 saveVBLANK_A; | |
141 | u32 saveVSYNC_A; | |
142 | u32 saveBCLRPAT_A; | |
0da3ea12 | 143 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
144 | u32 saveDSPASTRIDE; |
145 | u32 saveDSPASIZE; | |
146 | u32 saveDSPAPOS; | |
147 | u32 saveDSPABASE; | |
148 | u32 saveDSPASURF; | |
149 | u32 saveDSPATILEOFF; | |
150 | u32 savePFIT_PGM_RATIOS; | |
151 | u32 saveBLC_PWM_CTL; | |
152 | u32 saveBLC_PWM_CTL2; | |
153 | u32 saveFPB0; | |
154 | u32 saveFPB1; | |
155 | u32 saveDPLL_B; | |
156 | u32 saveDPLL_B_MD; | |
157 | u32 saveHTOTAL_B; | |
158 | u32 saveHBLANK_B; | |
159 | u32 saveHSYNC_B; | |
160 | u32 saveVTOTAL_B; | |
161 | u32 saveVBLANK_B; | |
162 | u32 saveVSYNC_B; | |
163 | u32 saveBCLRPAT_B; | |
0da3ea12 | 164 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
165 | u32 saveDSPBSTRIDE; |
166 | u32 saveDSPBSIZE; | |
167 | u32 saveDSPBPOS; | |
168 | u32 saveDSPBBASE; | |
169 | u32 saveDSPBSURF; | |
170 | u32 saveDSPBTILEOFF; | |
171 | u32 saveVCLK_DIVISOR_VGA0; | |
172 | u32 saveVCLK_DIVISOR_VGA1; | |
173 | u32 saveVCLK_POST_DIV; | |
174 | u32 saveVGACNTRL; | |
175 | u32 saveADPA; | |
176 | u32 saveLVDS; | |
177 | u32 saveLVDSPP_ON; | |
178 | u32 saveLVDSPP_OFF; | |
179 | u32 saveDVOA; | |
180 | u32 saveDVOB; | |
181 | u32 saveDVOC; | |
182 | u32 savePP_ON; | |
183 | u32 savePP_OFF; | |
184 | u32 savePP_CONTROL; | |
185 | u32 savePP_CYCLE; | |
186 | u32 savePFIT_CONTROL; | |
187 | u32 save_palette_a[256]; | |
188 | u32 save_palette_b[256]; | |
189 | u32 saveFBC_CFB_BASE; | |
190 | u32 saveFBC_LL_BASE; | |
191 | u32 saveFBC_CONTROL; | |
192 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
193 | u32 saveIER; |
194 | u32 saveIIR; | |
195 | u32 saveIMR; | |
1f84e550 KP |
196 | u32 saveCACHE_MODE_0; |
197 | u32 saveDSPCLK_GATE_D; | |
198 | u32 saveMI_ARB_STATE; | |
ba8bbcf6 JB |
199 | u32 saveSWF0[16]; |
200 | u32 saveSWF1[16]; | |
201 | u32 saveSWF2[3]; | |
202 | u8 saveMSR; | |
203 | u8 saveSR[8]; | |
123f794f | 204 | u8 saveGR[25]; |
ba8bbcf6 JB |
205 | u8 saveAR_INDEX; |
206 | u8 saveAR[20]; | |
207 | u8 saveDACMASK; | |
208 | u8 saveDACDATA[256*3]; /* 256 3-byte colors */ | |
209 | u8 saveCR[36]; | |
1da177e4 LT |
210 | } drm_i915_private_t; |
211 | ||
c153f45f | 212 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
213 | extern int i915_max_ioctl; |
214 | ||
1da177e4 | 215 | /* i915_dma.c */ |
84b1fd10 | 216 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 217 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 218 | extern int i915_driver_unload(struct drm_device *); |
84b1fd10 | 219 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
220 | extern void i915_driver_preclose(struct drm_device *dev, |
221 | struct drm_file *file_priv); | |
84b1fd10 | 222 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
223 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
224 | unsigned long arg); | |
ac741ab7 | 225 | extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); |
1da177e4 | 226 | /* i915_irq.c */ |
c153f45f EA |
227 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
228 | struct drm_file *file_priv); | |
229 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
230 | struct drm_file *file_priv); | |
1da177e4 | 231 | |
84b1fd10 DA |
232 | extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); |
233 | extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence); | |
1da177e4 | 234 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); |
84b1fd10 | 235 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
ac741ab7 | 236 | extern int i915_driver_irq_postinstall(struct drm_device * dev); |
84b1fd10 | 237 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
238 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
239 | struct drm_file *file_priv); | |
240 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
241 | struct drm_file *file_priv); | |
242 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | |
243 | struct drm_file *file_priv); | |
ac741ab7 JB |
244 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
245 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
246 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
1da177e4 LT |
247 | |
248 | /* i915_mem.c */ | |
c153f45f EA |
249 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
250 | struct drm_file *file_priv); | |
251 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
252 | struct drm_file *file_priv); | |
253 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
254 | struct drm_file *file_priv); | |
255 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
256 | struct drm_file *file_priv); | |
1da177e4 | 257 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 258 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 259 | struct drm_file *file_priv, struct mem_block *heap); |
1da177e4 | 260 | |
0d6aa60b DA |
261 | #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) |
262 | #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) | |
bc5f4523 | 263 | #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) |
0d6aa60b | 264 | #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) |
1da177e4 LT |
265 | |
266 | #define I915_VERBOSE 0 | |
267 | ||
268 | #define RING_LOCALS unsigned int outring, ringmask, outcount; \ | |
269 | volatile char *virt; | |
270 | ||
271 | #define BEGIN_LP_RING(n) do { \ | |
272 | if (I915_VERBOSE) \ | |
3e684eae MN |
273 | DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ |
274 | if (dev_priv->ring.space < (n)*4) \ | |
c29b669c | 275 | i915_wait_ring(dev, (n)*4, __FUNCTION__); \ |
1da177e4 LT |
276 | outcount = 0; \ |
277 | outring = dev_priv->ring.tail; \ | |
278 | ringmask = dev_priv->ring.tail_mask; \ | |
279 | virt = dev_priv->ring.virtual_start; \ | |
280 | } while (0) | |
281 | ||
282 | #define OUT_RING(n) do { \ | |
283 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ | |
c29b669c | 284 | *(volatile unsigned int *)(virt + outring) = (n); \ |
1da177e4 LT |
285 | outcount++; \ |
286 | outring += 4; \ | |
287 | outring &= ringmask; \ | |
288 | } while (0) | |
289 | ||
290 | #define ADVANCE_LP_RING() do { \ | |
291 | if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ | |
292 | dev_priv->ring.tail = outring; \ | |
293 | dev_priv->ring.space -= outcount * 4; \ | |
294 | I915_WRITE(LP_RING + RING_TAIL, outring); \ | |
295 | } while(0) | |
296 | ||
84b1fd10 | 297 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
1da177e4 | 298 | |
ba8bbcf6 JB |
299 | /* Extended config space */ |
300 | #define LBB 0xf4 | |
301 | ||
302 | /* VGA stuff */ | |
303 | ||
304 | #define VGA_ST01_MDA 0x3ba | |
305 | #define VGA_ST01_CGA 0x3da | |
306 | ||
307 | #define VGA_MSR_WRITE 0x3c2 | |
308 | #define VGA_MSR_READ 0x3cc | |
309 | #define VGA_MSR_MEM_EN (1<<1) | |
310 | #define VGA_MSR_CGA_MODE (1<<0) | |
311 | ||
312 | #define VGA_SR_INDEX 0x3c4 | |
313 | #define VGA_SR_DATA 0x3c5 | |
314 | ||
315 | #define VGA_AR_INDEX 0x3c0 | |
316 | #define VGA_AR_VID_EN (1<<5) | |
317 | #define VGA_AR_DATA_WRITE 0x3c0 | |
318 | #define VGA_AR_DATA_READ 0x3c1 | |
319 | ||
320 | #define VGA_GR_INDEX 0x3ce | |
321 | #define VGA_GR_DATA 0x3cf | |
322 | /* GR05 */ | |
323 | #define VGA_GR_MEM_READ_MODE_SHIFT 3 | |
324 | #define VGA_GR_MEM_READ_MODE_PLANE 1 | |
325 | /* GR06 */ | |
326 | #define VGA_GR_MEM_MODE_MASK 0xc | |
327 | #define VGA_GR_MEM_MODE_SHIFT 2 | |
328 | #define VGA_GR_MEM_A0000_AFFFF 0 | |
329 | #define VGA_GR_MEM_A0000_BFFFF 1 | |
330 | #define VGA_GR_MEM_B0000_B7FFF 2 | |
331 | #define VGA_GR_MEM_B0000_BFFFF 3 | |
332 | ||
333 | #define VGA_DACMASK 0x3c6 | |
334 | #define VGA_DACRX 0x3c7 | |
335 | #define VGA_DACWX 0x3c8 | |
336 | #define VGA_DACDATA 0x3c9 | |
337 | ||
338 | #define VGA_CR_INDEX_MDA 0x3b4 | |
339 | #define VGA_CR_DATA_MDA 0x3b5 | |
340 | #define VGA_CR_INDEX_CGA 0x3d4 | |
341 | #define VGA_CR_DATA_CGA 0x3d5 | |
342 | ||
bc5f4523 | 343 | #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) |
1da177e4 LT |
344 | #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) |
345 | #define CMD_REPORT_HEAD (7<<23) | |
346 | #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) | |
347 | #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) | |
348 | ||
349 | #define INST_PARSER_CLIENT 0x00000000 | |
350 | #define INST_OP_FLUSH 0x02000000 | |
351 | #define INST_FLUSH_MAP_CACHE 0x00000001 | |
352 | ||
353 | #define BB1_START_ADDR_MASK (~0x7) | |
354 | #define BB1_PROTECTED (1<<0) | |
355 | #define BB1_UNPROTECTED (0<<0) | |
356 | #define BB2_END_ADDR_MASK (~0x7) | |
357 | ||
ba8bbcf6 JB |
358 | /* Framebuffer compression */ |
359 | #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ | |
360 | #define FBC_LL_BASE 0x03204 /* 4k page aligned */ | |
361 | #define FBC_CONTROL 0x03208 | |
362 | #define FBC_CTL_EN (1<<31) | |
363 | #define FBC_CTL_PERIODIC (1<<30) | |
364 | #define FBC_CTL_INTERVAL_SHIFT (16) | |
365 | #define FBC_CTL_UNCOMPRESSIBLE (1<<14) | |
366 | #define FBC_CTL_STRIDE_SHIFT (5) | |
367 | #define FBC_CTL_FENCENO (1<<0) | |
368 | #define FBC_COMMAND 0x0320c | |
369 | #define FBC_CMD_COMPRESS (1<<0) | |
370 | #define FBC_STATUS 0x03210 | |
371 | #define FBC_STAT_COMPRESSING (1<<31) | |
372 | #define FBC_STAT_COMPRESSED (1<<30) | |
373 | #define FBC_STAT_MODIFIED (1<<29) | |
374 | #define FBC_STAT_CURRENT_LINE (1<<0) | |
375 | #define FBC_CONTROL2 0x03214 | |
376 | #define FBC_CTL_FENCE_DBL (0<<4) | |
377 | #define FBC_CTL_IDLE_IMM (0<<2) | |
378 | #define FBC_CTL_IDLE_FULL (1<<2) | |
379 | #define FBC_CTL_IDLE_LINE (2<<2) | |
380 | #define FBC_CTL_IDLE_DEBUG (3<<2) | |
381 | #define FBC_CTL_CPU_FENCE (1<<1) | |
382 | #define FBC_CTL_PLANEA (0<<0) | |
383 | #define FBC_CTL_PLANEB (1<<0) | |
384 | #define FBC_FENCE_OFF 0x0321b | |
385 | ||
386 | #define FBC_LL_SIZE (1536) | |
387 | #define FBC_LL_PAD (32) | |
388 | ||
389 | /* Interrupt bits: | |
390 | */ | |
ac741ab7 JB |
391 | #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) |
392 | #define I915_DISPLAY_PORT_INTERRUPT (1<<17) | |
393 | #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) | |
394 | #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) | |
395 | #define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */ | |
396 | #define I915_SYNC_STATUS_INTERRUPT (1<<12) | |
397 | #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) | |
398 | #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) | |
399 | #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) | |
400 | #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) | |
401 | #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) | |
402 | #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) | |
403 | #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) | |
404 | #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) | |
405 | #define I915_DEBUG_INTERRUPT (1<<2) | |
406 | #define I915_USER_INTERRUPT (1<<1) | |
407 | ||
ba8bbcf6 | 408 | |
1da177e4 LT |
409 | #define I915REG_HWSTAM 0x02098 |
410 | #define I915REG_INT_IDENTITY_R 0x020a4 | |
bc5f4523 | 411 | #define I915REG_INT_MASK_R 0x020a8 |
1da177e4 | 412 | #define I915REG_INT_ENABLE_R 0x020a0 |
ac741ab7 JB |
413 | #define I915REG_INSTPM 0x020c0 |
414 | ||
415 | #define PIPEADSL 0x70000 | |
416 | #define PIPEBDSL 0x71000 | |
1da177e4 | 417 | |
e4a7b1d1 DA |
418 | #define I915REG_PIPEASTAT 0x70024 |
419 | #define I915REG_PIPEBSTAT 0x71024 | |
ac741ab7 JB |
420 | /* |
421 | * The two pipe frame counter registers are not synchronized, so | |
422 | * reading a stable value is somewhat tricky. The following code | |
423 | * should work: | |
424 | * | |
425 | * do { | |
426 | * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
427 | * PIPE_FRAME_HIGH_SHIFT; | |
428 | * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >> | |
429 | * PIPE_FRAME_LOW_SHIFT); | |
430 | * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >> | |
431 | * PIPE_FRAME_HIGH_SHIFT); | |
432 | * } while (high1 != high2); | |
433 | * frame = (high1 << 8) | low1; | |
434 | */ | |
435 | #define PIPEAFRAMEHIGH 0x70040 | |
436 | #define PIPEBFRAMEHIGH 0x71040 | |
437 | #define PIPE_FRAME_HIGH_MASK 0x0000ffff | |
438 | #define PIPE_FRAME_HIGH_SHIFT 0 | |
439 | #define PIPEAFRAMEPIXEL 0x70044 | |
440 | #define PIPEBFRAMEPIXEL 0x71044 | |
441 | ||
442 | #define PIPE_FRAME_LOW_MASK 0xff000000 | |
443 | #define PIPE_FRAME_LOW_SHIFT 24 | |
444 | /* | |
445 | * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register | |
446 | * and is 24 bits wide. | |
447 | */ | |
448 | #define PIPE_PIXEL_MASK 0x00ffffff | |
449 | #define PIPE_PIXEL_SHIFT 0 | |
450 | ||
451 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) | |
452 | #define I915_CRC_ERROR_ENABLE (1UL<<29) | |
453 | #define I915_CRC_DONE_ENABLE (1UL<<28) | |
454 | #define I915_GMBUS_EVENT_ENABLE (1UL<<27) | |
455 | #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) | |
456 | #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | |
457 | #define I915_DPST_EVENT_ENABLE (1UL<<23) | |
458 | #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | |
459 | #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | |
460 | #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | |
461 | #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | |
462 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) | |
463 | #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) | |
464 | #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | |
465 | #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | |
466 | #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) | |
467 | #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) | |
468 | #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | |
469 | #define I915_DPST_EVENT_STATUS (1UL<<7) | |
470 | #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) | |
471 | #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | |
472 | #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | |
473 | #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | |
474 | #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) | |
475 | #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) | |
e4a7b1d1 | 476 | |
1da177e4 LT |
477 | #define SRX_INDEX 0x3c4 |
478 | #define SRX_DATA 0x3c5 | |
479 | #define SR01 1 | |
bc5f4523 | 480 | #define SR01_SCREEN_OFF (1<<5) |
1da177e4 LT |
481 | |
482 | #define PPCR 0x61204 | |
483 | #define PPCR_ON (1<<0) | |
484 | ||
0d6aa60b DA |
485 | #define DVOB 0x61140 |
486 | #define DVOB_ON (1<<31) | |
487 | #define DVOC 0x61160 | |
488 | #define DVOC_ON (1<<31) | |
489 | #define LVDS 0x61180 | |
490 | #define LVDS_ON (1<<31) | |
491 | ||
1da177e4 LT |
492 | #define ADPA 0x61100 |
493 | #define ADPA_DPMS_MASK (~(3<<10)) | |
494 | #define ADPA_DPMS_ON (0<<10) | |
495 | #define ADPA_DPMS_SUSPEND (1<<10) | |
496 | #define ADPA_DPMS_STANDBY (2<<10) | |
497 | #define ADPA_DPMS_OFF (3<<10) | |
498 | ||
499 | #define NOPID 0x2094 | |
bc5f4523 DA |
500 | #define LP_RING 0x2030 |
501 | #define HP_RING 0x2040 | |
ba8bbcf6 JB |
502 | /* The binner has its own ring buffer: |
503 | */ | |
504 | #define HWB_RING 0x2400 | |
505 | ||
bc5f4523 | 506 | #define RING_TAIL 0x00 |
1da177e4 | 507 | #define TAIL_ADDR 0x001FFFF8 |
bc5f4523 DA |
508 | #define RING_HEAD 0x04 |
509 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
510 | #define HEAD_WRAP_ONE 0x00200000 | |
511 | #define HEAD_ADDR 0x001FFFFC | |
512 | #define RING_START 0x08 | |
513 | #define START_ADDR 0x0xFFFFF000 | |
514 | #define RING_LEN 0x0C | |
515 | #define RING_NR_PAGES 0x001FF000 | |
516 | #define RING_REPORT_MASK 0x00000006 | |
517 | #define RING_REPORT_64K 0x00000002 | |
518 | #define RING_REPORT_128K 0x00000004 | |
519 | #define RING_NO_REPORT 0x00000000 | |
520 | #define RING_VALID_MASK 0x00000001 | |
521 | #define RING_VALID 0x00000001 | |
522 | #define RING_INVALID 0x00000000 | |
1da177e4 | 523 | |
ba8bbcf6 JB |
524 | /* Instruction parser error reg: |
525 | */ | |
526 | #define IPEIR 0x2088 | |
527 | ||
528 | /* Scratch pad debug 0 reg: | |
529 | */ | |
530 | #define SCPD0 0x209c | |
531 | ||
532 | /* Error status reg: | |
533 | */ | |
534 | #define ESR 0x20b8 | |
535 | ||
536 | /* Secondary DMA fetch address debug reg: | |
537 | */ | |
538 | #define DMA_FADD_S 0x20d4 | |
539 | ||
1f84e550 KP |
540 | /* Memory Interface Arbitration State |
541 | */ | |
542 | #define MI_ARB_STATE 0x20e4 | |
543 | ||
ba8bbcf6 JB |
544 | /* Cache mode 0 reg. |
545 | * - Manipulating render cache behaviour is central | |
546 | * to the concept of zone rendering, tuning this reg can help avoid | |
547 | * unnecessary render cache reads and even writes (for z/stencil) | |
548 | * at beginning and end of scene. | |
549 | * | |
550 | * - To change a bit, write to this reg with a mask bit set and the | |
551 | * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. | |
552 | */ | |
553 | #define Cache_Mode_0 0x2120 | |
1f84e550 | 554 | #define CACHE_MODE_0 0x2120 |
ba8bbcf6 JB |
555 | #define CM0_MASK_SHIFT 16 |
556 | #define CM0_IZ_OPT_DISABLE (1<<6) | |
557 | #define CM0_ZR_OPT_DISABLE (1<<5) | |
558 | #define CM0_DEPTH_EVICT_DISABLE (1<<4) | |
559 | #define CM0_COLOR_EVICT_DISABLE (1<<3) | |
560 | #define CM0_DEPTH_WRITE_DISABLE (1<<1) | |
561 | #define CM0_RC_OP_FLUSH_DISABLE (1<<0) | |
562 | ||
563 | ||
564 | /* Graphics flush control. A CPU write flushes the GWB of all writes. | |
565 | * The data is discarded. | |
566 | */ | |
567 | #define GFX_FLSH_CNTL 0x2170 | |
568 | ||
569 | /* Binner control. Defines the location of the bin pointer list: | |
570 | */ | |
571 | #define BINCTL 0x2420 | |
572 | #define BC_MASK (1 << 9) | |
573 | ||
574 | /* Binned scene info. | |
575 | */ | |
576 | #define BINSCENE 0x2428 | |
577 | #define BS_OP_LOAD (1 << 8) | |
578 | #define BS_MASK (1 << 22) | |
579 | ||
580 | /* Bin command parser debug reg: | |
581 | */ | |
582 | #define BCPD 0x2480 | |
583 | ||
584 | /* Bin memory control debug reg: | |
585 | */ | |
586 | #define BMCD 0x2484 | |
587 | ||
588 | /* Bin data cache debug reg: | |
589 | */ | |
590 | #define BDCD 0x2488 | |
591 | ||
592 | /* Binner pointer cache debug reg: | |
593 | */ | |
594 | #define BPCD 0x248c | |
595 | ||
596 | /* Binner scratch pad debug reg: | |
597 | */ | |
598 | #define BINSKPD 0x24f0 | |
599 | ||
600 | /* HWB scratch pad debug reg: | |
601 | */ | |
602 | #define HWBSKPD 0x24f4 | |
603 | ||
604 | /* Binner memory pool reg: | |
605 | */ | |
606 | #define BMP_BUFFER 0x2430 | |
607 | #define BMP_PAGE_SIZE_4K (0 << 10) | |
608 | #define BMP_BUFFER_SIZE_SHIFT 1 | |
609 | #define BMP_ENABLE (1 << 0) | |
610 | ||
611 | /* Get/put memory from the binner memory pool: | |
612 | */ | |
613 | #define BMP_GET 0x2438 | |
614 | #define BMP_PUT 0x2440 | |
615 | #define BMP_OFFSET_SHIFT 5 | |
616 | ||
617 | /* 3D state packets: | |
618 | */ | |
619 | #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) | |
620 | ||
1da177e4 LT |
621 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) |
622 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
623 | #define SC_ENABLE_MASK (0x1<<0) | |
624 | #define SC_ENABLE (0x1<<0) | |
625 | ||
ba8bbcf6 JB |
626 | #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) |
627 | ||
1da177e4 LT |
628 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) |
629 | #define SCI_YMIN_MASK (0xffff<<16) | |
630 | #define SCI_XMIN_MASK (0xffff<<0) | |
631 | #define SCI_YMAX_MASK (0xffff<<16) | |
632 | #define SCI_XMAX_MASK (0xffff<<0) | |
633 | ||
634 | #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
635 | #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) | |
636 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
637 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
638 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) | |
639 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
640 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
641 | ||
c29b669c AH |
642 | #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) |
643 | ||
ba8bbcf6 | 644 | #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) |
a6b54f3f MCA |
645 | #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
646 | #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) | |
647 | #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) | |
7b832b56 KP |
648 | #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) |
649 | #define XY_SRC_COPY_BLT_DST_TILED (1<<11) | |
a6b54f3f | 650 | |
bc5f4523 DA |
651 | #define MI_BATCH_BUFFER ((0x30<<23)|1) |
652 | #define MI_BATCH_BUFFER_START (0x31<<23) | |
653 | #define MI_BATCH_BUFFER_END (0xA<<23) | |
1da177e4 | 654 | #define MI_BATCH_NON_SECURE (1) |
21f16289 | 655 | #define MI_BATCH_NON_SECURE_I965 (1<<8) |
1da177e4 LT |
656 | |
657 | #define MI_WAIT_FOR_EVENT ((0x3<<23)) | |
ba8bbcf6 | 658 | #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |
1da177e4 LT |
659 | #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) |
660 | #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) | |
661 | ||
662 | #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) | |
663 | ||
664 | #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) | |
665 | #define ASYNC_FLIP (1<<22) | |
ba8bbcf6 JB |
666 | #define DISPLAY_PLANE_A (0<<20) |
667 | #define DISPLAY_PLANE_B (1<<20) | |
668 | ||
669 | /* Display regs */ | |
670 | #define DSPACNTR 0x70180 | |
671 | #define DSPBCNTR 0x71180 | |
672 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) | |
673 | ||
674 | /* Define the region of interest for the binner: | |
675 | */ | |
676 | #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4) | |
1da177e4 LT |
677 | |
678 | #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) | |
679 | ||
ba8bbcf6 JB |
680 | #define CMD_MI_FLUSH (0x04 << 23) |
681 | #define MI_NO_WRITE_FLUSH (1 << 2) | |
682 | #define MI_READ_FLUSH (1 << 0) | |
683 | #define MI_EXE_FLUSH (1 << 1) | |
684 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | |
685 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | |
686 | ||
687 | #define BREADCRUMB_BITS 31 | |
688 | #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) | |
689 | ||
690 | #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) | |
691 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) | |
692 | ||
693 | #define BLC_PWM_CTL 0x61254 | |
694 | #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) | |
695 | ||
696 | #define BLC_PWM_CTL2 0x61250 | |
697 | /** | |
698 | * This is the most significant 15 bits of the number of backlight cycles in a | |
699 | * complete cycle of the modulated backlight control. | |
700 | * | |
701 | * The actual value is this field multiplied by two. | |
702 | */ | |
703 | #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) | |
704 | #define BLM_LEGACY_MODE (1 << 16) | |
705 | /** | |
706 | * This is the number of cycles out of the backlight modulation cycle for which | |
707 | * the backlight is on. | |
708 | * | |
709 | * This field must be no greater than the number of cycles in the complete | |
710 | * backlight modulation cycle. | |
711 | */ | |
712 | #define BACKLIGHT_DUTY_CYCLE_SHIFT (0) | |
713 | #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) | |
714 | ||
715 | #define I915_GCFGC 0xf0 | |
716 | #define I915_LOW_FREQUENCY_ENABLE (1 << 7) | |
717 | #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) | |
718 | #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) | |
719 | #define I915_DISPLAY_CLOCK_MASK (7 << 4) | |
720 | ||
721 | #define I855_HPLLCC 0xc0 | |
722 | #define I855_CLOCK_CONTROL_MASK (3 << 0) | |
723 | #define I855_CLOCK_133_200 (0 << 0) | |
724 | #define I855_CLOCK_100_200 (1 << 0) | |
725 | #define I855_CLOCK_100_133 (2 << 0) | |
726 | #define I855_CLOCK_166_250 (3 << 0) | |
727 | ||
728 | /* p317, 319 | |
729 | */ | |
730 | #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ | |
731 | #define VCLK2_VCO_N 0x600a | |
732 | #define VCLK2_VCO_DIV_SEL 0x6012 | |
733 | ||
734 | #define VCLK_DIVISOR_VGA0 0x6000 | |
735 | #define VCLK_DIVISOR_VGA1 0x6004 | |
736 | #define VCLK_POST_DIV 0x6010 | |
737 | /** Selects a post divisor of 4 instead of 2. */ | |
738 | # define VGA1_PD_P2_DIV_4 (1 << 15) | |
739 | /** Overrides the p2 post divisor field */ | |
740 | # define VGA1_PD_P1_DIV_2 (1 << 13) | |
741 | # define VGA1_PD_P1_SHIFT 8 | |
742 | /** P1 value is 2 greater than this field */ | |
743 | # define VGA1_PD_P1_MASK (0x1f << 8) | |
744 | /** Selects a post divisor of 4 instead of 2. */ | |
745 | # define VGA0_PD_P2_DIV_4 (1 << 7) | |
746 | /** Overrides the p2 post divisor field */ | |
747 | # define VGA0_PD_P1_DIV_2 (1 << 5) | |
748 | # define VGA0_PD_P1_SHIFT 0 | |
749 | /** P1 value is 2 greater than this field */ | |
750 | # define VGA0_PD_P1_MASK (0x1f << 0) | |
751 | ||
1f84e550 KP |
752 | #define DSPCLK_GATE_D 0x6200 |
753 | ||
ba8bbcf6 JB |
754 | /* I830 CRTC registers */ |
755 | #define HTOTAL_A 0x60000 | |
756 | #define HBLANK_A 0x60004 | |
757 | #define HSYNC_A 0x60008 | |
758 | #define VTOTAL_A 0x6000c | |
759 | #define VBLANK_A 0x60010 | |
760 | #define VSYNC_A 0x60014 | |
761 | #define PIPEASRC 0x6001c | |
762 | #define BCLRPAT_A 0x60020 | |
763 | #define VSYNCSHIFT_A 0x60028 | |
764 | ||
765 | #define HTOTAL_B 0x61000 | |
766 | #define HBLANK_B 0x61004 | |
767 | #define HSYNC_B 0x61008 | |
768 | #define VTOTAL_B 0x6100c | |
769 | #define VBLANK_B 0x61010 | |
770 | #define VSYNC_B 0x61014 | |
771 | #define PIPEBSRC 0x6101c | |
772 | #define BCLRPAT_B 0x61020 | |
773 | #define VSYNCSHIFT_B 0x61028 | |
774 | ||
775 | #define PP_STATUS 0x61200 | |
776 | # define PP_ON (1 << 31) | |
777 | /** | |
778 | * Indicates that all dependencies of the panel are on: | |
779 | * | |
780 | * - PLL enabled | |
781 | * - pipe enabled | |
782 | * - LVDS/DVOB/DVOC on | |
783 | */ | |
784 | # define PP_READY (1 << 30) | |
785 | # define PP_SEQUENCE_NONE (0 << 28) | |
786 | # define PP_SEQUENCE_ON (1 << 28) | |
787 | # define PP_SEQUENCE_OFF (2 << 28) | |
788 | # define PP_SEQUENCE_MASK 0x30000000 | |
789 | #define PP_CONTROL 0x61204 | |
790 | # define POWER_TARGET_ON (1 << 0) | |
791 | ||
792 | #define LVDSPP_ON 0x61208 | |
793 | #define LVDSPP_OFF 0x6120c | |
794 | #define PP_CYCLE 0x61210 | |
795 | ||
796 | #define PFIT_CONTROL 0x61230 | |
797 | # define PFIT_ENABLE (1 << 31) | |
798 | # define PFIT_PIPE_MASK (3 << 29) | |
799 | # define PFIT_PIPE_SHIFT 29 | |
800 | # define VERT_INTERP_DISABLE (0 << 10) | |
801 | # define VERT_INTERP_BILINEAR (1 << 10) | |
802 | # define VERT_INTERP_MASK (3 << 10) | |
803 | # define VERT_AUTO_SCALE (1 << 9) | |
804 | # define HORIZ_INTERP_DISABLE (0 << 6) | |
805 | # define HORIZ_INTERP_BILINEAR (1 << 6) | |
806 | # define HORIZ_INTERP_MASK (3 << 6) | |
807 | # define HORIZ_AUTO_SCALE (1 << 5) | |
808 | # define PANEL_8TO6_DITHER_ENABLE (1 << 3) | |
809 | ||
810 | #define PFIT_PGM_RATIOS 0x61234 | |
811 | # define PFIT_VERT_SCALE_MASK 0xfff00000 | |
812 | # define PFIT_HORIZ_SCALE_MASK 0x0000fff0 | |
813 | ||
814 | #define PFIT_AUTO_RATIOS 0x61238 | |
815 | ||
816 | ||
817 | #define DPLL_A 0x06014 | |
818 | #define DPLL_B 0x06018 | |
819 | # define DPLL_VCO_ENABLE (1 << 31) | |
820 | # define DPLL_DVO_HIGH_SPEED (1 << 30) | |
821 | # define DPLL_SYNCLOCK_ENABLE (1 << 29) | |
822 | # define DPLL_VGA_MODE_DIS (1 << 28) | |
823 | # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ | |
824 | # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ | |
825 | # define DPLL_MODE_MASK (3 << 26) | |
826 | # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ | |
827 | # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ | |
828 | # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ | |
829 | # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ | |
830 | # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ | |
831 | # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | |
832 | /** | |
833 | * The i830 generation, in DAC/serial mode, defines p1 as two plus this | |
834 | * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. | |
835 | */ | |
836 | # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 | |
837 | /** | |
838 | * The i830 generation, in LVDS mode, defines P1 as the bit number set within | |
839 | * this field (only one bit may be set). | |
840 | */ | |
841 | # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 | |
842 | # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 | |
843 | # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ | |
844 | # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ | |
845 | # define PLL_REF_INPUT_DREFCLK (0 << 13) | |
846 | # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ | |
847 | # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ | |
848 | # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) | |
849 | # define PLL_REF_INPUT_MASK (3 << 13) | |
850 | # define PLL_LOAD_PULSE_PHASE_SHIFT 9 | |
851 | /* | |
852 | * Parallel to Serial Load Pulse phase selection. | |
853 | * Selects the phase for the 10X DPLL clock for the PCIe | |
854 | * digital display port. The range is 4 to 13; 10 or more | |
855 | * is just a flip delay. The default is 6 | |
856 | */ | |
857 | # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) | |
858 | # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) | |
859 | ||
860 | /** | |
861 | * SDVO multiplier for 945G/GM. Not used on 965. | |
862 | * | |
863 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK | |
864 | */ | |
865 | # define SDVO_MULTIPLIER_MASK 0x000000ff | |
866 | # define SDVO_MULTIPLIER_SHIFT_HIRES 4 | |
867 | # define SDVO_MULTIPLIER_SHIFT_VGA 0 | |
868 | ||
869 | /** @defgroup DPLL_MD | |
870 | * @{ | |
871 | */ | |
872 | /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ | |
873 | #define DPLL_A_MD 0x0601c | |
874 | /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ | |
875 | #define DPLL_B_MD 0x06020 | |
876 | /** | |
877 | * UDI pixel divider, controlling how many pixels are stuffed into a packet. | |
878 | * | |
879 | * Value is pixels minus 1. Must be set to 1 pixel for SDVO. | |
880 | */ | |
881 | # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 | |
882 | # define DPLL_MD_UDI_DIVIDER_SHIFT 24 | |
883 | /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ | |
884 | # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 | |
885 | # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 | |
886 | /** | |
887 | * SDVO/UDI pixel multiplier. | |
888 | * | |
889 | * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus | |
890 | * clock rate is 10 times the DPLL clock. At low resolution/refresh rate | |
891 | * modes, the bus rate would be below the limits, so SDVO allows for stuffing | |
892 | * dummy bytes in the datastream at an increased clock rate, with both sides of | |
893 | * the link knowing how many bytes are fill. | |
894 | * | |
895 | * So, for a mode with a dotclock of 65Mhz, we would want to double the clock | |
896 | * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be | |
897 | * set to 130Mhz, and the SDVO multiplier set to 2x in this register and | |
898 | * through an SDVO command. | |
899 | * | |
900 | * This register field has values of multiplication factor minus 1, with | |
901 | * a maximum multiplier of 5 for SDVO. | |
902 | */ | |
903 | # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 | |
904 | # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 | |
905 | /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. | |
906 | * This best be set to the default value (3) or the CRT won't work. No, | |
907 | * I don't entirely understand what this does... | |
908 | */ | |
909 | # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f | |
910 | # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 | |
911 | /** @} */ | |
912 | ||
913 | #define DPLL_TEST 0x606c | |
914 | # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) | |
915 | # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) | |
916 | # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) | |
917 | # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) | |
918 | # define DPLLB_TEST_N_BYPASS (1 << 19) | |
919 | # define DPLLB_TEST_M_BYPASS (1 << 18) | |
920 | # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) | |
921 | # define DPLLA_TEST_N_BYPASS (1 << 3) | |
922 | # define DPLLA_TEST_M_BYPASS (1 << 2) | |
923 | # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) | |
924 | ||
925 | #define ADPA 0x61100 | |
926 | #define ADPA_DAC_ENABLE (1<<31) | |
927 | #define ADPA_DAC_DISABLE 0 | |
928 | #define ADPA_PIPE_SELECT_MASK (1<<30) | |
929 | #define ADPA_PIPE_A_SELECT 0 | |
930 | #define ADPA_PIPE_B_SELECT (1<<30) | |
931 | #define ADPA_USE_VGA_HVPOLARITY (1<<15) | |
932 | #define ADPA_SETS_HVPOLARITY 0 | |
933 | #define ADPA_VSYNC_CNTL_DISABLE (1<<11) | |
934 | #define ADPA_VSYNC_CNTL_ENABLE 0 | |
935 | #define ADPA_HSYNC_CNTL_DISABLE (1<<10) | |
936 | #define ADPA_HSYNC_CNTL_ENABLE 0 | |
937 | #define ADPA_VSYNC_ACTIVE_HIGH (1<<4) | |
938 | #define ADPA_VSYNC_ACTIVE_LOW 0 | |
939 | #define ADPA_HSYNC_ACTIVE_HIGH (1<<3) | |
940 | #define ADPA_HSYNC_ACTIVE_LOW 0 | |
941 | ||
942 | #define FPA0 0x06040 | |
943 | #define FPA1 0x06044 | |
944 | #define FPB0 0x06048 | |
945 | #define FPB1 0x0604c | |
946 | # define FP_N_DIV_MASK 0x003f0000 | |
947 | # define FP_N_DIV_SHIFT 16 | |
948 | # define FP_M1_DIV_MASK 0x00003f00 | |
949 | # define FP_M1_DIV_SHIFT 8 | |
950 | # define FP_M2_DIV_MASK 0x0000003f | |
951 | # define FP_M2_DIV_SHIFT 0 | |
952 | ||
953 | ||
954 | #define PORT_HOTPLUG_EN 0x61110 | |
955 | # define SDVOB_HOTPLUG_INT_EN (1 << 26) | |
956 | # define SDVOC_HOTPLUG_INT_EN (1 << 25) | |
957 | # define TV_HOTPLUG_INT_EN (1 << 18) | |
958 | # define CRT_HOTPLUG_INT_EN (1 << 9) | |
959 | # define CRT_HOTPLUG_FORCE_DETECT (1 << 3) | |
960 | ||
961 | #define PORT_HOTPLUG_STAT 0x61114 | |
962 | # define CRT_HOTPLUG_INT_STATUS (1 << 11) | |
963 | # define TV_HOTPLUG_INT_STATUS (1 << 10) | |
964 | # define CRT_HOTPLUG_MONITOR_MASK (3 << 8) | |
965 | # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) | |
966 | # define CRT_HOTPLUG_MONITOR_MONO (2 << 8) | |
967 | # define CRT_HOTPLUG_MONITOR_NONE (0 << 8) | |
968 | # define SDVOC_HOTPLUG_INT_STATUS (1 << 7) | |
969 | # define SDVOB_HOTPLUG_INT_STATUS (1 << 6) | |
970 | ||
971 | #define SDVOB 0x61140 | |
972 | #define SDVOC 0x61160 | |
973 | #define SDVO_ENABLE (1 << 31) | |
974 | #define SDVO_PIPE_B_SELECT (1 << 30) | |
975 | #define SDVO_STALL_SELECT (1 << 29) | |
976 | #define SDVO_INTERRUPT_ENABLE (1 << 26) | |
977 | /** | |
978 | * 915G/GM SDVO pixel multiplier. | |
979 | * | |
980 | * Programmed value is multiplier - 1, up to 5x. | |
981 | * | |
982 | * \sa DPLL_MD_UDI_MULTIPLIER_MASK | |
983 | */ | |
984 | #define SDVO_PORT_MULTIPLY_MASK (7 << 23) | |
985 | #define SDVO_PORT_MULTIPLY_SHIFT 23 | |
986 | #define SDVO_PHASE_SELECT_MASK (15 << 19) | |
987 | #define SDVO_PHASE_SELECT_DEFAULT (6 << 19) | |
988 | #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) | |
989 | #define SDVOC_GANG_MODE (1 << 16) | |
990 | #define SDVO_BORDER_ENABLE (1 << 7) | |
991 | #define SDVOB_PCIE_CONCURRENCY (1 << 3) | |
992 | #define SDVO_DETECTED (1 << 2) | |
993 | /* Bits to be preserved when writing */ | |
994 | #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) | |
995 | #define SDVOC_PRESERVE_MASK (1 << 17) | |
996 | ||
997 | /** @defgroup LVDS | |
998 | * @{ | |
999 | */ | |
1000 | /** | |
1001 | * This register controls the LVDS output enable, pipe selection, and data | |
1002 | * format selection. | |
1003 | * | |
1004 | * All of the clock/data pairs are force powered down by power sequencing. | |
1005 | */ | |
1006 | #define LVDS 0x61180 | |
1007 | /** | |
1008 | * Enables the LVDS port. This bit must be set before DPLLs are enabled, as | |
1009 | * the DPLL semantics change when the LVDS is assigned to that pipe. | |
1010 | */ | |
1011 | # define LVDS_PORT_EN (1 << 31) | |
1012 | /** Selects pipe B for LVDS data. Must be set on pre-965. */ | |
1013 | # define LVDS_PIPEB_SELECT (1 << 30) | |
1014 | ||
1015 | /** | |
1016 | * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per | |
1017 | * pixel. | |
1018 | */ | |
1019 | # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) | |
1020 | # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) | |
1021 | # define LVDS_A0A2_CLKA_POWER_UP (3 << 8) | |
1022 | /** | |
1023 | * Controls the A3 data pair, which contains the additional LSBs for 24 bit | |
1024 | * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be | |
1025 | * on. | |
1026 | */ | |
1027 | # define LVDS_A3_POWER_MASK (3 << 6) | |
1028 | # define LVDS_A3_POWER_DOWN (0 << 6) | |
1029 | # define LVDS_A3_POWER_UP (3 << 6) | |
1030 | /** | |
1031 | * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP | |
1032 | * is set. | |
1033 | */ | |
1034 | # define LVDS_CLKB_POWER_MASK (3 << 4) | |
1035 | # define LVDS_CLKB_POWER_DOWN (0 << 4) | |
1036 | # define LVDS_CLKB_POWER_UP (3 << 4) | |
1037 | ||
1038 | /** | |
1039 | * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 | |
1040 | * setting for whether we are in dual-channel mode. The B3 pair will | |
1041 | * additionally only be powered up when LVDS_A3_POWER_UP is set. | |
1042 | */ | |
1043 | # define LVDS_B0B3_POWER_MASK (3 << 2) | |
1044 | # define LVDS_B0B3_POWER_DOWN (0 << 2) | |
1045 | # define LVDS_B0B3_POWER_UP (3 << 2) | |
1046 | ||
1047 | #define PIPEACONF 0x70008 | |
1048 | #define PIPEACONF_ENABLE (1<<31) | |
1049 | #define PIPEACONF_DISABLE 0 | |
1050 | #define PIPEACONF_DOUBLE_WIDE (1<<30) | |
1051 | #define I965_PIPECONF_ACTIVE (1<<30) | |
1052 | #define PIPEACONF_SINGLE_WIDE 0 | |
1053 | #define PIPEACONF_PIPE_UNLOCKED 0 | |
1054 | #define PIPEACONF_PIPE_LOCKED (1<<25) | |
1055 | #define PIPEACONF_PALETTE 0 | |
1056 | #define PIPEACONF_GAMMA (1<<24) | |
1057 | #define PIPECONF_FORCE_BORDER (1<<25) | |
1058 | #define PIPECONF_PROGRESSIVE (0 << 21) | |
1059 | #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) | |
1060 | #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) | |
1061 | ||
1062 | #define PIPEBCONF 0x71008 | |
1063 | #define PIPEBCONF_ENABLE (1<<31) | |
1064 | #define PIPEBCONF_DISABLE 0 | |
1065 | #define PIPEBCONF_DOUBLE_WIDE (1<<30) | |
1066 | #define PIPEBCONF_DISABLE 0 | |
1067 | #define PIPEBCONF_GAMMA (1<<24) | |
1068 | #define PIPEBCONF_PALETTE 0 | |
1069 | ||
1070 | #define PIPEBGCMAXRED 0x71010 | |
1071 | #define PIPEBGCMAXGREEN 0x71014 | |
1072 | #define PIPEBGCMAXBLUE 0x71018 | |
1073 | #define PIPEBSTAT 0x71024 | |
1074 | #define PIPEBFRAMEHIGH 0x71040 | |
1075 | #define PIPEBFRAMEPIXEL 0x71044 | |
1076 | ||
1077 | #define DSPACNTR 0x70180 | |
1078 | #define DSPBCNTR 0x71180 | |
1079 | #define DISPLAY_PLANE_ENABLE (1<<31) | |
1080 | #define DISPLAY_PLANE_DISABLE 0 | |
1081 | #define DISPPLANE_GAMMA_ENABLE (1<<30) | |
1082 | #define DISPPLANE_GAMMA_DISABLE 0 | |
1083 | #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) | |
1084 | #define DISPPLANE_8BPP (0x2<<26) | |
1085 | #define DISPPLANE_15_16BPP (0x4<<26) | |
1086 | #define DISPPLANE_16BPP (0x5<<26) | |
1087 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) | |
1088 | #define DISPPLANE_32BPP (0x7<<26) | |
1089 | #define DISPPLANE_STEREO_ENABLE (1<<25) | |
1090 | #define DISPPLANE_STEREO_DISABLE 0 | |
1091 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) | |
1092 | #define DISPPLANE_SEL_PIPE_A 0 | |
1093 | #define DISPPLANE_SEL_PIPE_B (1<<24) | |
1094 | #define DISPPLANE_SRC_KEY_ENABLE (1<<22) | |
1095 | #define DISPPLANE_SRC_KEY_DISABLE 0 | |
1096 | #define DISPPLANE_LINE_DOUBLE (1<<20) | |
1097 | #define DISPPLANE_NO_LINE_DOUBLE 0 | |
1098 | #define DISPPLANE_STEREO_POLARITY_FIRST 0 | |
1099 | #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) | |
1100 | /* plane B only */ | |
1101 | #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) | |
1102 | #define DISPPLANE_ALPHA_TRANS_DISABLE 0 | |
1103 | #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 | |
1104 | #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) | |
1105 | ||
1106 | #define DSPABASE 0x70184 | |
1107 | #define DSPASTRIDE 0x70188 | |
1108 | ||
1109 | #define DSPBBASE 0x71184 | |
1110 | #define DSPBADDR DSPBBASE | |
1111 | #define DSPBSTRIDE 0x71188 | |
1112 | ||
1113 | #define DSPAKEYVAL 0x70194 | |
1114 | #define DSPAKEYMASK 0x70198 | |
1115 | ||
1116 | #define DSPAPOS 0x7018C /* reserved */ | |
1117 | #define DSPASIZE 0x70190 | |
1118 | #define DSPBPOS 0x7118C | |
1119 | #define DSPBSIZE 0x71190 | |
1120 | ||
1121 | #define DSPASURF 0x7019C | |
1122 | #define DSPATILEOFF 0x701A4 | |
1123 | ||
1124 | #define DSPBSURF 0x7119C | |
1125 | #define DSPBTILEOFF 0x711A4 | |
1126 | ||
1127 | #define VGACNTRL 0x71400 | |
1128 | # define VGA_DISP_DISABLE (1 << 31) | |
1129 | # define VGA_2X_MODE (1 << 30) | |
1130 | # define VGA_PIPE_B_SELECT (1 << 29) | |
1131 | ||
1132 | /* | |
1133 | * Some BIOS scratch area registers. The 845 (and 830?) store the amount | |
1134 | * of video memory available to the BIOS in SWF1. | |
1135 | */ | |
1136 | ||
1137 | #define SWF0 0x71410 | |
1138 | ||
1139 | /* | |
1140 | * 855 scratch registers. | |
1141 | */ | |
1142 | #define SWF10 0x70410 | |
1143 | ||
1144 | #define SWF30 0x72414 | |
1145 | ||
1146 | /* | |
1147 | * Overlay registers. These are overlay registers accessed via MMIO. | |
1148 | * Those loaded via the overlay register page are defined in i830_video.c. | |
1149 | */ | |
1150 | #define OVADD 0x30000 | |
1151 | ||
1152 | #define DOVSTA 0x30008 | |
1153 | #define OC_BUF (0x3<<20) | |
1154 | ||
1155 | #define OGAMC5 0x30010 | |
1156 | #define OGAMC4 0x30014 | |
1157 | #define OGAMC3 0x30018 | |
1158 | #define OGAMC2 0x3001c | |
1159 | #define OGAMC1 0x30020 | |
1160 | #define OGAMC0 0x30024 | |
1161 | /* | |
1162 | * Palette registers | |
1163 | */ | |
1164 | #define PALETTE_A 0x0a000 | |
1165 | #define PALETTE_B 0x0a800 | |
1166 | ||
1167 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1168 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1169 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | |
1170 | #define IS_I855(dev) ((dev)->pci_device == 0x3582) | |
1171 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1172 | ||
4d1f7888 | 1173 | #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) |
ba8bbcf6 JB |
1174 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) |
1175 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
3bf48468 JB |
1176 | #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ |
1177 | (dev)->pci_device == 0x27AE) | |
ba8bbcf6 JB |
1178 | #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ |
1179 | (dev)->pci_device == 0x2982 || \ | |
1180 | (dev)->pci_device == 0x2992 || \ | |
1181 | (dev)->pci_device == 0x29A2 || \ | |
1182 | (dev)->pci_device == 0x2A02 || \ | |
5f5f9d4c ZW |
1183 | (dev)->pci_device == 0x2A12 || \ |
1184 | (dev)->pci_device == 0x2A42) | |
ba8bbcf6 JB |
1185 | |
1186 | #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) | |
1187 | ||
5f5f9d4c ZW |
1188 | #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42) |
1189 | ||
ba8bbcf6 JB |
1190 | #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ |
1191 | (dev)->pci_device == 0x29B2 || \ | |
1192 | (dev)->pci_device == 0x29D2) | |
1193 | ||
1194 | #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ | |
1195 | IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) | |
1196 | ||
1197 | #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ | |
5f5f9d4c | 1198 | IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev)) |
ba8bbcf6 | 1199 | |
b39d50e5 ZW |
1200 | #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev)) |
1201 | ||
ba8bbcf6 | 1202 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1203 | |
1da177e4 | 1204 | #endif |