Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All rights reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: Rickard E. (Rik) Faith <faith@valinux.com> | |
28 | * Jeff Hartmann <jhartmann@valinux.com> | |
29 | * | |
30 | */ | |
31 | ||
32 | #ifndef _I810_DRV_H_ | |
33 | #define _I810_DRV_H_ | |
34 | ||
35 | /* General customization: | |
36 | */ | |
37 | ||
38 | #define DRIVER_AUTHOR "VA Linux Systems Inc." | |
39 | ||
40 | #define DRIVER_NAME "i810" | |
41 | #define DRIVER_DESC "Intel i810" | |
42 | #define DRIVER_DATE "20030605" | |
43 | ||
44 | /* Interface history | |
45 | * | |
46 | * 1.1 - XFree86 4.1 | |
47 | * 1.2 - XvMC interfaces | |
48 | * - XFree86 4.2 | |
49 | * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility) | |
50 | * - Remove requirement for interrupt (leave stubs again) | |
51 | * 1.3 - Add page flipping. | |
52 | * 1.4 - fix DRM interface | |
53 | */ | |
54 | #define DRIVER_MAJOR 1 | |
55 | #define DRIVER_MINOR 4 | |
56 | #define DRIVER_PATCHLEVEL 0 | |
57 | ||
58 | typedef struct drm_i810_buf_priv { | |
b5e89ed5 DA |
59 | u32 *in_use; |
60 | int my_use_idx; | |
1da177e4 LT |
61 | int currently_mapped; |
62 | void *virtual; | |
63 | void *kernel_virtual; | |
64 | } drm_i810_buf_priv_t; | |
65 | ||
b5e89ed5 | 66 | typedef struct _drm_i810_ring_buffer { |
1da177e4 LT |
67 | int tail_mask; |
68 | unsigned long Start; | |
69 | unsigned long End; | |
70 | unsigned long Size; | |
71 | u8 *virtual_start; | |
72 | int head; | |
73 | int tail; | |
74 | int space; | |
75 | } drm_i810_ring_buffer_t; | |
76 | ||
77 | typedef struct drm_i810_private { | |
78 | drm_map_t *sarea_map; | |
79 | drm_map_t *mmio_map; | |
80 | ||
81 | drm_i810_sarea_t *sarea_priv; | |
b5e89ed5 | 82 | drm_i810_ring_buffer_t ring; |
1da177e4 | 83 | |
b5e89ed5 DA |
84 | void *hw_status_page; |
85 | unsigned long counter; | |
1da177e4 LT |
86 | |
87 | dma_addr_t dma_status_page; | |
88 | ||
89 | drm_buf_t *mmap_buffer; | |
90 | ||
1da177e4 LT |
91 | u32 front_di1, back_di1, zi1; |
92 | ||
93 | int back_offset; | |
94 | int depth_offset; | |
95 | int overlay_offset; | |
96 | int overlay_physical; | |
97 | int w, h; | |
98 | int pitch; | |
b5e89ed5 | 99 | int back_pitch; |
1da177e4 LT |
100 | int depth_pitch; |
101 | ||
102 | int do_boxes; | |
103 | int dma_used; | |
104 | ||
105 | int current_page; | |
106 | int page_flipping; | |
107 | ||
108 | wait_queue_head_t irq_queue; | |
b5e89ed5 DA |
109 | atomic_t irq_received; |
110 | atomic_t irq_emitted; | |
111 | ||
112 | int front_offset; | |
1da177e4 LT |
113 | } drm_i810_private_t; |
114 | ||
115 | /* i810_dma.c */ | |
b5e89ed5 | 116 | extern void i810_reclaim_buffers(drm_device_t * dev, struct file *filp); |
1da177e4 | 117 | |
b5e89ed5 | 118 | extern int i810_driver_dma_quiescent(drm_device_t * dev); |
22eae947 DA |
119 | extern void i810_driver_reclaim_buffers_locked(drm_device_t * dev, |
120 | struct file *filp); | |
121 | extern int i810_driver_load(struct drm_device *, unsigned long flags); | |
122 | extern void i810_driver_lastclose(drm_device_t * dev); | |
123 | extern void i810_driver_preclose(drm_device_t * dev, DRMFILE filp); | |
124 | extern void i810_driver_reclaim_buffers_locked(drm_device_t * dev, | |
125 | struct file *filp); | |
cda17380 | 126 | extern int i810_driver_device_is_agp(drm_device_t * dev); |
1da177e4 | 127 | |
b3a83639 DA |
128 | extern drm_ioctl_desc_t i810_ioctls[]; |
129 | extern int i810_max_ioctl; | |
130 | ||
1da177e4 LT |
131 | #define I810_BASE(reg) ((unsigned long) \ |
132 | dev_priv->mmio_map->handle) | |
133 | #define I810_ADDR(reg) (I810_BASE(reg) + reg) | |
134 | #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg) | |
135 | #define I810_READ(reg) I810_DEREF(reg) | |
136 | #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0) | |
137 | #define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg) | |
138 | #define I810_READ16(reg) I810_DEREF16(reg) | |
139 | #define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0) | |
140 | ||
141 | #define I810_VERBOSE 0 | |
142 | #define RING_LOCALS unsigned int outring, ringmask; \ | |
143 | volatile char *virt; | |
144 | ||
145 | #define BEGIN_LP_RING(n) do { \ | |
146 | if (I810_VERBOSE) \ | |
147 | DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", n, __FUNCTION__); \ | |
148 | if (dev_priv->ring.space < n*4) \ | |
149 | i810_wait_ring(dev, n*4); \ | |
150 | dev_priv->ring.space -= n*4; \ | |
151 | outring = dev_priv->ring.tail; \ | |
152 | ringmask = dev_priv->ring.tail_mask; \ | |
153 | virt = dev_priv->ring.virtual_start; \ | |
154 | } while (0) | |
155 | ||
156 | #define ADVANCE_LP_RING() do { \ | |
157 | if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \ | |
158 | dev_priv->ring.tail = outring; \ | |
159 | I810_WRITE(LP_RING + RING_TAIL, outring); \ | |
160 | } while(0) | |
161 | ||
162 | #define OUT_RING(n) do { \ | |
163 | if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ | |
164 | *(volatile unsigned int *)(virt + outring) = n; \ | |
165 | outring += 4; \ | |
166 | outring &= ringmask; \ | |
167 | } while (0) | |
168 | ||
169 | #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) | |
170 | #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) | |
171 | #define CMD_REPORT_HEAD (7<<23) | |
172 | #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) | |
173 | #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) | |
174 | ||
175 | #define INST_PARSER_CLIENT 0x00000000 | |
176 | #define INST_OP_FLUSH 0x02000000 | |
177 | #define INST_FLUSH_MAP_CACHE 0x00000001 | |
178 | ||
1da177e4 LT |
179 | #define BB1_START_ADDR_MASK (~0x7) |
180 | #define BB1_PROTECTED (1<<0) | |
181 | #define BB1_UNPROTECTED (0<<0) | |
182 | #define BB2_END_ADDR_MASK (~0x7) | |
183 | ||
184 | #define I810REG_HWSTAM 0x02098 | |
185 | #define I810REG_INT_IDENTITY_R 0x020a4 | |
186 | #define I810REG_INT_MASK_R 0x020a8 | |
187 | #define I810REG_INT_ENABLE_R 0x020a0 | |
188 | ||
189 | #define LP_RING 0x2030 | |
190 | #define HP_RING 0x2040 | |
191 | #define RING_TAIL 0x00 | |
192 | #define TAIL_ADDR 0x000FFFF8 | |
193 | #define RING_HEAD 0x04 | |
194 | #define HEAD_WRAP_COUNT 0xFFE00000 | |
195 | #define HEAD_WRAP_ONE 0x00200000 | |
196 | #define HEAD_ADDR 0x001FFFFC | |
197 | #define RING_START 0x08 | |
198 | #define START_ADDR 0x00FFFFF8 | |
199 | #define RING_LEN 0x0C | |
200 | #define RING_NR_PAGES 0x000FF000 | |
201 | #define RING_REPORT_MASK 0x00000006 | |
202 | #define RING_REPORT_64K 0x00000002 | |
203 | #define RING_REPORT_128K 0x00000004 | |
204 | #define RING_NO_REPORT 0x00000000 | |
205 | #define RING_VALID_MASK 0x00000001 | |
206 | #define RING_VALID 0x00000001 | |
207 | #define RING_INVALID 0x00000000 | |
208 | ||
209 | #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) | |
210 | #define SC_UPDATE_SCISSOR (0x1<<1) | |
211 | #define SC_ENABLE_MASK (0x1<<0) | |
212 | #define SC_ENABLE (0x1<<0) | |
213 | ||
214 | #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) | |
215 | #define SCI_YMIN_MASK (0xffff<<16) | |
216 | #define SCI_XMIN_MASK (0xffff<<0) | |
217 | #define SCI_YMAX_MASK (0xffff<<16) | |
218 | #define SCI_XMAX_MASK (0xffff<<0) | |
219 | ||
220 | #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) | |
221 | #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) | |
222 | #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2) | |
223 | #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) | |
224 | #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) | |
225 | #define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24)) | |
226 | ||
227 | #define CMD_OP_Z_BUFFER_INFO ((0x0<<29)|(0x16<<23)) | |
228 | #define CMD_OP_DESTBUFFER_INFO ((0x0<<29)|(0x15<<23)) | |
229 | #define CMD_OP_FRONTBUFFER_INFO ((0x0<<29)|(0x14<<23)) | |
230 | #define CMD_OP_WAIT_FOR_EVENT ((0x0<<29)|(0x03<<23)) | |
231 | ||
232 | #define BR00_BITBLT_CLIENT 0x40000000 | |
233 | #define BR00_OP_COLOR_BLT 0x10000000 | |
234 | #define BR00_OP_SRC_COPY_BLT 0x10C00000 | |
235 | #define BR13_SOLID_PATTERN 0x80000000 | |
236 | ||
b5e89ed5 DA |
237 | #define WAIT_FOR_PLANE_A_SCANLINES (1<<1) |
238 | #define WAIT_FOR_PLANE_A_FLIP (1<<2) | |
1da177e4 LT |
239 | #define WAIT_FOR_VBLANK (1<<3) |
240 | ||
241 | #endif |