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1da177e4 LT |
1 | #ifndef _I810_DRM_H_ |
2 | #define _I810_DRM_H_ | |
3 | ||
4 | /* WARNING: These defines must be the same as what the Xserver uses. | |
5 | * if you change them, you must change the defines in the Xserver. | |
6 | */ | |
7 | ||
8 | #ifndef _I810_DEFINES_ | |
9 | #define _I810_DEFINES_ | |
10 | ||
11 | #define I810_DMA_BUF_ORDER 12 | |
12 | #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER) | |
13 | #define I810_DMA_BUF_NR 256 | |
14 | #define I810_NR_SAREA_CLIPRECTS 8 | |
15 | ||
16 | /* Each region is a minimum of 64k, and there are at most 64 of them. | |
17 | */ | |
18 | #define I810_NR_TEX_REGIONS 64 | |
19 | #define I810_LOG_MIN_TEX_REGION_SIZE 16 | |
20 | #endif | |
21 | ||
b5e89ed5 DA |
22 | #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */ |
23 | #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */ | |
1da177e4 LT |
24 | #define I810_UPLOAD_CTX 0x4 |
25 | #define I810_UPLOAD_BUFFERS 0x8 | |
26 | #define I810_UPLOAD_TEX0 0x10 | |
27 | #define I810_UPLOAD_TEX1 0x20 | |
28 | #define I810_UPLOAD_CLIPRECTS 0x40 | |
29 | ||
1da177e4 LT |
30 | /* Indices into buf.Setup where various bits of state are mirrored per |
31 | * context and per buffer. These can be fired at the card as a unit, | |
32 | * or in a piecewise fashion as required. | |
33 | */ | |
34 | ||
b5e89ed5 | 35 | /* Destbuffer state |
1da177e4 LT |
36 | * - backbuffer linear offset and pitch -- invarient in the current dri |
37 | * - zbuffer linear offset and pitch -- also invarient | |
38 | * - drawing origin in back and depth buffers. | |
39 | * | |
40 | * Keep the depth/back buffer state here to accommodate private buffers | |
41 | * in the future. | |
42 | */ | |
43 | #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */ | |
44 | #define I810_DESTREG_DI1 1 | |
45 | #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */ | |
46 | #define I810_DESTREG_DV1 3 | |
47 | #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */ | |
48 | #define I810_DESTREG_DR1 5 | |
49 | #define I810_DESTREG_DR2 6 | |
50 | #define I810_DESTREG_DR3 7 | |
51 | #define I810_DESTREG_DR4 8 | |
52 | #define I810_DEST_SETUP_SIZE 10 | |
53 | ||
54 | /* Context state | |
55 | */ | |
56 | #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */ | |
b5e89ed5 DA |
57 | #define I810_CTXREG_CF1 1 |
58 | #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */ | |
1da177e4 LT |
59 | #define I810_CTXREG_ST1 3 |
60 | #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */ | |
61 | #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */ | |
62 | #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */ | |
b5e89ed5 | 63 | #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */ |
1da177e4 LT |
64 | #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */ |
65 | #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */ | |
66 | #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */ | |
67 | #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */ | |
68 | #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */ | |
69 | #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */ | |
70 | #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */ | |
71 | #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */ | |
72 | #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */ | |
73 | #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */ | |
74 | #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */ | |
75 | #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */ | |
b5e89ed5 | 76 | #define I810_CTX_SETUP_SIZE 20 |
1da177e4 LT |
77 | |
78 | /* Texture state (per tex unit) | |
79 | */ | |
80 | #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */ | |
b5e89ed5 DA |
81 | #define I810_TEXREG_MI1 1 |
82 | #define I810_TEXREG_MI2 2 | |
83 | #define I810_TEXREG_MI3 3 | |
1da177e4 LT |
84 | #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */ |
85 | #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */ | |
86 | #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */ | |
87 | #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */ | |
88 | #define I810_TEX_SETUP_SIZE 8 | |
89 | ||
90 | /* Flags for clear ioctl | |
91 | */ | |
92 | #define I810_FRONT 0x1 | |
93 | #define I810_BACK 0x2 | |
94 | #define I810_DEPTH 0x4 | |
95 | ||
96 | typedef enum _drm_i810_init_func { | |
97 | I810_INIT_DMA = 0x01, | |
98 | I810_CLEANUP_DMA = 0x02, | |
99 | I810_INIT_DMA_1_4 = 0x03 | |
b5e89ed5 | 100 | } drm_i810_init_func_t; |
1da177e4 LT |
101 | |
102 | /* This is the init structure after v1.2 */ | |
103 | typedef struct _drm_i810_init { | |
104 | drm_i810_init_func_t func; | |
105 | #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) | |
106 | int ring_map_idx; | |
107 | int buffer_map_idx; | |
108 | #else | |
109 | unsigned int mmio_offset; | |
110 | unsigned int buffers_offset; | |
111 | #endif | |
112 | int sarea_priv_offset; | |
113 | unsigned int ring_start; | |
114 | unsigned int ring_end; | |
115 | unsigned int ring_size; | |
116 | unsigned int front_offset; | |
117 | unsigned int back_offset; | |
118 | unsigned int depth_offset; | |
119 | unsigned int overlay_offset; | |
120 | unsigned int overlay_physical; | |
121 | unsigned int w; | |
122 | unsigned int h; | |
123 | unsigned int pitch; | |
b5e89ed5 | 124 | unsigned int pitch_bits; |
1da177e4 LT |
125 | } drm_i810_init_t; |
126 | ||
127 | /* This is the init structure prior to v1.2 */ | |
128 | typedef struct _drm_i810_pre12_init { | |
129 | drm_i810_init_func_t func; | |
130 | unsigned int mmio_offset; | |
131 | unsigned int buffers_offset; | |
132 | int sarea_priv_offset; | |
133 | unsigned int ring_start; | |
134 | unsigned int ring_end; | |
135 | unsigned int ring_size; | |
136 | unsigned int front_offset; | |
137 | unsigned int back_offset; | |
138 | unsigned int depth_offset; | |
139 | unsigned int w; | |
140 | unsigned int h; | |
141 | unsigned int pitch; | |
b5e89ed5 | 142 | unsigned int pitch_bits; |
1da177e4 LT |
143 | } drm_i810_pre12_init_t; |
144 | ||
145 | /* Warning: If you change the SAREA structure you must change the Xserver | |
146 | * structure as well */ | |
147 | ||
148 | typedef struct _drm_i810_tex_region { | |
b5e89ed5 | 149 | unsigned char next, prev; /* indices to form a circular LRU */ |
1da177e4 LT |
150 | unsigned char in_use; /* owned by a client, or free? */ |
151 | int age; /* tracked by clients to update local LRU's */ | |
152 | } drm_i810_tex_region_t; | |
153 | ||
154 | typedef struct _drm_i810_sarea { | |
b5e89ed5 DA |
155 | unsigned int ContextState[I810_CTX_SETUP_SIZE]; |
156 | unsigned int BufferState[I810_DEST_SETUP_SIZE]; | |
157 | unsigned int TexState[2][I810_TEX_SETUP_SIZE]; | |
158 | unsigned int dirty; | |
1da177e4 LT |
159 | |
160 | unsigned int nbox; | |
161 | drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS]; | |
162 | ||
163 | /* Maintain an LRU of contiguous regions of texture space. If | |
164 | * you think you own a region of texture memory, and it has an | |
165 | * age different to the one you set, then you are mistaken and | |
166 | * it has been stolen by another client. If global texAge | |
167 | * hasn't changed, there is no need to walk the list. | |
168 | * | |
169 | * These regions can be used as a proxy for the fine-grained | |
170 | * texture information of other clients - by maintaining them | |
171 | * in the same lru which is used to age their own textures, | |
172 | * clients have an approximate lru for the whole of global | |
173 | * texture space, and can make informed decisions as to which | |
174 | * areas to kick out. There is no need to choose whether to | |
175 | * kick out your own texture or someone else's - simply eject | |
b5e89ed5 | 176 | * them all in LRU order. |
1da177e4 | 177 | */ |
b5e89ed5 DA |
178 | |
179 | drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1]; | |
180 | /* Last elt is sentinal */ | |
181 | int texAge; /* last time texture was uploaded */ | |
182 | int last_enqueue; /* last time a buffer was enqueued */ | |
1da177e4 | 183 | int last_dispatch; /* age of the most recently dispatched buffer */ |
b5e89ed5 | 184 | int last_quiescent; /* */ |
1da177e4 LT |
185 | int ctxOwner; /* last context to upload state */ |
186 | ||
187 | int vertex_prim; | |
188 | ||
b5e89ed5 | 189 | int pf_enabled; /* is pageflipping allowed? */ |
1da177e4 | 190 | int pf_active; |
b5e89ed5 | 191 | int pf_current_page; /* which buffer is being displayed? */ |
1da177e4 LT |
192 | } drm_i810_sarea_t; |
193 | ||
194 | /* WARNING: If you change any of these defines, make sure to change the | |
195 | * defines in the Xserver file (xf86drmMga.h) | |
196 | */ | |
197 | ||
198 | /* i810 specific ioctls | |
199 | * The device specific ioctl range is 0x40 to 0x79. | |
200 | */ | |
201 | #define DRM_I810_INIT 0x00 | |
202 | #define DRM_I810_VERTEX 0x01 | |
203 | #define DRM_I810_CLEAR 0x02 | |
204 | #define DRM_I810_FLUSH 0x03 | |
205 | #define DRM_I810_GETAGE 0x04 | |
206 | #define DRM_I810_GETBUF 0x05 | |
207 | #define DRM_I810_SWAP 0x06 | |
208 | #define DRM_I810_COPY 0x07 | |
209 | #define DRM_I810_DOCOPY 0x08 | |
210 | #define DRM_I810_OV0INFO 0x09 | |
211 | #define DRM_I810_FSTATUS 0x0a | |
212 | #define DRM_I810_OV0FLIP 0x0b | |
213 | #define DRM_I810_MC 0x0c | |
214 | #define DRM_I810_RSTATUS 0x0d | |
215 | #define DRM_I810_FLIP 0x0e | |
216 | ||
217 | #define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t) | |
218 | #define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t) | |
219 | #define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t) | |
220 | #define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH) | |
221 | #define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE) | |
222 | #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t) | |
223 | #define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP) | |
224 | #define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t) | |
225 | #define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY) | |
226 | #define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t) | |
227 | #define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS) | |
228 | #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP) | |
229 | #define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t) | |
230 | #define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS) | |
231 | #define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP) | |
232 | ||
233 | typedef struct _drm_i810_clear { | |
234 | int clear_color; | |
235 | int clear_depth; | |
236 | int flags; | |
237 | } drm_i810_clear_t; | |
238 | ||
239 | /* These may be placeholders if we have more cliprects than | |
240 | * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to | |
241 | * false, indicating that the buffer will be dispatched again with a | |
242 | * new set of cliprects. | |
243 | */ | |
244 | typedef struct _drm_i810_vertex { | |
b5e89ed5 | 245 | int idx; /* buffer index */ |
1da177e4 LT |
246 | int used; /* nr bytes in use */ |
247 | int discard; /* client is finished with the buffer? */ | |
248 | } drm_i810_vertex_t; | |
249 | ||
250 | typedef struct _drm_i810_copy_t { | |
b5e89ed5 | 251 | int idx; /* buffer index */ |
1da177e4 LT |
252 | int used; /* nr bytes in use */ |
253 | void *address; /* Address to copy from */ | |
254 | } drm_i810_copy_t; | |
255 | ||
256 | #define PR_TRIANGLES (0x0<<18) | |
257 | #define PR_TRISTRIP_0 (0x1<<18) | |
258 | #define PR_TRISTRIP_1 (0x2<<18) | |
259 | #define PR_TRIFAN (0x3<<18) | |
260 | #define PR_POLYGON (0x4<<18) | |
261 | #define PR_LINES (0x5<<18) | |
262 | #define PR_LINESTRIP (0x6<<18) | |
263 | #define PR_RECTS (0x7<<18) | |
264 | #define PR_MASK (0x7<<18) | |
265 | ||
1da177e4 LT |
266 | typedef struct drm_i810_dma { |
267 | void *virtual; | |
268 | int request_idx; | |
269 | int request_size; | |
270 | int granted; | |
271 | } drm_i810_dma_t; | |
272 | ||
273 | typedef struct _drm_i810_overlay_t { | |
b5e89ed5 | 274 | unsigned int offset; /* Address of the Overlay Regs */ |
1da177e4 LT |
275 | unsigned int physical; |
276 | } drm_i810_overlay_t; | |
277 | ||
278 | typedef struct _drm_i810_mc { | |
b5e89ed5 DA |
279 | int idx; /* buffer index */ |
280 | int used; /* nr bytes in use */ | |
281 | int num_blocks; /* number of GFXBlocks */ | |
282 | int *length; /* List of lengths for GFXBlocks (FUTURE) */ | |
283 | unsigned int last_render; /* Last Render Request */ | |
1da177e4 LT |
284 | } drm_i810_mc_t; |
285 | ||
b5e89ed5 | 286 | #endif /* _I810_DRM_H_ */ |