Commit | Line | Data |
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1da177e4 LT |
1 | /* i810_dma.c -- DMA support for the i810 -*- linux-c -*- |
2 | * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com | |
3 | * | |
4 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
6 | * All Rights Reserved. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: Rickard E. (Rik) Faith <faith@valinux.com> | |
28 | * Jeff Hartmann <jhartmann@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | * | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "i810_drm.h" | |
36 | #include "i810_drv.h" | |
37 | #include <linux/interrupt.h> /* For task queue support */ | |
38 | #include <linux/delay.h> | |
39 | #include <linux/pagemap.h> | |
40 | ||
41 | #define I810_BUF_FREE 2 | |
42 | #define I810_BUF_CLIENT 1 | |
43 | #define I810_BUF_HARDWARE 0 | |
44 | ||
45 | #define I810_BUF_UNMAPPED 0 | |
46 | #define I810_BUF_MAPPED 1 | |
47 | ||
b5e89ed5 | 48 | static drm_buf_t *i810_freelist_get(drm_device_t * dev) |
1da177e4 | 49 | { |
b5e89ed5 DA |
50 | drm_device_dma_t *dma = dev->dma; |
51 | int i; | |
52 | int used; | |
1da177e4 LT |
53 | |
54 | /* Linear search might not be the best solution */ | |
55 | ||
b5e89ed5 DA |
56 | for (i = 0; i < dma->buf_count; i++) { |
57 | drm_buf_t *buf = dma->buflist[i]; | |
58 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 | 59 | /* In use is already a pointer */ |
b5e89ed5 | 60 | used = cmpxchg(buf_priv->in_use, I810_BUF_FREE, |
1da177e4 LT |
61 | I810_BUF_CLIENT); |
62 | if (used == I810_BUF_FREE) { | |
63 | return buf; | |
64 | } | |
65 | } | |
b5e89ed5 | 66 | return NULL; |
1da177e4 LT |
67 | } |
68 | ||
69 | /* This should only be called if the buffer is not sent to the hardware | |
70 | * yet, the hardware updates in use for us once its on the ring buffer. | |
71 | */ | |
72 | ||
b5e89ed5 | 73 | static int i810_freelist_put(drm_device_t * dev, drm_buf_t * buf) |
1da177e4 | 74 | { |
b5e89ed5 DA |
75 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
76 | int used; | |
1da177e4 | 77 | |
b5e89ed5 DA |
78 | /* In use is already a pointer */ |
79 | used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE); | |
1da177e4 | 80 | if (used != I810_BUF_CLIENT) { |
b5e89ed5 DA |
81 | DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx); |
82 | return -EINVAL; | |
1da177e4 LT |
83 | } |
84 | ||
b5e89ed5 | 85 | return 0; |
1da177e4 LT |
86 | } |
87 | ||
c94f7029 | 88 | static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) |
1da177e4 | 89 | { |
b5e89ed5 DA |
90 | drm_file_t *priv = filp->private_data; |
91 | drm_device_t *dev; | |
92 | drm_i810_private_t *dev_priv; | |
93 | drm_buf_t *buf; | |
1da177e4 LT |
94 | drm_i810_buf_priv_t *buf_priv; |
95 | ||
96 | lock_kernel(); | |
b5e89ed5 | 97 | dev = priv->head->dev; |
1da177e4 | 98 | dev_priv = dev->dev_private; |
b5e89ed5 | 99 | buf = dev_priv->mmap_buffer; |
1da177e4 LT |
100 | buf_priv = buf->dev_private; |
101 | ||
102 | vma->vm_flags |= (VM_IO | VM_DONTCOPY); | |
103 | vma->vm_file = filp; | |
104 | ||
b5e89ed5 | 105 | buf_priv->currently_mapped = I810_BUF_MAPPED; |
1da177e4 LT |
106 | unlock_kernel(); |
107 | ||
108 | if (io_remap_pfn_range(vma, vma->vm_start, | |
b5e89ed5 DA |
109 | VM_OFFSET(vma) >> PAGE_SHIFT, |
110 | vma->vm_end - vma->vm_start, vma->vm_page_prot)) | |
111 | return -EAGAIN; | |
1da177e4 LT |
112 | return 0; |
113 | } | |
114 | ||
c94f7029 | 115 | static struct file_operations i810_buffer_fops = { |
b5e89ed5 DA |
116 | .open = drm_open, |
117 | .flush = drm_flush, | |
c94f7029 | 118 | .release = drm_release, |
b5e89ed5 DA |
119 | .ioctl = drm_ioctl, |
120 | .mmap = i810_mmap_buffers, | |
121 | .fasync = drm_fasync, | |
c94f7029 DA |
122 | }; |
123 | ||
b5e89ed5 | 124 | static int i810_map_buffer(drm_buf_t * buf, struct file *filp) |
1da177e4 | 125 | { |
b5e89ed5 DA |
126 | drm_file_t *priv = filp->private_data; |
127 | drm_device_t *dev = priv->head->dev; | |
1da177e4 | 128 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
b5e89ed5 DA |
129 | drm_i810_private_t *dev_priv = dev->dev_private; |
130 | struct file_operations *old_fops; | |
1da177e4 LT |
131 | int retcode = 0; |
132 | ||
b5e89ed5 | 133 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) |
1da177e4 LT |
134 | return -EINVAL; |
135 | ||
b5e89ed5 | 136 | down_write(¤t->mm->mmap_sem); |
1da177e4 LT |
137 | old_fops = filp->f_op; |
138 | filp->f_op = &i810_buffer_fops; | |
139 | dev_priv->mmap_buffer = buf; | |
140 | buf_priv->virtual = (void *)do_mmap(filp, 0, buf->total, | |
b5e89ed5 DA |
141 | PROT_READ | PROT_WRITE, |
142 | MAP_SHARED, buf->bus_address); | |
1da177e4 LT |
143 | dev_priv->mmap_buffer = NULL; |
144 | filp->f_op = old_fops; | |
145 | if ((unsigned long)buf_priv->virtual > -1024UL) { | |
146 | /* Real error */ | |
147 | DRM_ERROR("mmap error\n"); | |
148 | retcode = (signed int)buf_priv->virtual; | |
149 | buf_priv->virtual = NULL; | |
150 | } | |
b5e89ed5 | 151 | up_write(¤t->mm->mmap_sem); |
1da177e4 LT |
152 | |
153 | return retcode; | |
154 | } | |
155 | ||
b5e89ed5 | 156 | static int i810_unmap_buffer(drm_buf_t * buf) |
1da177e4 LT |
157 | { |
158 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
159 | int retcode = 0; | |
160 | ||
161 | if (buf_priv->currently_mapped != I810_BUF_MAPPED) | |
162 | return -EINVAL; | |
163 | ||
164 | down_write(¤t->mm->mmap_sem); | |
165 | retcode = do_munmap(current->mm, | |
166 | (unsigned long)buf_priv->virtual, | |
167 | (size_t) buf->total); | |
168 | up_write(¤t->mm->mmap_sem); | |
169 | ||
b5e89ed5 DA |
170 | buf_priv->currently_mapped = I810_BUF_UNMAPPED; |
171 | buf_priv->virtual = NULL; | |
1da177e4 LT |
172 | |
173 | return retcode; | |
174 | } | |
175 | ||
b5e89ed5 | 176 | static int i810_dma_get_buffer(drm_device_t * dev, drm_i810_dma_t * d, |
1da177e4 LT |
177 | struct file *filp) |
178 | { | |
b5e89ed5 | 179 | drm_buf_t *buf; |
1da177e4 LT |
180 | drm_i810_buf_priv_t *buf_priv; |
181 | int retcode = 0; | |
182 | ||
183 | buf = i810_freelist_get(dev); | |
184 | if (!buf) { | |
185 | retcode = -ENOMEM; | |
b5e89ed5 | 186 | DRM_DEBUG("retcode=%d\n", retcode); |
1da177e4 LT |
187 | return retcode; |
188 | } | |
189 | ||
190 | retcode = i810_map_buffer(buf, filp); | |
191 | if (retcode) { | |
192 | i810_freelist_put(dev, buf); | |
b5e89ed5 | 193 | DRM_ERROR("mapbuf failed, retcode %d\n", retcode); |
1da177e4 LT |
194 | return retcode; |
195 | } | |
196 | buf->filp = filp; | |
197 | buf_priv = buf->dev_private; | |
198 | d->granted = 1; | |
b5e89ed5 DA |
199 | d->request_idx = buf->idx; |
200 | d->request_size = buf->total; | |
201 | d->virtual = buf_priv->virtual; | |
1da177e4 LT |
202 | |
203 | return retcode; | |
204 | } | |
205 | ||
b5e89ed5 | 206 | static int i810_dma_cleanup(drm_device_t * dev) |
1da177e4 LT |
207 | { |
208 | drm_device_dma_t *dma = dev->dma; | |
209 | ||
210 | /* Make sure interrupts are disabled here because the uninstall ioctl | |
211 | * may not have been called from userspace and after dev_private | |
212 | * is freed, it's too late. | |
213 | */ | |
214 | if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled) | |
215 | drm_irq_uninstall(dev); | |
216 | ||
217 | if (dev->dev_private) { | |
218 | int i; | |
b5e89ed5 DA |
219 | drm_i810_private_t *dev_priv = |
220 | (drm_i810_private_t *) dev->dev_private; | |
1da177e4 LT |
221 | |
222 | if (dev_priv->ring.virtual_start) { | |
b5e89ed5 DA |
223 | drm_ioremapfree((void *)dev_priv->ring.virtual_start, |
224 | dev_priv->ring.Size, dev); | |
1da177e4 | 225 | } |
b5e89ed5 DA |
226 | if (dev_priv->hw_status_page) { |
227 | pci_free_consistent(dev->pdev, PAGE_SIZE, | |
1da177e4 LT |
228 | dev_priv->hw_status_page, |
229 | dev_priv->dma_status_page); | |
b5e89ed5 DA |
230 | /* Need to rewrite hardware status page */ |
231 | I810_WRITE(0x02080, 0x1ffff000); | |
1da177e4 | 232 | } |
b5e89ed5 | 233 | drm_free(dev->dev_private, sizeof(drm_i810_private_t), |
1da177e4 | 234 | DRM_MEM_DRIVER); |
b5e89ed5 | 235 | dev->dev_private = NULL; |
1da177e4 LT |
236 | |
237 | for (i = 0; i < dma->buf_count; i++) { | |
b5e89ed5 | 238 | drm_buf_t *buf = dma->buflist[i]; |
1da177e4 | 239 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
b5e89ed5 DA |
240 | if (buf_priv->kernel_virtual && buf->total) |
241 | drm_ioremapfree(buf_priv->kernel_virtual, | |
242 | buf->total, dev); | |
1da177e4 LT |
243 | } |
244 | } | |
b5e89ed5 | 245 | return 0; |
1da177e4 LT |
246 | } |
247 | ||
b5e89ed5 | 248 | static int i810_wait_ring(drm_device_t * dev, int n) |
1da177e4 | 249 | { |
b5e89ed5 DA |
250 | drm_i810_private_t *dev_priv = dev->dev_private; |
251 | drm_i810_ring_buffer_t *ring = &(dev_priv->ring); | |
252 | int iters = 0; | |
253 | unsigned long end; | |
1da177e4 LT |
254 | unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; |
255 | ||
b5e89ed5 DA |
256 | end = jiffies + (HZ * 3); |
257 | while (ring->space < n) { | |
258 | ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; | |
259 | ring->space = ring->head - (ring->tail + 8); | |
260 | if (ring->space < 0) | |
261 | ring->space += ring->Size; | |
262 | ||
1da177e4 | 263 | if (ring->head != last_head) { |
b5e89ed5 | 264 | end = jiffies + (HZ * 3); |
1da177e4 LT |
265 | last_head = ring->head; |
266 | } | |
b5e89ed5 DA |
267 | |
268 | iters++; | |
1da177e4 | 269 | if (time_before(end, jiffies)) { |
b5e89ed5 DA |
270 | DRM_ERROR("space: %d wanted %d\n", ring->space, n); |
271 | DRM_ERROR("lockup\n"); | |
272 | goto out_wait_ring; | |
1da177e4 LT |
273 | } |
274 | udelay(1); | |
275 | } | |
276 | ||
b5e89ed5 DA |
277 | out_wait_ring: |
278 | return iters; | |
1da177e4 LT |
279 | } |
280 | ||
b5e89ed5 | 281 | static void i810_kernel_lost_context(drm_device_t * dev) |
1da177e4 | 282 | { |
b5e89ed5 DA |
283 | drm_i810_private_t *dev_priv = dev->dev_private; |
284 | drm_i810_ring_buffer_t *ring = &(dev_priv->ring); | |
1da177e4 | 285 | |
b5e89ed5 DA |
286 | ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR; |
287 | ring->tail = I810_READ(LP_RING + RING_TAIL); | |
288 | ring->space = ring->head - (ring->tail + 8); | |
289 | if (ring->space < 0) | |
290 | ring->space += ring->Size; | |
1da177e4 LT |
291 | } |
292 | ||
b5e89ed5 | 293 | static int i810_freelist_init(drm_device_t * dev, drm_i810_private_t * dev_priv) |
1da177e4 | 294 | { |
b5e89ed5 DA |
295 | drm_device_dma_t *dma = dev->dma; |
296 | int my_idx = 24; | |
297 | u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx); | |
298 | int i; | |
1da177e4 LT |
299 | |
300 | if (dma->buf_count > 1019) { | |
b5e89ed5 DA |
301 | /* Not enough space in the status page for the freelist */ |
302 | return -EINVAL; | |
1da177e4 LT |
303 | } |
304 | ||
b5e89ed5 DA |
305 | for (i = 0; i < dma->buf_count; i++) { |
306 | drm_buf_t *buf = dma->buflist[i]; | |
307 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 | 308 | |
b5e89ed5 DA |
309 | buf_priv->in_use = hw_status++; |
310 | buf_priv->my_use_idx = my_idx; | |
311 | my_idx += 4; | |
1da177e4 | 312 | |
b5e89ed5 | 313 | *buf_priv->in_use = I810_BUF_FREE; |
1da177e4 LT |
314 | |
315 | buf_priv->kernel_virtual = drm_ioremap(buf->bus_address, | |
b5e89ed5 | 316 | buf->total, dev); |
1da177e4 LT |
317 | } |
318 | return 0; | |
319 | } | |
320 | ||
b5e89ed5 DA |
321 | static int i810_dma_initialize(drm_device_t * dev, |
322 | drm_i810_private_t * dev_priv, | |
323 | drm_i810_init_t * init) | |
1da177e4 LT |
324 | { |
325 | struct list_head *list; | |
326 | ||
b5e89ed5 | 327 | memset(dev_priv, 0, sizeof(drm_i810_private_t)); |
1da177e4 LT |
328 | |
329 | list_for_each(list, &dev->maplist->head) { | |
330 | drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head); | |
331 | if (r_list->map && | |
332 | r_list->map->type == _DRM_SHM && | |
b5e89ed5 | 333 | r_list->map->flags & _DRM_CONTAINS_LOCK) { |
1da177e4 | 334 | dev_priv->sarea_map = r_list->map; |
b5e89ed5 DA |
335 | break; |
336 | } | |
337 | } | |
1da177e4 LT |
338 | if (!dev_priv->sarea_map) { |
339 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
340 | i810_dma_cleanup(dev); |
341 | DRM_ERROR("can not find sarea!\n"); | |
342 | return -EINVAL; | |
1da177e4 LT |
343 | } |
344 | dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset); | |
345 | if (!dev_priv->mmio_map) { | |
346 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
347 | i810_dma_cleanup(dev); |
348 | DRM_ERROR("can not find mmio map!\n"); | |
349 | return -EINVAL; | |
1da177e4 | 350 | } |
d1f2b55a | 351 | dev->agp_buffer_token = init->buffers_offset; |
1da177e4 LT |
352 | dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); |
353 | if (!dev->agp_buffer_map) { | |
354 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
355 | i810_dma_cleanup(dev); |
356 | DRM_ERROR("can not find dma buffer map!\n"); | |
357 | return -EINVAL; | |
1da177e4 LT |
358 | } |
359 | ||
360 | dev_priv->sarea_priv = (drm_i810_sarea_t *) | |
b5e89ed5 | 361 | ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset); |
1da177e4 | 362 | |
b5e89ed5 DA |
363 | dev_priv->ring.Start = init->ring_start; |
364 | dev_priv->ring.End = init->ring_end; | |
365 | dev_priv->ring.Size = init->ring_size; | |
1da177e4 | 366 | |
b5e89ed5 DA |
367 | dev_priv->ring.virtual_start = drm_ioremap(dev->agp->base + |
368 | init->ring_start, | |
369 | init->ring_size, dev); | |
1da177e4 | 370 | |
b5e89ed5 DA |
371 | if (dev_priv->ring.virtual_start == NULL) { |
372 | dev->dev_private = (void *)dev_priv; | |
373 | i810_dma_cleanup(dev); | |
374 | DRM_ERROR("can not ioremap virtual address for" | |
1da177e4 | 375 | " ring buffer\n"); |
b5e89ed5 | 376 | return -ENOMEM; |
1da177e4 LT |
377 | } |
378 | ||
b5e89ed5 | 379 | dev_priv->ring.tail_mask = dev_priv->ring.Size - 1; |
1da177e4 LT |
380 | |
381 | dev_priv->w = init->w; | |
382 | dev_priv->h = init->h; | |
383 | dev_priv->pitch = init->pitch; | |
384 | dev_priv->back_offset = init->back_offset; | |
385 | dev_priv->depth_offset = init->depth_offset; | |
386 | dev_priv->front_offset = init->front_offset; | |
387 | ||
388 | dev_priv->overlay_offset = init->overlay_offset; | |
389 | dev_priv->overlay_physical = init->overlay_physical; | |
390 | ||
391 | dev_priv->front_di1 = init->front_offset | init->pitch_bits; | |
392 | dev_priv->back_di1 = init->back_offset | init->pitch_bits; | |
393 | dev_priv->zi1 = init->depth_offset | init->pitch_bits; | |
394 | ||
b5e89ed5 DA |
395 | /* Program Hardware Status Page */ |
396 | dev_priv->hw_status_page = | |
397 | pci_alloc_consistent(dev->pdev, PAGE_SIZE, | |
398 | &dev_priv->dma_status_page); | |
399 | if (!dev_priv->hw_status_page) { | |
1da177e4 LT |
400 | dev->dev_private = (void *)dev_priv; |
401 | i810_dma_cleanup(dev); | |
402 | DRM_ERROR("Can not allocate hardware status page\n"); | |
403 | return -ENOMEM; | |
404 | } | |
b5e89ed5 DA |
405 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
406 | DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); | |
1da177e4 LT |
407 | |
408 | I810_WRITE(0x02080, dev_priv->dma_status_page); | |
b5e89ed5 | 409 | DRM_DEBUG("Enabled hardware status page\n"); |
1da177e4 | 410 | |
b5e89ed5 | 411 | /* Now we need to init our freelist */ |
1da177e4 LT |
412 | if (i810_freelist_init(dev, dev_priv) != 0) { |
413 | dev->dev_private = (void *)dev_priv; | |
b5e89ed5 DA |
414 | i810_dma_cleanup(dev); |
415 | DRM_ERROR("Not enough space in the status page for" | |
1da177e4 | 416 | " the freelist\n"); |
b5e89ed5 | 417 | return -ENOMEM; |
1da177e4 LT |
418 | } |
419 | dev->dev_private = (void *)dev_priv; | |
420 | ||
b5e89ed5 | 421 | return 0; |
1da177e4 LT |
422 | } |
423 | ||
424 | /* i810 DRM version 1.1 used a smaller init structure with different | |
425 | * ordering of values than is currently used (drm >= 1.2). There is | |
426 | * no defined way to detect the XFree version to correct this problem, | |
427 | * however by checking using this procedure we can detect the correct | |
428 | * thing to do. | |
429 | * | |
430 | * #1 Read the Smaller init structure from user-space | |
431 | * #2 Verify the overlay_physical is a valid physical address, or NULL | |
432 | * If it isn't then we have a v1.1 client. Fix up params. | |
433 | * If it is, then we have a 1.2 client... get the rest of the data. | |
434 | */ | |
b5e89ed5 | 435 | static int i810_dma_init_compat(drm_i810_init_t * init, unsigned long arg) |
1da177e4 LT |
436 | { |
437 | ||
438 | /* Get v1.1 init data */ | |
b5e89ed5 DA |
439 | if (copy_from_user(init, (drm_i810_pre12_init_t __user *) arg, |
440 | sizeof(drm_i810_pre12_init_t))) { | |
1da177e4 LT |
441 | return -EFAULT; |
442 | } | |
443 | ||
444 | if ((!init->overlay_physical) || (init->overlay_physical > 4096)) { | |
445 | ||
446 | /* This is a v1.2 client, just get the v1.2 init data */ | |
447 | DRM_INFO("Using POST v1.2 init.\n"); | |
b5e89ed5 | 448 | if (copy_from_user(init, (drm_i810_init_t __user *) arg, |
1da177e4 LT |
449 | sizeof(drm_i810_init_t))) { |
450 | return -EFAULT; | |
451 | } | |
452 | } else { | |
453 | ||
454 | /* This is a v1.1 client, fix the params */ | |
455 | DRM_INFO("Using PRE v1.2 init.\n"); | |
b5e89ed5 DA |
456 | init->pitch_bits = init->h; |
457 | init->pitch = init->w; | |
458 | init->h = init->overlay_physical; | |
459 | init->w = init->overlay_offset; | |
460 | init->overlay_physical = 0; | |
461 | init->overlay_offset = 0; | |
1da177e4 LT |
462 | } |
463 | ||
464 | return 0; | |
465 | } | |
466 | ||
467 | static int i810_dma_init(struct inode *inode, struct file *filp, | |
b5e89ed5 | 468 | unsigned int cmd, unsigned long arg) |
1da177e4 | 469 | { |
b5e89ed5 DA |
470 | drm_file_t *priv = filp->private_data; |
471 | drm_device_t *dev = priv->head->dev; | |
472 | drm_i810_private_t *dev_priv; | |
473 | drm_i810_init_t init; | |
474 | int retcode = 0; | |
1da177e4 LT |
475 | |
476 | /* Get only the init func */ | |
b5e89ed5 DA |
477 | if (copy_from_user |
478 | (&init, (void __user *)arg, sizeof(drm_i810_init_func_t))) | |
1da177e4 LT |
479 | return -EFAULT; |
480 | ||
b5e89ed5 DA |
481 | switch (init.func) { |
482 | case I810_INIT_DMA: | |
483 | /* This case is for backward compatibility. It | |
484 | * handles XFree 4.1.0 and 4.2.0, and has to | |
485 | * do some parameter checking as described below. | |
486 | * It will someday go away. | |
487 | */ | |
488 | retcode = i810_dma_init_compat(&init, arg); | |
489 | if (retcode) | |
490 | return retcode; | |
491 | ||
492 | dev_priv = drm_alloc(sizeof(drm_i810_private_t), | |
493 | DRM_MEM_DRIVER); | |
494 | if (dev_priv == NULL) | |
495 | return -ENOMEM; | |
496 | retcode = i810_dma_initialize(dev, dev_priv, &init); | |
497 | break; | |
498 | ||
499 | default: | |
500 | case I810_INIT_DMA_1_4: | |
501 | DRM_INFO("Using v1.4 init.\n"); | |
502 | if (copy_from_user(&init, (drm_i810_init_t __user *) arg, | |
503 | sizeof(drm_i810_init_t))) { | |
504 | return -EFAULT; | |
505 | } | |
506 | dev_priv = drm_alloc(sizeof(drm_i810_private_t), | |
507 | DRM_MEM_DRIVER); | |
508 | if (dev_priv == NULL) | |
509 | return -ENOMEM; | |
510 | retcode = i810_dma_initialize(dev, dev_priv, &init); | |
511 | break; | |
512 | ||
513 | case I810_CLEANUP_DMA: | |
514 | DRM_INFO("DMA Cleanup\n"); | |
515 | retcode = i810_dma_cleanup(dev); | |
516 | break; | |
1da177e4 LT |
517 | } |
518 | ||
b5e89ed5 | 519 | return retcode; |
1da177e4 LT |
520 | } |
521 | ||
1da177e4 LT |
522 | /* Most efficient way to verify state for the i810 is as it is |
523 | * emitted. Non-conformant state is silently dropped. | |
524 | * | |
525 | * Use 'volatile' & local var tmp to force the emitted values to be | |
526 | * identical to the verified ones. | |
527 | */ | |
b5e89ed5 DA |
528 | static void i810EmitContextVerified(drm_device_t * dev, |
529 | volatile unsigned int *code) | |
1da177e4 | 530 | { |
b5e89ed5 | 531 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
532 | int i, j = 0; |
533 | unsigned int tmp; | |
534 | RING_LOCALS; | |
535 | ||
b5e89ed5 | 536 | BEGIN_LP_RING(I810_CTX_SETUP_SIZE); |
1da177e4 | 537 | |
b5e89ed5 DA |
538 | OUT_RING(GFX_OP_COLOR_FACTOR); |
539 | OUT_RING(code[I810_CTXREG_CF1]); | |
1da177e4 | 540 | |
b5e89ed5 DA |
541 | OUT_RING(GFX_OP_STIPPLE); |
542 | OUT_RING(code[I810_CTXREG_ST1]); | |
1da177e4 | 543 | |
b5e89ed5 | 544 | for (i = 4; i < I810_CTX_SETUP_SIZE; i++) { |
1da177e4 LT |
545 | tmp = code[i]; |
546 | ||
b5e89ed5 DA |
547 | if ((tmp & (7 << 29)) == (3 << 29) && |
548 | (tmp & (0x1f << 24)) < (0x1d << 24)) { | |
549 | OUT_RING(tmp); | |
1da177e4 | 550 | j++; |
b5e89ed5 DA |
551 | } else |
552 | printk("constext state dropped!!!\n"); | |
1da177e4 LT |
553 | } |
554 | ||
555 | if (j & 1) | |
b5e89ed5 | 556 | OUT_RING(0); |
1da177e4 LT |
557 | |
558 | ADVANCE_LP_RING(); | |
559 | } | |
560 | ||
b5e89ed5 | 561 | static void i810EmitTexVerified(drm_device_t * dev, volatile unsigned int *code) |
1da177e4 | 562 | { |
b5e89ed5 | 563 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
564 | int i, j = 0; |
565 | unsigned int tmp; | |
566 | RING_LOCALS; | |
567 | ||
b5e89ed5 | 568 | BEGIN_LP_RING(I810_TEX_SETUP_SIZE); |
1da177e4 | 569 | |
b5e89ed5 DA |
570 | OUT_RING(GFX_OP_MAP_INFO); |
571 | OUT_RING(code[I810_TEXREG_MI1]); | |
572 | OUT_RING(code[I810_TEXREG_MI2]); | |
573 | OUT_RING(code[I810_TEXREG_MI3]); | |
1da177e4 | 574 | |
b5e89ed5 | 575 | for (i = 4; i < I810_TEX_SETUP_SIZE; i++) { |
1da177e4 LT |
576 | tmp = code[i]; |
577 | ||
b5e89ed5 DA |
578 | if ((tmp & (7 << 29)) == (3 << 29) && |
579 | (tmp & (0x1f << 24)) < (0x1d << 24)) { | |
580 | OUT_RING(tmp); | |
1da177e4 | 581 | j++; |
b5e89ed5 DA |
582 | } else |
583 | printk("texture state dropped!!!\n"); | |
1da177e4 LT |
584 | } |
585 | ||
586 | if (j & 1) | |
b5e89ed5 | 587 | OUT_RING(0); |
1da177e4 LT |
588 | |
589 | ADVANCE_LP_RING(); | |
590 | } | |
591 | ||
1da177e4 LT |
592 | /* Need to do some additional checking when setting the dest buffer. |
593 | */ | |
b5e89ed5 DA |
594 | static void i810EmitDestVerified(drm_device_t * dev, |
595 | volatile unsigned int *code) | |
1da177e4 | 596 | { |
b5e89ed5 | 597 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
598 | unsigned int tmp; |
599 | RING_LOCALS; | |
600 | ||
b5e89ed5 | 601 | BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); |
1da177e4 LT |
602 | |
603 | tmp = code[I810_DESTREG_DI1]; | |
604 | if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) { | |
b5e89ed5 DA |
605 | OUT_RING(CMD_OP_DESTBUFFER_INFO); |
606 | OUT_RING(tmp); | |
1da177e4 | 607 | } else |
b5e89ed5 DA |
608 | DRM_DEBUG("bad di1 %x (allow %x or %x)\n", |
609 | tmp, dev_priv->front_di1, dev_priv->back_di1); | |
1da177e4 LT |
610 | |
611 | /* invarient: | |
612 | */ | |
b5e89ed5 DA |
613 | OUT_RING(CMD_OP_Z_BUFFER_INFO); |
614 | OUT_RING(dev_priv->zi1); | |
1da177e4 | 615 | |
b5e89ed5 DA |
616 | OUT_RING(GFX_OP_DESTBUFFER_VARS); |
617 | OUT_RING(code[I810_DESTREG_DV1]); | |
1da177e4 | 618 | |
b5e89ed5 DA |
619 | OUT_RING(GFX_OP_DRAWRECT_INFO); |
620 | OUT_RING(code[I810_DESTREG_DR1]); | |
621 | OUT_RING(code[I810_DESTREG_DR2]); | |
622 | OUT_RING(code[I810_DESTREG_DR3]); | |
623 | OUT_RING(code[I810_DESTREG_DR4]); | |
624 | OUT_RING(0); | |
1da177e4 LT |
625 | |
626 | ADVANCE_LP_RING(); | |
627 | } | |
628 | ||
b5e89ed5 | 629 | static void i810EmitState(drm_device_t * dev) |
1da177e4 | 630 | { |
b5e89ed5 DA |
631 | drm_i810_private_t *dev_priv = dev->dev_private; |
632 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1da177e4 | 633 | unsigned int dirty = sarea_priv->dirty; |
b5e89ed5 | 634 | |
1da177e4 LT |
635 | DRM_DEBUG("%s %x\n", __FUNCTION__, dirty); |
636 | ||
637 | if (dirty & I810_UPLOAD_BUFFERS) { | |
b5e89ed5 | 638 | i810EmitDestVerified(dev, sarea_priv->BufferState); |
1da177e4 LT |
639 | sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; |
640 | } | |
641 | ||
642 | if (dirty & I810_UPLOAD_CTX) { | |
b5e89ed5 | 643 | i810EmitContextVerified(dev, sarea_priv->ContextState); |
1da177e4 LT |
644 | sarea_priv->dirty &= ~I810_UPLOAD_CTX; |
645 | } | |
646 | ||
647 | if (dirty & I810_UPLOAD_TEX0) { | |
b5e89ed5 | 648 | i810EmitTexVerified(dev, sarea_priv->TexState[0]); |
1da177e4 LT |
649 | sarea_priv->dirty &= ~I810_UPLOAD_TEX0; |
650 | } | |
651 | ||
652 | if (dirty & I810_UPLOAD_TEX1) { | |
b5e89ed5 | 653 | i810EmitTexVerified(dev, sarea_priv->TexState[1]); |
1da177e4 LT |
654 | sarea_priv->dirty &= ~I810_UPLOAD_TEX1; |
655 | } | |
656 | } | |
657 | ||
1da177e4 LT |
658 | /* need to verify |
659 | */ | |
b5e89ed5 DA |
660 | static void i810_dma_dispatch_clear(drm_device_t * dev, int flags, |
661 | unsigned int clear_color, | |
662 | unsigned int clear_zval) | |
1da177e4 | 663 | { |
b5e89ed5 DA |
664 | drm_i810_private_t *dev_priv = dev->dev_private; |
665 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1da177e4 LT |
666 | int nbox = sarea_priv->nbox; |
667 | drm_clip_rect_t *pbox = sarea_priv->boxes; | |
668 | int pitch = dev_priv->pitch; | |
669 | int cpp = 2; | |
670 | int i; | |
671 | RING_LOCALS; | |
b5e89ed5 DA |
672 | |
673 | if (dev_priv->current_page == 1) { | |
674 | unsigned int tmp = flags; | |
675 | ||
1da177e4 | 676 | flags &= ~(I810_FRONT | I810_BACK); |
b5e89ed5 DA |
677 | if (tmp & I810_FRONT) |
678 | flags |= I810_BACK; | |
679 | if (tmp & I810_BACK) | |
680 | flags |= I810_FRONT; | |
1da177e4 LT |
681 | } |
682 | ||
b5e89ed5 | 683 | i810_kernel_lost_context(dev); |
1da177e4 | 684 | |
b5e89ed5 DA |
685 | if (nbox > I810_NR_SAREA_CLIPRECTS) |
686 | nbox = I810_NR_SAREA_CLIPRECTS; | |
1da177e4 | 687 | |
b5e89ed5 | 688 | for (i = 0; i < nbox; i++, pbox++) { |
1da177e4 LT |
689 | unsigned int x = pbox->x1; |
690 | unsigned int y = pbox->y1; | |
691 | unsigned int width = (pbox->x2 - x) * cpp; | |
692 | unsigned int height = pbox->y2 - y; | |
693 | unsigned int start = y * pitch + x * cpp; | |
694 | ||
695 | if (pbox->x1 > pbox->x2 || | |
696 | pbox->y1 > pbox->y2 || | |
b5e89ed5 | 697 | pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) |
1da177e4 LT |
698 | continue; |
699 | ||
b5e89ed5 DA |
700 | if (flags & I810_FRONT) { |
701 | BEGIN_LP_RING(6); | |
702 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); | |
703 | OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); | |
704 | OUT_RING((height << 16) | width); | |
705 | OUT_RING(start); | |
706 | OUT_RING(clear_color); | |
707 | OUT_RING(0); | |
1da177e4 LT |
708 | ADVANCE_LP_RING(); |
709 | } | |
710 | ||
b5e89ed5 DA |
711 | if (flags & I810_BACK) { |
712 | BEGIN_LP_RING(6); | |
713 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); | |
714 | OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); | |
715 | OUT_RING((height << 16) | width); | |
716 | OUT_RING(dev_priv->back_offset + start); | |
717 | OUT_RING(clear_color); | |
718 | OUT_RING(0); | |
1da177e4 LT |
719 | ADVANCE_LP_RING(); |
720 | } | |
721 | ||
b5e89ed5 DA |
722 | if (flags & I810_DEPTH) { |
723 | BEGIN_LP_RING(6); | |
724 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3); | |
725 | OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch); | |
726 | OUT_RING((height << 16) | width); | |
727 | OUT_RING(dev_priv->depth_offset + start); | |
728 | OUT_RING(clear_zval); | |
729 | OUT_RING(0); | |
1da177e4 LT |
730 | ADVANCE_LP_RING(); |
731 | } | |
732 | } | |
733 | } | |
734 | ||
b5e89ed5 | 735 | static void i810_dma_dispatch_swap(drm_device_t * dev) |
1da177e4 | 736 | { |
b5e89ed5 DA |
737 | drm_i810_private_t *dev_priv = dev->dev_private; |
738 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1da177e4 LT |
739 | int nbox = sarea_priv->nbox; |
740 | drm_clip_rect_t *pbox = sarea_priv->boxes; | |
741 | int pitch = dev_priv->pitch; | |
742 | int cpp = 2; | |
743 | int i; | |
744 | RING_LOCALS; | |
745 | ||
746 | DRM_DEBUG("swapbuffers\n"); | |
747 | ||
b5e89ed5 | 748 | i810_kernel_lost_context(dev); |
1da177e4 | 749 | |
b5e89ed5 DA |
750 | if (nbox > I810_NR_SAREA_CLIPRECTS) |
751 | nbox = I810_NR_SAREA_CLIPRECTS; | |
1da177e4 | 752 | |
b5e89ed5 | 753 | for (i = 0; i < nbox; i++, pbox++) { |
1da177e4 LT |
754 | unsigned int w = pbox->x2 - pbox->x1; |
755 | unsigned int h = pbox->y2 - pbox->y1; | |
b5e89ed5 | 756 | unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch; |
1da177e4 LT |
757 | unsigned int start = dst; |
758 | ||
759 | if (pbox->x1 > pbox->x2 || | |
760 | pbox->y1 > pbox->y2 || | |
b5e89ed5 | 761 | pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h) |
1da177e4 LT |
762 | continue; |
763 | ||
b5e89ed5 DA |
764 | BEGIN_LP_RING(6); |
765 | OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4); | |
766 | OUT_RING(pitch | (0xCC << 16)); | |
767 | OUT_RING((h << 16) | (w * cpp)); | |
1da177e4 | 768 | if (dev_priv->current_page == 0) |
b5e89ed5 | 769 | OUT_RING(dev_priv->front_offset + start); |
1da177e4 | 770 | else |
b5e89ed5 DA |
771 | OUT_RING(dev_priv->back_offset + start); |
772 | OUT_RING(pitch); | |
1da177e4 | 773 | if (dev_priv->current_page == 0) |
b5e89ed5 | 774 | OUT_RING(dev_priv->back_offset + start); |
1da177e4 | 775 | else |
b5e89ed5 | 776 | OUT_RING(dev_priv->front_offset + start); |
1da177e4 LT |
777 | ADVANCE_LP_RING(); |
778 | } | |
779 | } | |
780 | ||
b5e89ed5 DA |
781 | static void i810_dma_dispatch_vertex(drm_device_t * dev, |
782 | drm_buf_t * buf, int discard, int used) | |
1da177e4 | 783 | { |
b5e89ed5 | 784 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 | 785 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; |
b5e89ed5 DA |
786 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; |
787 | drm_clip_rect_t *box = sarea_priv->boxes; | |
788 | int nbox = sarea_priv->nbox; | |
1da177e4 LT |
789 | unsigned long address = (unsigned long)buf->bus_address; |
790 | unsigned long start = address - dev->agp->base; | |
791 | int i = 0; | |
b5e89ed5 | 792 | RING_LOCALS; |
1da177e4 | 793 | |
b5e89ed5 | 794 | i810_kernel_lost_context(dev); |
1da177e4 | 795 | |
b5e89ed5 | 796 | if (nbox > I810_NR_SAREA_CLIPRECTS) |
1da177e4 LT |
797 | nbox = I810_NR_SAREA_CLIPRECTS; |
798 | ||
b5e89ed5 | 799 | if (used > 4 * 1024) |
1da177e4 LT |
800 | used = 0; |
801 | ||
802 | if (sarea_priv->dirty) | |
b5e89ed5 | 803 | i810EmitState(dev); |
1da177e4 LT |
804 | |
805 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) { | |
806 | unsigned int prim = (sarea_priv->vertex_prim & PR_MASK); | |
807 | ||
b5e89ed5 DA |
808 | *(u32 *) buf_priv->kernel_virtual = |
809 | ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2))); | |
1da177e4 LT |
810 | |
811 | if (used & 4) { | |
b5e89ed5 | 812 | *(u32 *) ((u32) buf_priv->kernel_virtual + used) = 0; |
1da177e4 LT |
813 | used += 4; |
814 | } | |
815 | ||
816 | i810_unmap_buffer(buf); | |
817 | } | |
818 | ||
819 | if (used) { | |
820 | do { | |
821 | if (i < nbox) { | |
822 | BEGIN_LP_RING(4); | |
b5e89ed5 DA |
823 | OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR | |
824 | SC_ENABLE); | |
825 | OUT_RING(GFX_OP_SCISSOR_INFO); | |
826 | OUT_RING(box[i].x1 | (box[i].y1 << 16)); | |
827 | OUT_RING((box[i].x2 - | |
828 | 1) | ((box[i].y2 - 1) << 16)); | |
1da177e4 LT |
829 | ADVANCE_LP_RING(); |
830 | } | |
831 | ||
832 | BEGIN_LP_RING(4); | |
b5e89ed5 DA |
833 | OUT_RING(CMD_OP_BATCH_BUFFER); |
834 | OUT_RING(start | BB1_PROTECTED); | |
835 | OUT_RING(start + used - 4); | |
836 | OUT_RING(0); | |
1da177e4 LT |
837 | ADVANCE_LP_RING(); |
838 | ||
839 | } while (++i < nbox); | |
840 | } | |
841 | ||
842 | if (discard) { | |
843 | dev_priv->counter++; | |
844 | ||
b5e89ed5 DA |
845 | (void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, |
846 | I810_BUF_HARDWARE); | |
1da177e4 LT |
847 | |
848 | BEGIN_LP_RING(8); | |
b5e89ed5 DA |
849 | OUT_RING(CMD_STORE_DWORD_IDX); |
850 | OUT_RING(20); | |
851 | OUT_RING(dev_priv->counter); | |
852 | OUT_RING(CMD_STORE_DWORD_IDX); | |
853 | OUT_RING(buf_priv->my_use_idx); | |
854 | OUT_RING(I810_BUF_FREE); | |
855 | OUT_RING(CMD_REPORT_HEAD); | |
856 | OUT_RING(0); | |
1da177e4 LT |
857 | ADVANCE_LP_RING(); |
858 | } | |
859 | } | |
860 | ||
b5e89ed5 | 861 | static void i810_dma_dispatch_flip(drm_device_t * dev) |
1da177e4 | 862 | { |
b5e89ed5 | 863 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 LT |
864 | int pitch = dev_priv->pitch; |
865 | RING_LOCALS; | |
866 | ||
b5e89ed5 DA |
867 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
868 | __FUNCTION__, | |
869 | dev_priv->current_page, | |
870 | dev_priv->sarea_priv->pf_current_page); | |
871 | ||
872 | i810_kernel_lost_context(dev); | |
1da177e4 | 873 | |
b5e89ed5 DA |
874 | BEGIN_LP_RING(2); |
875 | OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); | |
876 | OUT_RING(0); | |
1da177e4 LT |
877 | ADVANCE_LP_RING(); |
878 | ||
b5e89ed5 | 879 | BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2); |
1da177e4 LT |
880 | /* On i815 at least ASYNC is buggy */ |
881 | /* pitch<<5 is from 11.2.8 p158, | |
882 | its the pitch / 8 then left shifted 8, | |
883 | so (pitch >> 3) << 8 */ | |
b5e89ed5 DA |
884 | OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ ); |
885 | if (dev_priv->current_page == 0) { | |
886 | OUT_RING(dev_priv->back_offset); | |
1da177e4 LT |
887 | dev_priv->current_page = 1; |
888 | } else { | |
b5e89ed5 | 889 | OUT_RING(dev_priv->front_offset); |
1da177e4 LT |
890 | dev_priv->current_page = 0; |
891 | } | |
892 | OUT_RING(0); | |
893 | ADVANCE_LP_RING(); | |
894 | ||
895 | BEGIN_LP_RING(2); | |
b5e89ed5 DA |
896 | OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP); |
897 | OUT_RING(0); | |
1da177e4 LT |
898 | ADVANCE_LP_RING(); |
899 | ||
900 | /* Increment the frame counter. The client-side 3D driver must | |
901 | * throttle the framerate by waiting for this value before | |
902 | * performing the swapbuffer ioctl. | |
903 | */ | |
904 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
905 | ||
906 | } | |
907 | ||
b5e89ed5 | 908 | static void i810_dma_quiescent(drm_device_t * dev) |
1da177e4 | 909 | { |
b5e89ed5 DA |
910 | drm_i810_private_t *dev_priv = dev->dev_private; |
911 | RING_LOCALS; | |
1da177e4 LT |
912 | |
913 | /* printk("%s\n", __FUNCTION__); */ | |
914 | ||
b5e89ed5 | 915 | i810_kernel_lost_context(dev); |
1da177e4 | 916 | |
b5e89ed5 DA |
917 | BEGIN_LP_RING(4); |
918 | OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); | |
919 | OUT_RING(CMD_REPORT_HEAD); | |
920 | OUT_RING(0); | |
921 | OUT_RING(0); | |
922 | ADVANCE_LP_RING(); | |
1da177e4 | 923 | |
b5e89ed5 | 924 | i810_wait_ring(dev, dev_priv->ring.Size - 8); |
1da177e4 LT |
925 | } |
926 | ||
b5e89ed5 | 927 | static int i810_flush_queue(drm_device_t * dev) |
1da177e4 | 928 | { |
b5e89ed5 | 929 | drm_i810_private_t *dev_priv = dev->dev_private; |
1da177e4 | 930 | drm_device_dma_t *dma = dev->dma; |
b5e89ed5 DA |
931 | int i, ret = 0; |
932 | RING_LOCALS; | |
933 | ||
1da177e4 LT |
934 | /* printk("%s\n", __FUNCTION__); */ |
935 | ||
b5e89ed5 | 936 | i810_kernel_lost_context(dev); |
1da177e4 | 937 | |
b5e89ed5 DA |
938 | BEGIN_LP_RING(2); |
939 | OUT_RING(CMD_REPORT_HEAD); | |
940 | OUT_RING(0); | |
941 | ADVANCE_LP_RING(); | |
1da177e4 | 942 | |
b5e89ed5 | 943 | i810_wait_ring(dev, dev_priv->ring.Size - 8); |
1da177e4 | 944 | |
b5e89ed5 DA |
945 | for (i = 0; i < dma->buf_count; i++) { |
946 | drm_buf_t *buf = dma->buflist[i]; | |
947 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 LT |
948 | |
949 | int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE, | |
950 | I810_BUF_FREE); | |
951 | ||
952 | if (used == I810_BUF_HARDWARE) | |
953 | DRM_DEBUG("reclaimed from HARDWARE\n"); | |
954 | if (used == I810_BUF_CLIENT) | |
955 | DRM_DEBUG("still on client\n"); | |
956 | } | |
957 | ||
b5e89ed5 | 958 | return ret; |
1da177e4 LT |
959 | } |
960 | ||
961 | /* Must be called with the lock held */ | |
b5e89ed5 | 962 | void i810_reclaim_buffers(drm_device_t * dev, struct file *filp) |
1da177e4 LT |
963 | { |
964 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 | 965 | int i; |
1da177e4 | 966 | |
b5e89ed5 DA |
967 | if (!dma) |
968 | return; | |
969 | if (!dev->dev_private) | |
970 | return; | |
971 | if (!dma->buflist) | |
972 | return; | |
1da177e4 | 973 | |
b5e89ed5 | 974 | i810_flush_queue(dev); |
1da177e4 LT |
975 | |
976 | for (i = 0; i < dma->buf_count; i++) { | |
b5e89ed5 DA |
977 | drm_buf_t *buf = dma->buflist[i]; |
978 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1da177e4 LT |
979 | |
980 | if (buf->filp == filp && buf_priv) { | |
981 | int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, | |
982 | I810_BUF_FREE); | |
983 | ||
984 | if (used == I810_BUF_CLIENT) | |
985 | DRM_DEBUG("reclaimed from client\n"); | |
986 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) | |
b5e89ed5 | 987 | buf_priv->currently_mapped = I810_BUF_UNMAPPED; |
1da177e4 LT |
988 | } |
989 | } | |
990 | } | |
991 | ||
c94f7029 DA |
992 | static int i810_flush_ioctl(struct inode *inode, struct file *filp, |
993 | unsigned int cmd, unsigned long arg) | |
1da177e4 | 994 | { |
b5e89ed5 DA |
995 | drm_file_t *priv = filp->private_data; |
996 | drm_device_t *dev = priv->head->dev; | |
1da177e4 LT |
997 | |
998 | LOCK_TEST_WITH_RETURN(dev, filp); | |
999 | ||
b5e89ed5 DA |
1000 | i810_flush_queue(dev); |
1001 | return 0; | |
1da177e4 LT |
1002 | } |
1003 | ||
1da177e4 | 1004 | static int i810_dma_vertex(struct inode *inode, struct file *filp, |
b5e89ed5 | 1005 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1006 | { |
1007 | drm_file_t *priv = filp->private_data; | |
1008 | drm_device_t *dev = priv->head->dev; | |
1009 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 DA |
1010 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1011 | u32 *hw_status = dev_priv->hw_status_page; | |
1012 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
1013 | dev_priv->sarea_priv; | |
1da177e4 LT |
1014 | drm_i810_vertex_t vertex; |
1015 | ||
b5e89ed5 DA |
1016 | if (copy_from_user |
1017 | (&vertex, (drm_i810_vertex_t __user *) arg, sizeof(vertex))) | |
1da177e4 LT |
1018 | return -EFAULT; |
1019 | ||
1020 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1021 | ||
1022 | DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n", | |
1023 | vertex.idx, vertex.used, vertex.discard); | |
1024 | ||
b5e89ed5 | 1025 | if (vertex.idx < 0 || vertex.idx > dma->buf_count) |
1da177e4 LT |
1026 | return -EINVAL; |
1027 | ||
b5e89ed5 DA |
1028 | i810_dma_dispatch_vertex(dev, |
1029 | dma->buflist[vertex.idx], | |
1030 | vertex.discard, vertex.used); | |
1da177e4 | 1031 | |
b5e89ed5 | 1032 | atomic_add(vertex.used, &dev->counts[_DRM_STAT_SECONDARY]); |
1da177e4 | 1033 | atomic_inc(&dev->counts[_DRM_STAT_DMA]); |
b5e89ed5 DA |
1034 | sarea_priv->last_enqueue = dev_priv->counter - 1; |
1035 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
1da177e4 LT |
1036 | |
1037 | return 0; | |
1038 | } | |
1039 | ||
1da177e4 | 1040 | static int i810_clear_bufs(struct inode *inode, struct file *filp, |
b5e89ed5 | 1041 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1042 | { |
1043 | drm_file_t *priv = filp->private_data; | |
1044 | drm_device_t *dev = priv->head->dev; | |
1045 | drm_i810_clear_t clear; | |
1046 | ||
b5e89ed5 DA |
1047 | if (copy_from_user |
1048 | (&clear, (drm_i810_clear_t __user *) arg, sizeof(clear))) | |
1da177e4 LT |
1049 | return -EFAULT; |
1050 | ||
1051 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1052 | ||
b5e89ed5 DA |
1053 | /* GH: Someone's doing nasty things... */ |
1054 | if (!dev->dev_private) { | |
1055 | return -EINVAL; | |
1056 | } | |
1da177e4 | 1057 | |
b5e89ed5 DA |
1058 | i810_dma_dispatch_clear(dev, clear.flags, |
1059 | clear.clear_color, clear.clear_depth); | |
1060 | return 0; | |
1da177e4 LT |
1061 | } |
1062 | ||
1063 | static int i810_swap_bufs(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1064 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1065 | { |
1066 | drm_file_t *priv = filp->private_data; | |
1067 | drm_device_t *dev = priv->head->dev; | |
1068 | ||
1069 | DRM_DEBUG("i810_swap_bufs\n"); | |
1070 | ||
1071 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1072 | ||
b5e89ed5 DA |
1073 | i810_dma_dispatch_swap(dev); |
1074 | return 0; | |
1da177e4 LT |
1075 | } |
1076 | ||
1077 | static int i810_getage(struct inode *inode, struct file *filp, unsigned int cmd, | |
b5e89ed5 | 1078 | unsigned long arg) |
1da177e4 | 1079 | { |
b5e89ed5 DA |
1080 | drm_file_t *priv = filp->private_data; |
1081 | drm_device_t *dev = priv->head->dev; | |
1082 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; | |
1083 | u32 *hw_status = dev_priv->hw_status_page; | |
1084 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
1085 | dev_priv->sarea_priv; | |
1086 | ||
1087 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
1da177e4 LT |
1088 | return 0; |
1089 | } | |
1090 | ||
1091 | static int i810_getbuf(struct inode *inode, struct file *filp, unsigned int cmd, | |
b5e89ed5 | 1092 | unsigned long arg) |
1da177e4 | 1093 | { |
b5e89ed5 DA |
1094 | drm_file_t *priv = filp->private_data; |
1095 | drm_device_t *dev = priv->head->dev; | |
1096 | int retcode = 0; | |
1097 | drm_i810_dma_t d; | |
1098 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; | |
1099 | u32 *hw_status = dev_priv->hw_status_page; | |
1100 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
1101 | dev_priv->sarea_priv; | |
1102 | ||
1103 | if (copy_from_user(&d, (drm_i810_dma_t __user *) arg, sizeof(d))) | |
1da177e4 LT |
1104 | return -EFAULT; |
1105 | ||
1106 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1107 | ||
1108 | d.granted = 0; | |
1109 | ||
1110 | retcode = i810_dma_get_buffer(dev, &d, filp); | |
1111 | ||
1112 | DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n", | |
1113 | current->pid, retcode, d.granted); | |
1114 | ||
b5e89ed5 | 1115 | if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d))) |
1da177e4 | 1116 | return -EFAULT; |
b5e89ed5 | 1117 | sarea_priv->last_dispatch = (int)hw_status[5]; |
1da177e4 LT |
1118 | |
1119 | return retcode; | |
1120 | } | |
1121 | ||
1122 | static int i810_copybuf(struct inode *inode, | |
b5e89ed5 | 1123 | struct file *filp, unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1124 | { |
1125 | /* Never copy - 2.4.x doesn't need it */ | |
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | static int i810_docopy(struct inode *inode, struct file *filp, unsigned int cmd, | |
b5e89ed5 | 1130 | unsigned long arg) |
1da177e4 LT |
1131 | { |
1132 | /* Never copy - 2.4.x doesn't need it */ | |
1133 | return 0; | |
1134 | } | |
1135 | ||
b5e89ed5 DA |
1136 | static void i810_dma_dispatch_mc(drm_device_t * dev, drm_buf_t * buf, int used, |
1137 | unsigned int last_render) | |
1da177e4 LT |
1138 | { |
1139 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1140 | drm_i810_buf_priv_t *buf_priv = buf->dev_private; | |
1141 | drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1142 | unsigned long address = (unsigned long)buf->bus_address; | |
1143 | unsigned long start = address - dev->agp->base; | |
1144 | int u; | |
1145 | RING_LOCALS; | |
1146 | ||
1147 | i810_kernel_lost_context(dev); | |
1148 | ||
b5e89ed5 | 1149 | u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE); |
1da177e4 LT |
1150 | if (u != I810_BUF_CLIENT) { |
1151 | DRM_DEBUG("MC found buffer that isn't mine!\n"); | |
1152 | } | |
1153 | ||
b5e89ed5 | 1154 | if (used > 4 * 1024) |
1da177e4 LT |
1155 | used = 0; |
1156 | ||
1157 | sarea_priv->dirty = 0x7f; | |
1158 | ||
b5e89ed5 | 1159 | DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used); |
1da177e4 LT |
1160 | |
1161 | dev_priv->counter++; | |
1162 | DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter); | |
1163 | DRM_DEBUG("i810_dma_dispatch_mc\n"); | |
1164 | DRM_DEBUG("start : %lx\n", start); | |
1165 | DRM_DEBUG("used : %d\n", used); | |
1166 | DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4); | |
1167 | ||
1168 | if (buf_priv->currently_mapped == I810_BUF_MAPPED) { | |
1169 | if (used & 4) { | |
b5e89ed5 | 1170 | *(u32 *) ((u32) buf_priv->virtual + used) = 0; |
1da177e4 LT |
1171 | used += 4; |
1172 | } | |
1173 | ||
1174 | i810_unmap_buffer(buf); | |
1175 | } | |
1176 | BEGIN_LP_RING(4); | |
b5e89ed5 DA |
1177 | OUT_RING(CMD_OP_BATCH_BUFFER); |
1178 | OUT_RING(start | BB1_PROTECTED); | |
1179 | OUT_RING(start + used - 4); | |
1180 | OUT_RING(0); | |
1da177e4 LT |
1181 | ADVANCE_LP_RING(); |
1182 | ||
1da177e4 | 1183 | BEGIN_LP_RING(8); |
b5e89ed5 DA |
1184 | OUT_RING(CMD_STORE_DWORD_IDX); |
1185 | OUT_RING(buf_priv->my_use_idx); | |
1186 | OUT_RING(I810_BUF_FREE); | |
1187 | OUT_RING(0); | |
1188 | ||
1189 | OUT_RING(CMD_STORE_DWORD_IDX); | |
1190 | OUT_RING(16); | |
1191 | OUT_RING(last_render); | |
1192 | OUT_RING(0); | |
1da177e4 LT |
1193 | ADVANCE_LP_RING(); |
1194 | } | |
1195 | ||
1196 | static int i810_dma_mc(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1197 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1198 | { |
1199 | drm_file_t *priv = filp->private_data; | |
1200 | drm_device_t *dev = priv->head->dev; | |
1201 | drm_device_dma_t *dma = dev->dma; | |
b5e89ed5 | 1202 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1203 | u32 *hw_status = dev_priv->hw_status_page; |
1204 | drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) | |
b5e89ed5 | 1205 | dev_priv->sarea_priv; |
1da177e4 LT |
1206 | drm_i810_mc_t mc; |
1207 | ||
b5e89ed5 | 1208 | if (copy_from_user(&mc, (drm_i810_mc_t __user *) arg, sizeof(mc))) |
1da177e4 LT |
1209 | return -EFAULT; |
1210 | ||
1211 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1212 | ||
1213 | if (mc.idx >= dma->buf_count || mc.idx < 0) | |
1214 | return -EINVAL; | |
1215 | ||
1216 | i810_dma_dispatch_mc(dev, dma->buflist[mc.idx], mc.used, | |
b5e89ed5 | 1217 | mc.last_render); |
1da177e4 LT |
1218 | |
1219 | atomic_add(mc.used, &dev->counts[_DRM_STAT_SECONDARY]); | |
1220 | atomic_inc(&dev->counts[_DRM_STAT_DMA]); | |
b5e89ed5 DA |
1221 | sarea_priv->last_enqueue = dev_priv->counter - 1; |
1222 | sarea_priv->last_dispatch = (int)hw_status[5]; | |
1da177e4 LT |
1223 | |
1224 | return 0; | |
1225 | } | |
1226 | ||
1227 | static int i810_rstatus(struct inode *inode, struct file *filp, | |
1228 | unsigned int cmd, unsigned long arg) | |
1229 | { | |
1230 | drm_file_t *priv = filp->private_data; | |
1231 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1232 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 | 1233 | |
b5e89ed5 | 1234 | return (int)(((u32 *) (dev_priv->hw_status_page))[4]); |
1da177e4 LT |
1235 | } |
1236 | ||
1237 | static int i810_ov0_info(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1238 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1239 | { |
1240 | drm_file_t *priv = filp->private_data; | |
1241 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1242 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1243 | drm_i810_overlay_t data; |
1244 | ||
1245 | data.offset = dev_priv->overlay_offset; | |
1246 | data.physical = dev_priv->overlay_physical; | |
b5e89ed5 DA |
1247 | if (copy_to_user |
1248 | ((drm_i810_overlay_t __user *) arg, &data, sizeof(data))) | |
1da177e4 LT |
1249 | return -EFAULT; |
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | static int i810_fstatus(struct inode *inode, struct file *filp, | |
1254 | unsigned int cmd, unsigned long arg) | |
1255 | { | |
1256 | drm_file_t *priv = filp->private_data; | |
1257 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1258 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1259 | |
1260 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1261 | ||
1262 | return I810_READ(0x30008); | |
1263 | } | |
1264 | ||
1265 | static int i810_ov0_flip(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1266 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1267 | { |
1268 | drm_file_t *priv = filp->private_data; | |
1269 | drm_device_t *dev = priv->head->dev; | |
b5e89ed5 | 1270 | drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private; |
1da177e4 LT |
1271 | |
1272 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1273 | ||
1274 | //Tell the overlay to update | |
b5e89ed5 | 1275 | I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000); |
1da177e4 LT |
1276 | |
1277 | return 0; | |
1278 | } | |
1279 | ||
1da177e4 | 1280 | /* Not sure why this isn't set all the time: |
b5e89ed5 DA |
1281 | */ |
1282 | static void i810_do_init_pageflip(drm_device_t * dev) | |
1da177e4 LT |
1283 | { |
1284 | drm_i810_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1285 | |
1da177e4 LT |
1286 | DRM_DEBUG("%s\n", __FUNCTION__); |
1287 | dev_priv->page_flipping = 1; | |
1288 | dev_priv->current_page = 0; | |
1289 | dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; | |
1290 | } | |
1291 | ||
b5e89ed5 | 1292 | static int i810_do_cleanup_pageflip(drm_device_t * dev) |
1da177e4 LT |
1293 | { |
1294 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1295 | ||
1296 | DRM_DEBUG("%s\n", __FUNCTION__); | |
1297 | if (dev_priv->current_page != 0) | |
b5e89ed5 | 1298 | i810_dma_dispatch_flip(dev); |
1da177e4 LT |
1299 | |
1300 | dev_priv->page_flipping = 0; | |
1301 | return 0; | |
1302 | } | |
1303 | ||
1304 | static int i810_flip_bufs(struct inode *inode, struct file *filp, | |
b5e89ed5 | 1305 | unsigned int cmd, unsigned long arg) |
1da177e4 LT |
1306 | { |
1307 | drm_file_t *priv = filp->private_data; | |
1308 | drm_device_t *dev = priv->head->dev; | |
1309 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1310 | ||
1311 | DRM_DEBUG("%s\n", __FUNCTION__); | |
1312 | ||
1313 | LOCK_TEST_WITH_RETURN(dev, filp); | |
1314 | ||
b5e89ed5 DA |
1315 | if (!dev_priv->page_flipping) |
1316 | i810_do_init_pageflip(dev); | |
1da177e4 | 1317 | |
b5e89ed5 DA |
1318 | i810_dma_dispatch_flip(dev); |
1319 | return 0; | |
1da177e4 LT |
1320 | } |
1321 | ||
b5e89ed5 | 1322 | void i810_driver_pretakedown(drm_device_t * dev) |
1da177e4 | 1323 | { |
b5e89ed5 | 1324 | i810_dma_cleanup(dev); |
1da177e4 LT |
1325 | } |
1326 | ||
b5e89ed5 | 1327 | void i810_driver_prerelease(drm_device_t * dev, DRMFILE filp) |
1da177e4 LT |
1328 | { |
1329 | if (dev->dev_private) { | |
1330 | drm_i810_private_t *dev_priv = dev->dev_private; | |
1331 | if (dev_priv->page_flipping) { | |
1332 | i810_do_cleanup_pageflip(dev); | |
1333 | } | |
1334 | } | |
1335 | } | |
1336 | ||
b5e89ed5 | 1337 | void i810_driver_release(drm_device_t * dev, struct file *filp) |
1da177e4 LT |
1338 | { |
1339 | i810_reclaim_buffers(dev, filp); | |
1340 | } | |
1341 | ||
b5e89ed5 | 1342 | int i810_driver_dma_quiescent(drm_device_t * dev) |
1da177e4 | 1343 | { |
b5e89ed5 | 1344 | i810_dma_quiescent(dev); |
1da177e4 LT |
1345 | return 0; |
1346 | } | |
1347 | ||
1348 | drm_ioctl_desc_t i810_ioctls[] = { | |
b5e89ed5 DA |
1349 | [DRM_IOCTL_NR(DRM_I810_INIT)] = {i810_dma_init, 1, 1} |
1350 | , | |
1351 | [DRM_IOCTL_NR(DRM_I810_VERTEX)] = {i810_dma_vertex, 1, 0} | |
1352 | , | |
1353 | [DRM_IOCTL_NR(DRM_I810_CLEAR)] = {i810_clear_bufs, 1, 0} | |
1354 | , | |
1355 | [DRM_IOCTL_NR(DRM_I810_FLUSH)] = {i810_flush_ioctl, 1, 0} | |
1356 | , | |
1357 | [DRM_IOCTL_NR(DRM_I810_GETAGE)] = {i810_getage, 1, 0} | |
1358 | , | |
1359 | [DRM_IOCTL_NR(DRM_I810_GETBUF)] = {i810_getbuf, 1, 0} | |
1360 | , | |
1361 | [DRM_IOCTL_NR(DRM_I810_SWAP)] = {i810_swap_bufs, 1, 0} | |
1362 | , | |
1363 | [DRM_IOCTL_NR(DRM_I810_COPY)] = {i810_copybuf, 1, 0} | |
1364 | , | |
1365 | [DRM_IOCTL_NR(DRM_I810_DOCOPY)] = {i810_docopy, 1, 0} | |
1366 | , | |
1367 | [DRM_IOCTL_NR(DRM_I810_OV0INFO)] = {i810_ov0_info, 1, 0} | |
1368 | , | |
1369 | [DRM_IOCTL_NR(DRM_I810_FSTATUS)] = {i810_fstatus, 1, 0} | |
1370 | , | |
1371 | [DRM_IOCTL_NR(DRM_I810_OV0FLIP)] = {i810_ov0_flip, 1, 0} | |
1372 | , | |
1373 | [DRM_IOCTL_NR(DRM_I810_MC)] = {i810_dma_mc, 1, 1} | |
1374 | , | |
1375 | [DRM_IOCTL_NR(DRM_I810_RSTATUS)] = {i810_rstatus, 1, 0} | |
1376 | , | |
1377 | [DRM_IOCTL_NR(DRM_I810_FLIP)] = {i810_flip_bufs, 1, 0} | |
1da177e4 LT |
1378 | }; |
1379 | ||
1380 | int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls); | |
cda17380 DA |
1381 | |
1382 | /** | |
1383 | * Determine if the device really is AGP or not. | |
1384 | * | |
1385 | * All Intel graphics chipsets are treated as AGP, even if they are really | |
1386 | * PCI-e. | |
1387 | * | |
1388 | * \param dev The device to be tested. | |
1389 | * | |
1390 | * \returns | |
1391 | * A value of 1 is always retured to indictate every i810 is AGP. | |
1392 | */ | |
1393 | int i810_driver_device_is_agp(drm_device_t * dev) | |
1394 | { | |
1395 | return 1; | |
1396 | } |