Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file drm.h |
1da177e4 | 3 | * Header for the Direct Rendering Manager |
b5e89ed5 | 4 | * |
1da177e4 LT |
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
6 | * | |
7 | * \par Acknowledgments: | |
8 | * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
14 | * All rights reserved. | |
15 | * | |
16 | * Permission is hereby granted, free of charge, to any person obtaining a | |
17 | * copy of this software and associated documentation files (the "Software"), | |
18 | * to deal in the Software without restriction, including without limitation | |
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
20 | * and/or sell copies of the Software, and to permit persons to whom the | |
21 | * Software is furnished to do so, subject to the following conditions: | |
22 | * | |
23 | * The above copyright notice and this permission notice (including the next | |
24 | * paragraph) shall be included in all copies or substantial portions of the | |
25 | * Software. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
33 | * OTHER DEALINGS IN THE SOFTWARE. | |
34 | */ | |
35 | ||
1da177e4 LT |
36 | #ifndef _DRM_H_ |
37 | #define _DRM_H_ | |
38 | ||
39 | #if defined(__linux__) | |
850eb83a | 40 | #if defined(__KERNEL__) |
850eb83a | 41 | #endif |
1da177e4 LT |
42 | #include <asm/ioctl.h> /* For _IO* macros */ |
43 | #define DRM_IOCTL_NR(n) _IOC_NR(n) | |
44 | #define DRM_IOC_VOID _IOC_NONE | |
45 | #define DRM_IOC_READ _IOC_READ | |
46 | #define DRM_IOC_WRITE _IOC_WRITE | |
47 | #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE | |
48 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | |
49 | #elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) | |
50 | #if defined(__FreeBSD__) && defined(IN_MODULE) | |
51 | /* Prevent name collision when including sys/ioccom.h */ | |
52 | #undef ioctl | |
53 | #include <sys/ioccom.h> | |
54 | #define ioctl(a,b,c) xf86ioctl(a,b,c) | |
55 | #else | |
56 | #include <sys/ioccom.h> | |
b5e89ed5 | 57 | #endif /* __FreeBSD__ && xf86ioctl */ |
1da177e4 LT |
58 | #define DRM_IOCTL_NR(n) ((n) & 0xff) |
59 | #define DRM_IOC_VOID IOC_VOID | |
60 | #define DRM_IOC_READ IOC_OUT | |
61 | #define DRM_IOC_WRITE IOC_IN | |
62 | #define DRM_IOC_READWRITE IOC_INOUT | |
63 | #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) | |
64 | #endif | |
65 | ||
1da177e4 LT |
66 | #define DRM_MAJOR 226 |
67 | #define DRM_MAX_MINOR 15 | |
b589ee59 | 68 | |
1da177e4 LT |
69 | #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
70 | #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ | |
71 | #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ | |
72 | #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ | |
73 | ||
b3a80a22 DA |
74 | #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ |
75 | #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ | |
1da177e4 LT |
76 | #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) |
77 | #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) | |
78 | #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) | |
79 | ||
b5e89ed5 DA |
80 | typedef unsigned int drm_handle_t; |
81 | typedef unsigned int drm_context_t; | |
82 | typedef unsigned int drm_drawable_t; | |
83 | typedef unsigned int drm_magic_t; | |
1da177e4 LT |
84 | |
85 | /** | |
86 | * Cliprect. | |
b5e89ed5 | 87 | * |
1da177e4 LT |
88 | * \warning: If you change this structure, make sure you change |
89 | * XF86DRIClipRectRec in the server as well | |
90 | * | |
91 | * \note KW: Actually it's illegal to change either for | |
92 | * backwards-compatibility reasons. | |
93 | */ | |
c60ce623 | 94 | struct drm_clip_rect { |
b5e89ed5 DA |
95 | unsigned short x1; |
96 | unsigned short y1; | |
97 | unsigned short x2; | |
98 | unsigned short y2; | |
c60ce623 | 99 | }; |
1da177e4 | 100 | |
bea5679f MCA |
101 | /** |
102 | * Drawable information. | |
103 | */ | |
c60ce623 | 104 | struct drm_drawable_info { |
bea5679f | 105 | unsigned int num_rects; |
c60ce623 DA |
106 | struct drm_clip_rect *rects; |
107 | }; | |
bea5679f | 108 | |
1da177e4 LT |
109 | /** |
110 | * Texture region, | |
111 | */ | |
c60ce623 | 112 | struct drm_tex_region { |
b5e89ed5 DA |
113 | unsigned char next; |
114 | unsigned char prev; | |
115 | unsigned char in_use; | |
116 | unsigned char padding; | |
117 | unsigned int age; | |
c60ce623 | 118 | }; |
1da177e4 LT |
119 | |
120 | /** | |
121 | * Hardware lock. | |
122 | * | |
123 | * The lock structure is a simple cache-line aligned integer. To avoid | |
124 | * processor bus contention on a multiprocessor system, there should not be any | |
125 | * other data stored in the same cache line. | |
126 | */ | |
c60ce623 | 127 | struct drm_hw_lock { |
1da177e4 | 128 | __volatile__ unsigned int lock; /**< lock variable */ |
b5e89ed5 | 129 | char padding[60]; /**< Pad to cache line */ |
c60ce623 | 130 | }; |
1da177e4 | 131 | |
1da177e4 LT |
132 | /** |
133 | * DRM_IOCTL_VERSION ioctl argument type. | |
b5e89ed5 | 134 | * |
1da177e4 LT |
135 | * \sa drmGetVersion(). |
136 | */ | |
c60ce623 | 137 | struct drm_version { |
b5e89ed5 DA |
138 | int version_major; /**< Major version */ |
139 | int version_minor; /**< Minor version */ | |
140 | int version_patchlevel; /**< Patch level */ | |
1da177e4 | 141 | size_t name_len; /**< Length of name buffer */ |
b5e89ed5 | 142 | char __user *name; /**< Name of driver */ |
1da177e4 | 143 | size_t date_len; /**< Length of date buffer */ |
b5e89ed5 | 144 | char __user *date; /**< User-space buffer to hold date */ |
1da177e4 | 145 | size_t desc_len; /**< Length of desc buffer */ |
b5e89ed5 | 146 | char __user *desc; /**< User-space buffer to hold desc */ |
c60ce623 | 147 | }; |
1da177e4 | 148 | |
1da177e4 LT |
149 | /** |
150 | * DRM_IOCTL_GET_UNIQUE ioctl argument type. | |
151 | * | |
152 | * \sa drmGetBusid() and drmSetBusId(). | |
153 | */ | |
c60ce623 | 154 | struct drm_unique { |
1da177e4 | 155 | size_t unique_len; /**< Length of unique */ |
b5e89ed5 | 156 | char __user *unique; /**< Unique name for driver instantiation */ |
c60ce623 | 157 | }; |
1da177e4 | 158 | |
c60ce623 | 159 | struct drm_list { |
b5e89ed5 | 160 | int count; /**< Length of user-space structures */ |
c60ce623 DA |
161 | struct drm_version __user *version; |
162 | }; | |
1da177e4 | 163 | |
c60ce623 | 164 | struct drm_block { |
b5e89ed5 | 165 | int unused; |
c60ce623 | 166 | }; |
1da177e4 | 167 | |
1da177e4 LT |
168 | /** |
169 | * DRM_IOCTL_CONTROL ioctl argument type. | |
170 | * | |
171 | * \sa drmCtlInstHandler() and drmCtlUninstHandler(). | |
172 | */ | |
c60ce623 | 173 | struct drm_control { |
1da177e4 LT |
174 | enum { |
175 | DRM_ADD_COMMAND, | |
176 | DRM_RM_COMMAND, | |
177 | DRM_INST_HANDLER, | |
178 | DRM_UNINST_HANDLER | |
b5e89ed5 DA |
179 | } func; |
180 | int irq; | |
c60ce623 | 181 | }; |
1da177e4 | 182 | |
1da177e4 LT |
183 | /** |
184 | * Type of memory to map. | |
185 | */ | |
c60ce623 | 186 | enum drm_map_type { |
b5e89ed5 DA |
187 | _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ |
188 | _DRM_REGISTERS = 1, /**< no caching, no core dump */ | |
189 | _DRM_SHM = 2, /**< shared, cached */ | |
190 | _DRM_AGP = 3, /**< AGP/GART */ | |
2d0f9eaf | 191 | _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ |
b5e89ed5 | 192 | _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ |
c60ce623 | 193 | }; |
1da177e4 | 194 | |
1da177e4 LT |
195 | /** |
196 | * Memory mapping flags. | |
197 | */ | |
c60ce623 | 198 | enum drm_map_flags { |
b5e89ed5 DA |
199 | _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ |
200 | _DRM_READ_ONLY = 0x02, | |
201 | _DRM_LOCKED = 0x04, /**< shared, cached, locked */ | |
202 | _DRM_KERNEL = 0x08, /**< kernel requires access */ | |
1da177e4 | 203 | _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ |
b5e89ed5 DA |
204 | _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ |
205 | _DRM_REMOVABLE = 0x40 /**< Removable mapping */ | |
c60ce623 | 206 | }; |
1da177e4 | 207 | |
c60ce623 | 208 | struct drm_ctx_priv_map { |
b5e89ed5 DA |
209 | unsigned int ctx_id; /**< Context requesting private mapping */ |
210 | void *handle; /**< Handle of map */ | |
c60ce623 | 211 | }; |
1da177e4 | 212 | |
1da177e4 LT |
213 | /** |
214 | * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls | |
215 | * argument type. | |
216 | * | |
217 | * \sa drmAddMap(). | |
218 | */ | |
c60ce623 | 219 | struct drm_map { |
b5e89ed5 DA |
220 | unsigned long offset; /**< Requested physical address (0 for SAREA)*/ |
221 | unsigned long size; /**< Requested physical size (bytes) */ | |
c60ce623 DA |
222 | enum drm_map_type type; /**< Type of memory to map */ |
223 | enum drm_map_flags flags; /**< Flags */ | |
b5e89ed5 | 224 | void *handle; /**< User-space: "Handle" to pass to mmap() */ |
1da177e4 | 225 | /**< Kernel-space: kernel-virtual address */ |
b5e89ed5 DA |
226 | int mtrr; /**< MTRR slot used */ |
227 | /* Private data */ | |
c60ce623 | 228 | }; |
1da177e4 | 229 | |
1da177e4 LT |
230 | /** |
231 | * DRM_IOCTL_GET_CLIENT ioctl argument type. | |
232 | */ | |
c60ce623 | 233 | struct drm_client { |
b5e89ed5 DA |
234 | int idx; /**< Which client desired? */ |
235 | int auth; /**< Is client authenticated? */ | |
236 | unsigned long pid; /**< Process ID */ | |
237 | unsigned long uid; /**< User ID */ | |
238 | unsigned long magic; /**< Magic */ | |
239 | unsigned long iocs; /**< Ioctl count */ | |
c60ce623 | 240 | }; |
1da177e4 | 241 | |
c60ce623 | 242 | enum drm_stat_type { |
1da177e4 LT |
243 | _DRM_STAT_LOCK, |
244 | _DRM_STAT_OPENS, | |
245 | _DRM_STAT_CLOSES, | |
246 | _DRM_STAT_IOCTLS, | |
247 | _DRM_STAT_LOCKS, | |
248 | _DRM_STAT_UNLOCKS, | |
249 | _DRM_STAT_VALUE, /**< Generic value */ | |
250 | _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ | |
251 | _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ | |
252 | ||
253 | _DRM_STAT_IRQ, /**< IRQ */ | |
254 | _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ | |
255 | _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ | |
256 | _DRM_STAT_DMA, /**< DMA */ | |
257 | _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ | |
258 | _DRM_STAT_MISSED /**< Missed DMA opportunity */ | |
b5e89ed5 | 259 | /* Add to the *END* of the list */ |
c60ce623 | 260 | }; |
1da177e4 | 261 | |
1da177e4 LT |
262 | /** |
263 | * DRM_IOCTL_GET_STATS ioctl argument type. | |
264 | */ | |
c60ce623 | 265 | struct drm_stats { |
1da177e4 LT |
266 | unsigned long count; |
267 | struct { | |
b5e89ed5 | 268 | unsigned long value; |
c60ce623 | 269 | enum drm_stat_type type; |
1da177e4 | 270 | } data[15]; |
c60ce623 | 271 | }; |
1da177e4 | 272 | |
1da177e4 LT |
273 | /** |
274 | * Hardware locking flags. | |
275 | */ | |
c60ce623 | 276 | enum drm_lock_flags { |
b5e89ed5 DA |
277 | _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ |
278 | _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ | |
279 | _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ | |
280 | _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ | |
281 | /* These *HALT* flags aren't supported yet | |
282 | -- they will be used to support the | |
283 | full-screen DGA-like mode. */ | |
1da177e4 LT |
284 | _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ |
285 | _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ | |
c60ce623 | 286 | }; |
1da177e4 | 287 | |
1da177e4 LT |
288 | /** |
289 | * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. | |
b5e89ed5 | 290 | * |
1da177e4 LT |
291 | * \sa drmGetLock() and drmUnlock(). |
292 | */ | |
c60ce623 | 293 | struct drm_lock { |
b5e89ed5 | 294 | int context; |
c60ce623 DA |
295 | enum drm_lock_flags flags; |
296 | }; | |
1da177e4 | 297 | |
1da177e4 LT |
298 | /** |
299 | * DMA flags | |
300 | * | |
b5e89ed5 | 301 | * \warning |
1da177e4 LT |
302 | * These values \e must match xf86drm.h. |
303 | * | |
304 | * \sa drm_dma. | |
305 | */ | |
c60ce623 | 306 | enum drm_dma_flags { |
b5e89ed5 DA |
307 | /* Flags for DMA buffer dispatch */ |
308 | _DRM_DMA_BLOCK = 0x01, /**< | |
1da177e4 | 309 | * Block until buffer dispatched. |
b5e89ed5 | 310 | * |
1da177e4 LT |
311 | * \note The buffer may not yet have |
312 | * been processed by the hardware -- | |
313 | * getting a hardware lock with the | |
314 | * hardware quiescent will ensure | |
315 | * that the buffer has been | |
316 | * processed. | |
317 | */ | |
318 | _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ | |
b5e89ed5 | 319 | _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ |
1da177e4 | 320 | |
b5e89ed5 DA |
321 | /* Flags for DMA buffer request */ |
322 | _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ | |
323 | _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ | |
324 | _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ | |
c60ce623 | 325 | }; |
1da177e4 | 326 | |
1da177e4 LT |
327 | /** |
328 | * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. | |
329 | * | |
330 | * \sa drmAddBufs(). | |
331 | */ | |
c60ce623 | 332 | struct drm_buf_desc { |
b5e89ed5 DA |
333 | int count; /**< Number of buffers of this size */ |
334 | int size; /**< Size in bytes */ | |
335 | int low_mark; /**< Low water mark */ | |
336 | int high_mark; /**< High water mark */ | |
1da177e4 | 337 | enum { |
b5e89ed5 DA |
338 | _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ |
339 | _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ | |
340 | _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ | |
3417f33e GS |
341 | _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ |
342 | _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ | |
b5e89ed5 DA |
343 | } flags; |
344 | unsigned long agp_start; /**< | |
1da177e4 LT |
345 | * Start address of where the AGP buffers are |
346 | * in the AGP aperture | |
347 | */ | |
c60ce623 | 348 | }; |
1da177e4 | 349 | |
1da177e4 LT |
350 | /** |
351 | * DRM_IOCTL_INFO_BUFS ioctl argument type. | |
352 | */ | |
c60ce623 | 353 | struct drm_buf_info { |
b5e89ed5 | 354 | int count; /**< Entries in list */ |
c60ce623 DA |
355 | struct drm_buf_desc __user *list; |
356 | }; | |
1da177e4 | 357 | |
1da177e4 LT |
358 | /** |
359 | * DRM_IOCTL_FREE_BUFS ioctl argument type. | |
360 | */ | |
c60ce623 | 361 | struct drm_buf_free { |
b5e89ed5 DA |
362 | int count; |
363 | int __user *list; | |
c60ce623 | 364 | }; |
1da177e4 | 365 | |
1da177e4 LT |
366 | /** |
367 | * Buffer information | |
368 | * | |
369 | * \sa drm_buf_map. | |
370 | */ | |
c60ce623 | 371 | struct drm_buf_pub { |
b5e89ed5 DA |
372 | int idx; /**< Index into the master buffer list */ |
373 | int total; /**< Buffer size */ | |
374 | int used; /**< Amount of buffer in use (for DMA) */ | |
375 | void __user *address; /**< Address of buffer */ | |
c60ce623 | 376 | }; |
1da177e4 | 377 | |
1da177e4 LT |
378 | /** |
379 | * DRM_IOCTL_MAP_BUFS ioctl argument type. | |
380 | */ | |
c60ce623 | 381 | struct drm_buf_map { |
b5e89ed5 DA |
382 | int count; /**< Length of the buffer list */ |
383 | void __user *virtual; /**< Mmap'd area in user-virtual */ | |
c60ce623 DA |
384 | struct drm_buf_pub __user *list; /**< Buffer information */ |
385 | }; | |
1da177e4 | 386 | |
1da177e4 LT |
387 | /** |
388 | * DRM_IOCTL_DMA ioctl argument type. | |
389 | * | |
390 | * Indices here refer to the offset into the buffer list in drm_buf_get. | |
391 | * | |
392 | * \sa drmDMA(). | |
393 | */ | |
c60ce623 | 394 | struct drm_dma { |
b5e89ed5 DA |
395 | int context; /**< Context handle */ |
396 | int send_count; /**< Number of buffers to send */ | |
397 | int __user *send_indices; /**< List of handles to buffers */ | |
398 | int __user *send_sizes; /**< Lengths of data to send */ | |
c60ce623 | 399 | enum drm_dma_flags flags; /**< Flags */ |
b5e89ed5 DA |
400 | int request_count; /**< Number of buffers requested */ |
401 | int request_size; /**< Desired size for buffers */ | |
402 | int __user *request_indices; /**< Buffer information */ | |
403 | int __user *request_sizes; | |
404 | int granted_count; /**< Number of buffers granted */ | |
c60ce623 | 405 | }; |
1da177e4 | 406 | |
c60ce623 | 407 | enum drm_ctx_flags { |
1da177e4 | 408 | _DRM_CONTEXT_PRESERVED = 0x01, |
b5e89ed5 | 409 | _DRM_CONTEXT_2DONLY = 0x02 |
c60ce623 | 410 | }; |
1da177e4 | 411 | |
1da177e4 LT |
412 | /** |
413 | * DRM_IOCTL_ADD_CTX ioctl argument type. | |
414 | * | |
415 | * \sa drmCreateContext() and drmDestroyContext(). | |
416 | */ | |
c60ce623 | 417 | struct drm_ctx { |
b5e89ed5 | 418 | drm_context_t handle; |
c60ce623 DA |
419 | enum drm_ctx_flags flags; |
420 | }; | |
1da177e4 | 421 | |
1da177e4 LT |
422 | /** |
423 | * DRM_IOCTL_RES_CTX ioctl argument type. | |
424 | */ | |
c60ce623 | 425 | struct drm_ctx_res { |
b5e89ed5 | 426 | int count; |
c60ce623 DA |
427 | struct drm_ctx __user *contexts; |
428 | }; | |
1da177e4 | 429 | |
1da177e4 LT |
430 | /** |
431 | * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. | |
432 | */ | |
c60ce623 | 433 | struct drm_draw { |
b5e89ed5 | 434 | drm_drawable_t handle; |
c60ce623 | 435 | }; |
1da177e4 | 436 | |
bea5679f MCA |
437 | /** |
438 | * DRM_IOCTL_UPDATE_DRAW ioctl argument type. | |
439 | */ | |
440 | typedef enum { | |
441 | DRM_DRAWABLE_CLIPRECTS, | |
442 | } drm_drawable_info_type_t; | |
443 | ||
c60ce623 | 444 | struct drm_update_draw { |
bea5679f MCA |
445 | drm_drawable_t handle; |
446 | unsigned int type; | |
447 | unsigned int num; | |
448 | unsigned long long data; | |
c60ce623 | 449 | }; |
bea5679f | 450 | |
1da177e4 LT |
451 | /** |
452 | * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. | |
453 | */ | |
c60ce623 | 454 | struct drm_auth { |
b5e89ed5 | 455 | drm_magic_t magic; |
c60ce623 | 456 | }; |
1da177e4 | 457 | |
1da177e4 LT |
458 | /** |
459 | * DRM_IOCTL_IRQ_BUSID ioctl argument type. | |
460 | * | |
461 | * \sa drmGetInterruptFromBusID(). | |
462 | */ | |
c60ce623 | 463 | struct drm_irq_busid { |
1da177e4 LT |
464 | int irq; /**< IRQ number */ |
465 | int busnum; /**< bus number */ | |
466 | int devnum; /**< device number */ | |
467 | int funcnum; /**< function number */ | |
c60ce623 | 468 | }; |
1da177e4 | 469 | |
c60ce623 | 470 | enum drm_vblank_seq_type { |
b5e89ed5 DA |
471 | _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ |
472 | _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ | |
ab285d74 | 473 | _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ |
776c9443 | 474 | _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ |
b5e89ed5 | 475 | _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ |
c60ce623 | 476 | }; |
1da177e4 | 477 | |
776c9443 | 478 | #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) |
ab285d74 MCA |
479 | #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ |
480 | _DRM_VBLANK_NEXTONMISS) | |
1da177e4 | 481 | |
1da177e4 | 482 | struct drm_wait_vblank_request { |
c60ce623 | 483 | enum drm_vblank_seq_type type; |
1da177e4 LT |
484 | unsigned int sequence; |
485 | unsigned long signal; | |
486 | }; | |
487 | ||
1da177e4 | 488 | struct drm_wait_vblank_reply { |
c60ce623 | 489 | enum drm_vblank_seq_type type; |
1da177e4 LT |
490 | unsigned int sequence; |
491 | long tval_sec; | |
492 | long tval_usec; | |
493 | }; | |
494 | ||
1da177e4 LT |
495 | /** |
496 | * DRM_IOCTL_WAIT_VBLANK ioctl argument type. | |
497 | * | |
498 | * \sa drmWaitVBlank(). | |
499 | */ | |
c60ce623 | 500 | union drm_wait_vblank { |
1da177e4 LT |
501 | struct drm_wait_vblank_request request; |
502 | struct drm_wait_vblank_reply reply; | |
c60ce623 | 503 | }; |
1da177e4 | 504 | |
1da177e4 LT |
505 | /** |
506 | * DRM_IOCTL_AGP_ENABLE ioctl argument type. | |
507 | * | |
508 | * \sa drmAgpEnable(). | |
509 | */ | |
c60ce623 | 510 | struct drm_agp_mode { |
1da177e4 | 511 | unsigned long mode; /**< AGP mode */ |
c60ce623 | 512 | }; |
1da177e4 | 513 | |
1da177e4 LT |
514 | /** |
515 | * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. | |
516 | * | |
517 | * \sa drmAgpAlloc() and drmAgpFree(). | |
518 | */ | |
c60ce623 | 519 | struct drm_agp_buffer { |
1da177e4 LT |
520 | unsigned long size; /**< In bytes -- will round to page boundary */ |
521 | unsigned long handle; /**< Used for binding / unbinding */ | |
b5e89ed5 DA |
522 | unsigned long type; /**< Type of memory to allocate */ |
523 | unsigned long physical; /**< Physical used by i810 */ | |
c60ce623 | 524 | }; |
1da177e4 | 525 | |
1da177e4 LT |
526 | /** |
527 | * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. | |
528 | * | |
529 | * \sa drmAgpBind() and drmAgpUnbind(). | |
530 | */ | |
c60ce623 | 531 | struct drm_agp_binding { |
b5e89ed5 | 532 | unsigned long handle; /**< From drm_agp_buffer */ |
1da177e4 | 533 | unsigned long offset; /**< In bytes -- will round to page boundary */ |
c60ce623 | 534 | }; |
1da177e4 | 535 | |
1da177e4 LT |
536 | /** |
537 | * DRM_IOCTL_AGP_INFO ioctl argument type. | |
538 | * | |
539 | * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), | |
540 | * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), | |
541 | * drmAgpVendorId() and drmAgpDeviceId(). | |
542 | */ | |
c60ce623 | 543 | struct drm_agp_info { |
b5e89ed5 DA |
544 | int agp_version_major; |
545 | int agp_version_minor; | |
546 | unsigned long mode; | |
547 | unsigned long aperture_base; /* physical address */ | |
548 | unsigned long aperture_size; /* bytes */ | |
549 | unsigned long memory_allowed; /* bytes */ | |
550 | unsigned long memory_used; | |
551 | ||
552 | /* PCI information */ | |
1da177e4 LT |
553 | unsigned short id_vendor; |
554 | unsigned short id_device; | |
c60ce623 | 555 | }; |
1da177e4 | 556 | |
1da177e4 LT |
557 | /** |
558 | * DRM_IOCTL_SG_ALLOC ioctl argument type. | |
559 | */ | |
c60ce623 | 560 | struct drm_scatter_gather { |
1da177e4 LT |
561 | unsigned long size; /**< In bytes -- will round to page boundary */ |
562 | unsigned long handle; /**< Used for mapping / unmapping */ | |
c60ce623 | 563 | }; |
1da177e4 LT |
564 | |
565 | /** | |
566 | * DRM_IOCTL_SET_VERSION ioctl argument type. | |
567 | */ | |
c60ce623 | 568 | struct drm_set_version { |
1da177e4 LT |
569 | int drm_di_major; |
570 | int drm_di_minor; | |
571 | int drm_dd_major; | |
572 | int drm_dd_minor; | |
c60ce623 | 573 | }; |
1da177e4 | 574 | |
1da177e4 LT |
575 | #define DRM_IOCTL_BASE 'd' |
576 | #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) | |
577 | #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) | |
578 | #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) | |
579 | #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) | |
580 | ||
c60ce623 DA |
581 | #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) |
582 | #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) | |
583 | #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) | |
584 | #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) | |
585 | #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) | |
586 | #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) | |
587 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) | |
588 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) | |
589 | ||
590 | #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) | |
591 | #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) | |
592 | #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) | |
593 | #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) | |
594 | #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) | |
595 | #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) | |
596 | #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) | |
597 | #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) | |
598 | #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) | |
599 | #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) | |
600 | #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) | |
601 | ||
602 | #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) | |
603 | ||
604 | #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) | |
605 | #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) | |
606 | ||
607 | #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) | |
608 | #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) | |
609 | #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) | |
610 | #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) | |
611 | #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) | |
612 | #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) | |
613 | #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) | |
614 | #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) | |
615 | #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) | |
616 | #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) | |
617 | #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) | |
618 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) | |
619 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) | |
1da177e4 LT |
620 | |
621 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) | |
622 | #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) | |
c60ce623 DA |
623 | #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) |
624 | #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) | |
625 | #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) | |
626 | #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) | |
627 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) | |
628 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) | |
1da177e4 | 629 | |
c60ce623 DA |
630 | #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather) |
631 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) | |
1da177e4 | 632 | |
c60ce623 | 633 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) |
1da177e4 | 634 | |
c60ce623 | 635 | #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) |
bea5679f | 636 | |
1da177e4 LT |
637 | /** |
638 | * Device specific ioctls should only be in their respective headers | |
99da6d86 TH |
639 | * The device specific ioctl range is from 0x40 to 0x99. |
640 | * Generic IOCTLS restart at 0xA0. | |
1da177e4 LT |
641 | * |
642 | * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and | |
643 | * drmCommandReadWrite(). | |
644 | */ | |
645 | #define DRM_COMMAND_BASE 0x40 | |
99da6d86 | 646 | #define DRM_COMMAND_END 0xA0 |
1da177e4 | 647 | |
c60ce623 DA |
648 | /* typedef area */ |
649 | #ifndef __KERNEL__ | |
650 | typedef struct drm_clip_rect drm_clip_rect_t; | |
651 | typedef struct drm_drawable_info drm_drawable_info_t; | |
652 | typedef struct drm_tex_region drm_tex_region_t; | |
653 | typedef struct drm_hw_lock drm_hw_lock_t; | |
654 | typedef struct drm_version drm_version_t; | |
655 | typedef struct drm_unique drm_unique_t; | |
656 | typedef struct drm_list drm_list_t; | |
657 | typedef struct drm_block drm_block_t; | |
658 | typedef struct drm_control drm_control_t; | |
659 | typedef enum drm_map_type drm_map_type_t; | |
660 | typedef enum drm_map_flags drm_map_flags_t; | |
661 | typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; | |
662 | typedef struct drm_map drm_map_t; | |
663 | typedef struct drm_client drm_client_t; | |
664 | typedef enum drm_stat_type drm_stat_type_t; | |
665 | typedef struct drm_stats drm_stats_t; | |
666 | typedef enum drm_lock_flags drm_lock_flags_t; | |
667 | typedef struct drm_lock drm_lock_t; | |
668 | typedef enum drm_dma_flags drm_dma_flags_t; | |
669 | typedef struct drm_buf_desc drm_buf_desc_t; | |
670 | typedef struct drm_buf_info drm_buf_info_t; | |
671 | typedef struct drm_buf_free drm_buf_free_t; | |
672 | typedef struct drm_buf_pub drm_buf_pub_t; | |
673 | typedef struct drm_buf_map drm_buf_map_t; | |
674 | typedef struct drm_dma drm_dma_t; | |
675 | typedef union drm_wait_vblank drm_wait_vblank_t; | |
676 | typedef struct drm_agp_mode drm_agp_mode_t; | |
677 | typedef enum drm_ctx_flags drm_ctx_flags_t; | |
678 | typedef struct drm_ctx drm_ctx_t; | |
679 | typedef struct drm_ctx_res drm_ctx_res_t; | |
680 | typedef struct drm_draw drm_draw_t; | |
681 | typedef struct drm_update_draw drm_update_draw_t; | |
682 | typedef struct drm_auth drm_auth_t; | |
683 | typedef struct drm_irq_busid drm_irq_busid_t; | |
684 | typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; | |
685 | ||
686 | typedef struct drm_agp_buffer drm_agp_buffer_t; | |
687 | typedef struct drm_agp_binding drm_agp_binding_t; | |
688 | typedef struct drm_agp_info drm_agp_info_t; | |
689 | typedef struct drm_scatter_gather drm_scatter_gather_t; | |
690 | typedef struct drm_set_version drm_set_version_t; | |
691 | #endif | |
692 | ||
1da177e4 | 693 | #endif |