Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * SiS AGPGART routines. | |
3 | */ | |
4 | ||
5 | #include <linux/module.h> | |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/agp_backend.h> | |
9 | #include <linux/delay.h> | |
10 | #include "agp.h" | |
11 | ||
12 | #define SIS_ATTBASE 0x90 | |
13 | #define SIS_APSIZE 0x94 | |
14 | #define SIS_TLBCNTRL 0x97 | |
15 | #define SIS_TLBFLUSH 0x98 | |
16 | ||
17 | static int __devinitdata agp_sis_force_delay = 0; | |
18 | static int __devinitdata agp_sis_agp_spec = -1; | |
19 | ||
20 | static int sis_fetch_size(void) | |
21 | { | |
22 | u8 temp_size; | |
23 | int i; | |
24 | struct aper_size_info_8 *values; | |
25 | ||
26 | pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size); | |
27 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
28 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
29 | if ((temp_size == values[i].size_value) || | |
30 | ((temp_size & ~(0x03)) == | |
31 | (values[i].size_value & ~(0x03)))) { | |
32 | agp_bridge->previous_size = | |
33 | agp_bridge->current_size = (void *) (values + i); | |
34 | ||
35 | agp_bridge->aperture_size_idx = i; | |
36 | return values[i].size; | |
37 | } | |
38 | } | |
39 | ||
40 | return 0; | |
41 | } | |
42 | ||
43 | static void sis_tlbflush(struct agp_memory *mem) | |
44 | { | |
45 | pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02); | |
46 | } | |
47 | ||
48 | static int sis_configure(void) | |
49 | { | |
50 | u32 temp; | |
51 | struct aper_size_info_8 *current_size; | |
52 | ||
53 | current_size = A_SIZE_8(agp_bridge->current_size); | |
54 | pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05); | |
55 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
56 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
57 | pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE, | |
58 | agp_bridge->gatt_bus_addr); | |
59 | pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, | |
60 | current_size->size_value); | |
61 | return 0; | |
62 | } | |
63 | ||
64 | static void sis_cleanup(void) | |
65 | { | |
66 | struct aper_size_info_8 *previous_size; | |
67 | ||
68 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
69 | pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, | |
70 | (previous_size->size_value & ~(0x03))); | |
71 | } | |
72 | ||
73 | static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode) | |
74 | { | |
75 | struct pci_dev *device = NULL; | |
76 | u32 command; | |
77 | int rate; | |
78 | ||
79 | printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n", | |
80 | agp_bridge->major_version, | |
81 | agp_bridge->minor_version, | |
82 | pci_name(agp_bridge->dev)); | |
83 | ||
84 | pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command); | |
85 | command = agp_collect_device_status(bridge, mode, command); | |
86 | command |= AGPSTAT_AGP_ENABLE; | |
87 | rate = (command & 0x7) << 2; | |
88 | ||
89 | for_each_pci_dev(device) { | |
90 | u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP); | |
91 | if (!agp) | |
92 | continue; | |
93 | ||
94 | printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n", | |
95 | pci_name(device), rate); | |
96 | ||
97 | pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command); | |
98 | ||
99 | /* | |
100 | * Weird: on some sis chipsets any rate change in the target | |
101 | * command register triggers a 5ms screwup during which the master | |
102 | * cannot be configured | |
103 | */ | |
104 | if (device->device == bridge->dev->device) { | |
105 | printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n"); | |
106 | msleep(10); | |
107 | } | |
108 | } | |
109 | } | |
110 | ||
e5524f35 | 111 | static const struct aper_size_info_8 sis_generic_sizes[7] = |
1da177e4 LT |
112 | { |
113 | {256, 65536, 6, 99}, | |
114 | {128, 32768, 5, 83}, | |
115 | {64, 16384, 4, 67}, | |
116 | {32, 8192, 3, 51}, | |
117 | {16, 4096, 2, 35}, | |
118 | {8, 2048, 1, 19}, | |
119 | {4, 1024, 0, 3} | |
120 | }; | |
121 | ||
408b664a | 122 | static struct agp_bridge_driver sis_driver = { |
1da177e4 | 123 | .owner = THIS_MODULE, |
6a92a4e0 | 124 | .aperture_sizes = sis_generic_sizes, |
1da177e4 LT |
125 | .size_type = U8_APER_SIZE, |
126 | .num_aperture_sizes = 7, | |
127 | .configure = sis_configure, | |
128 | .fetch_size = sis_fetch_size, | |
129 | .cleanup = sis_cleanup, | |
130 | .tlb_flush = sis_tlbflush, | |
131 | .mask_memory = agp_generic_mask_memory, | |
132 | .masks = NULL, | |
133 | .agp_enable = agp_generic_enable, | |
134 | .cache_flush = global_cache_flush, | |
135 | .create_gatt_table = agp_generic_create_gatt_table, | |
136 | .free_gatt_table = agp_generic_free_gatt_table, | |
137 | .insert_memory = agp_generic_insert_memory, | |
138 | .remove_memory = agp_generic_remove_memory, | |
139 | .alloc_by_type = agp_generic_alloc_by_type, | |
140 | .free_by_type = agp_generic_free_by_type, | |
141 | .agp_alloc_page = agp_generic_alloc_page, | |
142 | .agp_destroy_page = agp_generic_destroy_page, | |
bf1e5989 | 143 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
144 | }; |
145 | ||
1da177e4 LT |
146 | // chipsets that require the 'delay hack' |
147 | static int sis_broken_chipsets[] __devinitdata = { | |
148 | PCI_DEVICE_ID_SI_648, | |
149 | PCI_DEVICE_ID_SI_746, | |
150 | 0 // terminator | |
151 | }; | |
152 | ||
153 | static void __devinit sis_get_driver(struct agp_bridge_data *bridge) | |
154 | { | |
155 | int i; | |
156 | ||
6a92a4e0 DJ |
157 | for (i=0; sis_broken_chipsets[i]!=0; ++i) |
158 | if (bridge->dev->device==sis_broken_chipsets[i]) | |
1da177e4 LT |
159 | break; |
160 | ||
6a92a4e0 | 161 | if (sis_broken_chipsets[i] || agp_sis_force_delay) |
1da177e4 LT |
162 | sis_driver.agp_enable=sis_delayed_enable; |
163 | ||
164 | // sis chipsets that indicate less than agp3.5 | |
165 | // are not actually fully agp3 compliant | |
166 | if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5 | |
167 | && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) { | |
168 | sis_driver.aperture_sizes = agp3_generic_sizes; | |
169 | sis_driver.size_type = U16_APER_SIZE; | |
170 | sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES; | |
171 | sis_driver.configure = agp3_generic_configure; | |
172 | sis_driver.fetch_size = agp3_generic_fetch_size; | |
173 | sis_driver.cleanup = agp3_generic_cleanup; | |
174 | sis_driver.tlb_flush = agp3_generic_tlbflush; | |
175 | } | |
176 | } | |
177 | ||
178 | ||
179 | static int __devinit agp_sis_probe(struct pci_dev *pdev, | |
180 | const struct pci_device_id *ent) | |
181 | { | |
1da177e4 LT |
182 | struct agp_bridge_data *bridge; |
183 | u8 cap_ptr; | |
1da177e4 LT |
184 | |
185 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
186 | if (!cap_ptr) | |
187 | return -ENODEV; | |
188 | ||
1da177e4 | 189 | |
82eab130 | 190 | printk(KERN_INFO PFX "Detected SiS chipset - id:%i\n", pdev->device); |
1da177e4 LT |
191 | bridge = agp_alloc_bridge(); |
192 | if (!bridge) | |
193 | return -ENOMEM; | |
194 | ||
195 | bridge->driver = &sis_driver; | |
196 | bridge->dev = pdev; | |
197 | bridge->capndx = cap_ptr; | |
198 | ||
199 | get_agp_version(bridge); | |
200 | ||
201 | /* Fill in the mode register */ | |
202 | pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); | |
203 | sis_get_driver(bridge); | |
204 | ||
205 | pci_set_drvdata(pdev, bridge); | |
206 | return agp_add_bridge(bridge); | |
207 | } | |
208 | ||
209 | static void __devexit agp_sis_remove(struct pci_dev *pdev) | |
210 | { | |
211 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
212 | ||
213 | agp_remove_bridge(bridge); | |
214 | agp_put_bridge(bridge); | |
215 | } | |
216 | ||
217 | static struct pci_device_id agp_sis_pci_table[] = { | |
218 | { | |
82eab130 ON |
219 | .class = (PCI_CLASS_BRIDGE_HOST << 8), |
220 | .class_mask = ~0, | |
221 | .vendor = PCI_VENDOR_ID_SI, | |
222 | .device = PCI_DEVICE_ID_SI_5591_AGP, | |
223 | .subvendor = PCI_ANY_ID, | |
224 | .subdevice = PCI_ANY_ID, | |
225 | }, | |
226 | { | |
227 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
228 | .class_mask = ~0, | |
229 | .vendor = PCI_VENDOR_ID_SI, | |
230 | .device = PCI_DEVICE_ID_SI_530, | |
231 | .subvendor = PCI_ANY_ID, | |
232 | .subdevice = PCI_ANY_ID, | |
233 | }, | |
234 | { | |
235 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
236 | .class_mask = ~0, | |
237 | .vendor = PCI_VENDOR_ID_SI, | |
238 | .device = PCI_DEVICE_ID_SI_540, | |
239 | .subvendor = PCI_ANY_ID, | |
240 | .subdevice = PCI_ANY_ID, | |
241 | }, | |
242 | { | |
243 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
244 | .class_mask = ~0, | |
245 | .vendor = PCI_VENDOR_ID_SI, | |
246 | .device = PCI_DEVICE_ID_SI_550, | |
247 | .subvendor = PCI_ANY_ID, | |
248 | .subdevice = PCI_ANY_ID, | |
249 | }, | |
250 | { | |
251 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
252 | .class_mask = ~0, | |
253 | .vendor = PCI_VENDOR_ID_SI, | |
254 | .device = PCI_DEVICE_ID_SI_620, | |
255 | .subvendor = PCI_ANY_ID, | |
256 | .subdevice = PCI_ANY_ID, | |
257 | }, | |
258 | { | |
259 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
260 | .class_mask = ~0, | |
261 | .vendor = PCI_VENDOR_ID_SI, | |
262 | .device = PCI_DEVICE_ID_SI_630, | |
263 | .subvendor = PCI_ANY_ID, | |
264 | .subdevice = PCI_ANY_ID, | |
265 | }, | |
266 | { | |
267 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
268 | .class_mask = ~0, | |
269 | .vendor = PCI_VENDOR_ID_SI, | |
270 | .device = PCI_DEVICE_ID_SI_635, | |
271 | .subvendor = PCI_ANY_ID, | |
272 | .subdevice = PCI_ANY_ID, | |
273 | }, | |
274 | { | |
275 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
276 | .class_mask = ~0, | |
277 | .vendor = PCI_VENDOR_ID_SI, | |
278 | .device = PCI_DEVICE_ID_SI_645, | |
279 | .subvendor = PCI_ANY_ID, | |
280 | .subdevice = PCI_ANY_ID, | |
281 | }, | |
282 | { | |
283 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
284 | .class_mask = ~0, | |
285 | .vendor = PCI_VENDOR_ID_SI, | |
286 | .device = PCI_DEVICE_ID_SI_646, | |
287 | .subvendor = PCI_ANY_ID, | |
288 | .subdevice = PCI_ANY_ID, | |
289 | }, | |
290 | { | |
291 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
292 | .class_mask = ~0, | |
293 | .vendor = PCI_VENDOR_ID_SI, | |
294 | .device = PCI_DEVICE_ID_SI_648, | |
295 | .subvendor = PCI_ANY_ID, | |
296 | .subdevice = PCI_ANY_ID, | |
297 | }, | |
298 | { | |
299 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
300 | .class_mask = ~0, | |
301 | .vendor = PCI_VENDOR_ID_SI, | |
302 | .device = PCI_DEVICE_ID_SI_650, | |
303 | .subvendor = PCI_ANY_ID, | |
304 | .subdevice = PCI_ANY_ID, | |
305 | }, | |
306 | { | |
307 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
308 | .class_mask = ~0, | |
309 | .vendor = PCI_VENDOR_ID_SI, | |
310 | .device = PCI_DEVICE_ID_SI_651, | |
311 | .subvendor = PCI_ANY_ID, | |
312 | .subdevice = PCI_ANY_ID, | |
313 | }, | |
314 | { | |
315 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
316 | .class_mask = ~0, | |
317 | .vendor = PCI_VENDOR_ID_SI, | |
318 | .device = PCI_DEVICE_ID_SI_655, | |
319 | .subvendor = PCI_ANY_ID, | |
320 | .subdevice = PCI_ANY_ID, | |
321 | }, | |
322 | { | |
323 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
324 | .class_mask = ~0, | |
325 | .vendor = PCI_VENDOR_ID_SI, | |
326 | .device = PCI_DEVICE_ID_SI_661, | |
327 | .subvendor = PCI_ANY_ID, | |
328 | .subdevice = PCI_ANY_ID, | |
329 | }, | |
330 | { | |
331 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
332 | .class_mask = ~0, | |
333 | .vendor = PCI_VENDOR_ID_SI, | |
334 | .device = PCI_DEVICE_ID_SI_730, | |
335 | .subvendor = PCI_ANY_ID, | |
336 | .subdevice = PCI_ANY_ID, | |
337 | }, | |
338 | { | |
339 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
340 | .class_mask = ~0, | |
341 | .vendor = PCI_VENDOR_ID_SI, | |
342 | .device = PCI_DEVICE_ID_SI_735, | |
343 | .subvendor = PCI_ANY_ID, | |
344 | .subdevice = PCI_ANY_ID, | |
345 | }, | |
346 | { | |
347 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
348 | .class_mask = ~0, | |
349 | .vendor = PCI_VENDOR_ID_SI, | |
350 | .device = PCI_DEVICE_ID_SI_740, | |
351 | .subvendor = PCI_ANY_ID, | |
352 | .subdevice = PCI_ANY_ID, | |
353 | }, | |
354 | { | |
355 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
356 | .class_mask = ~0, | |
357 | .vendor = PCI_VENDOR_ID_SI, | |
358 | .device = PCI_DEVICE_ID_SI_741, | |
359 | .subvendor = PCI_ANY_ID, | |
360 | .subdevice = PCI_ANY_ID, | |
361 | }, | |
362 | { | |
363 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
364 | .class_mask = ~0, | |
365 | .vendor = PCI_VENDOR_ID_SI, | |
366 | .device = PCI_DEVICE_ID_SI_745, | |
367 | .subvendor = PCI_ANY_ID, | |
368 | .subdevice = PCI_ANY_ID, | |
369 | }, | |
370 | { | |
371 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
372 | .class_mask = ~0, | |
373 | .vendor = PCI_VENDOR_ID_SI, | |
374 | .device = PCI_DEVICE_ID_SI_746, | |
375 | .subvendor = PCI_ANY_ID, | |
376 | .subdevice = PCI_ANY_ID, | |
377 | }, | |
378 | { | |
379 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
380 | .class_mask = ~0, | |
381 | .vendor = PCI_VENDOR_ID_SI, | |
382 | .device = PCI_DEVICE_ID_SI_760, | |
383 | .subvendor = PCI_ANY_ID, | |
384 | .subdevice = PCI_ANY_ID, | |
1da177e4 LT |
385 | }, |
386 | { } | |
387 | }; | |
388 | ||
389 | MODULE_DEVICE_TABLE(pci, agp_sis_pci_table); | |
390 | ||
391 | static struct pci_driver agp_sis_pci_driver = { | |
392 | .name = "agpgart-sis", | |
393 | .id_table = agp_sis_pci_table, | |
394 | .probe = agp_sis_probe, | |
395 | .remove = agp_sis_remove, | |
396 | }; | |
397 | ||
398 | static int __init agp_sis_init(void) | |
399 | { | |
400 | if (agp_off) | |
401 | return -EINVAL; | |
402 | return pci_register_driver(&agp_sis_pci_driver); | |
403 | } | |
404 | ||
405 | static void __exit agp_sis_cleanup(void) | |
406 | { | |
407 | pci_unregister_driver(&agp_sis_pci_driver); | |
408 | } | |
409 | ||
410 | module_init(agp_sis_init); | |
411 | module_exit(agp_sis_cleanup); | |
412 | ||
413 | module_param(agp_sis_force_delay, bool, 0); | |
414 | MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack"); | |
415 | module_param(agp_sis_agp_spec, int, 0); | |
416 | MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect"); | |
417 | MODULE_LICENSE("GPL and additional rights"); |