Commit | Line | Data |
---|---|---|
f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/pagemap.h> | |
23 | #include <linux/agp_backend.h> | |
bdb8b975 | 24 | #include <linux/delay.h> |
e2404e7c DV |
25 | #include <asm/smp.h> |
26 | #include "agp.h" | |
27 | #include "intel-agp.h" | |
0ade6386 | 28 | #include <drm/intel-gtt.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
33 | * on the Intel IOMMU support (CONFIG_DMAR). | |
34 | * Only newer chipsets need to bother with this, of course. | |
35 | */ | |
36 | #ifdef CONFIG_DMAR | |
37 | #define USE_PCI_DMA_API 1 | |
0e87d2b0 DV |
38 | #else |
39 | #define USE_PCI_DMA_API 0 | |
f51b7662 DV |
40 | #endif |
41 | ||
1a997ff2 DV |
42 | struct intel_gtt_driver { |
43 | unsigned int gen : 8; | |
44 | unsigned int is_g33 : 1; | |
45 | unsigned int is_pineview : 1; | |
46 | unsigned int is_ironlake : 1; | |
100519e2 | 47 | unsigned int has_pgtbl_enable : 1; |
22533b49 | 48 | unsigned int dma_mask_size : 8; |
73800422 DV |
49 | /* Chipset specific GTT setup */ |
50 | int (*setup)(void); | |
ae83dd5c DV |
51 | /* This should undo anything done in ->setup() save the unmapping |
52 | * of the mmio register file, that's done in the generic code. */ | |
53 | void (*cleanup)(void); | |
351bb278 DV |
54 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
55 | /* Flags is a more or less chipset specific opaque value. | |
56 | * For chipsets that need to support old ums (non-gem) code, this | |
57 | * needs to be identical to the various supported agp memory types! */ | |
5cbecafc | 58 | bool (*check_flags)(unsigned int flags); |
1b263f24 | 59 | void (*chipset_flush)(void); |
1a997ff2 DV |
60 | }; |
61 | ||
f51b7662 | 62 | static struct _intel_private { |
0ade6386 | 63 | struct intel_gtt base; |
1a997ff2 | 64 | const struct intel_gtt_driver *driver; |
f51b7662 | 65 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 66 | struct pci_dev *bridge_dev; |
f51b7662 | 67 | u8 __iomem *registers; |
f67eab66 | 68 | phys_addr_t gtt_bus_addr; |
73800422 | 69 | phys_addr_t gma_bus_addr; |
b3eafc5a | 70 | u32 PGETBL_save; |
f51b7662 | 71 | u32 __iomem *gtt; /* I915G */ |
bee4a186 | 72 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
f51b7662 | 73 | int num_dcache_entries; |
bdb8b975 | 74 | void __iomem *i9xx_flush_page; |
820647b9 | 75 | char *i81x_gtt_table; |
f51b7662 DV |
76 | struct resource ifp_resource; |
77 | int resource_valid; | |
0e87d2b0 DV |
78 | struct page *scratch_page; |
79 | dma_addr_t scratch_page_dma; | |
f51b7662 DV |
80 | } intel_private; |
81 | ||
1a997ff2 DV |
82 | #define INTEL_GTT_GEN intel_private.driver->gen |
83 | #define IS_G33 intel_private.driver->is_g33 | |
84 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
85 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
100519e2 | 86 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
1a997ff2 | 87 | |
4080775b DV |
88 | int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, |
89 | struct scatterlist **sg_list, int *num_sg) | |
f51b7662 DV |
90 | { |
91 | struct sg_table st; | |
92 | struct scatterlist *sg; | |
93 | int i; | |
94 | ||
4080775b | 95 | if (*sg_list) |
fefaa70f DV |
96 | return 0; /* already mapped (for e.g. resume */ |
97 | ||
4080775b | 98 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
f51b7662 | 99 | |
4080775b | 100 | if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) |
831cd445 | 101 | goto err; |
f51b7662 | 102 | |
4080775b | 103 | *sg_list = sg = st.sgl; |
f51b7662 | 104 | |
4080775b DV |
105 | for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) |
106 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); | |
f51b7662 | 107 | |
4080775b DV |
108 | *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, |
109 | num_entries, PCI_DMA_BIDIRECTIONAL); | |
110 | if (unlikely(!*num_sg)) | |
831cd445 CW |
111 | goto err; |
112 | ||
f51b7662 | 113 | return 0; |
831cd445 CW |
114 | |
115 | err: | |
116 | sg_free_table(&st); | |
117 | return -ENOMEM; | |
f51b7662 | 118 | } |
4080775b | 119 | EXPORT_SYMBOL(intel_gtt_map_memory); |
f51b7662 | 120 | |
4080775b | 121 | void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
f51b7662 | 122 | { |
4080775b | 123 | struct sg_table st; |
f51b7662 DV |
124 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
125 | ||
4080775b DV |
126 | pci_unmap_sg(intel_private.pcidev, sg_list, |
127 | num_sg, PCI_DMA_BIDIRECTIONAL); | |
128 | ||
129 | st.sgl = sg_list; | |
130 | st.orig_nents = st.nents = num_sg; | |
131 | ||
132 | sg_free_table(&st); | |
f51b7662 | 133 | } |
4080775b | 134 | EXPORT_SYMBOL(intel_gtt_unmap_memory); |
f51b7662 | 135 | |
ffdd7510 | 136 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
137 | { |
138 | return; | |
139 | } | |
140 | ||
141 | /* Exists to support ARGB cursors */ | |
142 | static struct page *i8xx_alloc_pages(void) | |
143 | { | |
144 | struct page *page; | |
145 | ||
146 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
147 | if (page == NULL) | |
148 | return NULL; | |
149 | ||
150 | if (set_pages_uc(page, 4) < 0) { | |
151 | set_pages_wb(page, 4); | |
152 | __free_pages(page, 2); | |
153 | return NULL; | |
154 | } | |
155 | get_page(page); | |
156 | atomic_inc(&agp_bridge->current_memory_agp); | |
157 | return page; | |
158 | } | |
159 | ||
160 | static void i8xx_destroy_pages(struct page *page) | |
161 | { | |
162 | if (page == NULL) | |
163 | return; | |
164 | ||
165 | set_pages_wb(page, 4); | |
166 | put_page(page); | |
167 | __free_pages(page, 2); | |
168 | atomic_dec(&agp_bridge->current_memory_agp); | |
169 | } | |
170 | ||
820647b9 DV |
171 | #define I810_GTT_ORDER 4 |
172 | static int i810_setup(void) | |
173 | { | |
174 | u32 reg_addr; | |
175 | char *gtt_table; | |
176 | ||
177 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ | |
178 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); | |
179 | if (gtt_table == NULL) | |
180 | return -ENOMEM; | |
181 | intel_private.i81x_gtt_table = gtt_table; | |
182 | ||
183 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
184 | reg_addr &= 0xfff80000; | |
185 | ||
186 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
187 | if (!intel_private.registers) | |
188 | return -ENOMEM; | |
189 | ||
190 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, | |
191 | intel_private.registers+I810_PGETBL_CTL); | |
192 | ||
193 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; | |
194 | ||
195 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
196 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
197 | dev_info(&intel_private.pcidev->dev, | |
198 | "detected 4MB dedicated video ram\n"); | |
199 | intel_private.num_dcache_entries = 1024; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static void i810_cleanup(void) | |
206 | { | |
207 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
208 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); | |
209 | } | |
210 | ||
ff26860f DV |
211 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
212 | int type) | |
f51b7662 | 213 | { |
625dd9d3 | 214 | int i; |
f51b7662 | 215 | |
ff26860f DV |
216 | if ((pg_start + mem->page_count) |
217 | > intel_private.num_dcache_entries) | |
218 | return -EINVAL; | |
625dd9d3 | 219 | |
ff26860f DV |
220 | if (!mem->is_flushed) |
221 | global_cache_flush(); | |
f51b7662 | 222 | |
ff26860f DV |
223 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
224 | dma_addr_t addr = i << PAGE_SHIFT; | |
225 | intel_private.driver->write_entry(addr, | |
226 | i, type); | |
f51b7662 | 227 | } |
ff26860f | 228 | readl(intel_private.gtt+i-1); |
f51b7662 | 229 | |
ff26860f | 230 | return 0; |
f51b7662 DV |
231 | } |
232 | ||
233 | /* | |
234 | * The i810/i830 requires a physical address to program its mouse | |
235 | * pointer into hardware. | |
236 | * However the Xserver still writes to it through the agp aperture. | |
237 | */ | |
238 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
239 | { | |
240 | struct agp_memory *new; | |
241 | struct page *page; | |
242 | ||
243 | switch (pg_count) { | |
244 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
245 | break; | |
246 | case 4: | |
247 | /* kludge to get 4 physical pages for ARGB cursor */ | |
248 | page = i8xx_alloc_pages(); | |
249 | break; | |
250 | default: | |
251 | return NULL; | |
252 | } | |
253 | ||
254 | if (page == NULL) | |
255 | return NULL; | |
256 | ||
257 | new = agp_create_memory(pg_count); | |
258 | if (new == NULL) | |
259 | return NULL; | |
260 | ||
261 | new->pages[0] = page; | |
262 | if (pg_count == 4) { | |
263 | /* kludge to get 4 physical pages for ARGB cursor */ | |
264 | new->pages[1] = new->pages[0] + 1; | |
265 | new->pages[2] = new->pages[1] + 1; | |
266 | new->pages[3] = new->pages[2] + 1; | |
267 | } | |
268 | new->page_count = pg_count; | |
269 | new->num_scratch_pages = pg_count; | |
270 | new->type = AGP_PHYS_MEMORY; | |
271 | new->physical = page_to_phys(new->pages[0]); | |
272 | return new; | |
273 | } | |
274 | ||
f51b7662 DV |
275 | static void intel_i810_free_by_type(struct agp_memory *curr) |
276 | { | |
277 | agp_free_key(curr->key); | |
278 | if (curr->type == AGP_PHYS_MEMORY) { | |
279 | if (curr->page_count == 4) | |
280 | i8xx_destroy_pages(curr->pages[0]); | |
281 | else { | |
282 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
283 | AGP_PAGE_DESTROY_UNMAP); | |
284 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
285 | AGP_PAGE_DESTROY_FREE); | |
286 | } | |
287 | agp_free_page_array(curr); | |
288 | } | |
289 | kfree(curr); | |
290 | } | |
291 | ||
0e87d2b0 DV |
292 | static int intel_gtt_setup_scratch_page(void) |
293 | { | |
294 | struct page *page; | |
295 | dma_addr_t dma_addr; | |
296 | ||
297 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
298 | if (page == NULL) | |
299 | return -ENOMEM; | |
300 | get_page(page); | |
301 | set_pages_uc(page, 1); | |
302 | ||
4080775b | 303 | if (intel_private.base.needs_dmar) { |
0e87d2b0 DV |
304 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
305 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
306 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) | |
307 | return -EINVAL; | |
308 | ||
309 | intel_private.scratch_page_dma = dma_addr; | |
310 | } else | |
311 | intel_private.scratch_page_dma = page_to_phys(page); | |
312 | ||
313 | intel_private.scratch_page = page; | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
625dd9d3 DV |
318 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
319 | unsigned int flags) | |
320 | { | |
321 | u32 pte_flags = I810_PTE_VALID; | |
322 | ||
323 | switch (flags) { | |
324 | case AGP_DCACHE_MEMORY: | |
325 | pte_flags |= I810_PTE_LOCAL; | |
326 | break; | |
327 | case AGP_USER_CACHED_MEMORY: | |
328 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
329 | break; | |
330 | } | |
331 | ||
332 | writel(addr | pte_flags, intel_private.gtt + entry); | |
333 | } | |
334 | ||
7bdc9ab0 | 335 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
820647b9 DV |
336 | {32, 8192, 3}, |
337 | {64, 16384, 4}, | |
f51b7662 | 338 | {128, 32768, 5}, |
f51b7662 DV |
339 | {256, 65536, 6}, |
340 | {512, 131072, 7}, | |
341 | }; | |
342 | ||
c64f7ba5 | 343 | static unsigned int intel_gtt_stolen_size(void) |
f51b7662 DV |
344 | { |
345 | u16 gmch_ctrl; | |
f51b7662 DV |
346 | u8 rdct; |
347 | int local = 0; | |
348 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
d8d9abcd | 349 | unsigned int stolen_size = 0; |
f51b7662 | 350 | |
820647b9 DV |
351 | if (INTEL_GTT_GEN == 1) |
352 | return 0; /* no stolen mem on i81x */ | |
353 | ||
d7cca2f7 DV |
354 | pci_read_config_word(intel_private.bridge_dev, |
355 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 356 | |
d7cca2f7 DV |
357 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
358 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
359 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
360 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 361 | stolen_size = KB(512); |
f51b7662 DV |
362 | break; |
363 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 364 | stolen_size = MB(1); |
f51b7662 DV |
365 | break; |
366 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 367 | stolen_size = MB(8); |
f51b7662 DV |
368 | break; |
369 | case I830_GMCH_GMS_LOCAL: | |
370 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 371 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
372 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
373 | local = 1; | |
374 | break; | |
375 | default: | |
d8d9abcd | 376 | stolen_size = 0; |
f51b7662 DV |
377 | break; |
378 | } | |
1a997ff2 | 379 | } else if (INTEL_GTT_GEN == 6) { |
f51b7662 DV |
380 | /* |
381 | * SandyBridge has new memory control reg at 0x50.w | |
382 | */ | |
383 | u16 snb_gmch_ctl; | |
384 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
385 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
386 | case SNB_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 387 | stolen_size = MB(32); |
f51b7662 DV |
388 | break; |
389 | case SNB_GMCH_GMS_STOLEN_64M: | |
d8d9abcd | 390 | stolen_size = MB(64); |
f51b7662 DV |
391 | break; |
392 | case SNB_GMCH_GMS_STOLEN_96M: | |
d8d9abcd | 393 | stolen_size = MB(96); |
f51b7662 DV |
394 | break; |
395 | case SNB_GMCH_GMS_STOLEN_128M: | |
d8d9abcd | 396 | stolen_size = MB(128); |
f51b7662 DV |
397 | break; |
398 | case SNB_GMCH_GMS_STOLEN_160M: | |
d8d9abcd | 399 | stolen_size = MB(160); |
f51b7662 DV |
400 | break; |
401 | case SNB_GMCH_GMS_STOLEN_192M: | |
d8d9abcd | 402 | stolen_size = MB(192); |
f51b7662 DV |
403 | break; |
404 | case SNB_GMCH_GMS_STOLEN_224M: | |
d8d9abcd | 405 | stolen_size = MB(224); |
f51b7662 DV |
406 | break; |
407 | case SNB_GMCH_GMS_STOLEN_256M: | |
d8d9abcd | 408 | stolen_size = MB(256); |
f51b7662 DV |
409 | break; |
410 | case SNB_GMCH_GMS_STOLEN_288M: | |
d8d9abcd | 411 | stolen_size = MB(288); |
f51b7662 DV |
412 | break; |
413 | case SNB_GMCH_GMS_STOLEN_320M: | |
d8d9abcd | 414 | stolen_size = MB(320); |
f51b7662 DV |
415 | break; |
416 | case SNB_GMCH_GMS_STOLEN_352M: | |
d8d9abcd | 417 | stolen_size = MB(352); |
f51b7662 DV |
418 | break; |
419 | case SNB_GMCH_GMS_STOLEN_384M: | |
d8d9abcd | 420 | stolen_size = MB(384); |
f51b7662 DV |
421 | break; |
422 | case SNB_GMCH_GMS_STOLEN_416M: | |
d8d9abcd | 423 | stolen_size = MB(416); |
f51b7662 DV |
424 | break; |
425 | case SNB_GMCH_GMS_STOLEN_448M: | |
d8d9abcd | 426 | stolen_size = MB(448); |
f51b7662 DV |
427 | break; |
428 | case SNB_GMCH_GMS_STOLEN_480M: | |
d8d9abcd | 429 | stolen_size = MB(480); |
f51b7662 DV |
430 | break; |
431 | case SNB_GMCH_GMS_STOLEN_512M: | |
d8d9abcd | 432 | stolen_size = MB(512); |
f51b7662 DV |
433 | break; |
434 | } | |
435 | } else { | |
436 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
437 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 438 | stolen_size = MB(1); |
f51b7662 DV |
439 | break; |
440 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 441 | stolen_size = MB(4); |
f51b7662 DV |
442 | break; |
443 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 444 | stolen_size = MB(8); |
f51b7662 DV |
445 | break; |
446 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 447 | stolen_size = MB(16); |
f51b7662 DV |
448 | break; |
449 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 450 | stolen_size = MB(32); |
f51b7662 DV |
451 | break; |
452 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 453 | stolen_size = MB(48); |
f51b7662 DV |
454 | break; |
455 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 456 | stolen_size = MB(64); |
f51b7662 DV |
457 | break; |
458 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 459 | stolen_size = MB(128); |
f51b7662 DV |
460 | break; |
461 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 462 | stolen_size = MB(256); |
f51b7662 DV |
463 | break; |
464 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 465 | stolen_size = MB(96); |
f51b7662 DV |
466 | break; |
467 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 468 | stolen_size = MB(160); |
f51b7662 DV |
469 | break; |
470 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 471 | stolen_size = MB(224); |
f51b7662 DV |
472 | break; |
473 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 474 | stolen_size = MB(352); |
f51b7662 DV |
475 | break; |
476 | default: | |
d8d9abcd | 477 | stolen_size = 0; |
f51b7662 DV |
478 | break; |
479 | } | |
480 | } | |
1784a5fb | 481 | |
1b6064d7 | 482 | if (stolen_size > 0) { |
d7cca2f7 | 483 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 484 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 485 | } else { |
d7cca2f7 | 486 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 487 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 488 | stolen_size = 0; |
f51b7662 DV |
489 | } |
490 | ||
c64f7ba5 | 491 | return stolen_size; |
f51b7662 DV |
492 | } |
493 | ||
20172842 DV |
494 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
495 | { | |
496 | u32 pgetbl_ctl, pgetbl_ctl2; | |
497 | ||
498 | /* ensure that ppgtt is disabled */ | |
499 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); | |
500 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; | |
501 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); | |
502 | ||
503 | /* write the new ggtt size */ | |
504 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
505 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; | |
506 | pgetbl_ctl |= size_flag; | |
507 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); | |
508 | } | |
509 | ||
510 | static unsigned int i965_gtt_total_entries(void) | |
fbe40783 DV |
511 | { |
512 | int size; | |
20172842 DV |
513 | u32 pgetbl_ctl; |
514 | u16 gmch_ctl; | |
fbe40783 | 515 | |
20172842 DV |
516 | pci_read_config_word(intel_private.bridge_dev, |
517 | I830_GMCH_CTRL, &gmch_ctl); | |
fbe40783 | 518 | |
20172842 DV |
519 | if (INTEL_GTT_GEN == 5) { |
520 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { | |
521 | case G4x_GMCH_SIZE_1M: | |
522 | case G4x_GMCH_SIZE_VT_1M: | |
523 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); | |
fbe40783 | 524 | break; |
20172842 DV |
525 | case G4x_GMCH_SIZE_VT_1_5M: |
526 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); | |
fbe40783 | 527 | break; |
20172842 DV |
528 | case G4x_GMCH_SIZE_2M: |
529 | case G4x_GMCH_SIZE_VT_2M: | |
530 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); | |
fbe40783 | 531 | break; |
fbe40783 | 532 | } |
20172842 | 533 | } |
e5e408fc | 534 | |
20172842 DV |
535 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
536 | ||
537 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
538 | case I965_PGETBL_SIZE_128KB: | |
539 | size = KB(128); | |
540 | break; | |
541 | case I965_PGETBL_SIZE_256KB: | |
542 | size = KB(256); | |
543 | break; | |
544 | case I965_PGETBL_SIZE_512KB: | |
545 | size = KB(512); | |
546 | break; | |
547 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ | |
548 | case I965_PGETBL_SIZE_1MB: | |
549 | size = KB(1024); | |
550 | break; | |
551 | case I965_PGETBL_SIZE_2MB: | |
552 | size = KB(2048); | |
553 | break; | |
554 | case I965_PGETBL_SIZE_1_5MB: | |
555 | size = KB(1024 + 512); | |
556 | break; | |
557 | default: | |
558 | dev_info(&intel_private.pcidev->dev, | |
559 | "unknown page table size, assuming 512KB\n"); | |
560 | size = KB(512); | |
561 | } | |
562 | ||
563 | return size/4; | |
564 | } | |
565 | ||
566 | static unsigned int intel_gtt_total_entries(void) | |
567 | { | |
568 | int size; | |
569 | ||
570 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) | |
571 | return i965_gtt_total_entries(); | |
572 | else if (INTEL_GTT_GEN == 6) { | |
210b23c2 DV |
573 | u16 snb_gmch_ctl; |
574 | ||
575 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
576 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | |
577 | default: | |
578 | case SNB_GTT_SIZE_0M: | |
579 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | |
580 | size = MB(0); | |
581 | break; | |
582 | case SNB_GTT_SIZE_1M: | |
583 | size = MB(1); | |
584 | break; | |
585 | case SNB_GTT_SIZE_2M: | |
586 | size = MB(2); | |
587 | break; | |
588 | } | |
e5e408fc | 589 | return size/4; |
fbe40783 DV |
590 | } else { |
591 | /* On previous hardware, the GTT size was just what was | |
592 | * required to map the aperture. | |
593 | */ | |
e5e408fc | 594 | return intel_private.base.gtt_mappable_entries; |
fbe40783 | 595 | } |
fbe40783 | 596 | } |
fbe40783 | 597 | |
1784a5fb DV |
598 | static unsigned int intel_gtt_mappable_entries(void) |
599 | { | |
600 | unsigned int aperture_size; | |
1784a5fb | 601 | |
820647b9 DV |
602 | if (INTEL_GTT_GEN == 1) { |
603 | u32 smram_miscc; | |
604 | ||
605 | pci_read_config_dword(intel_private.bridge_dev, | |
606 | I810_SMRAM_MISCC, &smram_miscc); | |
607 | ||
608 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) | |
609 | == I810_GFX_MEM_WIN_32M) | |
610 | aperture_size = MB(32); | |
611 | else | |
612 | aperture_size = MB(64); | |
613 | } else if (INTEL_GTT_GEN == 2) { | |
b1c5b0f8 | 614 | u16 gmch_ctrl; |
1784a5fb | 615 | |
b1c5b0f8 CW |
616 | pci_read_config_word(intel_private.bridge_dev, |
617 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 618 | |
1784a5fb | 619 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 620 | aperture_size = MB(64); |
1784a5fb | 621 | else |
b1c5b0f8 | 622 | aperture_size = MB(128); |
239918f7 | 623 | } else { |
1784a5fb DV |
624 | /* 9xx supports large sizes, just look at the length */ |
625 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
626 | } |
627 | ||
628 | return aperture_size >> PAGE_SHIFT; | |
629 | } | |
630 | ||
0e87d2b0 DV |
631 | static void intel_gtt_teardown_scratch_page(void) |
632 | { | |
633 | set_pages_wb(intel_private.scratch_page, 1); | |
634 | pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, | |
635 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
636 | put_page(intel_private.scratch_page); | |
637 | __free_page(intel_private.scratch_page); | |
638 | } | |
639 | ||
640 | static void intel_gtt_cleanup(void) | |
641 | { | |
ae83dd5c DV |
642 | intel_private.driver->cleanup(); |
643 | ||
0e87d2b0 DV |
644 | iounmap(intel_private.gtt); |
645 | iounmap(intel_private.registers); | |
625dd9d3 | 646 | |
0e87d2b0 DV |
647 | intel_gtt_teardown_scratch_page(); |
648 | } | |
649 | ||
1784a5fb DV |
650 | static int intel_gtt_init(void) |
651 | { | |
f67eab66 | 652 | u32 gtt_map_size; |
3b15a9d7 DV |
653 | int ret; |
654 | ||
3b15a9d7 DV |
655 | ret = intel_private.driver->setup(); |
656 | if (ret != 0) | |
657 | return ret; | |
f67eab66 DV |
658 | |
659 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
660 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); | |
661 | ||
b3eafc5a DV |
662 | /* save the PGETBL reg for resume */ |
663 | intel_private.PGETBL_save = | |
664 | readl(intel_private.registers+I810_PGETBL_CTL) | |
665 | & ~I810_PGETBL_ENABLED; | |
100519e2 CW |
666 | /* we only ever restore the register when enabling the PGTBL... */ |
667 | if (HAS_PGTBL_EN) | |
668 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; | |
b3eafc5a | 669 | |
0af9e92e DV |
670 | dev_info(&intel_private.bridge_dev->dev, |
671 | "detected gtt size: %dK total, %dK mappable\n", | |
672 | intel_private.base.gtt_total_entries * 4, | |
673 | intel_private.base.gtt_mappable_entries * 4); | |
674 | ||
f67eab66 DV |
675 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
676 | ||
677 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, | |
678 | gtt_map_size); | |
679 | if (!intel_private.gtt) { | |
ae83dd5c | 680 | intel_private.driver->cleanup(); |
f67eab66 DV |
681 | iounmap(intel_private.registers); |
682 | return -ENOMEM; | |
683 | } | |
684 | ||
685 | global_cache_flush(); /* FIXME: ? */ | |
686 | ||
c64f7ba5 | 687 | intel_private.base.stolen_size = intel_gtt_stolen_size(); |
1784a5fb | 688 | |
a46f3108 DA |
689 | intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
690 | ||
0e87d2b0 DV |
691 | ret = intel_gtt_setup_scratch_page(); |
692 | if (ret != 0) { | |
693 | intel_gtt_cleanup(); | |
694 | return ret; | |
695 | } | |
696 | ||
1784a5fb DV |
697 | return 0; |
698 | } | |
699 | ||
3e921f98 DV |
700 | static int intel_fake_agp_fetch_size(void) |
701 | { | |
9e76e7b8 | 702 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
703 | unsigned int aper_size; |
704 | int i; | |
3e921f98 DV |
705 | |
706 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) | |
707 | / MB(1); | |
708 | ||
709 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 710 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
711 | agp_bridge->current_size = |
712 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
713 | return aper_size; |
714 | } | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
ae83dd5c | 720 | static void i830_cleanup(void) |
f51b7662 | 721 | { |
f51b7662 DV |
722 | } |
723 | ||
724 | /* The chipset_flush interface needs to get data that has already been | |
725 | * flushed out of the CPU all the way out to main memory, because the GPU | |
726 | * doesn't snoop those buffers. | |
727 | * | |
728 | * The 8xx series doesn't have the same lovely interface for flushing the | |
729 | * chipset write buffers that the later chips do. According to the 865 | |
730 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
731 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
732 | * that it'll push whatever was in there out. It appears to work. | |
733 | */ | |
1b263f24 | 734 | static void i830_chipset_flush(void) |
f51b7662 | 735 | { |
bdb8b975 CW |
736 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
737 | ||
738 | /* Forcibly evict everything from the CPU write buffers. | |
739 | * clflush appears to be insufficient. | |
740 | */ | |
741 | wbinvd_on_all_cpus(); | |
742 | ||
743 | /* Now we've only seen documents for this magic bit on 855GM, | |
744 | * we hope it exists for the other gen2 chipsets... | |
745 | * | |
746 | * Also works as advertised on my 845G. | |
747 | */ | |
748 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), | |
749 | intel_private.registers+I830_HIC); | |
f51b7662 | 750 | |
bdb8b975 CW |
751 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
752 | if (time_after(jiffies, timeout)) | |
753 | break; | |
f51b7662 | 754 | |
bdb8b975 CW |
755 | udelay(50); |
756 | } | |
f51b7662 DV |
757 | } |
758 | ||
351bb278 DV |
759 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
760 | unsigned int flags) | |
761 | { | |
762 | u32 pte_flags = I810_PTE_VALID; | |
625dd9d3 | 763 | |
b47cf66f | 764 | if (flags == AGP_USER_CACHED_MEMORY) |
351bb278 | 765 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
351bb278 DV |
766 | |
767 | writel(addr | pte_flags, intel_private.gtt + entry); | |
768 | } | |
769 | ||
e380f60b | 770 | static bool intel_enable_gtt(void) |
f51b7662 | 771 | { |
3f08e4ef | 772 | u32 gma_addr; |
e380f60b | 773 | u8 __iomem *reg; |
f51b7662 | 774 | |
820647b9 | 775 | if (INTEL_GTT_GEN <= 2) |
2d2430cf DV |
776 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, |
777 | &gma_addr); | |
778 | else | |
779 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | |
780 | &gma_addr); | |
781 | ||
73800422 | 782 | intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
f51b7662 | 783 | |
e380f60b CW |
784 | if (INTEL_GTT_GEN >= 6) |
785 | return true; | |
786 | ||
100519e2 CW |
787 | if (INTEL_GTT_GEN == 2) { |
788 | u16 gmch_ctrl; | |
73800422 | 789 | |
100519e2 CW |
790 | pci_read_config_word(intel_private.bridge_dev, |
791 | I830_GMCH_CTRL, &gmch_ctrl); | |
792 | gmch_ctrl |= I830_GMCH_ENABLED; | |
793 | pci_write_config_word(intel_private.bridge_dev, | |
794 | I830_GMCH_CTRL, gmch_ctrl); | |
795 | ||
796 | pci_read_config_word(intel_private.bridge_dev, | |
797 | I830_GMCH_CTRL, &gmch_ctrl); | |
798 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { | |
799 | dev_err(&intel_private.pcidev->dev, | |
800 | "failed to enable the GTT: GMCH_CTRL=%x\n", | |
801 | gmch_ctrl); | |
802 | return false; | |
803 | } | |
e380f60b CW |
804 | } |
805 | ||
c97689d8 CW |
806 | /* On the resume path we may be adjusting the PGTBL value, so |
807 | * be paranoid and flush all chipset write buffers... | |
808 | */ | |
809 | if (INTEL_GTT_GEN >= 3) | |
810 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
811 | ||
e380f60b | 812 | reg = intel_private.registers+I810_PGETBL_CTL; |
100519e2 CW |
813 | writel(intel_private.PGETBL_save, reg); |
814 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { | |
e380f60b | 815 | dev_err(&intel_private.pcidev->dev, |
100519e2 | 816 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
e380f60b CW |
817 | readl(reg), intel_private.PGETBL_save); |
818 | return false; | |
819 | } | |
820 | ||
c97689d8 CW |
821 | if (INTEL_GTT_GEN >= 3) |
822 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
823 | ||
e380f60b | 824 | return true; |
73800422 DV |
825 | } |
826 | ||
827 | static int i830_setup(void) | |
828 | { | |
829 | u32 reg_addr; | |
830 | ||
831 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
832 | reg_addr &= 0xfff80000; | |
833 | ||
834 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
835 | if (!intel_private.registers) |
836 | return -ENOMEM; | |
837 | ||
73800422 DV |
838 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
839 | ||
73800422 DV |
840 | return 0; |
841 | } | |
842 | ||
3b15a9d7 | 843 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 844 | { |
73800422 | 845 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 846 | agp_bridge->gatt_table = NULL; |
73800422 | 847 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
848 | |
849 | return 0; | |
850 | } | |
851 | ||
ffdd7510 | 852 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
853 | { |
854 | return 0; | |
855 | } | |
856 | ||
351bb278 | 857 | static int intel_fake_agp_configure(void) |
f51b7662 | 858 | { |
e380f60b CW |
859 | if (!intel_enable_gtt()) |
860 | return -EIO; | |
f51b7662 | 861 | |
bee4a186 | 862 | intel_private.clear_fake_agp = true; |
73800422 | 863 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
f51b7662 | 864 | |
f51b7662 DV |
865 | return 0; |
866 | } | |
867 | ||
5cbecafc | 868 | static bool i830_check_flags(unsigned int flags) |
f51b7662 | 869 | { |
5cbecafc DV |
870 | switch (flags) { |
871 | case 0: | |
872 | case AGP_PHYS_MEMORY: | |
873 | case AGP_USER_CACHED_MEMORY: | |
874 | case AGP_USER_MEMORY: | |
875 | return true; | |
876 | } | |
877 | ||
878 | return false; | |
879 | } | |
880 | ||
4080775b DV |
881 | void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
882 | unsigned int sg_len, | |
883 | unsigned int pg_start, | |
884 | unsigned int flags) | |
fefaa70f DV |
885 | { |
886 | struct scatterlist *sg; | |
887 | unsigned int len, m; | |
888 | int i, j; | |
889 | ||
890 | j = pg_start; | |
891 | ||
892 | /* sg may merge pages, but we have to separate | |
893 | * per-page addr for GTT */ | |
894 | for_each_sg(sg_list, sg, sg_len, i) { | |
895 | len = sg_dma_len(sg) >> PAGE_SHIFT; | |
896 | for (m = 0; m < len; m++) { | |
897 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
898 | intel_private.driver->write_entry(addr, | |
899 | j, flags); | |
900 | j++; | |
901 | } | |
902 | } | |
903 | readl(intel_private.gtt+j-1); | |
904 | } | |
4080775b DV |
905 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
906 | ||
907 | void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, | |
908 | struct page **pages, unsigned int flags) | |
909 | { | |
910 | int i, j; | |
911 | ||
912 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { | |
913 | dma_addr_t addr = page_to_phys(pages[i]); | |
914 | intel_private.driver->write_entry(addr, | |
915 | j, flags); | |
916 | } | |
917 | readl(intel_private.gtt+j-1); | |
918 | } | |
919 | EXPORT_SYMBOL(intel_gtt_insert_pages); | |
fefaa70f | 920 | |
5cbecafc DV |
921 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
922 | off_t pg_start, int type) | |
923 | { | |
f51b7662 | 924 | int ret = -EINVAL; |
f51b7662 | 925 | |
bee4a186 CW |
926 | if (intel_private.clear_fake_agp) { |
927 | int start = intel_private.base.stolen_size / PAGE_SIZE; | |
928 | int end = intel_private.base.gtt_mappable_entries; | |
929 | intel_gtt_clear_range(start, end - start); | |
930 | intel_private.clear_fake_agp = false; | |
931 | } | |
932 | ||
ff26860f DV |
933 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
934 | return i810_insert_dcache_entries(mem, pg_start, type); | |
935 | ||
f51b7662 DV |
936 | if (mem->page_count == 0) |
937 | goto out; | |
938 | ||
c64f7ba5 | 939 | if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) |
f51b7662 DV |
940 | goto out_err; |
941 | ||
f51b7662 DV |
942 | if (type != mem->type) |
943 | goto out_err; | |
944 | ||
5cbecafc | 945 | if (!intel_private.driver->check_flags(type)) |
f51b7662 DV |
946 | goto out_err; |
947 | ||
948 | if (!mem->is_flushed) | |
949 | global_cache_flush(); | |
950 | ||
4080775b DV |
951 | if (intel_private.base.needs_dmar) { |
952 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, | |
953 | &mem->sg_list, &mem->num_sg); | |
fefaa70f DV |
954 | if (ret != 0) |
955 | return ret; | |
956 | ||
957 | intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, | |
958 | pg_start, type); | |
4080775b DV |
959 | } else |
960 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, | |
961 | type); | |
f51b7662 DV |
962 | |
963 | out: | |
964 | ret = 0; | |
965 | out_err: | |
966 | mem->is_flushed = true; | |
967 | return ret; | |
968 | } | |
969 | ||
4080775b DV |
970 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
971 | { | |
972 | unsigned int i; | |
973 | ||
974 | for (i = first_entry; i < (first_entry + num_entries); i++) { | |
975 | intel_private.driver->write_entry(intel_private.scratch_page_dma, | |
976 | i, 0); | |
977 | } | |
978 | readl(intel_private.gtt+i-1); | |
979 | } | |
980 | EXPORT_SYMBOL(intel_gtt_clear_range); | |
981 | ||
5cbecafc DV |
982 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
983 | off_t pg_start, int type) | |
f51b7662 | 984 | { |
f51b7662 DV |
985 | if (mem->page_count == 0) |
986 | return 0; | |
987 | ||
d15eda5c DA |
988 | intel_gtt_clear_range(pg_start, mem->page_count); |
989 | ||
4080775b DV |
990 | if (intel_private.base.needs_dmar) { |
991 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); | |
992 | mem->sg_list = NULL; | |
993 | mem->num_sg = 0; | |
f51b7662 | 994 | } |
4080775b | 995 | |
f51b7662 DV |
996 | return 0; |
997 | } | |
998 | ||
ffdd7510 DV |
999 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
1000 | int type) | |
f51b7662 | 1001 | { |
625dd9d3 DV |
1002 | struct agp_memory *new; |
1003 | ||
1004 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { | |
1005 | if (pg_count != intel_private.num_dcache_entries) | |
1006 | return NULL; | |
1007 | ||
1008 | new = agp_create_memory(1); | |
1009 | if (new == NULL) | |
1010 | return NULL; | |
1011 | ||
1012 | new->type = AGP_DCACHE_MEMORY; | |
1013 | new->page_count = pg_count; | |
1014 | new->num_scratch_pages = 0; | |
1015 | agp_free_page_array(new); | |
1016 | return new; | |
1017 | } | |
f51b7662 DV |
1018 | if (type == AGP_PHYS_MEMORY) |
1019 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1020 | /* always return NULL for other allocation types for now */ | |
1021 | return NULL; | |
1022 | } | |
1023 | ||
1024 | static int intel_alloc_chipset_flush_resource(void) | |
1025 | { | |
1026 | int ret; | |
d7cca2f7 | 1027 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1028 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1029 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1030 | |
1031 | return ret; | |
1032 | } | |
1033 | ||
1034 | static void intel_i915_setup_chipset_flush(void) | |
1035 | { | |
1036 | int ret; | |
1037 | u32 temp; | |
1038 | ||
d7cca2f7 | 1039 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1040 | if (!(temp & 0x1)) { |
1041 | intel_alloc_chipset_flush_resource(); | |
1042 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1043 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1044 | } else { |
1045 | temp &= ~1; | |
1046 | ||
1047 | intel_private.resource_valid = 1; | |
1048 | intel_private.ifp_resource.start = temp; | |
1049 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1050 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1051 | /* some BIOSes reserve this area in a pnp some don't */ | |
1052 | if (ret) | |
1053 | intel_private.resource_valid = 0; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | static void intel_i965_g33_setup_chipset_flush(void) | |
1058 | { | |
1059 | u32 temp_hi, temp_lo; | |
1060 | int ret; | |
1061 | ||
d7cca2f7 DV |
1062 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1063 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1064 | |
1065 | if (!(temp_lo & 0x1)) { | |
1066 | ||
1067 | intel_alloc_chipset_flush_resource(); | |
1068 | ||
1069 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1070 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1071 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1072 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1073 | } else { |
1074 | u64 l64; | |
1075 | ||
1076 | temp_lo &= ~0x1; | |
1077 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1078 | ||
1079 | intel_private.resource_valid = 1; | |
1080 | intel_private.ifp_resource.start = l64; | |
1081 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1082 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1083 | /* some BIOSes reserve this area in a pnp some don't */ | |
1084 | if (ret) | |
1085 | intel_private.resource_valid = 0; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static void intel_i9xx_setup_flush(void) | |
1090 | { | |
1091 | /* return if already configured */ | |
1092 | if (intel_private.ifp_resource.start) | |
1093 | return; | |
1094 | ||
1a997ff2 | 1095 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1096 | return; |
1097 | ||
1098 | /* setup a resource for this object */ | |
1099 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1100 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1101 | ||
1102 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1103 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1104 | intel_i965_g33_setup_chipset_flush(); |
1105 | } else { | |
1106 | intel_i915_setup_chipset_flush(); | |
1107 | } | |
1108 | ||
df51e7aa | 1109 | if (intel_private.ifp_resource.start) |
f51b7662 | 1110 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1111 | if (!intel_private.i9xx_flush_page) |
1112 | dev_err(&intel_private.pcidev->dev, | |
1113 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1114 | } |
1115 | ||
ae83dd5c DV |
1116 | static void i9xx_cleanup(void) |
1117 | { | |
1118 | if (intel_private.i9xx_flush_page) | |
1119 | iounmap(intel_private.i9xx_flush_page); | |
1120 | if (intel_private.resource_valid) | |
1121 | release_resource(&intel_private.ifp_resource); | |
1122 | intel_private.ifp_resource.start = 0; | |
1123 | intel_private.resource_valid = 0; | |
1124 | } | |
1125 | ||
1b263f24 | 1126 | static void i9xx_chipset_flush(void) |
f51b7662 DV |
1127 | { |
1128 | if (intel_private.i9xx_flush_page) | |
1129 | writel(1, intel_private.i9xx_flush_page); | |
1130 | } | |
1131 | ||
71f45660 CW |
1132 | static void i965_write_entry(dma_addr_t addr, |
1133 | unsigned int entry, | |
a6963596 DV |
1134 | unsigned int flags) |
1135 | { | |
71f45660 CW |
1136 | u32 pte_flags; |
1137 | ||
1138 | pte_flags = I810_PTE_VALID; | |
1139 | if (flags == AGP_USER_CACHED_MEMORY) | |
1140 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
1141 | ||
a6963596 DV |
1142 | /* Shift high bits down */ |
1143 | addr |= (addr >> 28) & 0xf0; | |
71f45660 | 1144 | writel(addr | pte_flags, intel_private.gtt + entry); |
a6963596 DV |
1145 | } |
1146 | ||
90cb149e DV |
1147 | static bool gen6_check_flags(unsigned int flags) |
1148 | { | |
1149 | return true; | |
1150 | } | |
1151 | ||
97ef1bdd DV |
1152 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
1153 | unsigned int flags) | |
1154 | { | |
1155 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; | |
1156 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | |
1157 | u32 pte_flags; | |
1158 | ||
897ef192 | 1159 | if (type_mask == AGP_USER_MEMORY) |
85ccc35b | 1160 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
97ef1bdd | 1161 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
d1108525 | 1162 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
97ef1bdd DV |
1163 | if (gfdt) |
1164 | pte_flags |= GEN6_PTE_GFDT; | |
1165 | } else { /* set 'normal'/'cached' to LLC by default */ | |
d1108525 | 1166 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
97ef1bdd DV |
1167 | if (gfdt) |
1168 | pte_flags |= GEN6_PTE_GFDT; | |
1169 | } | |
1170 | ||
1171 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1172 | addr |= (addr >> 28) & 0xff0; | |
1173 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1174 | } | |
1175 | ||
ae83dd5c DV |
1176 | static void gen6_cleanup(void) |
1177 | { | |
1178 | } | |
1179 | ||
2d2430cf | 1180 | static int i9xx_setup(void) |
f51b7662 | 1181 | { |
2d2430cf | 1182 | u32 reg_addr; |
f51b7662 | 1183 | |
2d2430cf | 1184 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
f51b7662 | 1185 | |
2d2430cf | 1186 | reg_addr &= 0xfff80000; |
f1befe71 | 1187 | |
2d2430cf | 1188 | intel_private.registers = ioremap(reg_addr, 128 * 4096); |
ccc4e67b | 1189 | if (!intel_private.registers) |
f51b7662 DV |
1190 | return -ENOMEM; |
1191 | ||
2d2430cf DV |
1192 | if (INTEL_GTT_GEN == 3) { |
1193 | u32 gtt_addr; | |
3f08e4ef | 1194 | |
2d2430cf DV |
1195 | pci_read_config_dword(intel_private.pcidev, |
1196 | I915_PTEADDR, >t_addr); | |
1197 | intel_private.gtt_bus_addr = gtt_addr; | |
1198 | } else { | |
1199 | u32 gtt_offset; | |
1200 | ||
1201 | switch (INTEL_GTT_GEN) { | |
1202 | case 5: | |
1203 | case 6: | |
1204 | gtt_offset = MB(2); | |
1205 | break; | |
1206 | case 4: | |
1207 | default: | |
1208 | gtt_offset = KB(512); | |
1209 | break; | |
1210 | } | |
1211 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; | |
1212 | } | |
1213 | ||
1214 | intel_i9xx_setup_flush(); | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
e9b1cc81 | 1219 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
f51b7662 | 1220 | .owner = THIS_MODULE, |
f51b7662 | 1221 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1222 | .aperture_sizes = intel_fake_agp_sizes, |
1223 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
a6963596 | 1224 | .configure = intel_fake_agp_configure, |
3e921f98 | 1225 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1226 | .cleanup = intel_gtt_cleanup, |
ffdd7510 | 1227 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1228 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1229 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1230 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
450f2b3d DV |
1231 | .insert_memory = intel_fake_agp_insert_entries, |
1232 | .remove_memory = intel_fake_agp_remove_entries, | |
ffdd7510 | 1233 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1234 | .free_by_type = intel_i810_free_by_type, |
1235 | .agp_alloc_page = agp_generic_alloc_page, | |
1236 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1237 | .agp_destroy_page = agp_generic_destroy_page, | |
1238 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f51b7662 | 1239 | }; |
02c026ce | 1240 | |
bdd30729 DV |
1241 | static const struct intel_gtt_driver i81x_gtt_driver = { |
1242 | .gen = 1, | |
820647b9 | 1243 | .has_pgtbl_enable = 1, |
22533b49 | 1244 | .dma_mask_size = 32, |
820647b9 DV |
1245 | .setup = i810_setup, |
1246 | .cleanup = i810_cleanup, | |
625dd9d3 DV |
1247 | .check_flags = i830_check_flags, |
1248 | .write_entry = i810_write_entry, | |
bdd30729 | 1249 | }; |
1a997ff2 DV |
1250 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1251 | .gen = 2, | |
100519e2 | 1252 | .has_pgtbl_enable = 1, |
73800422 | 1253 | .setup = i830_setup, |
ae83dd5c | 1254 | .cleanup = i830_cleanup, |
351bb278 | 1255 | .write_entry = i830_write_entry, |
22533b49 | 1256 | .dma_mask_size = 32, |
5cbecafc | 1257 | .check_flags = i830_check_flags, |
1b263f24 | 1258 | .chipset_flush = i830_chipset_flush, |
1a997ff2 DV |
1259 | }; |
1260 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1261 | .gen = 3, | |
100519e2 | 1262 | .has_pgtbl_enable = 1, |
2d2430cf | 1263 | .setup = i9xx_setup, |
ae83dd5c | 1264 | .cleanup = i9xx_cleanup, |
351bb278 | 1265 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
625dd9d3 | 1266 | .write_entry = i830_write_entry, |
22533b49 | 1267 | .dma_mask_size = 32, |
fefaa70f | 1268 | .check_flags = i830_check_flags, |
1b263f24 | 1269 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1270 | }; |
1271 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1272 | .gen = 3, | |
1273 | .is_g33 = 1, | |
2d2430cf | 1274 | .setup = i9xx_setup, |
ae83dd5c | 1275 | .cleanup = i9xx_cleanup, |
a6963596 | 1276 | .write_entry = i965_write_entry, |
22533b49 | 1277 | .dma_mask_size = 36, |
450f2b3d | 1278 | .check_flags = i830_check_flags, |
1b263f24 | 1279 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1280 | }; |
1281 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1282 | .gen = 3, | |
1283 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1284 | .setup = i9xx_setup, |
ae83dd5c | 1285 | .cleanup = i9xx_cleanup, |
a6963596 | 1286 | .write_entry = i965_write_entry, |
22533b49 | 1287 | .dma_mask_size = 36, |
450f2b3d | 1288 | .check_flags = i830_check_flags, |
1b263f24 | 1289 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1290 | }; |
1291 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1292 | .gen = 4, | |
100519e2 | 1293 | .has_pgtbl_enable = 1, |
2d2430cf | 1294 | .setup = i9xx_setup, |
ae83dd5c | 1295 | .cleanup = i9xx_cleanup, |
a6963596 | 1296 | .write_entry = i965_write_entry, |
22533b49 | 1297 | .dma_mask_size = 36, |
450f2b3d | 1298 | .check_flags = i830_check_flags, |
1b263f24 | 1299 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1300 | }; |
1301 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1302 | .gen = 5, | |
2d2430cf | 1303 | .setup = i9xx_setup, |
ae83dd5c | 1304 | .cleanup = i9xx_cleanup, |
a6963596 | 1305 | .write_entry = i965_write_entry, |
22533b49 | 1306 | .dma_mask_size = 36, |
450f2b3d | 1307 | .check_flags = i830_check_flags, |
1b263f24 | 1308 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1309 | }; |
1310 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1311 | .gen = 5, | |
1312 | .is_ironlake = 1, | |
2d2430cf | 1313 | .setup = i9xx_setup, |
ae83dd5c | 1314 | .cleanup = i9xx_cleanup, |
a6963596 | 1315 | .write_entry = i965_write_entry, |
22533b49 | 1316 | .dma_mask_size = 36, |
450f2b3d | 1317 | .check_flags = i830_check_flags, |
1b263f24 | 1318 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1319 | }; |
1320 | static const struct intel_gtt_driver sandybridge_gtt_driver = { | |
1321 | .gen = 6, | |
2d2430cf | 1322 | .setup = i9xx_setup, |
ae83dd5c | 1323 | .cleanup = gen6_cleanup, |
97ef1bdd | 1324 | .write_entry = gen6_write_entry, |
22533b49 | 1325 | .dma_mask_size = 40, |
90cb149e | 1326 | .check_flags = gen6_check_flags, |
1b263f24 | 1327 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1328 | }; |
1329 | ||
02c026ce DV |
1330 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1331 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1332 | * which one should be used if a gmch_chip_id is present. | |
1333 | */ | |
1334 | static const struct intel_gtt_driver_description { | |
1335 | unsigned int gmch_chip_id; | |
1336 | char *name; | |
1a997ff2 | 1337 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1338 | } intel_gtt_chipsets[] = { |
ff26860f | 1339 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
bdd30729 | 1340 | &i81x_gtt_driver}, |
ff26860f | 1341 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
bdd30729 | 1342 | &i81x_gtt_driver}, |
ff26860f | 1343 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
bdd30729 | 1344 | &i81x_gtt_driver}, |
ff26860f | 1345 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
bdd30729 | 1346 | &i81x_gtt_driver}, |
1a997ff2 | 1347 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
ff26860f | 1348 | &i8xx_gtt_driver}, |
53371eda | 1349 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
ff26860f | 1350 | &i8xx_gtt_driver}, |
1a997ff2 | 1351 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
ff26860f | 1352 | &i8xx_gtt_driver}, |
1a997ff2 | 1353 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
ff26860f | 1354 | &i8xx_gtt_driver}, |
1a997ff2 | 1355 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
ff26860f | 1356 | &i8xx_gtt_driver}, |
1a997ff2 | 1357 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
ff26860f | 1358 | &i915_gtt_driver }, |
1a997ff2 | 1359 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
ff26860f | 1360 | &i915_gtt_driver }, |
1a997ff2 | 1361 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
ff26860f | 1362 | &i915_gtt_driver }, |
1a997ff2 | 1363 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
ff26860f | 1364 | &i915_gtt_driver }, |
1a997ff2 | 1365 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
ff26860f | 1366 | &i915_gtt_driver }, |
1a997ff2 | 1367 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
ff26860f | 1368 | &i915_gtt_driver }, |
1a997ff2 | 1369 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
ff26860f | 1370 | &i965_gtt_driver }, |
1a997ff2 | 1371 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
ff26860f | 1372 | &i965_gtt_driver }, |
1a997ff2 | 1373 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
ff26860f | 1374 | &i965_gtt_driver }, |
1a997ff2 | 1375 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
ff26860f | 1376 | &i965_gtt_driver }, |
1a997ff2 | 1377 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
ff26860f | 1378 | &i965_gtt_driver }, |
1a997ff2 | 1379 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
ff26860f | 1380 | &i965_gtt_driver }, |
1a997ff2 | 1381 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
ff26860f | 1382 | &g33_gtt_driver }, |
1a997ff2 | 1383 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
ff26860f | 1384 | &g33_gtt_driver }, |
1a997ff2 | 1385 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
ff26860f | 1386 | &g33_gtt_driver }, |
1a997ff2 | 1387 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
ff26860f | 1388 | &pineview_gtt_driver }, |
1a997ff2 | 1389 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
ff26860f | 1390 | &pineview_gtt_driver }, |
1a997ff2 | 1391 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
ff26860f | 1392 | &g4x_gtt_driver }, |
1a997ff2 | 1393 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
ff26860f | 1394 | &g4x_gtt_driver }, |
1a997ff2 | 1395 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
ff26860f | 1396 | &g4x_gtt_driver }, |
1a997ff2 | 1397 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
ff26860f | 1398 | &g4x_gtt_driver }, |
1a997ff2 | 1399 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
ff26860f | 1400 | &g4x_gtt_driver }, |
e9e5f8e8 | 1401 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
ff26860f | 1402 | &g4x_gtt_driver }, |
1a997ff2 | 1403 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
ff26860f | 1404 | &g4x_gtt_driver }, |
02c026ce | 1405 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
ff26860f | 1406 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1407 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
ff26860f | 1408 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1409 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
ff26860f | 1410 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1411 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
ff26860f | 1412 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1413 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
ff26860f | 1414 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1415 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
ff26860f | 1416 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1417 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
ff26860f | 1418 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1419 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
ff26860f | 1420 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1421 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
ff26860f | 1422 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce DV |
1423 | { 0, NULL, NULL } |
1424 | }; | |
1425 | ||
1426 | static int find_gmch(u16 device) | |
1427 | { | |
1428 | struct pci_dev *gmch_device; | |
1429 | ||
1430 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1431 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1432 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1433 | device, gmch_device); | |
1434 | } | |
1435 | ||
1436 | if (!gmch_device) | |
1437 | return 0; | |
1438 | ||
1439 | intel_private.pcidev = gmch_device; | |
1440 | return 1; | |
1441 | } | |
1442 | ||
e2404e7c | 1443 | int intel_gmch_probe(struct pci_dev *pdev, |
02c026ce DV |
1444 | struct agp_bridge_data *bridge) |
1445 | { | |
1446 | int i, mask; | |
ff26860f | 1447 | intel_private.driver = NULL; |
02c026ce DV |
1448 | |
1449 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | |
1450 | if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
625dd9d3 | 1451 | intel_private.driver = |
1a997ff2 | 1452 | intel_gtt_chipsets[i].gtt_driver; |
02c026ce DV |
1453 | break; |
1454 | } | |
1455 | } | |
1456 | ||
ff26860f | 1457 | if (!intel_private.driver) |
02c026ce DV |
1458 | return 0; |
1459 | ||
ff26860f | 1460 | bridge->driver = &intel_fake_agp_driver; |
02c026ce DV |
1461 | bridge->dev_private_data = &intel_private; |
1462 | bridge->dev = pdev; | |
1463 | ||
d7cca2f7 DV |
1464 | intel_private.bridge_dev = pci_dev_get(pdev); |
1465 | ||
02c026ce DV |
1466 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
1467 | ||
22533b49 | 1468 | mask = intel_private.driver->dma_mask_size; |
02c026ce DV |
1469 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
1470 | dev_err(&intel_private.pcidev->dev, | |
1471 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1472 | else | |
1473 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1474 | DMA_BIT_MASK(mask)); | |
1475 | ||
820647b9 DV |
1476 | /*if (bridge->driver == &intel_810_driver) |
1477 | return 1;*/ | |
1784a5fb | 1478 | |
3b15a9d7 DV |
1479 | if (intel_gtt_init() != 0) |
1480 | return 0; | |
1784a5fb | 1481 | |
02c026ce DV |
1482 | return 1; |
1483 | } | |
e2404e7c | 1484 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1485 | |
c64f7ba5 | 1486 | const struct intel_gtt *intel_gtt_get(void) |
19966754 DV |
1487 | { |
1488 | return &intel_private.base; | |
1489 | } | |
1490 | EXPORT_SYMBOL(intel_gtt_get); | |
1491 | ||
40ce6575 DV |
1492 | void intel_gtt_chipset_flush(void) |
1493 | { | |
1494 | if (intel_private.driver->chipset_flush) | |
1495 | intel_private.driver->chipset_flush(); | |
1496 | } | |
1497 | EXPORT_SYMBOL(intel_gtt_chipset_flush); | |
1498 | ||
e2404e7c | 1499 | void intel_gmch_remove(struct pci_dev *pdev) |
02c026ce DV |
1500 | { |
1501 | if (intel_private.pcidev) | |
1502 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1503 | if (intel_private.bridge_dev) |
1504 | pci_dev_put(intel_private.bridge_dev); | |
02c026ce | 1505 | } |
e2404e7c DV |
1506 | EXPORT_SYMBOL(intel_gmch_remove); |
1507 | ||
1508 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); | |
1509 | MODULE_LICENSE("GPL and additional rights"); |