Commit | Line | Data |
---|---|---|
f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/pagemap.h> | |
23 | #include <linux/agp_backend.h> | |
24 | #include <asm/smp.h> | |
25 | #include "agp.h" | |
26 | #include "intel-agp.h" | |
27 | #include <linux/intel-gtt.h> | |
0ade6386 | 28 | #include <drm/intel-gtt.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
33 | * on the Intel IOMMU support (CONFIG_DMAR). | |
34 | * Only newer chipsets need to bother with this, of course. | |
35 | */ | |
36 | #ifdef CONFIG_DMAR | |
37 | #define USE_PCI_DMA_API 1 | |
0e87d2b0 DV |
38 | #else |
39 | #define USE_PCI_DMA_API 0 | |
f51b7662 DV |
40 | #endif |
41 | ||
42 | static const struct aper_size_info_fixed intel_i810_sizes[] = | |
43 | { | |
44 | {64, 16384, 4}, | |
45 | /* The 32M mode still requires a 64k gatt */ | |
46 | {32, 8192, 4} | |
47 | }; | |
48 | ||
49 | #define AGP_DCACHE_MEMORY 1 | |
50 | #define AGP_PHYS_MEMORY 2 | |
51 | #define INTEL_AGP_CACHED_MEMORY 3 | |
52 | ||
53 | static struct gatt_mask intel_i810_masks[] = | |
54 | { | |
55 | {.mask = I810_PTE_VALID, .type = 0}, | |
56 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
57 | {.mask = I810_PTE_VALID, .type = 0}, | |
58 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
59 | .type = INTEL_AGP_CACHED_MEMORY} | |
60 | }; | |
61 | ||
f8f235e5 ZW |
62 | #define INTEL_AGP_UNCACHED_MEMORY 0 |
63 | #define INTEL_AGP_CACHED_MEMORY_LLC 1 | |
64 | #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2 | |
65 | #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3 | |
66 | #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4 | |
67 | ||
1a997ff2 DV |
68 | struct intel_gtt_driver { |
69 | unsigned int gen : 8; | |
70 | unsigned int is_g33 : 1; | |
71 | unsigned int is_pineview : 1; | |
72 | unsigned int is_ironlake : 1; | |
100519e2 | 73 | unsigned int has_pgtbl_enable : 1; |
22533b49 | 74 | unsigned int dma_mask_size : 8; |
73800422 DV |
75 | /* Chipset specific GTT setup */ |
76 | int (*setup)(void); | |
ae83dd5c DV |
77 | /* This should undo anything done in ->setup() save the unmapping |
78 | * of the mmio register file, that's done in the generic code. */ | |
79 | void (*cleanup)(void); | |
351bb278 DV |
80 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
81 | /* Flags is a more or less chipset specific opaque value. | |
82 | * For chipsets that need to support old ums (non-gem) code, this | |
83 | * needs to be identical to the various supported agp memory types! */ | |
5cbecafc | 84 | bool (*check_flags)(unsigned int flags); |
1b263f24 | 85 | void (*chipset_flush)(void); |
1a997ff2 DV |
86 | }; |
87 | ||
f51b7662 | 88 | static struct _intel_private { |
0ade6386 | 89 | struct intel_gtt base; |
1a997ff2 | 90 | const struct intel_gtt_driver *driver; |
f51b7662 | 91 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 92 | struct pci_dev *bridge_dev; |
f51b7662 | 93 | u8 __iomem *registers; |
f67eab66 | 94 | phys_addr_t gtt_bus_addr; |
73800422 | 95 | phys_addr_t gma_bus_addr; |
b3eafc5a | 96 | u32 PGETBL_save; |
f51b7662 DV |
97 | u32 __iomem *gtt; /* I915G */ |
98 | int num_dcache_entries; | |
f51b7662 DV |
99 | union { |
100 | void __iomem *i9xx_flush_page; | |
101 | void *i8xx_flush_page; | |
102 | }; | |
103 | struct page *i8xx_page; | |
104 | struct resource ifp_resource; | |
105 | int resource_valid; | |
0e87d2b0 DV |
106 | struct page *scratch_page; |
107 | dma_addr_t scratch_page_dma; | |
f51b7662 DV |
108 | } intel_private; |
109 | ||
1a997ff2 DV |
110 | #define INTEL_GTT_GEN intel_private.driver->gen |
111 | #define IS_G33 intel_private.driver->is_g33 | |
112 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
113 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
100519e2 | 114 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
1a997ff2 | 115 | |
f51b7662 DV |
116 | static void intel_agp_free_sglist(struct agp_memory *mem) |
117 | { | |
118 | struct sg_table st; | |
119 | ||
120 | st.sgl = mem->sg_list; | |
121 | st.orig_nents = st.nents = mem->page_count; | |
122 | ||
123 | sg_free_table(&st); | |
124 | ||
125 | mem->sg_list = NULL; | |
126 | mem->num_sg = 0; | |
127 | } | |
128 | ||
129 | static int intel_agp_map_memory(struct agp_memory *mem) | |
130 | { | |
131 | struct sg_table st; | |
132 | struct scatterlist *sg; | |
133 | int i; | |
134 | ||
fefaa70f DV |
135 | if (mem->sg_list) |
136 | return 0; /* already mapped (for e.g. resume */ | |
137 | ||
f51b7662 DV |
138 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); |
139 | ||
140 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) | |
831cd445 | 141 | goto err; |
f51b7662 DV |
142 | |
143 | mem->sg_list = sg = st.sgl; | |
144 | ||
145 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) | |
146 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
147 | ||
148 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
149 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
831cd445 CW |
150 | if (unlikely(!mem->num_sg)) |
151 | goto err; | |
152 | ||
f51b7662 | 153 | return 0; |
831cd445 CW |
154 | |
155 | err: | |
156 | sg_free_table(&st); | |
157 | return -ENOMEM; | |
f51b7662 DV |
158 | } |
159 | ||
160 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
161 | { | |
162 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
163 | ||
164 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
165 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
166 | intel_agp_free_sglist(mem); | |
167 | } | |
168 | ||
f51b7662 DV |
169 | static int intel_i810_fetch_size(void) |
170 | { | |
171 | u32 smram_miscc; | |
172 | struct aper_size_info_fixed *values; | |
173 | ||
d7cca2f7 DV |
174 | pci_read_config_dword(intel_private.bridge_dev, |
175 | I810_SMRAM_MISCC, &smram_miscc); | |
f51b7662 DV |
176 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); |
177 | ||
178 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
d7cca2f7 | 179 | dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n"); |
f51b7662 DV |
180 | return 0; |
181 | } | |
182 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
e1583165 | 183 | agp_bridge->current_size = (void *) (values + 1); |
f51b7662 DV |
184 | agp_bridge->aperture_size_idx = 1; |
185 | return values[1].size; | |
186 | } else { | |
e1583165 | 187 | agp_bridge->current_size = (void *) (values); |
f51b7662 DV |
188 | agp_bridge->aperture_size_idx = 0; |
189 | return values[0].size; | |
190 | } | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | static int intel_i810_configure(void) | |
196 | { | |
197 | struct aper_size_info_fixed *current_size; | |
198 | u32 temp; | |
199 | int i; | |
200 | ||
201 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
202 | ||
203 | if (!intel_private.registers) { | |
204 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
205 | temp &= 0xfff80000; | |
206 | ||
207 | intel_private.registers = ioremap(temp, 128 * 4096); | |
208 | if (!intel_private.registers) { | |
209 | dev_err(&intel_private.pcidev->dev, | |
210 | "can't remap memory\n"); | |
211 | return -ENOMEM; | |
212 | } | |
213 | } | |
214 | ||
215 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
216 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
217 | /* This will need to be dynamically assigned */ | |
218 | dev_info(&intel_private.pcidev->dev, | |
219 | "detected 4MB dedicated video ram\n"); | |
220 | intel_private.num_dcache_entries = 1024; | |
221 | } | |
222 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); | |
223 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
224 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); | |
225 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
226 | ||
227 | if (agp_bridge->driver->needs_scratch_page) { | |
228 | for (i = 0; i < current_size->num_entries; i++) { | |
229 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
230 | } | |
231 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ | |
232 | } | |
233 | global_cache_flush(); | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static void intel_i810_cleanup(void) | |
238 | { | |
239 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
240 | readl(intel_private.registers); /* PCI Posting. */ | |
241 | iounmap(intel_private.registers); | |
242 | } | |
243 | ||
ffdd7510 | 244 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
245 | { |
246 | return; | |
247 | } | |
248 | ||
249 | /* Exists to support ARGB cursors */ | |
250 | static struct page *i8xx_alloc_pages(void) | |
251 | { | |
252 | struct page *page; | |
253 | ||
254 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
255 | if (page == NULL) | |
256 | return NULL; | |
257 | ||
258 | if (set_pages_uc(page, 4) < 0) { | |
259 | set_pages_wb(page, 4); | |
260 | __free_pages(page, 2); | |
261 | return NULL; | |
262 | } | |
263 | get_page(page); | |
264 | atomic_inc(&agp_bridge->current_memory_agp); | |
265 | return page; | |
266 | } | |
267 | ||
268 | static void i8xx_destroy_pages(struct page *page) | |
269 | { | |
270 | if (page == NULL) | |
271 | return; | |
272 | ||
273 | set_pages_wb(page, 4); | |
274 | put_page(page); | |
275 | __free_pages(page, 2); | |
276 | atomic_dec(&agp_bridge->current_memory_agp); | |
277 | } | |
278 | ||
f51b7662 DV |
279 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
280 | int type) | |
281 | { | |
282 | int i, j, num_entries; | |
283 | void *temp; | |
284 | int ret = -EINVAL; | |
285 | int mask_type; | |
286 | ||
287 | if (mem->page_count == 0) | |
288 | goto out; | |
289 | ||
290 | temp = agp_bridge->current_size; | |
291 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
292 | ||
293 | if ((pg_start + mem->page_count) > num_entries) | |
294 | goto out_err; | |
295 | ||
296 | ||
297 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { | |
298 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
299 | ret = -EBUSY; | |
300 | goto out_err; | |
301 | } | |
302 | } | |
303 | ||
304 | if (type != mem->type) | |
305 | goto out_err; | |
306 | ||
307 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
308 | ||
309 | switch (mask_type) { | |
310 | case AGP_DCACHE_MEMORY: | |
311 | if (!mem->is_flushed) | |
312 | global_cache_flush(); | |
313 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
314 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
315 | intel_private.registers+I810_PTE_BASE+(i*4)); | |
316 | } | |
317 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); | |
318 | break; | |
319 | case AGP_PHYS_MEMORY: | |
320 | case AGP_NORMAL_MEMORY: | |
321 | if (!mem->is_flushed) | |
322 | global_cache_flush(); | |
323 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
324 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
325 | page_to_phys(mem->pages[i]), mask_type), | |
326 | intel_private.registers+I810_PTE_BASE+(j*4)); | |
327 | } | |
328 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); | |
329 | break; | |
330 | default: | |
331 | goto out_err; | |
332 | } | |
333 | ||
f51b7662 DV |
334 | out: |
335 | ret = 0; | |
336 | out_err: | |
337 | mem->is_flushed = true; | |
338 | return ret; | |
339 | } | |
340 | ||
341 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
342 | int type) | |
343 | { | |
344 | int i; | |
345 | ||
346 | if (mem->page_count == 0) | |
347 | return 0; | |
348 | ||
349 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
350 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
351 | } | |
352 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); | |
353 | ||
f51b7662 DV |
354 | return 0; |
355 | } | |
356 | ||
357 | /* | |
358 | * The i810/i830 requires a physical address to program its mouse | |
359 | * pointer into hardware. | |
360 | * However the Xserver still writes to it through the agp aperture. | |
361 | */ | |
362 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
363 | { | |
364 | struct agp_memory *new; | |
365 | struct page *page; | |
366 | ||
367 | switch (pg_count) { | |
368 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
369 | break; | |
370 | case 4: | |
371 | /* kludge to get 4 physical pages for ARGB cursor */ | |
372 | page = i8xx_alloc_pages(); | |
373 | break; | |
374 | default: | |
375 | return NULL; | |
376 | } | |
377 | ||
378 | if (page == NULL) | |
379 | return NULL; | |
380 | ||
381 | new = agp_create_memory(pg_count); | |
382 | if (new == NULL) | |
383 | return NULL; | |
384 | ||
385 | new->pages[0] = page; | |
386 | if (pg_count == 4) { | |
387 | /* kludge to get 4 physical pages for ARGB cursor */ | |
388 | new->pages[1] = new->pages[0] + 1; | |
389 | new->pages[2] = new->pages[1] + 1; | |
390 | new->pages[3] = new->pages[2] + 1; | |
391 | } | |
392 | new->page_count = pg_count; | |
393 | new->num_scratch_pages = pg_count; | |
394 | new->type = AGP_PHYS_MEMORY; | |
395 | new->physical = page_to_phys(new->pages[0]); | |
396 | return new; | |
397 | } | |
398 | ||
399 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
400 | { | |
401 | struct agp_memory *new; | |
402 | ||
403 | if (type == AGP_DCACHE_MEMORY) { | |
404 | if (pg_count != intel_private.num_dcache_entries) | |
405 | return NULL; | |
406 | ||
407 | new = agp_create_memory(1); | |
408 | if (new == NULL) | |
409 | return NULL; | |
410 | ||
411 | new->type = AGP_DCACHE_MEMORY; | |
412 | new->page_count = pg_count; | |
413 | new->num_scratch_pages = 0; | |
414 | agp_free_page_array(new); | |
415 | return new; | |
416 | } | |
417 | if (type == AGP_PHYS_MEMORY) | |
418 | return alloc_agpphysmem_i8xx(pg_count, type); | |
419 | return NULL; | |
420 | } | |
421 | ||
422 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
423 | { | |
424 | agp_free_key(curr->key); | |
425 | if (curr->type == AGP_PHYS_MEMORY) { | |
426 | if (curr->page_count == 4) | |
427 | i8xx_destroy_pages(curr->pages[0]); | |
428 | else { | |
429 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
430 | AGP_PAGE_DESTROY_UNMAP); | |
431 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
432 | AGP_PAGE_DESTROY_FREE); | |
433 | } | |
434 | agp_free_page_array(curr); | |
435 | } | |
436 | kfree(curr); | |
437 | } | |
438 | ||
439 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
440 | dma_addr_t addr, int type) | |
441 | { | |
442 | /* Type checking must be done elsewhere */ | |
443 | return addr | bridge->driver->masks[type].mask; | |
444 | } | |
445 | ||
0e87d2b0 DV |
446 | static int intel_gtt_setup_scratch_page(void) |
447 | { | |
448 | struct page *page; | |
449 | dma_addr_t dma_addr; | |
450 | ||
451 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
452 | if (page == NULL) | |
453 | return -ENOMEM; | |
454 | get_page(page); | |
455 | set_pages_uc(page, 1); | |
456 | ||
457 | if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { | |
458 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, | |
459 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
460 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) | |
461 | return -EINVAL; | |
462 | ||
463 | intel_private.scratch_page_dma = dma_addr; | |
464 | } else | |
465 | intel_private.scratch_page_dma = page_to_phys(page); | |
466 | ||
467 | intel_private.scratch_page = page; | |
468 | ||
469 | return 0; | |
470 | } | |
471 | ||
9e76e7b8 | 472 | static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = { |
f51b7662 DV |
473 | {128, 32768, 5}, |
474 | /* The 64M mode still requires a 128k gatt */ | |
475 | {64, 16384, 5}, | |
476 | {256, 65536, 6}, | |
477 | {512, 131072, 7}, | |
478 | }; | |
479 | ||
bfde067b | 480 | static unsigned int intel_gtt_stolen_entries(void) |
f51b7662 DV |
481 | { |
482 | u16 gmch_ctrl; | |
f51b7662 DV |
483 | u8 rdct; |
484 | int local = 0; | |
485 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
1b6064d7 | 486 | unsigned int overhead_entries; |
d8d9abcd | 487 | unsigned int stolen_size = 0; |
f51b7662 | 488 | |
d7cca2f7 DV |
489 | pci_read_config_word(intel_private.bridge_dev, |
490 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 491 | |
1a997ff2 | 492 | if (INTEL_GTT_GEN > 4 || IS_PINEVIEW) |
fbe40783 DV |
493 | overhead_entries = 0; |
494 | else | |
495 | overhead_entries = intel_private.base.gtt_mappable_entries | |
496 | / 1024; | |
f51b7662 | 497 | |
fbe40783 | 498 | overhead_entries += 1; /* BIOS popup */ |
d8d9abcd | 499 | |
d7cca2f7 DV |
500 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
501 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
502 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
503 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 504 | stolen_size = KB(512); |
f51b7662 DV |
505 | break; |
506 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 507 | stolen_size = MB(1); |
f51b7662 DV |
508 | break; |
509 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 510 | stolen_size = MB(8); |
f51b7662 DV |
511 | break; |
512 | case I830_GMCH_GMS_LOCAL: | |
513 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 514 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
515 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
516 | local = 1; | |
517 | break; | |
518 | default: | |
d8d9abcd | 519 | stolen_size = 0; |
f51b7662 DV |
520 | break; |
521 | } | |
1a997ff2 | 522 | } else if (INTEL_GTT_GEN == 6) { |
f51b7662 DV |
523 | /* |
524 | * SandyBridge has new memory control reg at 0x50.w | |
525 | */ | |
526 | u16 snb_gmch_ctl; | |
527 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
528 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
529 | case SNB_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 530 | stolen_size = MB(32); |
f51b7662 DV |
531 | break; |
532 | case SNB_GMCH_GMS_STOLEN_64M: | |
d8d9abcd | 533 | stolen_size = MB(64); |
f51b7662 DV |
534 | break; |
535 | case SNB_GMCH_GMS_STOLEN_96M: | |
d8d9abcd | 536 | stolen_size = MB(96); |
f51b7662 DV |
537 | break; |
538 | case SNB_GMCH_GMS_STOLEN_128M: | |
d8d9abcd | 539 | stolen_size = MB(128); |
f51b7662 DV |
540 | break; |
541 | case SNB_GMCH_GMS_STOLEN_160M: | |
d8d9abcd | 542 | stolen_size = MB(160); |
f51b7662 DV |
543 | break; |
544 | case SNB_GMCH_GMS_STOLEN_192M: | |
d8d9abcd | 545 | stolen_size = MB(192); |
f51b7662 DV |
546 | break; |
547 | case SNB_GMCH_GMS_STOLEN_224M: | |
d8d9abcd | 548 | stolen_size = MB(224); |
f51b7662 DV |
549 | break; |
550 | case SNB_GMCH_GMS_STOLEN_256M: | |
d8d9abcd | 551 | stolen_size = MB(256); |
f51b7662 DV |
552 | break; |
553 | case SNB_GMCH_GMS_STOLEN_288M: | |
d8d9abcd | 554 | stolen_size = MB(288); |
f51b7662 DV |
555 | break; |
556 | case SNB_GMCH_GMS_STOLEN_320M: | |
d8d9abcd | 557 | stolen_size = MB(320); |
f51b7662 DV |
558 | break; |
559 | case SNB_GMCH_GMS_STOLEN_352M: | |
d8d9abcd | 560 | stolen_size = MB(352); |
f51b7662 DV |
561 | break; |
562 | case SNB_GMCH_GMS_STOLEN_384M: | |
d8d9abcd | 563 | stolen_size = MB(384); |
f51b7662 DV |
564 | break; |
565 | case SNB_GMCH_GMS_STOLEN_416M: | |
d8d9abcd | 566 | stolen_size = MB(416); |
f51b7662 DV |
567 | break; |
568 | case SNB_GMCH_GMS_STOLEN_448M: | |
d8d9abcd | 569 | stolen_size = MB(448); |
f51b7662 DV |
570 | break; |
571 | case SNB_GMCH_GMS_STOLEN_480M: | |
d8d9abcd | 572 | stolen_size = MB(480); |
f51b7662 DV |
573 | break; |
574 | case SNB_GMCH_GMS_STOLEN_512M: | |
d8d9abcd | 575 | stolen_size = MB(512); |
f51b7662 DV |
576 | break; |
577 | } | |
578 | } else { | |
579 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
580 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 581 | stolen_size = MB(1); |
f51b7662 DV |
582 | break; |
583 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 584 | stolen_size = MB(4); |
f51b7662 DV |
585 | break; |
586 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 587 | stolen_size = MB(8); |
f51b7662 DV |
588 | break; |
589 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 590 | stolen_size = MB(16); |
f51b7662 DV |
591 | break; |
592 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 593 | stolen_size = MB(32); |
f51b7662 DV |
594 | break; |
595 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 596 | stolen_size = MB(48); |
f51b7662 DV |
597 | break; |
598 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 599 | stolen_size = MB(64); |
f51b7662 DV |
600 | break; |
601 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 602 | stolen_size = MB(128); |
f51b7662 DV |
603 | break; |
604 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 605 | stolen_size = MB(256); |
f51b7662 DV |
606 | break; |
607 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 608 | stolen_size = MB(96); |
f51b7662 DV |
609 | break; |
610 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 611 | stolen_size = MB(160); |
f51b7662 DV |
612 | break; |
613 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 614 | stolen_size = MB(224); |
f51b7662 DV |
615 | break; |
616 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 617 | stolen_size = MB(352); |
f51b7662 DV |
618 | break; |
619 | default: | |
d8d9abcd | 620 | stolen_size = 0; |
f51b7662 DV |
621 | break; |
622 | } | |
623 | } | |
1784a5fb | 624 | |
1b6064d7 | 625 | if (stolen_size > 0) { |
d7cca2f7 | 626 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 627 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 628 | } else { |
d7cca2f7 | 629 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 630 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 631 | stolen_size = 0; |
f51b7662 DV |
632 | } |
633 | ||
1b6064d7 | 634 | return stolen_size/KB(4) - overhead_entries; |
f51b7662 DV |
635 | } |
636 | ||
20172842 DV |
637 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
638 | { | |
639 | u32 pgetbl_ctl, pgetbl_ctl2; | |
640 | ||
641 | /* ensure that ppgtt is disabled */ | |
642 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); | |
643 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; | |
644 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); | |
645 | ||
646 | /* write the new ggtt size */ | |
647 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
648 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; | |
649 | pgetbl_ctl |= size_flag; | |
650 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); | |
651 | } | |
652 | ||
653 | static unsigned int i965_gtt_total_entries(void) | |
fbe40783 DV |
654 | { |
655 | int size; | |
20172842 DV |
656 | u32 pgetbl_ctl; |
657 | u16 gmch_ctl; | |
fbe40783 | 658 | |
20172842 DV |
659 | pci_read_config_word(intel_private.bridge_dev, |
660 | I830_GMCH_CTRL, &gmch_ctl); | |
fbe40783 | 661 | |
20172842 DV |
662 | if (INTEL_GTT_GEN == 5) { |
663 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { | |
664 | case G4x_GMCH_SIZE_1M: | |
665 | case G4x_GMCH_SIZE_VT_1M: | |
666 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); | |
fbe40783 | 667 | break; |
20172842 DV |
668 | case G4x_GMCH_SIZE_VT_1_5M: |
669 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); | |
fbe40783 | 670 | break; |
20172842 DV |
671 | case G4x_GMCH_SIZE_2M: |
672 | case G4x_GMCH_SIZE_VT_2M: | |
673 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); | |
fbe40783 | 674 | break; |
fbe40783 | 675 | } |
20172842 | 676 | } |
e5e408fc | 677 | |
20172842 DV |
678 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
679 | ||
680 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
681 | case I965_PGETBL_SIZE_128KB: | |
682 | size = KB(128); | |
683 | break; | |
684 | case I965_PGETBL_SIZE_256KB: | |
685 | size = KB(256); | |
686 | break; | |
687 | case I965_PGETBL_SIZE_512KB: | |
688 | size = KB(512); | |
689 | break; | |
690 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ | |
691 | case I965_PGETBL_SIZE_1MB: | |
692 | size = KB(1024); | |
693 | break; | |
694 | case I965_PGETBL_SIZE_2MB: | |
695 | size = KB(2048); | |
696 | break; | |
697 | case I965_PGETBL_SIZE_1_5MB: | |
698 | size = KB(1024 + 512); | |
699 | break; | |
700 | default: | |
701 | dev_info(&intel_private.pcidev->dev, | |
702 | "unknown page table size, assuming 512KB\n"); | |
703 | size = KB(512); | |
704 | } | |
705 | ||
706 | return size/4; | |
707 | } | |
708 | ||
709 | static unsigned int intel_gtt_total_entries(void) | |
710 | { | |
711 | int size; | |
712 | ||
713 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) | |
714 | return i965_gtt_total_entries(); | |
715 | else if (INTEL_GTT_GEN == 6) { | |
210b23c2 DV |
716 | u16 snb_gmch_ctl; |
717 | ||
718 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
719 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | |
720 | default: | |
721 | case SNB_GTT_SIZE_0M: | |
722 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | |
723 | size = MB(0); | |
724 | break; | |
725 | case SNB_GTT_SIZE_1M: | |
726 | size = MB(1); | |
727 | break; | |
728 | case SNB_GTT_SIZE_2M: | |
729 | size = MB(2); | |
730 | break; | |
731 | } | |
e5e408fc | 732 | return size/4; |
fbe40783 DV |
733 | } else { |
734 | /* On previous hardware, the GTT size was just what was | |
735 | * required to map the aperture. | |
736 | */ | |
e5e408fc | 737 | return intel_private.base.gtt_mappable_entries; |
fbe40783 | 738 | } |
fbe40783 | 739 | } |
fbe40783 | 740 | |
1784a5fb DV |
741 | static unsigned int intel_gtt_mappable_entries(void) |
742 | { | |
743 | unsigned int aperture_size; | |
1784a5fb | 744 | |
b1c5b0f8 CW |
745 | if (INTEL_GTT_GEN == 2) { |
746 | u16 gmch_ctrl; | |
1784a5fb | 747 | |
b1c5b0f8 CW |
748 | pci_read_config_word(intel_private.bridge_dev, |
749 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 750 | |
1784a5fb | 751 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 752 | aperture_size = MB(64); |
1784a5fb | 753 | else |
b1c5b0f8 | 754 | aperture_size = MB(128); |
239918f7 | 755 | } else { |
1784a5fb DV |
756 | /* 9xx supports large sizes, just look at the length */ |
757 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
758 | } |
759 | ||
760 | return aperture_size >> PAGE_SHIFT; | |
761 | } | |
762 | ||
0e87d2b0 DV |
763 | static void intel_gtt_teardown_scratch_page(void) |
764 | { | |
765 | set_pages_wb(intel_private.scratch_page, 1); | |
766 | pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, | |
767 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
768 | put_page(intel_private.scratch_page); | |
769 | __free_page(intel_private.scratch_page); | |
770 | } | |
771 | ||
772 | static void intel_gtt_cleanup(void) | |
773 | { | |
ae83dd5c DV |
774 | intel_private.driver->cleanup(); |
775 | ||
0e87d2b0 DV |
776 | iounmap(intel_private.gtt); |
777 | iounmap(intel_private.registers); | |
778 | ||
779 | intel_gtt_teardown_scratch_page(); | |
780 | } | |
781 | ||
1784a5fb DV |
782 | static int intel_gtt_init(void) |
783 | { | |
f67eab66 | 784 | u32 gtt_map_size; |
3b15a9d7 DV |
785 | int ret; |
786 | ||
3b15a9d7 DV |
787 | ret = intel_private.driver->setup(); |
788 | if (ret != 0) | |
789 | return ret; | |
f67eab66 DV |
790 | |
791 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
792 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); | |
793 | ||
b3eafc5a DV |
794 | /* save the PGETBL reg for resume */ |
795 | intel_private.PGETBL_save = | |
796 | readl(intel_private.registers+I810_PGETBL_CTL) | |
797 | & ~I810_PGETBL_ENABLED; | |
100519e2 CW |
798 | /* we only ever restore the register when enabling the PGTBL... */ |
799 | if (HAS_PGTBL_EN) | |
800 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; | |
b3eafc5a | 801 | |
0af9e92e DV |
802 | dev_info(&intel_private.bridge_dev->dev, |
803 | "detected gtt size: %dK total, %dK mappable\n", | |
804 | intel_private.base.gtt_total_entries * 4, | |
805 | intel_private.base.gtt_mappable_entries * 4); | |
806 | ||
f67eab66 DV |
807 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
808 | ||
809 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, | |
810 | gtt_map_size); | |
811 | if (!intel_private.gtt) { | |
ae83dd5c | 812 | intel_private.driver->cleanup(); |
f67eab66 DV |
813 | iounmap(intel_private.registers); |
814 | return -ENOMEM; | |
815 | } | |
816 | ||
817 | global_cache_flush(); /* FIXME: ? */ | |
818 | ||
1784a5fb DV |
819 | /* we have to call this as early as possible after the MMIO base address is known */ |
820 | intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries(); | |
821 | if (intel_private.base.gtt_stolen_entries == 0) { | |
ae83dd5c | 822 | intel_private.driver->cleanup(); |
1784a5fb | 823 | iounmap(intel_private.registers); |
f67eab66 | 824 | iounmap(intel_private.gtt); |
1784a5fb DV |
825 | return -ENOMEM; |
826 | } | |
827 | ||
0e87d2b0 DV |
828 | ret = intel_gtt_setup_scratch_page(); |
829 | if (ret != 0) { | |
830 | intel_gtt_cleanup(); | |
831 | return ret; | |
832 | } | |
833 | ||
1784a5fb DV |
834 | return 0; |
835 | } | |
836 | ||
3e921f98 DV |
837 | static int intel_fake_agp_fetch_size(void) |
838 | { | |
9e76e7b8 | 839 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
840 | unsigned int aper_size; |
841 | int i; | |
3e921f98 DV |
842 | |
843 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) | |
844 | / MB(1); | |
845 | ||
846 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 847 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
848 | agp_bridge->current_size = |
849 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
850 | return aper_size; |
851 | } | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
ae83dd5c | 857 | static void i830_cleanup(void) |
f51b7662 DV |
858 | { |
859 | kunmap(intel_private.i8xx_page); | |
860 | intel_private.i8xx_flush_page = NULL; | |
f51b7662 DV |
861 | |
862 | __free_page(intel_private.i8xx_page); | |
863 | intel_private.i8xx_page = NULL; | |
864 | } | |
865 | ||
866 | static void intel_i830_setup_flush(void) | |
867 | { | |
868 | /* return if we've already set the flush mechanism up */ | |
869 | if (intel_private.i8xx_page) | |
870 | return; | |
871 | ||
e61cb0d5 | 872 | intel_private.i8xx_page = alloc_page(GFP_KERNEL); |
f51b7662 DV |
873 | if (!intel_private.i8xx_page) |
874 | return; | |
875 | ||
876 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); | |
877 | if (!intel_private.i8xx_flush_page) | |
ae83dd5c | 878 | i830_cleanup(); |
f51b7662 DV |
879 | } |
880 | ||
881 | /* The chipset_flush interface needs to get data that has already been | |
882 | * flushed out of the CPU all the way out to main memory, because the GPU | |
883 | * doesn't snoop those buffers. | |
884 | * | |
885 | * The 8xx series doesn't have the same lovely interface for flushing the | |
886 | * chipset write buffers that the later chips do. According to the 865 | |
887 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
888 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
889 | * that it'll push whatever was in there out. It appears to work. | |
890 | */ | |
1b263f24 | 891 | static void i830_chipset_flush(void) |
f51b7662 DV |
892 | { |
893 | unsigned int *pg = intel_private.i8xx_flush_page; | |
894 | ||
895 | memset(pg, 0, 1024); | |
896 | ||
897 | if (cpu_has_clflush) | |
898 | clflush_cache_range(pg, 1024); | |
899 | else if (wbinvd_on_all_cpus() != 0) | |
900 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
901 | } | |
902 | ||
351bb278 DV |
903 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
904 | unsigned int flags) | |
905 | { | |
906 | u32 pte_flags = I810_PTE_VALID; | |
907 | ||
908 | switch (flags) { | |
909 | case AGP_DCACHE_MEMORY: | |
910 | pte_flags |= I810_PTE_LOCAL; | |
911 | break; | |
912 | case AGP_USER_CACHED_MEMORY: | |
913 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
914 | break; | |
915 | } | |
916 | ||
917 | writel(addr | pte_flags, intel_private.gtt + entry); | |
918 | } | |
919 | ||
e380f60b | 920 | static bool intel_enable_gtt(void) |
f51b7662 | 921 | { |
3f08e4ef | 922 | u32 gma_addr; |
e380f60b | 923 | u8 __iomem *reg; |
f51b7662 | 924 | |
2d2430cf DV |
925 | if (INTEL_GTT_GEN == 2) |
926 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, | |
927 | &gma_addr); | |
928 | else | |
929 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | |
930 | &gma_addr); | |
931 | ||
73800422 | 932 | intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
f51b7662 | 933 | |
e380f60b CW |
934 | if (INTEL_GTT_GEN >= 6) |
935 | return true; | |
936 | ||
100519e2 CW |
937 | if (INTEL_GTT_GEN == 2) { |
938 | u16 gmch_ctrl; | |
73800422 | 939 | |
100519e2 CW |
940 | pci_read_config_word(intel_private.bridge_dev, |
941 | I830_GMCH_CTRL, &gmch_ctrl); | |
942 | gmch_ctrl |= I830_GMCH_ENABLED; | |
943 | pci_write_config_word(intel_private.bridge_dev, | |
944 | I830_GMCH_CTRL, gmch_ctrl); | |
945 | ||
946 | pci_read_config_word(intel_private.bridge_dev, | |
947 | I830_GMCH_CTRL, &gmch_ctrl); | |
948 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { | |
949 | dev_err(&intel_private.pcidev->dev, | |
950 | "failed to enable the GTT: GMCH_CTRL=%x\n", | |
951 | gmch_ctrl); | |
952 | return false; | |
953 | } | |
e380f60b CW |
954 | } |
955 | ||
956 | reg = intel_private.registers+I810_PGETBL_CTL; | |
100519e2 CW |
957 | writel(intel_private.PGETBL_save, reg); |
958 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { | |
e380f60b | 959 | dev_err(&intel_private.pcidev->dev, |
100519e2 | 960 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
e380f60b CW |
961 | readl(reg), intel_private.PGETBL_save); |
962 | return false; | |
963 | } | |
964 | ||
965 | return true; | |
73800422 DV |
966 | } |
967 | ||
968 | static int i830_setup(void) | |
969 | { | |
970 | u32 reg_addr; | |
971 | ||
972 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
973 | reg_addr &= 0xfff80000; | |
974 | ||
975 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
976 | if (!intel_private.registers) |
977 | return -ENOMEM; | |
978 | ||
73800422 DV |
979 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
980 | ||
981 | intel_i830_setup_flush(); | |
982 | ||
983 | return 0; | |
984 | } | |
985 | ||
3b15a9d7 | 986 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 987 | { |
73800422 | 988 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 989 | agp_bridge->gatt_table = NULL; |
73800422 | 990 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
991 | |
992 | return 0; | |
993 | } | |
994 | ||
ffdd7510 | 995 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
996 | { |
997 | return 0; | |
998 | } | |
999 | ||
351bb278 | 1000 | static int intel_fake_agp_configure(void) |
f51b7662 | 1001 | { |
f51b7662 DV |
1002 | int i; |
1003 | ||
e380f60b CW |
1004 | if (!intel_enable_gtt()) |
1005 | return -EIO; | |
f51b7662 | 1006 | |
73800422 | 1007 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
f51b7662 | 1008 | |
351bb278 DV |
1009 | for (i = intel_private.base.gtt_stolen_entries; |
1010 | i < intel_private.base.gtt_total_entries; i++) { | |
1011 | intel_private.driver->write_entry(intel_private.scratch_page_dma, | |
1012 | i, 0); | |
f51b7662 | 1013 | } |
351bb278 | 1014 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
f51b7662 DV |
1015 | |
1016 | global_cache_flush(); | |
1017 | ||
f51b7662 DV |
1018 | return 0; |
1019 | } | |
1020 | ||
5cbecafc | 1021 | static bool i830_check_flags(unsigned int flags) |
f51b7662 | 1022 | { |
5cbecafc DV |
1023 | switch (flags) { |
1024 | case 0: | |
1025 | case AGP_PHYS_MEMORY: | |
1026 | case AGP_USER_CACHED_MEMORY: | |
1027 | case AGP_USER_MEMORY: | |
1028 | return true; | |
1029 | } | |
1030 | ||
1031 | return false; | |
1032 | } | |
1033 | ||
fefaa70f DV |
1034 | static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
1035 | unsigned int sg_len, | |
1036 | unsigned int pg_start, | |
1037 | unsigned int flags) | |
1038 | { | |
1039 | struct scatterlist *sg; | |
1040 | unsigned int len, m; | |
1041 | int i, j; | |
1042 | ||
1043 | j = pg_start; | |
1044 | ||
1045 | /* sg may merge pages, but we have to separate | |
1046 | * per-page addr for GTT */ | |
1047 | for_each_sg(sg_list, sg, sg_len, i) { | |
1048 | len = sg_dma_len(sg) >> PAGE_SHIFT; | |
1049 | for (m = 0; m < len; m++) { | |
1050 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
1051 | intel_private.driver->write_entry(addr, | |
1052 | j, flags); | |
1053 | j++; | |
1054 | } | |
1055 | } | |
1056 | readl(intel_private.gtt+j-1); | |
1057 | } | |
1058 | ||
5cbecafc DV |
1059 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
1060 | off_t pg_start, int type) | |
1061 | { | |
1062 | int i, j; | |
f51b7662 | 1063 | int ret = -EINVAL; |
f51b7662 DV |
1064 | |
1065 | if (mem->page_count == 0) | |
1066 | goto out; | |
1067 | ||
0ade6386 | 1068 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 | 1069 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
0ade6386 DV |
1070 | "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n", |
1071 | pg_start, intel_private.base.gtt_stolen_entries); | |
f51b7662 DV |
1072 | |
1073 | dev_info(&intel_private.pcidev->dev, | |
1074 | "trying to insert into local/stolen memory\n"); | |
1075 | goto out_err; | |
1076 | } | |
1077 | ||
5cbecafc | 1078 | if ((pg_start + mem->page_count) > intel_private.base.gtt_total_entries) |
f51b7662 DV |
1079 | goto out_err; |
1080 | ||
f51b7662 DV |
1081 | if (type != mem->type) |
1082 | goto out_err; | |
1083 | ||
5cbecafc | 1084 | if (!intel_private.driver->check_flags(type)) |
f51b7662 DV |
1085 | goto out_err; |
1086 | ||
1087 | if (!mem->is_flushed) | |
1088 | global_cache_flush(); | |
1089 | ||
fefaa70f DV |
1090 | if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) { |
1091 | ret = intel_agp_map_memory(mem); | |
1092 | if (ret != 0) | |
1093 | return ret; | |
1094 | ||
1095 | intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, | |
1096 | pg_start, type); | |
1097 | } else { | |
1098 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1099 | dma_addr_t addr = page_to_phys(mem->pages[i]); | |
1100 | intel_private.driver->write_entry(addr, | |
1101 | j, type); | |
1102 | } | |
1103 | readl(intel_private.gtt+j-1); | |
f51b7662 | 1104 | } |
f51b7662 DV |
1105 | |
1106 | out: | |
1107 | ret = 0; | |
1108 | out_err: | |
1109 | mem->is_flushed = true; | |
1110 | return ret; | |
1111 | } | |
1112 | ||
5cbecafc DV |
1113 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
1114 | off_t pg_start, int type) | |
f51b7662 DV |
1115 | { |
1116 | int i; | |
1117 | ||
1118 | if (mem->page_count == 0) | |
1119 | return 0; | |
1120 | ||
0ade6386 | 1121 | if (pg_start < intel_private.base.gtt_stolen_entries) { |
f51b7662 DV |
1122 | dev_info(&intel_private.pcidev->dev, |
1123 | "trying to disable local/stolen memory\n"); | |
1124 | return -EINVAL; | |
1125 | } | |
1126 | ||
fefaa70f DV |
1127 | if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) |
1128 | intel_agp_unmap_memory(mem); | |
1129 | ||
f51b7662 | 1130 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
5cbecafc DV |
1131 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
1132 | i, 0); | |
f51b7662 | 1133 | } |
fdfb58a9 | 1134 | readl(intel_private.gtt+i-1); |
f51b7662 | 1135 | |
f51b7662 DV |
1136 | return 0; |
1137 | } | |
1138 | ||
1b263f24 DV |
1139 | static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge) |
1140 | { | |
1141 | intel_private.driver->chipset_flush(); | |
1142 | } | |
1143 | ||
ffdd7510 DV |
1144 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
1145 | int type) | |
f51b7662 DV |
1146 | { |
1147 | if (type == AGP_PHYS_MEMORY) | |
1148 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1149 | /* always return NULL for other allocation types for now */ | |
1150 | return NULL; | |
1151 | } | |
1152 | ||
1153 | static int intel_alloc_chipset_flush_resource(void) | |
1154 | { | |
1155 | int ret; | |
d7cca2f7 | 1156 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1157 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1158 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1159 | |
1160 | return ret; | |
1161 | } | |
1162 | ||
1163 | static void intel_i915_setup_chipset_flush(void) | |
1164 | { | |
1165 | int ret; | |
1166 | u32 temp; | |
1167 | ||
d7cca2f7 | 1168 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1169 | if (!(temp & 0x1)) { |
1170 | intel_alloc_chipset_flush_resource(); | |
1171 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1172 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1173 | } else { |
1174 | temp &= ~1; | |
1175 | ||
1176 | intel_private.resource_valid = 1; | |
1177 | intel_private.ifp_resource.start = temp; | |
1178 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1179 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1180 | /* some BIOSes reserve this area in a pnp some don't */ | |
1181 | if (ret) | |
1182 | intel_private.resource_valid = 0; | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | static void intel_i965_g33_setup_chipset_flush(void) | |
1187 | { | |
1188 | u32 temp_hi, temp_lo; | |
1189 | int ret; | |
1190 | ||
d7cca2f7 DV |
1191 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1192 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1193 | |
1194 | if (!(temp_lo & 0x1)) { | |
1195 | ||
1196 | intel_alloc_chipset_flush_resource(); | |
1197 | ||
1198 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1199 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1200 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1201 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1202 | } else { |
1203 | u64 l64; | |
1204 | ||
1205 | temp_lo &= ~0x1; | |
1206 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1207 | ||
1208 | intel_private.resource_valid = 1; | |
1209 | intel_private.ifp_resource.start = l64; | |
1210 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1211 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1212 | /* some BIOSes reserve this area in a pnp some don't */ | |
1213 | if (ret) | |
1214 | intel_private.resource_valid = 0; | |
1215 | } | |
1216 | } | |
1217 | ||
1218 | static void intel_i9xx_setup_flush(void) | |
1219 | { | |
1220 | /* return if already configured */ | |
1221 | if (intel_private.ifp_resource.start) | |
1222 | return; | |
1223 | ||
1a997ff2 | 1224 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1225 | return; |
1226 | ||
1227 | /* setup a resource for this object */ | |
1228 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1229 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1230 | ||
1231 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1232 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1233 | intel_i965_g33_setup_chipset_flush(); |
1234 | } else { | |
1235 | intel_i915_setup_chipset_flush(); | |
1236 | } | |
1237 | ||
df51e7aa | 1238 | if (intel_private.ifp_resource.start) |
f51b7662 | 1239 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1240 | if (!intel_private.i9xx_flush_page) |
1241 | dev_err(&intel_private.pcidev->dev, | |
1242 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1243 | } |
1244 | ||
ae83dd5c DV |
1245 | static void i9xx_cleanup(void) |
1246 | { | |
1247 | if (intel_private.i9xx_flush_page) | |
1248 | iounmap(intel_private.i9xx_flush_page); | |
1249 | if (intel_private.resource_valid) | |
1250 | release_resource(&intel_private.ifp_resource); | |
1251 | intel_private.ifp_resource.start = 0; | |
1252 | intel_private.resource_valid = 0; | |
1253 | } | |
1254 | ||
1b263f24 | 1255 | static void i9xx_chipset_flush(void) |
f51b7662 DV |
1256 | { |
1257 | if (intel_private.i9xx_flush_page) | |
1258 | writel(1, intel_private.i9xx_flush_page); | |
1259 | } | |
1260 | ||
a6963596 DV |
1261 | static void i965_write_entry(dma_addr_t addr, unsigned int entry, |
1262 | unsigned int flags) | |
1263 | { | |
1264 | /* Shift high bits down */ | |
1265 | addr |= (addr >> 28) & 0xf0; | |
1266 | writel(addr | I810_PTE_VALID, intel_private.gtt + entry); | |
1267 | } | |
1268 | ||
90cb149e DV |
1269 | static bool gen6_check_flags(unsigned int flags) |
1270 | { | |
1271 | return true; | |
1272 | } | |
1273 | ||
97ef1bdd DV |
1274 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
1275 | unsigned int flags) | |
1276 | { | |
1277 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; | |
1278 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | |
1279 | u32 pte_flags; | |
1280 | ||
897ef192 | 1281 | if (type_mask == AGP_USER_MEMORY) |
85ccc35b | 1282 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
97ef1bdd | 1283 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
d1108525 | 1284 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
97ef1bdd DV |
1285 | if (gfdt) |
1286 | pte_flags |= GEN6_PTE_GFDT; | |
1287 | } else { /* set 'normal'/'cached' to LLC by default */ | |
d1108525 | 1288 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
97ef1bdd DV |
1289 | if (gfdt) |
1290 | pte_flags |= GEN6_PTE_GFDT; | |
1291 | } | |
1292 | ||
1293 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1294 | addr |= (addr >> 28) & 0xff0; | |
1295 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1296 | } | |
1297 | ||
ae83dd5c DV |
1298 | static void gen6_cleanup(void) |
1299 | { | |
1300 | } | |
1301 | ||
2d2430cf | 1302 | static int i9xx_setup(void) |
f51b7662 | 1303 | { |
2d2430cf | 1304 | u32 reg_addr; |
f51b7662 | 1305 | |
2d2430cf | 1306 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
f51b7662 | 1307 | |
2d2430cf | 1308 | reg_addr &= 0xfff80000; |
f1befe71 | 1309 | |
2d2430cf | 1310 | intel_private.registers = ioremap(reg_addr, 128 * 4096); |
ccc4e67b | 1311 | if (!intel_private.registers) |
f51b7662 DV |
1312 | return -ENOMEM; |
1313 | ||
2d2430cf DV |
1314 | if (INTEL_GTT_GEN == 3) { |
1315 | u32 gtt_addr; | |
3f08e4ef | 1316 | |
2d2430cf DV |
1317 | pci_read_config_dword(intel_private.pcidev, |
1318 | I915_PTEADDR, >t_addr); | |
1319 | intel_private.gtt_bus_addr = gtt_addr; | |
1320 | } else { | |
1321 | u32 gtt_offset; | |
1322 | ||
1323 | switch (INTEL_GTT_GEN) { | |
1324 | case 5: | |
1325 | case 6: | |
1326 | gtt_offset = MB(2); | |
1327 | break; | |
1328 | case 4: | |
1329 | default: | |
1330 | gtt_offset = KB(512); | |
1331 | break; | |
1332 | } | |
1333 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; | |
1334 | } | |
1335 | ||
1336 | intel_i9xx_setup_flush(); | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
f51b7662 DV |
1341 | static const struct agp_bridge_driver intel_810_driver = { |
1342 | .owner = THIS_MODULE, | |
1343 | .aperture_sizes = intel_i810_sizes, | |
1344 | .size_type = FIXED_APER_SIZE, | |
1345 | .num_aperture_sizes = 2, | |
1346 | .needs_scratch_page = true, | |
1347 | .configure = intel_i810_configure, | |
1348 | .fetch_size = intel_i810_fetch_size, | |
1349 | .cleanup = intel_i810_cleanup, | |
f51b7662 DV |
1350 | .mask_memory = intel_i810_mask_memory, |
1351 | .masks = intel_i810_masks, | |
ffdd7510 | 1352 | .agp_enable = intel_fake_agp_enable, |
f51b7662 DV |
1353 | .cache_flush = global_cache_flush, |
1354 | .create_gatt_table = agp_generic_create_gatt_table, | |
1355 | .free_gatt_table = agp_generic_free_gatt_table, | |
1356 | .insert_memory = intel_i810_insert_entries, | |
1357 | .remove_memory = intel_i810_remove_entries, | |
1358 | .alloc_by_type = intel_i810_alloc_by_type, | |
1359 | .free_by_type = intel_i810_free_by_type, | |
1360 | .agp_alloc_page = agp_generic_alloc_page, | |
1361 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1362 | .agp_destroy_page = agp_generic_destroy_page, | |
1363 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1364 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, | |
1365 | }; | |
1366 | ||
e9b1cc81 | 1367 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
f51b7662 | 1368 | .owner = THIS_MODULE, |
f51b7662 | 1369 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1370 | .aperture_sizes = intel_fake_agp_sizes, |
1371 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
a6963596 | 1372 | .configure = intel_fake_agp_configure, |
3e921f98 | 1373 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1374 | .cleanup = intel_gtt_cleanup, |
ffdd7510 | 1375 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1376 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1377 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1378 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
450f2b3d DV |
1379 | .insert_memory = intel_fake_agp_insert_entries, |
1380 | .remove_memory = intel_fake_agp_remove_entries, | |
ffdd7510 | 1381 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1382 | .free_by_type = intel_i810_free_by_type, |
1383 | .agp_alloc_page = agp_generic_alloc_page, | |
1384 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1385 | .agp_destroy_page = agp_generic_destroy_page, | |
1386 | .agp_destroy_pages = agp_generic_destroy_pages, | |
1b263f24 | 1387 | .chipset_flush = intel_fake_agp_chipset_flush, |
f51b7662 | 1388 | }; |
02c026ce | 1389 | |
bdd30729 DV |
1390 | static const struct intel_gtt_driver i81x_gtt_driver = { |
1391 | .gen = 1, | |
22533b49 | 1392 | .dma_mask_size = 32, |
bdd30729 | 1393 | }; |
1a997ff2 DV |
1394 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1395 | .gen = 2, | |
100519e2 | 1396 | .has_pgtbl_enable = 1, |
73800422 | 1397 | .setup = i830_setup, |
ae83dd5c | 1398 | .cleanup = i830_cleanup, |
351bb278 | 1399 | .write_entry = i830_write_entry, |
22533b49 | 1400 | .dma_mask_size = 32, |
5cbecafc | 1401 | .check_flags = i830_check_flags, |
1b263f24 | 1402 | .chipset_flush = i830_chipset_flush, |
1a997ff2 DV |
1403 | }; |
1404 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1405 | .gen = 3, | |
100519e2 | 1406 | .has_pgtbl_enable = 1, |
2d2430cf | 1407 | .setup = i9xx_setup, |
ae83dd5c | 1408 | .cleanup = i9xx_cleanup, |
351bb278 DV |
1409 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
1410 | .write_entry = i830_write_entry, | |
22533b49 | 1411 | .dma_mask_size = 32, |
fefaa70f | 1412 | .check_flags = i830_check_flags, |
1b263f24 | 1413 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1414 | }; |
1415 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1416 | .gen = 3, | |
1417 | .is_g33 = 1, | |
2d2430cf | 1418 | .setup = i9xx_setup, |
ae83dd5c | 1419 | .cleanup = i9xx_cleanup, |
a6963596 | 1420 | .write_entry = i965_write_entry, |
22533b49 | 1421 | .dma_mask_size = 36, |
450f2b3d | 1422 | .check_flags = i830_check_flags, |
1b263f24 | 1423 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1424 | }; |
1425 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1426 | .gen = 3, | |
1427 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1428 | .setup = i9xx_setup, |
ae83dd5c | 1429 | .cleanup = i9xx_cleanup, |
a6963596 | 1430 | .write_entry = i965_write_entry, |
22533b49 | 1431 | .dma_mask_size = 36, |
450f2b3d | 1432 | .check_flags = i830_check_flags, |
1b263f24 | 1433 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1434 | }; |
1435 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1436 | .gen = 4, | |
100519e2 | 1437 | .has_pgtbl_enable = 1, |
2d2430cf | 1438 | .setup = i9xx_setup, |
ae83dd5c | 1439 | .cleanup = i9xx_cleanup, |
a6963596 | 1440 | .write_entry = i965_write_entry, |
22533b49 | 1441 | .dma_mask_size = 36, |
450f2b3d | 1442 | .check_flags = i830_check_flags, |
1b263f24 | 1443 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1444 | }; |
1445 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1446 | .gen = 5, | |
2d2430cf | 1447 | .setup = i9xx_setup, |
ae83dd5c | 1448 | .cleanup = i9xx_cleanup, |
a6963596 | 1449 | .write_entry = i965_write_entry, |
22533b49 | 1450 | .dma_mask_size = 36, |
450f2b3d | 1451 | .check_flags = i830_check_flags, |
1b263f24 | 1452 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1453 | }; |
1454 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1455 | .gen = 5, | |
1456 | .is_ironlake = 1, | |
2d2430cf | 1457 | .setup = i9xx_setup, |
ae83dd5c | 1458 | .cleanup = i9xx_cleanup, |
a6963596 | 1459 | .write_entry = i965_write_entry, |
22533b49 | 1460 | .dma_mask_size = 36, |
450f2b3d | 1461 | .check_flags = i830_check_flags, |
1b263f24 | 1462 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1463 | }; |
1464 | static const struct intel_gtt_driver sandybridge_gtt_driver = { | |
1465 | .gen = 6, | |
2d2430cf | 1466 | .setup = i9xx_setup, |
ae83dd5c | 1467 | .cleanup = gen6_cleanup, |
97ef1bdd | 1468 | .write_entry = gen6_write_entry, |
22533b49 | 1469 | .dma_mask_size = 40, |
90cb149e | 1470 | .check_flags = gen6_check_flags, |
1b263f24 | 1471 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1472 | }; |
1473 | ||
02c026ce DV |
1474 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1475 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1476 | * which one should be used if a gmch_chip_id is present. | |
1477 | */ | |
1478 | static const struct intel_gtt_driver_description { | |
1479 | unsigned int gmch_chip_id; | |
1480 | char *name; | |
1481 | const struct agp_bridge_driver *gmch_driver; | |
1a997ff2 | 1482 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1483 | } intel_gtt_chipsets[] = { |
bdd30729 DV |
1484 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver, |
1485 | &i81x_gtt_driver}, | |
1486 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver, | |
1487 | &i81x_gtt_driver}, | |
1488 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver, | |
1489 | &i81x_gtt_driver}, | |
1490 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver, | |
1491 | &i81x_gtt_driver}, | |
1a997ff2 | 1492 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
e9b1cc81 | 1493 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
1a997ff2 | 1494 | { PCI_DEVICE_ID_INTEL_82845G_IG, "830M", |
e9b1cc81 | 1495 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
1a997ff2 | 1496 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
e9b1cc81 | 1497 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
1a997ff2 | 1498 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
e9b1cc81 | 1499 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
1a997ff2 | 1500 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
e9b1cc81 | 1501 | &intel_fake_agp_driver, &i8xx_gtt_driver}, |
1a997ff2 | 1502 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
e9b1cc81 | 1503 | &intel_fake_agp_driver, &i915_gtt_driver }, |
1a997ff2 | 1504 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
e9b1cc81 | 1505 | &intel_fake_agp_driver, &i915_gtt_driver }, |
1a997ff2 | 1506 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
e9b1cc81 | 1507 | &intel_fake_agp_driver, &i915_gtt_driver }, |
1a997ff2 | 1508 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
e9b1cc81 | 1509 | &intel_fake_agp_driver, &i915_gtt_driver }, |
1a997ff2 | 1510 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
e9b1cc81 | 1511 | &intel_fake_agp_driver, &i915_gtt_driver }, |
1a997ff2 | 1512 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
e9b1cc81 | 1513 | &intel_fake_agp_driver, &i915_gtt_driver }, |
1a997ff2 | 1514 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
e9b1cc81 | 1515 | &intel_fake_agp_driver, &i965_gtt_driver }, |
1a997ff2 | 1516 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
e9b1cc81 | 1517 | &intel_fake_agp_driver, &i965_gtt_driver }, |
1a997ff2 | 1518 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
e9b1cc81 | 1519 | &intel_fake_agp_driver, &i965_gtt_driver }, |
1a997ff2 | 1520 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
e9b1cc81 | 1521 | &intel_fake_agp_driver, &i965_gtt_driver }, |
1a997ff2 | 1522 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
e9b1cc81 | 1523 | &intel_fake_agp_driver, &i965_gtt_driver }, |
1a997ff2 | 1524 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
e9b1cc81 | 1525 | &intel_fake_agp_driver, &i965_gtt_driver }, |
1a997ff2 | 1526 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
e9b1cc81 | 1527 | &intel_fake_agp_driver, &g33_gtt_driver }, |
1a997ff2 | 1528 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
e9b1cc81 | 1529 | &intel_fake_agp_driver, &g33_gtt_driver }, |
1a997ff2 | 1530 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
e9b1cc81 | 1531 | &intel_fake_agp_driver, &g33_gtt_driver }, |
1a997ff2 | 1532 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
e9b1cc81 | 1533 | &intel_fake_agp_driver, &pineview_gtt_driver }, |
1a997ff2 | 1534 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
e9b1cc81 | 1535 | &intel_fake_agp_driver, &pineview_gtt_driver }, |
1a997ff2 | 1536 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
e9b1cc81 | 1537 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
1a997ff2 | 1538 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
e9b1cc81 | 1539 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
1a997ff2 | 1540 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
e9b1cc81 | 1541 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
1a997ff2 | 1542 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
e9b1cc81 | 1543 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
1a997ff2 | 1544 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
e9b1cc81 | 1545 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
e9e5f8e8 | 1546 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
e9b1cc81 | 1547 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
1a997ff2 | 1548 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
e9b1cc81 | 1549 | &intel_fake_agp_driver, &g4x_gtt_driver }, |
02c026ce | 1550 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
e9b1cc81 | 1551 | "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver }, |
02c026ce | 1552 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
e9b1cc81 | 1553 | "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver }, |
02c026ce | 1554 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
e9b1cc81 | 1555 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce | 1556 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
e9b1cc81 | 1557 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce | 1558 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
e9b1cc81 | 1559 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce | 1560 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
e9b1cc81 | 1561 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce | 1562 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
e9b1cc81 | 1563 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce | 1564 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
e9b1cc81 | 1565 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce | 1566 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
e9b1cc81 | 1567 | "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver }, |
02c026ce DV |
1568 | { 0, NULL, NULL } |
1569 | }; | |
1570 | ||
1571 | static int find_gmch(u16 device) | |
1572 | { | |
1573 | struct pci_dev *gmch_device; | |
1574 | ||
1575 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1576 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1577 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1578 | device, gmch_device); | |
1579 | } | |
1580 | ||
1581 | if (!gmch_device) | |
1582 | return 0; | |
1583 | ||
1584 | intel_private.pcidev = gmch_device; | |
1585 | return 1; | |
1586 | } | |
1587 | ||
e2404e7c | 1588 | int intel_gmch_probe(struct pci_dev *pdev, |
02c026ce DV |
1589 | struct agp_bridge_data *bridge) |
1590 | { | |
1591 | int i, mask; | |
1592 | bridge->driver = NULL; | |
1593 | ||
1594 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | |
1595 | if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
1596 | bridge->driver = | |
1597 | intel_gtt_chipsets[i].gmch_driver; | |
1a997ff2 DV |
1598 | intel_private.driver = |
1599 | intel_gtt_chipsets[i].gtt_driver; | |
02c026ce DV |
1600 | break; |
1601 | } | |
1602 | } | |
1603 | ||
1604 | if (!bridge->driver) | |
1605 | return 0; | |
1606 | ||
1607 | bridge->dev_private_data = &intel_private; | |
1608 | bridge->dev = pdev; | |
1609 | ||
d7cca2f7 DV |
1610 | intel_private.bridge_dev = pci_dev_get(pdev); |
1611 | ||
02c026ce DV |
1612 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
1613 | ||
22533b49 | 1614 | mask = intel_private.driver->dma_mask_size; |
02c026ce DV |
1615 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
1616 | dev_err(&intel_private.pcidev->dev, | |
1617 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1618 | else | |
1619 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1620 | DMA_BIT_MASK(mask)); | |
1621 | ||
1784a5fb DV |
1622 | if (bridge->driver == &intel_810_driver) |
1623 | return 1; | |
1624 | ||
3b15a9d7 DV |
1625 | if (intel_gtt_init() != 0) |
1626 | return 0; | |
1784a5fb | 1627 | |
02c026ce DV |
1628 | return 1; |
1629 | } | |
e2404e7c | 1630 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1631 | |
19966754 DV |
1632 | struct intel_gtt *intel_gtt_get(void) |
1633 | { | |
1634 | return &intel_private.base; | |
1635 | } | |
1636 | EXPORT_SYMBOL(intel_gtt_get); | |
1637 | ||
e2404e7c | 1638 | void intel_gmch_remove(struct pci_dev *pdev) |
02c026ce DV |
1639 | { |
1640 | if (intel_private.pcidev) | |
1641 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1642 | if (intel_private.bridge_dev) |
1643 | pci_dev_put(intel_private.bridge_dev); | |
02c026ce | 1644 | } |
e2404e7c DV |
1645 | EXPORT_SYMBOL(intel_gmch_remove); |
1646 | ||
1647 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); | |
1648 | MODULE_LICENSE("GPL and additional rights"); |