Commit | Line | Data |
---|---|---|
f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/pagemap.h> | |
23 | #include <linux/agp_backend.h> | |
bdb8b975 | 24 | #include <linux/delay.h> |
e2404e7c DV |
25 | #include <asm/smp.h> |
26 | #include "agp.h" | |
27 | #include "intel-agp.h" | |
0ade6386 | 28 | #include <drm/intel-gtt.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
d3f13810 | 33 | * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). |
f51b7662 DV |
34 | * Only newer chipsets need to bother with this, of course. |
35 | */ | |
d3f13810 | 36 | #ifdef CONFIG_INTEL_IOMMU |
f51b7662 | 37 | #define USE_PCI_DMA_API 1 |
0e87d2b0 DV |
38 | #else |
39 | #define USE_PCI_DMA_API 0 | |
f51b7662 DV |
40 | #endif |
41 | ||
1a997ff2 DV |
42 | struct intel_gtt_driver { |
43 | unsigned int gen : 8; | |
44 | unsigned int is_g33 : 1; | |
45 | unsigned int is_pineview : 1; | |
46 | unsigned int is_ironlake : 1; | |
100519e2 | 47 | unsigned int has_pgtbl_enable : 1; |
22533b49 | 48 | unsigned int dma_mask_size : 8; |
73800422 DV |
49 | /* Chipset specific GTT setup */ |
50 | int (*setup)(void); | |
ae83dd5c DV |
51 | /* This should undo anything done in ->setup() save the unmapping |
52 | * of the mmio register file, that's done in the generic code. */ | |
53 | void (*cleanup)(void); | |
351bb278 DV |
54 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
55 | /* Flags is a more or less chipset specific opaque value. | |
56 | * For chipsets that need to support old ums (non-gem) code, this | |
57 | * needs to be identical to the various supported agp memory types! */ | |
5cbecafc | 58 | bool (*check_flags)(unsigned int flags); |
1b263f24 | 59 | void (*chipset_flush)(void); |
1a997ff2 DV |
60 | }; |
61 | ||
f51b7662 | 62 | static struct _intel_private { |
0ade6386 | 63 | struct intel_gtt base; |
1a997ff2 | 64 | const struct intel_gtt_driver *driver; |
f51b7662 | 65 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 66 | struct pci_dev *bridge_dev; |
f51b7662 | 67 | u8 __iomem *registers; |
f67eab66 | 68 | phys_addr_t gtt_bus_addr; |
b3eafc5a | 69 | u32 PGETBL_save; |
f51b7662 | 70 | u32 __iomem *gtt; /* I915G */ |
bee4a186 | 71 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
f51b7662 | 72 | int num_dcache_entries; |
bdb8b975 | 73 | void __iomem *i9xx_flush_page; |
820647b9 | 74 | char *i81x_gtt_table; |
f51b7662 DV |
75 | struct resource ifp_resource; |
76 | int resource_valid; | |
0e87d2b0 | 77 | struct page *scratch_page; |
14be93dd | 78 | int refcount; |
f51b7662 DV |
79 | } intel_private; |
80 | ||
1a997ff2 DV |
81 | #define INTEL_GTT_GEN intel_private.driver->gen |
82 | #define IS_G33 intel_private.driver->is_g33 | |
83 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
84 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
100519e2 | 85 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
1a997ff2 | 86 | |
4080775b DV |
87 | int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, |
88 | struct scatterlist **sg_list, int *num_sg) | |
f51b7662 DV |
89 | { |
90 | struct sg_table st; | |
91 | struct scatterlist *sg; | |
92 | int i; | |
93 | ||
4080775b | 94 | if (*sg_list) |
fefaa70f DV |
95 | return 0; /* already mapped (for e.g. resume */ |
96 | ||
4080775b | 97 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
f51b7662 | 98 | |
4080775b | 99 | if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) |
831cd445 | 100 | goto err; |
f51b7662 | 101 | |
4080775b | 102 | *sg_list = sg = st.sgl; |
f51b7662 | 103 | |
4080775b DV |
104 | for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) |
105 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); | |
f51b7662 | 106 | |
4080775b DV |
107 | *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, |
108 | num_entries, PCI_DMA_BIDIRECTIONAL); | |
109 | if (unlikely(!*num_sg)) | |
831cd445 CW |
110 | goto err; |
111 | ||
f51b7662 | 112 | return 0; |
831cd445 CW |
113 | |
114 | err: | |
115 | sg_free_table(&st); | |
116 | return -ENOMEM; | |
f51b7662 | 117 | } |
4080775b | 118 | EXPORT_SYMBOL(intel_gtt_map_memory); |
f51b7662 | 119 | |
4080775b | 120 | void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
f51b7662 | 121 | { |
4080775b | 122 | struct sg_table st; |
f51b7662 DV |
123 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
124 | ||
4080775b DV |
125 | pci_unmap_sg(intel_private.pcidev, sg_list, |
126 | num_sg, PCI_DMA_BIDIRECTIONAL); | |
127 | ||
128 | st.sgl = sg_list; | |
129 | st.orig_nents = st.nents = num_sg; | |
130 | ||
131 | sg_free_table(&st); | |
f51b7662 | 132 | } |
4080775b | 133 | EXPORT_SYMBOL(intel_gtt_unmap_memory); |
f51b7662 | 134 | |
ffdd7510 | 135 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
136 | { |
137 | return; | |
138 | } | |
139 | ||
140 | /* Exists to support ARGB cursors */ | |
141 | static struct page *i8xx_alloc_pages(void) | |
142 | { | |
143 | struct page *page; | |
144 | ||
145 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
146 | if (page == NULL) | |
147 | return NULL; | |
148 | ||
149 | if (set_pages_uc(page, 4) < 0) { | |
150 | set_pages_wb(page, 4); | |
151 | __free_pages(page, 2); | |
152 | return NULL; | |
153 | } | |
154 | get_page(page); | |
155 | atomic_inc(&agp_bridge->current_memory_agp); | |
156 | return page; | |
157 | } | |
158 | ||
159 | static void i8xx_destroy_pages(struct page *page) | |
160 | { | |
161 | if (page == NULL) | |
162 | return; | |
163 | ||
164 | set_pages_wb(page, 4); | |
165 | put_page(page); | |
166 | __free_pages(page, 2); | |
167 | atomic_dec(&agp_bridge->current_memory_agp); | |
168 | } | |
169 | ||
820647b9 DV |
170 | #define I810_GTT_ORDER 4 |
171 | static int i810_setup(void) | |
172 | { | |
173 | u32 reg_addr; | |
174 | char *gtt_table; | |
175 | ||
176 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ | |
177 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); | |
178 | if (gtt_table == NULL) | |
179 | return -ENOMEM; | |
180 | intel_private.i81x_gtt_table = gtt_table; | |
181 | ||
182 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
183 | reg_addr &= 0xfff80000; | |
184 | ||
185 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
186 | if (!intel_private.registers) | |
187 | return -ENOMEM; | |
188 | ||
189 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, | |
190 | intel_private.registers+I810_PGETBL_CTL); | |
191 | ||
192 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; | |
193 | ||
194 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
195 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
196 | dev_info(&intel_private.pcidev->dev, | |
197 | "detected 4MB dedicated video ram\n"); | |
198 | intel_private.num_dcache_entries = 1024; | |
199 | } | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | static void i810_cleanup(void) | |
205 | { | |
206 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
207 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); | |
208 | } | |
209 | ||
ff26860f DV |
210 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
211 | int type) | |
f51b7662 | 212 | { |
625dd9d3 | 213 | int i; |
f51b7662 | 214 | |
ff26860f DV |
215 | if ((pg_start + mem->page_count) |
216 | > intel_private.num_dcache_entries) | |
217 | return -EINVAL; | |
625dd9d3 | 218 | |
ff26860f DV |
219 | if (!mem->is_flushed) |
220 | global_cache_flush(); | |
f51b7662 | 221 | |
ff26860f DV |
222 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
223 | dma_addr_t addr = i << PAGE_SHIFT; | |
224 | intel_private.driver->write_entry(addr, | |
225 | i, type); | |
f51b7662 | 226 | } |
ff26860f | 227 | readl(intel_private.gtt+i-1); |
f51b7662 | 228 | |
ff26860f | 229 | return 0; |
f51b7662 DV |
230 | } |
231 | ||
232 | /* | |
233 | * The i810/i830 requires a physical address to program its mouse | |
234 | * pointer into hardware. | |
235 | * However the Xserver still writes to it through the agp aperture. | |
236 | */ | |
237 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
238 | { | |
239 | struct agp_memory *new; | |
240 | struct page *page; | |
241 | ||
242 | switch (pg_count) { | |
243 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
244 | break; | |
245 | case 4: | |
246 | /* kludge to get 4 physical pages for ARGB cursor */ | |
247 | page = i8xx_alloc_pages(); | |
248 | break; | |
249 | default: | |
250 | return NULL; | |
251 | } | |
252 | ||
253 | if (page == NULL) | |
254 | return NULL; | |
255 | ||
256 | new = agp_create_memory(pg_count); | |
257 | if (new == NULL) | |
258 | return NULL; | |
259 | ||
260 | new->pages[0] = page; | |
261 | if (pg_count == 4) { | |
262 | /* kludge to get 4 physical pages for ARGB cursor */ | |
263 | new->pages[1] = new->pages[0] + 1; | |
264 | new->pages[2] = new->pages[1] + 1; | |
265 | new->pages[3] = new->pages[2] + 1; | |
266 | } | |
267 | new->page_count = pg_count; | |
268 | new->num_scratch_pages = pg_count; | |
269 | new->type = AGP_PHYS_MEMORY; | |
270 | new->physical = page_to_phys(new->pages[0]); | |
271 | return new; | |
272 | } | |
273 | ||
f51b7662 DV |
274 | static void intel_i810_free_by_type(struct agp_memory *curr) |
275 | { | |
276 | agp_free_key(curr->key); | |
277 | if (curr->type == AGP_PHYS_MEMORY) { | |
278 | if (curr->page_count == 4) | |
279 | i8xx_destroy_pages(curr->pages[0]); | |
280 | else { | |
281 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
282 | AGP_PAGE_DESTROY_UNMAP); | |
283 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
284 | AGP_PAGE_DESTROY_FREE); | |
285 | } | |
286 | agp_free_page_array(curr); | |
287 | } | |
288 | kfree(curr); | |
289 | } | |
290 | ||
0e87d2b0 DV |
291 | static int intel_gtt_setup_scratch_page(void) |
292 | { | |
293 | struct page *page; | |
294 | dma_addr_t dma_addr; | |
295 | ||
296 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
297 | if (page == NULL) | |
298 | return -ENOMEM; | |
299 | get_page(page); | |
300 | set_pages_uc(page, 1); | |
301 | ||
4080775b | 302 | if (intel_private.base.needs_dmar) { |
0e87d2b0 DV |
303 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
304 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
305 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) | |
306 | return -EINVAL; | |
307 | ||
50a4c4a9 | 308 | intel_private.base.scratch_page_dma = dma_addr; |
0e87d2b0 | 309 | } else |
50a4c4a9 | 310 | intel_private.base.scratch_page_dma = page_to_phys(page); |
0e87d2b0 DV |
311 | |
312 | intel_private.scratch_page = page; | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
625dd9d3 DV |
317 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
318 | unsigned int flags) | |
319 | { | |
320 | u32 pte_flags = I810_PTE_VALID; | |
321 | ||
322 | switch (flags) { | |
323 | case AGP_DCACHE_MEMORY: | |
324 | pte_flags |= I810_PTE_LOCAL; | |
325 | break; | |
326 | case AGP_USER_CACHED_MEMORY: | |
327 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
328 | break; | |
329 | } | |
330 | ||
331 | writel(addr | pte_flags, intel_private.gtt + entry); | |
332 | } | |
333 | ||
7bdc9ab0 | 334 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
820647b9 DV |
335 | {32, 8192, 3}, |
336 | {64, 16384, 4}, | |
f51b7662 | 337 | {128, 32768, 5}, |
f51b7662 DV |
338 | {256, 65536, 6}, |
339 | {512, 131072, 7}, | |
340 | }; | |
341 | ||
c64f7ba5 | 342 | static unsigned int intel_gtt_stolen_size(void) |
f51b7662 DV |
343 | { |
344 | u16 gmch_ctrl; | |
f51b7662 DV |
345 | u8 rdct; |
346 | int local = 0; | |
347 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
d8d9abcd | 348 | unsigned int stolen_size = 0; |
f51b7662 | 349 | |
820647b9 DV |
350 | if (INTEL_GTT_GEN == 1) |
351 | return 0; /* no stolen mem on i81x */ | |
352 | ||
d7cca2f7 DV |
353 | pci_read_config_word(intel_private.bridge_dev, |
354 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 355 | |
d7cca2f7 DV |
356 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
357 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
358 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
359 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 360 | stolen_size = KB(512); |
f51b7662 DV |
361 | break; |
362 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 363 | stolen_size = MB(1); |
f51b7662 DV |
364 | break; |
365 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 366 | stolen_size = MB(8); |
f51b7662 DV |
367 | break; |
368 | case I830_GMCH_GMS_LOCAL: | |
369 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 370 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
371 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
372 | local = 1; | |
373 | break; | |
374 | default: | |
d8d9abcd | 375 | stolen_size = 0; |
f51b7662 DV |
376 | break; |
377 | } | |
1a997ff2 | 378 | } else if (INTEL_GTT_GEN == 6) { |
f51b7662 DV |
379 | /* |
380 | * SandyBridge has new memory control reg at 0x50.w | |
381 | */ | |
382 | u16 snb_gmch_ctl; | |
383 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
384 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
385 | case SNB_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 386 | stolen_size = MB(32); |
f51b7662 DV |
387 | break; |
388 | case SNB_GMCH_GMS_STOLEN_64M: | |
d8d9abcd | 389 | stolen_size = MB(64); |
f51b7662 DV |
390 | break; |
391 | case SNB_GMCH_GMS_STOLEN_96M: | |
d8d9abcd | 392 | stolen_size = MB(96); |
f51b7662 DV |
393 | break; |
394 | case SNB_GMCH_GMS_STOLEN_128M: | |
d8d9abcd | 395 | stolen_size = MB(128); |
f51b7662 DV |
396 | break; |
397 | case SNB_GMCH_GMS_STOLEN_160M: | |
d8d9abcd | 398 | stolen_size = MB(160); |
f51b7662 DV |
399 | break; |
400 | case SNB_GMCH_GMS_STOLEN_192M: | |
d8d9abcd | 401 | stolen_size = MB(192); |
f51b7662 DV |
402 | break; |
403 | case SNB_GMCH_GMS_STOLEN_224M: | |
d8d9abcd | 404 | stolen_size = MB(224); |
f51b7662 DV |
405 | break; |
406 | case SNB_GMCH_GMS_STOLEN_256M: | |
d8d9abcd | 407 | stolen_size = MB(256); |
f51b7662 DV |
408 | break; |
409 | case SNB_GMCH_GMS_STOLEN_288M: | |
d8d9abcd | 410 | stolen_size = MB(288); |
f51b7662 DV |
411 | break; |
412 | case SNB_GMCH_GMS_STOLEN_320M: | |
d8d9abcd | 413 | stolen_size = MB(320); |
f51b7662 DV |
414 | break; |
415 | case SNB_GMCH_GMS_STOLEN_352M: | |
d8d9abcd | 416 | stolen_size = MB(352); |
f51b7662 DV |
417 | break; |
418 | case SNB_GMCH_GMS_STOLEN_384M: | |
d8d9abcd | 419 | stolen_size = MB(384); |
f51b7662 DV |
420 | break; |
421 | case SNB_GMCH_GMS_STOLEN_416M: | |
d8d9abcd | 422 | stolen_size = MB(416); |
f51b7662 DV |
423 | break; |
424 | case SNB_GMCH_GMS_STOLEN_448M: | |
d8d9abcd | 425 | stolen_size = MB(448); |
f51b7662 DV |
426 | break; |
427 | case SNB_GMCH_GMS_STOLEN_480M: | |
d8d9abcd | 428 | stolen_size = MB(480); |
f51b7662 DV |
429 | break; |
430 | case SNB_GMCH_GMS_STOLEN_512M: | |
d8d9abcd | 431 | stolen_size = MB(512); |
f51b7662 DV |
432 | break; |
433 | } | |
434 | } else { | |
435 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
436 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 437 | stolen_size = MB(1); |
f51b7662 DV |
438 | break; |
439 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 440 | stolen_size = MB(4); |
f51b7662 DV |
441 | break; |
442 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 443 | stolen_size = MB(8); |
f51b7662 DV |
444 | break; |
445 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 446 | stolen_size = MB(16); |
f51b7662 DV |
447 | break; |
448 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 449 | stolen_size = MB(32); |
f51b7662 DV |
450 | break; |
451 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 452 | stolen_size = MB(48); |
f51b7662 DV |
453 | break; |
454 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 455 | stolen_size = MB(64); |
f51b7662 DV |
456 | break; |
457 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 458 | stolen_size = MB(128); |
f51b7662 DV |
459 | break; |
460 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 461 | stolen_size = MB(256); |
f51b7662 DV |
462 | break; |
463 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 464 | stolen_size = MB(96); |
f51b7662 DV |
465 | break; |
466 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 467 | stolen_size = MB(160); |
f51b7662 DV |
468 | break; |
469 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 470 | stolen_size = MB(224); |
f51b7662 DV |
471 | break; |
472 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 473 | stolen_size = MB(352); |
f51b7662 DV |
474 | break; |
475 | default: | |
d8d9abcd | 476 | stolen_size = 0; |
f51b7662 DV |
477 | break; |
478 | } | |
479 | } | |
1784a5fb | 480 | |
1b6064d7 | 481 | if (stolen_size > 0) { |
d7cca2f7 | 482 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
d8d9abcd | 483 | stolen_size / KB(1), local ? "local" : "stolen"); |
f51b7662 | 484 | } else { |
d7cca2f7 | 485 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 486 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 487 | stolen_size = 0; |
f51b7662 DV |
488 | } |
489 | ||
c64f7ba5 | 490 | return stolen_size; |
f51b7662 DV |
491 | } |
492 | ||
20172842 DV |
493 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
494 | { | |
495 | u32 pgetbl_ctl, pgetbl_ctl2; | |
496 | ||
497 | /* ensure that ppgtt is disabled */ | |
498 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); | |
499 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; | |
500 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); | |
501 | ||
502 | /* write the new ggtt size */ | |
503 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
504 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; | |
505 | pgetbl_ctl |= size_flag; | |
506 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); | |
507 | } | |
508 | ||
509 | static unsigned int i965_gtt_total_entries(void) | |
fbe40783 DV |
510 | { |
511 | int size; | |
20172842 DV |
512 | u32 pgetbl_ctl; |
513 | u16 gmch_ctl; | |
fbe40783 | 514 | |
20172842 DV |
515 | pci_read_config_word(intel_private.bridge_dev, |
516 | I830_GMCH_CTRL, &gmch_ctl); | |
fbe40783 | 517 | |
20172842 DV |
518 | if (INTEL_GTT_GEN == 5) { |
519 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { | |
520 | case G4x_GMCH_SIZE_1M: | |
521 | case G4x_GMCH_SIZE_VT_1M: | |
522 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); | |
fbe40783 | 523 | break; |
20172842 DV |
524 | case G4x_GMCH_SIZE_VT_1_5M: |
525 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); | |
fbe40783 | 526 | break; |
20172842 DV |
527 | case G4x_GMCH_SIZE_2M: |
528 | case G4x_GMCH_SIZE_VT_2M: | |
529 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); | |
fbe40783 | 530 | break; |
fbe40783 | 531 | } |
20172842 | 532 | } |
e5e408fc | 533 | |
20172842 DV |
534 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
535 | ||
536 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
537 | case I965_PGETBL_SIZE_128KB: | |
538 | size = KB(128); | |
539 | break; | |
540 | case I965_PGETBL_SIZE_256KB: | |
541 | size = KB(256); | |
542 | break; | |
543 | case I965_PGETBL_SIZE_512KB: | |
544 | size = KB(512); | |
545 | break; | |
546 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ | |
547 | case I965_PGETBL_SIZE_1MB: | |
548 | size = KB(1024); | |
549 | break; | |
550 | case I965_PGETBL_SIZE_2MB: | |
551 | size = KB(2048); | |
552 | break; | |
553 | case I965_PGETBL_SIZE_1_5MB: | |
554 | size = KB(1024 + 512); | |
555 | break; | |
556 | default: | |
557 | dev_info(&intel_private.pcidev->dev, | |
558 | "unknown page table size, assuming 512KB\n"); | |
559 | size = KB(512); | |
560 | } | |
561 | ||
562 | return size/4; | |
563 | } | |
564 | ||
565 | static unsigned int intel_gtt_total_entries(void) | |
566 | { | |
567 | int size; | |
568 | ||
569 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) | |
570 | return i965_gtt_total_entries(); | |
571 | else if (INTEL_GTT_GEN == 6) { | |
210b23c2 DV |
572 | u16 snb_gmch_ctl; |
573 | ||
574 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
575 | switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { | |
576 | default: | |
577 | case SNB_GTT_SIZE_0M: | |
578 | printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); | |
579 | size = MB(0); | |
580 | break; | |
581 | case SNB_GTT_SIZE_1M: | |
582 | size = MB(1); | |
583 | break; | |
584 | case SNB_GTT_SIZE_2M: | |
585 | size = MB(2); | |
586 | break; | |
587 | } | |
e5e408fc | 588 | return size/4; |
fbe40783 DV |
589 | } else { |
590 | /* On previous hardware, the GTT size was just what was | |
591 | * required to map the aperture. | |
592 | */ | |
e5e408fc | 593 | return intel_private.base.gtt_mappable_entries; |
fbe40783 | 594 | } |
fbe40783 | 595 | } |
fbe40783 | 596 | |
1784a5fb DV |
597 | static unsigned int intel_gtt_mappable_entries(void) |
598 | { | |
599 | unsigned int aperture_size; | |
1784a5fb | 600 | |
820647b9 DV |
601 | if (INTEL_GTT_GEN == 1) { |
602 | u32 smram_miscc; | |
603 | ||
604 | pci_read_config_dword(intel_private.bridge_dev, | |
605 | I810_SMRAM_MISCC, &smram_miscc); | |
606 | ||
607 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) | |
608 | == I810_GFX_MEM_WIN_32M) | |
609 | aperture_size = MB(32); | |
610 | else | |
611 | aperture_size = MB(64); | |
612 | } else if (INTEL_GTT_GEN == 2) { | |
b1c5b0f8 | 613 | u16 gmch_ctrl; |
1784a5fb | 614 | |
b1c5b0f8 CW |
615 | pci_read_config_word(intel_private.bridge_dev, |
616 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 617 | |
1784a5fb | 618 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 619 | aperture_size = MB(64); |
1784a5fb | 620 | else |
b1c5b0f8 | 621 | aperture_size = MB(128); |
239918f7 | 622 | } else { |
1784a5fb DV |
623 | /* 9xx supports large sizes, just look at the length */ |
624 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
625 | } |
626 | ||
627 | return aperture_size >> PAGE_SHIFT; | |
628 | } | |
629 | ||
0e87d2b0 DV |
630 | static void intel_gtt_teardown_scratch_page(void) |
631 | { | |
632 | set_pages_wb(intel_private.scratch_page, 1); | |
50a4c4a9 | 633 | pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, |
0e87d2b0 DV |
634 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
635 | put_page(intel_private.scratch_page); | |
636 | __free_page(intel_private.scratch_page); | |
637 | } | |
638 | ||
639 | static void intel_gtt_cleanup(void) | |
640 | { | |
ae83dd5c DV |
641 | intel_private.driver->cleanup(); |
642 | ||
0e87d2b0 DV |
643 | iounmap(intel_private.gtt); |
644 | iounmap(intel_private.registers); | |
625dd9d3 | 645 | |
0e87d2b0 DV |
646 | intel_gtt_teardown_scratch_page(); |
647 | } | |
648 | ||
1784a5fb DV |
649 | static int intel_gtt_init(void) |
650 | { | |
f67eab66 | 651 | u32 gtt_map_size; |
3b15a9d7 DV |
652 | int ret; |
653 | ||
3b15a9d7 DV |
654 | ret = intel_private.driver->setup(); |
655 | if (ret != 0) | |
656 | return ret; | |
f67eab66 DV |
657 | |
658 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); | |
659 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); | |
660 | ||
b3eafc5a DV |
661 | /* save the PGETBL reg for resume */ |
662 | intel_private.PGETBL_save = | |
663 | readl(intel_private.registers+I810_PGETBL_CTL) | |
664 | & ~I810_PGETBL_ENABLED; | |
100519e2 CW |
665 | /* we only ever restore the register when enabling the PGTBL... */ |
666 | if (HAS_PGTBL_EN) | |
667 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; | |
b3eafc5a | 668 | |
0af9e92e DV |
669 | dev_info(&intel_private.bridge_dev->dev, |
670 | "detected gtt size: %dK total, %dK mappable\n", | |
671 | intel_private.base.gtt_total_entries * 4, | |
672 | intel_private.base.gtt_mappable_entries * 4); | |
673 | ||
f67eab66 DV |
674 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
675 | ||
676 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, | |
677 | gtt_map_size); | |
678 | if (!intel_private.gtt) { | |
ae83dd5c | 679 | intel_private.driver->cleanup(); |
f67eab66 DV |
680 | iounmap(intel_private.registers); |
681 | return -ENOMEM; | |
682 | } | |
428ccb21 | 683 | intel_private.base.gtt = intel_private.gtt; |
f67eab66 DV |
684 | |
685 | global_cache_flush(); /* FIXME: ? */ | |
686 | ||
c64f7ba5 | 687 | intel_private.base.stolen_size = intel_gtt_stolen_size(); |
1784a5fb | 688 | |
a46f3108 DA |
689 | intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
690 | ||
0e87d2b0 DV |
691 | ret = intel_gtt_setup_scratch_page(); |
692 | if (ret != 0) { | |
693 | intel_gtt_cleanup(); | |
694 | return ret; | |
695 | } | |
696 | ||
1784a5fb DV |
697 | return 0; |
698 | } | |
699 | ||
3e921f98 DV |
700 | static int intel_fake_agp_fetch_size(void) |
701 | { | |
9e76e7b8 | 702 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
703 | unsigned int aper_size; |
704 | int i; | |
3e921f98 DV |
705 | |
706 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) | |
707 | / MB(1); | |
708 | ||
709 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 710 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
711 | agp_bridge->current_size = |
712 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
713 | return aper_size; |
714 | } | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
ae83dd5c | 720 | static void i830_cleanup(void) |
f51b7662 | 721 | { |
f51b7662 DV |
722 | } |
723 | ||
724 | /* The chipset_flush interface needs to get data that has already been | |
725 | * flushed out of the CPU all the way out to main memory, because the GPU | |
726 | * doesn't snoop those buffers. | |
727 | * | |
728 | * The 8xx series doesn't have the same lovely interface for flushing the | |
729 | * chipset write buffers that the later chips do. According to the 865 | |
730 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
731 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
732 | * that it'll push whatever was in there out. It appears to work. | |
733 | */ | |
1b263f24 | 734 | static void i830_chipset_flush(void) |
f51b7662 | 735 | { |
bdb8b975 CW |
736 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
737 | ||
738 | /* Forcibly evict everything from the CPU write buffers. | |
739 | * clflush appears to be insufficient. | |
740 | */ | |
741 | wbinvd_on_all_cpus(); | |
742 | ||
743 | /* Now we've only seen documents for this magic bit on 855GM, | |
744 | * we hope it exists for the other gen2 chipsets... | |
745 | * | |
746 | * Also works as advertised on my 845G. | |
747 | */ | |
748 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), | |
749 | intel_private.registers+I830_HIC); | |
f51b7662 | 750 | |
bdb8b975 CW |
751 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
752 | if (time_after(jiffies, timeout)) | |
753 | break; | |
f51b7662 | 754 | |
bdb8b975 CW |
755 | udelay(50); |
756 | } | |
f51b7662 DV |
757 | } |
758 | ||
351bb278 DV |
759 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
760 | unsigned int flags) | |
761 | { | |
762 | u32 pte_flags = I810_PTE_VALID; | |
625dd9d3 | 763 | |
b47cf66f | 764 | if (flags == AGP_USER_CACHED_MEMORY) |
351bb278 | 765 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
351bb278 DV |
766 | |
767 | writel(addr | pte_flags, intel_private.gtt + entry); | |
768 | } | |
769 | ||
e380f60b | 770 | static bool intel_enable_gtt(void) |
f51b7662 | 771 | { |
3f08e4ef | 772 | u32 gma_addr; |
e380f60b | 773 | u8 __iomem *reg; |
f51b7662 | 774 | |
820647b9 | 775 | if (INTEL_GTT_GEN <= 2) |
2d2430cf DV |
776 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, |
777 | &gma_addr); | |
778 | else | |
779 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, | |
780 | &gma_addr); | |
781 | ||
dd2757f8 | 782 | intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
f51b7662 | 783 | |
e380f60b CW |
784 | if (INTEL_GTT_GEN >= 6) |
785 | return true; | |
786 | ||
100519e2 CW |
787 | if (INTEL_GTT_GEN == 2) { |
788 | u16 gmch_ctrl; | |
73800422 | 789 | |
100519e2 CW |
790 | pci_read_config_word(intel_private.bridge_dev, |
791 | I830_GMCH_CTRL, &gmch_ctrl); | |
792 | gmch_ctrl |= I830_GMCH_ENABLED; | |
793 | pci_write_config_word(intel_private.bridge_dev, | |
794 | I830_GMCH_CTRL, gmch_ctrl); | |
795 | ||
796 | pci_read_config_word(intel_private.bridge_dev, | |
797 | I830_GMCH_CTRL, &gmch_ctrl); | |
798 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { | |
799 | dev_err(&intel_private.pcidev->dev, | |
800 | "failed to enable the GTT: GMCH_CTRL=%x\n", | |
801 | gmch_ctrl); | |
802 | return false; | |
803 | } | |
e380f60b CW |
804 | } |
805 | ||
c97689d8 CW |
806 | /* On the resume path we may be adjusting the PGTBL value, so |
807 | * be paranoid and flush all chipset write buffers... | |
808 | */ | |
809 | if (INTEL_GTT_GEN >= 3) | |
810 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
811 | ||
e380f60b | 812 | reg = intel_private.registers+I810_PGETBL_CTL; |
100519e2 CW |
813 | writel(intel_private.PGETBL_save, reg); |
814 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { | |
e380f60b | 815 | dev_err(&intel_private.pcidev->dev, |
100519e2 | 816 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
e380f60b CW |
817 | readl(reg), intel_private.PGETBL_save); |
818 | return false; | |
819 | } | |
820 | ||
c97689d8 CW |
821 | if (INTEL_GTT_GEN >= 3) |
822 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
823 | ||
e380f60b | 824 | return true; |
73800422 DV |
825 | } |
826 | ||
827 | static int i830_setup(void) | |
828 | { | |
829 | u32 reg_addr; | |
830 | ||
831 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); | |
832 | reg_addr &= 0xfff80000; | |
833 | ||
834 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
835 | if (!intel_private.registers) |
836 | return -ENOMEM; | |
837 | ||
73800422 DV |
838 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
839 | ||
73800422 DV |
840 | return 0; |
841 | } | |
842 | ||
3b15a9d7 | 843 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 844 | { |
73800422 | 845 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 846 | agp_bridge->gatt_table = NULL; |
73800422 | 847 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
848 | |
849 | return 0; | |
850 | } | |
851 | ||
ffdd7510 | 852 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
853 | { |
854 | return 0; | |
855 | } | |
856 | ||
351bb278 | 857 | static int intel_fake_agp_configure(void) |
f51b7662 | 858 | { |
e380f60b CW |
859 | if (!intel_enable_gtt()) |
860 | return -EIO; | |
f51b7662 | 861 | |
bee4a186 | 862 | intel_private.clear_fake_agp = true; |
dd2757f8 | 863 | agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr; |
f51b7662 | 864 | |
f51b7662 DV |
865 | return 0; |
866 | } | |
867 | ||
5cbecafc | 868 | static bool i830_check_flags(unsigned int flags) |
f51b7662 | 869 | { |
5cbecafc DV |
870 | switch (flags) { |
871 | case 0: | |
872 | case AGP_PHYS_MEMORY: | |
873 | case AGP_USER_CACHED_MEMORY: | |
874 | case AGP_USER_MEMORY: | |
875 | return true; | |
876 | } | |
877 | ||
878 | return false; | |
879 | } | |
880 | ||
4080775b DV |
881 | void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
882 | unsigned int sg_len, | |
883 | unsigned int pg_start, | |
884 | unsigned int flags) | |
fefaa70f DV |
885 | { |
886 | struct scatterlist *sg; | |
887 | unsigned int len, m; | |
888 | int i, j; | |
889 | ||
890 | j = pg_start; | |
891 | ||
892 | /* sg may merge pages, but we have to separate | |
893 | * per-page addr for GTT */ | |
894 | for_each_sg(sg_list, sg, sg_len, i) { | |
895 | len = sg_dma_len(sg) >> PAGE_SHIFT; | |
896 | for (m = 0; m < len; m++) { | |
897 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
898 | intel_private.driver->write_entry(addr, | |
899 | j, flags); | |
900 | j++; | |
901 | } | |
902 | } | |
903 | readl(intel_private.gtt+j-1); | |
904 | } | |
4080775b DV |
905 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
906 | ||
907 | void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, | |
908 | struct page **pages, unsigned int flags) | |
909 | { | |
910 | int i, j; | |
911 | ||
912 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { | |
913 | dma_addr_t addr = page_to_phys(pages[i]); | |
914 | intel_private.driver->write_entry(addr, | |
915 | j, flags); | |
916 | } | |
917 | readl(intel_private.gtt+j-1); | |
918 | } | |
919 | EXPORT_SYMBOL(intel_gtt_insert_pages); | |
fefaa70f | 920 | |
5cbecafc DV |
921 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
922 | off_t pg_start, int type) | |
923 | { | |
f51b7662 | 924 | int ret = -EINVAL; |
f51b7662 | 925 | |
5c042287 BW |
926 | if (intel_private.base.do_idle_maps) |
927 | return -ENODEV; | |
928 | ||
bee4a186 CW |
929 | if (intel_private.clear_fake_agp) { |
930 | int start = intel_private.base.stolen_size / PAGE_SIZE; | |
931 | int end = intel_private.base.gtt_mappable_entries; | |
932 | intel_gtt_clear_range(start, end - start); | |
933 | intel_private.clear_fake_agp = false; | |
934 | } | |
935 | ||
ff26860f DV |
936 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
937 | return i810_insert_dcache_entries(mem, pg_start, type); | |
938 | ||
f51b7662 DV |
939 | if (mem->page_count == 0) |
940 | goto out; | |
941 | ||
c64f7ba5 | 942 | if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) |
f51b7662 DV |
943 | goto out_err; |
944 | ||
f51b7662 DV |
945 | if (type != mem->type) |
946 | goto out_err; | |
947 | ||
5cbecafc | 948 | if (!intel_private.driver->check_flags(type)) |
f51b7662 DV |
949 | goto out_err; |
950 | ||
951 | if (!mem->is_flushed) | |
952 | global_cache_flush(); | |
953 | ||
4080775b DV |
954 | if (intel_private.base.needs_dmar) { |
955 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, | |
956 | &mem->sg_list, &mem->num_sg); | |
fefaa70f DV |
957 | if (ret != 0) |
958 | return ret; | |
959 | ||
960 | intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, | |
961 | pg_start, type); | |
4080775b DV |
962 | } else |
963 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, | |
964 | type); | |
f51b7662 DV |
965 | |
966 | out: | |
967 | ret = 0; | |
968 | out_err: | |
969 | mem->is_flushed = true; | |
970 | return ret; | |
971 | } | |
972 | ||
4080775b DV |
973 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
974 | { | |
975 | unsigned int i; | |
976 | ||
977 | for (i = first_entry; i < (first_entry + num_entries); i++) { | |
50a4c4a9 | 978 | intel_private.driver->write_entry(intel_private.base.scratch_page_dma, |
4080775b DV |
979 | i, 0); |
980 | } | |
981 | readl(intel_private.gtt+i-1); | |
982 | } | |
983 | EXPORT_SYMBOL(intel_gtt_clear_range); | |
984 | ||
5cbecafc DV |
985 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
986 | off_t pg_start, int type) | |
f51b7662 | 987 | { |
f51b7662 DV |
988 | if (mem->page_count == 0) |
989 | return 0; | |
990 | ||
5c042287 BW |
991 | if (intel_private.base.do_idle_maps) |
992 | return -ENODEV; | |
993 | ||
d15eda5c DA |
994 | intel_gtt_clear_range(pg_start, mem->page_count); |
995 | ||
4080775b DV |
996 | if (intel_private.base.needs_dmar) { |
997 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); | |
998 | mem->sg_list = NULL; | |
999 | mem->num_sg = 0; | |
f51b7662 | 1000 | } |
4080775b | 1001 | |
f51b7662 DV |
1002 | return 0; |
1003 | } | |
1004 | ||
ffdd7510 DV |
1005 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
1006 | int type) | |
f51b7662 | 1007 | { |
625dd9d3 DV |
1008 | struct agp_memory *new; |
1009 | ||
1010 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { | |
1011 | if (pg_count != intel_private.num_dcache_entries) | |
1012 | return NULL; | |
1013 | ||
1014 | new = agp_create_memory(1); | |
1015 | if (new == NULL) | |
1016 | return NULL; | |
1017 | ||
1018 | new->type = AGP_DCACHE_MEMORY; | |
1019 | new->page_count = pg_count; | |
1020 | new->num_scratch_pages = 0; | |
1021 | agp_free_page_array(new); | |
1022 | return new; | |
1023 | } | |
f51b7662 DV |
1024 | if (type == AGP_PHYS_MEMORY) |
1025 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1026 | /* always return NULL for other allocation types for now */ | |
1027 | return NULL; | |
1028 | } | |
1029 | ||
1030 | static int intel_alloc_chipset_flush_resource(void) | |
1031 | { | |
1032 | int ret; | |
d7cca2f7 | 1033 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1034 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1035 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1036 | |
1037 | return ret; | |
1038 | } | |
1039 | ||
1040 | static void intel_i915_setup_chipset_flush(void) | |
1041 | { | |
1042 | int ret; | |
1043 | u32 temp; | |
1044 | ||
d7cca2f7 | 1045 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1046 | if (!(temp & 0x1)) { |
1047 | intel_alloc_chipset_flush_resource(); | |
1048 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1049 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1050 | } else { |
1051 | temp &= ~1; | |
1052 | ||
1053 | intel_private.resource_valid = 1; | |
1054 | intel_private.ifp_resource.start = temp; | |
1055 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1056 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1057 | /* some BIOSes reserve this area in a pnp some don't */ | |
1058 | if (ret) | |
1059 | intel_private.resource_valid = 0; | |
1060 | } | |
1061 | } | |
1062 | ||
1063 | static void intel_i965_g33_setup_chipset_flush(void) | |
1064 | { | |
1065 | u32 temp_hi, temp_lo; | |
1066 | int ret; | |
1067 | ||
d7cca2f7 DV |
1068 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1069 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1070 | |
1071 | if (!(temp_lo & 0x1)) { | |
1072 | ||
1073 | intel_alloc_chipset_flush_resource(); | |
1074 | ||
1075 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1076 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1077 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1078 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1079 | } else { |
1080 | u64 l64; | |
1081 | ||
1082 | temp_lo &= ~0x1; | |
1083 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1084 | ||
1085 | intel_private.resource_valid = 1; | |
1086 | intel_private.ifp_resource.start = l64; | |
1087 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1088 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1089 | /* some BIOSes reserve this area in a pnp some don't */ | |
1090 | if (ret) | |
1091 | intel_private.resource_valid = 0; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | static void intel_i9xx_setup_flush(void) | |
1096 | { | |
1097 | /* return if already configured */ | |
1098 | if (intel_private.ifp_resource.start) | |
1099 | return; | |
1100 | ||
1a997ff2 | 1101 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1102 | return; |
1103 | ||
1104 | /* setup a resource for this object */ | |
1105 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1106 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1107 | ||
1108 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1109 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1110 | intel_i965_g33_setup_chipset_flush(); |
1111 | } else { | |
1112 | intel_i915_setup_chipset_flush(); | |
1113 | } | |
1114 | ||
df51e7aa | 1115 | if (intel_private.ifp_resource.start) |
f51b7662 | 1116 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1117 | if (!intel_private.i9xx_flush_page) |
1118 | dev_err(&intel_private.pcidev->dev, | |
1119 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1120 | } |
1121 | ||
ae83dd5c DV |
1122 | static void i9xx_cleanup(void) |
1123 | { | |
1124 | if (intel_private.i9xx_flush_page) | |
1125 | iounmap(intel_private.i9xx_flush_page); | |
1126 | if (intel_private.resource_valid) | |
1127 | release_resource(&intel_private.ifp_resource); | |
1128 | intel_private.ifp_resource.start = 0; | |
1129 | intel_private.resource_valid = 0; | |
1130 | } | |
1131 | ||
1b263f24 | 1132 | static void i9xx_chipset_flush(void) |
f51b7662 DV |
1133 | { |
1134 | if (intel_private.i9xx_flush_page) | |
1135 | writel(1, intel_private.i9xx_flush_page); | |
1136 | } | |
1137 | ||
71f45660 CW |
1138 | static void i965_write_entry(dma_addr_t addr, |
1139 | unsigned int entry, | |
a6963596 DV |
1140 | unsigned int flags) |
1141 | { | |
71f45660 CW |
1142 | u32 pte_flags; |
1143 | ||
1144 | pte_flags = I810_PTE_VALID; | |
1145 | if (flags == AGP_USER_CACHED_MEMORY) | |
1146 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
1147 | ||
a6963596 DV |
1148 | /* Shift high bits down */ |
1149 | addr |= (addr >> 28) & 0xf0; | |
71f45660 | 1150 | writel(addr | pte_flags, intel_private.gtt + entry); |
a6963596 DV |
1151 | } |
1152 | ||
90cb149e DV |
1153 | static bool gen6_check_flags(unsigned int flags) |
1154 | { | |
1155 | return true; | |
1156 | } | |
1157 | ||
97ef1bdd DV |
1158 | static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
1159 | unsigned int flags) | |
1160 | { | |
1161 | unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; | |
1162 | unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; | |
1163 | u32 pte_flags; | |
1164 | ||
897ef192 | 1165 | if (type_mask == AGP_USER_MEMORY) |
85ccc35b | 1166 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
97ef1bdd | 1167 | else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
d1108525 | 1168 | pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
97ef1bdd DV |
1169 | if (gfdt) |
1170 | pte_flags |= GEN6_PTE_GFDT; | |
1171 | } else { /* set 'normal'/'cached' to LLC by default */ | |
d1108525 | 1172 | pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
97ef1bdd DV |
1173 | if (gfdt) |
1174 | pte_flags |= GEN6_PTE_GFDT; | |
1175 | } | |
1176 | ||
1177 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1178 | addr |= (addr >> 28) & 0xff0; | |
1179 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1180 | } | |
1181 | ||
64757876 JB |
1182 | static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, |
1183 | unsigned int flags) | |
1184 | { | |
1185 | u32 pte_flags; | |
1186 | ||
1187 | pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; | |
1188 | ||
1189 | /* gen6 has bit11-4 for physical addr bit39-32 */ | |
1190 | addr |= (addr >> 28) & 0xff0; | |
1191 | writel(addr | pte_flags, intel_private.gtt + entry); | |
1192 | ||
1193 | writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV); | |
1194 | } | |
1195 | ||
ae83dd5c DV |
1196 | static void gen6_cleanup(void) |
1197 | { | |
1198 | } | |
1199 | ||
5c042287 BW |
1200 | /* Certain Gen5 chipsets require require idling the GPU before |
1201 | * unmapping anything from the GTT when VT-d is enabled. | |
1202 | */ | |
5c042287 BW |
1203 | static inline int needs_idle_maps(void) |
1204 | { | |
a08185a3 | 1205 | #ifdef CONFIG_INTEL_IOMMU |
5c042287 BW |
1206 | const unsigned short gpu_devid = intel_private.pcidev->device; |
1207 | ||
1208 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1209 | * was loaded first. | |
1210 | */ | |
1211 | if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || | |
1212 | gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && | |
1213 | intel_iommu_gfx_mapped) | |
1214 | return 1; | |
a08185a3 | 1215 | #endif |
5c042287 BW |
1216 | return 0; |
1217 | } | |
1218 | ||
2d2430cf | 1219 | static int i9xx_setup(void) |
f51b7662 | 1220 | { |
2d2430cf | 1221 | u32 reg_addr; |
4b60d29e | 1222 | int size = KB(512); |
f51b7662 | 1223 | |
2d2430cf | 1224 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
f51b7662 | 1225 | |
2d2430cf | 1226 | reg_addr &= 0xfff80000; |
f1befe71 | 1227 | |
4b60d29e JB |
1228 | if (INTEL_GTT_GEN >= 7) |
1229 | size = MB(2); | |
1230 | ||
1231 | intel_private.registers = ioremap(reg_addr, size); | |
ccc4e67b | 1232 | if (!intel_private.registers) |
f51b7662 DV |
1233 | return -ENOMEM; |
1234 | ||
2d2430cf DV |
1235 | if (INTEL_GTT_GEN == 3) { |
1236 | u32 gtt_addr; | |
3f08e4ef | 1237 | |
2d2430cf DV |
1238 | pci_read_config_dword(intel_private.pcidev, |
1239 | I915_PTEADDR, >t_addr); | |
1240 | intel_private.gtt_bus_addr = gtt_addr; | |
1241 | } else { | |
1242 | u32 gtt_offset; | |
1243 | ||
1244 | switch (INTEL_GTT_GEN) { | |
1245 | case 5: | |
1246 | case 6: | |
1247 | gtt_offset = MB(2); | |
1248 | break; | |
1249 | case 4: | |
1250 | default: | |
1251 | gtt_offset = KB(512); | |
1252 | break; | |
1253 | } | |
1254 | intel_private.gtt_bus_addr = reg_addr + gtt_offset; | |
1255 | } | |
1256 | ||
35b09c9b | 1257 | if (needs_idle_maps()) |
5c042287 BW |
1258 | intel_private.base.do_idle_maps = 1; |
1259 | ||
2d2430cf DV |
1260 | intel_i9xx_setup_flush(); |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
e9b1cc81 | 1265 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
f51b7662 | 1266 | .owner = THIS_MODULE, |
f51b7662 | 1267 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1268 | .aperture_sizes = intel_fake_agp_sizes, |
1269 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
a6963596 | 1270 | .configure = intel_fake_agp_configure, |
3e921f98 | 1271 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1272 | .cleanup = intel_gtt_cleanup, |
ffdd7510 | 1273 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1274 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1275 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1276 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
450f2b3d DV |
1277 | .insert_memory = intel_fake_agp_insert_entries, |
1278 | .remove_memory = intel_fake_agp_remove_entries, | |
ffdd7510 | 1279 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1280 | .free_by_type = intel_i810_free_by_type, |
1281 | .agp_alloc_page = agp_generic_alloc_page, | |
1282 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1283 | .agp_destroy_page = agp_generic_destroy_page, | |
1284 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f51b7662 | 1285 | }; |
02c026ce | 1286 | |
bdd30729 DV |
1287 | static const struct intel_gtt_driver i81x_gtt_driver = { |
1288 | .gen = 1, | |
820647b9 | 1289 | .has_pgtbl_enable = 1, |
22533b49 | 1290 | .dma_mask_size = 32, |
820647b9 DV |
1291 | .setup = i810_setup, |
1292 | .cleanup = i810_cleanup, | |
625dd9d3 DV |
1293 | .check_flags = i830_check_flags, |
1294 | .write_entry = i810_write_entry, | |
bdd30729 | 1295 | }; |
1a997ff2 DV |
1296 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1297 | .gen = 2, | |
100519e2 | 1298 | .has_pgtbl_enable = 1, |
73800422 | 1299 | .setup = i830_setup, |
ae83dd5c | 1300 | .cleanup = i830_cleanup, |
351bb278 | 1301 | .write_entry = i830_write_entry, |
22533b49 | 1302 | .dma_mask_size = 32, |
5cbecafc | 1303 | .check_flags = i830_check_flags, |
1b263f24 | 1304 | .chipset_flush = i830_chipset_flush, |
1a997ff2 DV |
1305 | }; |
1306 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1307 | .gen = 3, | |
100519e2 | 1308 | .has_pgtbl_enable = 1, |
2d2430cf | 1309 | .setup = i9xx_setup, |
ae83dd5c | 1310 | .cleanup = i9xx_cleanup, |
351bb278 | 1311 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
625dd9d3 | 1312 | .write_entry = i830_write_entry, |
22533b49 | 1313 | .dma_mask_size = 32, |
fefaa70f | 1314 | .check_flags = i830_check_flags, |
1b263f24 | 1315 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1316 | }; |
1317 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1318 | .gen = 3, | |
1319 | .is_g33 = 1, | |
2d2430cf | 1320 | .setup = i9xx_setup, |
ae83dd5c | 1321 | .cleanup = i9xx_cleanup, |
a6963596 | 1322 | .write_entry = i965_write_entry, |
22533b49 | 1323 | .dma_mask_size = 36, |
450f2b3d | 1324 | .check_flags = i830_check_flags, |
1b263f24 | 1325 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1326 | }; |
1327 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1328 | .gen = 3, | |
1329 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1330 | .setup = i9xx_setup, |
ae83dd5c | 1331 | .cleanup = i9xx_cleanup, |
a6963596 | 1332 | .write_entry = i965_write_entry, |
22533b49 | 1333 | .dma_mask_size = 36, |
450f2b3d | 1334 | .check_flags = i830_check_flags, |
1b263f24 | 1335 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1336 | }; |
1337 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1338 | .gen = 4, | |
100519e2 | 1339 | .has_pgtbl_enable = 1, |
2d2430cf | 1340 | .setup = i9xx_setup, |
ae83dd5c | 1341 | .cleanup = i9xx_cleanup, |
a6963596 | 1342 | .write_entry = i965_write_entry, |
22533b49 | 1343 | .dma_mask_size = 36, |
450f2b3d | 1344 | .check_flags = i830_check_flags, |
1b263f24 | 1345 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1346 | }; |
1347 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1348 | .gen = 5, | |
2d2430cf | 1349 | .setup = i9xx_setup, |
ae83dd5c | 1350 | .cleanup = i9xx_cleanup, |
a6963596 | 1351 | .write_entry = i965_write_entry, |
22533b49 | 1352 | .dma_mask_size = 36, |
450f2b3d | 1353 | .check_flags = i830_check_flags, |
1b263f24 | 1354 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1355 | }; |
1356 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1357 | .gen = 5, | |
1358 | .is_ironlake = 1, | |
2d2430cf | 1359 | .setup = i9xx_setup, |
ae83dd5c | 1360 | .cleanup = i9xx_cleanup, |
a6963596 | 1361 | .write_entry = i965_write_entry, |
22533b49 | 1362 | .dma_mask_size = 36, |
450f2b3d | 1363 | .check_flags = i830_check_flags, |
1b263f24 | 1364 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1365 | }; |
1366 | static const struct intel_gtt_driver sandybridge_gtt_driver = { | |
1367 | .gen = 6, | |
2d2430cf | 1368 | .setup = i9xx_setup, |
ae83dd5c | 1369 | .cleanup = gen6_cleanup, |
97ef1bdd | 1370 | .write_entry = gen6_write_entry, |
22533b49 | 1371 | .dma_mask_size = 40, |
90cb149e | 1372 | .check_flags = gen6_check_flags, |
1b263f24 | 1373 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 | 1374 | }; |
64757876 JB |
1375 | static const struct intel_gtt_driver valleyview_gtt_driver = { |
1376 | .gen = 7, | |
1377 | .setup = i9xx_setup, | |
1378 | .cleanup = gen6_cleanup, | |
1379 | .write_entry = valleyview_write_entry, | |
1380 | .dma_mask_size = 40, | |
1381 | .check_flags = gen6_check_flags, | |
1382 | .chipset_flush = i9xx_chipset_flush, | |
1383 | }; | |
1a997ff2 | 1384 | |
02c026ce DV |
1385 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1386 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1387 | * which one should be used if a gmch_chip_id is present. | |
1388 | */ | |
1389 | static const struct intel_gtt_driver_description { | |
1390 | unsigned int gmch_chip_id; | |
1391 | char *name; | |
1a997ff2 | 1392 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1393 | } intel_gtt_chipsets[] = { |
ff26860f | 1394 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
bdd30729 | 1395 | &i81x_gtt_driver}, |
ff26860f | 1396 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
bdd30729 | 1397 | &i81x_gtt_driver}, |
ff26860f | 1398 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
bdd30729 | 1399 | &i81x_gtt_driver}, |
ff26860f | 1400 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
bdd30729 | 1401 | &i81x_gtt_driver}, |
1a997ff2 | 1402 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
ff26860f | 1403 | &i8xx_gtt_driver}, |
53371eda | 1404 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
ff26860f | 1405 | &i8xx_gtt_driver}, |
1a997ff2 | 1406 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
ff26860f | 1407 | &i8xx_gtt_driver}, |
1a997ff2 | 1408 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
ff26860f | 1409 | &i8xx_gtt_driver}, |
1a997ff2 | 1410 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
ff26860f | 1411 | &i8xx_gtt_driver}, |
1a997ff2 | 1412 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
ff26860f | 1413 | &i915_gtt_driver }, |
1a997ff2 | 1414 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
ff26860f | 1415 | &i915_gtt_driver }, |
1a997ff2 | 1416 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
ff26860f | 1417 | &i915_gtt_driver }, |
1a997ff2 | 1418 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
ff26860f | 1419 | &i915_gtt_driver }, |
1a997ff2 | 1420 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
ff26860f | 1421 | &i915_gtt_driver }, |
1a997ff2 | 1422 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
ff26860f | 1423 | &i915_gtt_driver }, |
1a997ff2 | 1424 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
ff26860f | 1425 | &i965_gtt_driver }, |
1a997ff2 | 1426 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
ff26860f | 1427 | &i965_gtt_driver }, |
1a997ff2 | 1428 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
ff26860f | 1429 | &i965_gtt_driver }, |
1a997ff2 | 1430 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
ff26860f | 1431 | &i965_gtt_driver }, |
1a997ff2 | 1432 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
ff26860f | 1433 | &i965_gtt_driver }, |
1a997ff2 | 1434 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
ff26860f | 1435 | &i965_gtt_driver }, |
1a997ff2 | 1436 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
ff26860f | 1437 | &g33_gtt_driver }, |
1a997ff2 | 1438 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
ff26860f | 1439 | &g33_gtt_driver }, |
1a997ff2 | 1440 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
ff26860f | 1441 | &g33_gtt_driver }, |
1a997ff2 | 1442 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
ff26860f | 1443 | &pineview_gtt_driver }, |
1a997ff2 | 1444 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
ff26860f | 1445 | &pineview_gtt_driver }, |
1a997ff2 | 1446 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
ff26860f | 1447 | &g4x_gtt_driver }, |
1a997ff2 | 1448 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
ff26860f | 1449 | &g4x_gtt_driver }, |
1a997ff2 | 1450 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
ff26860f | 1451 | &g4x_gtt_driver }, |
1a997ff2 | 1452 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
ff26860f | 1453 | &g4x_gtt_driver }, |
1a997ff2 | 1454 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
ff26860f | 1455 | &g4x_gtt_driver }, |
e9e5f8e8 | 1456 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
ff26860f | 1457 | &g4x_gtt_driver }, |
1a997ff2 | 1458 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
ff26860f | 1459 | &g4x_gtt_driver }, |
02c026ce | 1460 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
ff26860f | 1461 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1462 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
ff26860f | 1463 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1464 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
ff26860f | 1465 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1466 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
ff26860f | 1467 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1468 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
ff26860f | 1469 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1470 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
ff26860f | 1471 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1472 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
ff26860f | 1473 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1474 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
ff26860f | 1475 | "Sandybridge", &sandybridge_gtt_driver }, |
02c026ce | 1476 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
ff26860f | 1477 | "Sandybridge", &sandybridge_gtt_driver }, |
246d08b8 JB |
1478 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, |
1479 | "Ivybridge", &sandybridge_gtt_driver }, | |
1480 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, | |
1481 | "Ivybridge", &sandybridge_gtt_driver }, | |
1482 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, | |
1483 | "Ivybridge", &sandybridge_gtt_driver }, | |
1484 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, | |
1485 | "Ivybridge", &sandybridge_gtt_driver }, | |
1486 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, | |
cc22a938 ED |
1487 | "Ivybridge", &sandybridge_gtt_driver }, |
1488 | { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG, | |
246d08b8 | 1489 | "Ivybridge", &sandybridge_gtt_driver }, |
64757876 JB |
1490 | { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, |
1491 | "ValleyView", &valleyview_gtt_driver }, | |
4cae9ae0 ED |
1492 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, |
1493 | "Haswell", &sandybridge_gtt_driver }, | |
1494 | { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, | |
1495 | "Haswell", &sandybridge_gtt_driver }, | |
1496 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, | |
1497 | "Haswell", &sandybridge_gtt_driver }, | |
1498 | { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, | |
1499 | "Haswell", &sandybridge_gtt_driver }, | |
1500 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, | |
1501 | "Haswell", &sandybridge_gtt_driver }, | |
1502 | { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, | |
1503 | "Haswell", &sandybridge_gtt_driver }, | |
1504 | { PCI_DEVICE_ID_INTEL_HASWELL_SDV, | |
1505 | "Haswell", &sandybridge_gtt_driver }, | |
02c026ce DV |
1506 | { 0, NULL, NULL } |
1507 | }; | |
1508 | ||
1509 | static int find_gmch(u16 device) | |
1510 | { | |
1511 | struct pci_dev *gmch_device; | |
1512 | ||
1513 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1514 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1515 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1516 | device, gmch_device); | |
1517 | } | |
1518 | ||
1519 | if (!gmch_device) | |
1520 | return 0; | |
1521 | ||
1522 | intel_private.pcidev = gmch_device; | |
1523 | return 1; | |
1524 | } | |
1525 | ||
14be93dd DV |
1526 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
1527 | struct agp_bridge_data *bridge) | |
02c026ce DV |
1528 | { |
1529 | int i, mask; | |
14be93dd DV |
1530 | |
1531 | /* | |
1532 | * Can be called from the fake agp driver but also directly from | |
1533 | * drm/i915.ko. Hence we need to check whether everything is set up | |
1534 | * already. | |
1535 | */ | |
1536 | if (intel_private.driver) { | |
1537 | intel_private.refcount++; | |
1538 | return 1; | |
1539 | } | |
02c026ce DV |
1540 | |
1541 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { | |
14be93dd DV |
1542 | if (gpu_pdev) { |
1543 | if (gpu_pdev->device == | |
1544 | intel_gtt_chipsets[i].gmch_chip_id) { | |
1545 | intel_private.pcidev = pci_dev_get(gpu_pdev); | |
1546 | intel_private.driver = | |
1547 | intel_gtt_chipsets[i].gtt_driver; | |
1548 | ||
1549 | break; | |
1550 | } | |
1551 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
625dd9d3 | 1552 | intel_private.driver = |
1a997ff2 | 1553 | intel_gtt_chipsets[i].gtt_driver; |
02c026ce DV |
1554 | break; |
1555 | } | |
1556 | } | |
1557 | ||
ff26860f | 1558 | if (!intel_private.driver) |
02c026ce DV |
1559 | return 0; |
1560 | ||
14be93dd DV |
1561 | intel_private.refcount++; |
1562 | ||
7e8f6306 DV |
1563 | if (bridge) { |
1564 | bridge->driver = &intel_fake_agp_driver; | |
1565 | bridge->dev_private_data = &intel_private; | |
14be93dd | 1566 | bridge->dev = bridge_pdev; |
7e8f6306 | 1567 | } |
02c026ce | 1568 | |
14be93dd | 1569 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
d7cca2f7 | 1570 | |
14be93dd | 1571 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
02c026ce | 1572 | |
22533b49 | 1573 | mask = intel_private.driver->dma_mask_size; |
02c026ce DV |
1574 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
1575 | dev_err(&intel_private.pcidev->dev, | |
1576 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1577 | else | |
1578 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1579 | DMA_BIT_MASK(mask)); | |
1580 | ||
14be93dd DV |
1581 | if (intel_gtt_init() != 0) { |
1582 | intel_gmch_remove(); | |
1583 | ||
3b15a9d7 | 1584 | return 0; |
14be93dd | 1585 | } |
1784a5fb | 1586 | |
02c026ce DV |
1587 | return 1; |
1588 | } | |
e2404e7c | 1589 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1590 | |
c64f7ba5 | 1591 | const struct intel_gtt *intel_gtt_get(void) |
19966754 DV |
1592 | { |
1593 | return &intel_private.base; | |
1594 | } | |
1595 | EXPORT_SYMBOL(intel_gtt_get); | |
1596 | ||
40ce6575 DV |
1597 | void intel_gtt_chipset_flush(void) |
1598 | { | |
1599 | if (intel_private.driver->chipset_flush) | |
1600 | intel_private.driver->chipset_flush(); | |
1601 | } | |
1602 | EXPORT_SYMBOL(intel_gtt_chipset_flush); | |
1603 | ||
14be93dd | 1604 | void intel_gmch_remove(void) |
02c026ce | 1605 | { |
14be93dd DV |
1606 | if (--intel_private.refcount) |
1607 | return; | |
1608 | ||
02c026ce DV |
1609 | if (intel_private.pcidev) |
1610 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1611 | if (intel_private.bridge_dev) |
1612 | pci_dev_put(intel_private.bridge_dev); | |
14be93dd | 1613 | intel_private.driver = NULL; |
02c026ce | 1614 | } |
e2404e7c DV |
1615 | EXPORT_SYMBOL(intel_gmch_remove); |
1616 | ||
1617 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); | |
1618 | MODULE_LICENSE("GPL and additional rights"); |