Commit | Line | Data |
---|---|---|
f51b7662 DV |
1 | /* |
2 | * Intel GTT (Graphics Translation Table) routines | |
3 | * | |
4 | * Caveat: This driver implements the linux agp interface, but this is far from | |
5 | * a agp driver! GTT support ended up here for purely historical reasons: The | |
6 | * old userspace intel graphics drivers needed an interface to map memory into | |
7 | * the GTT. And the drm provides a default interface for graphic devices sitting | |
8 | * on an agp port. So it made sense to fake the GTT support as an agp port to | |
9 | * avoid having to create a new api. | |
10 | * | |
11 | * With gem this does not make much sense anymore, just needlessly complicates | |
12 | * the code. But as long as the old graphics stack is still support, it's stuck | |
13 | * here. | |
14 | * | |
15 | * /fairy-tale-mode off | |
16 | */ | |
17 | ||
e2404e7c DV |
18 | #include <linux/module.h> |
19 | #include <linux/pci.h> | |
e2404e7c DV |
20 | #include <linux/kernel.h> |
21 | #include <linux/pagemap.h> | |
22 | #include <linux/agp_backend.h> | |
bdb8b975 | 23 | #include <linux/delay.h> |
e2404e7c DV |
24 | #include <asm/smp.h> |
25 | #include "agp.h" | |
26 | #include "intel-agp.h" | |
0ade6386 | 27 | #include <drm/intel-gtt.h> |
e47036b4 | 28 | #include <asm/set_memory.h> |
e2404e7c | 29 | |
f51b7662 DV |
30 | /* |
31 | * If we have Intel graphics, we're not going to have anything other than | |
32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
d3f13810 | 33 | * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). |
f51b7662 DV |
34 | * Only newer chipsets need to bother with this, of course. |
35 | */ | |
d3f13810 | 36 | #ifdef CONFIG_INTEL_IOMMU |
f51b7662 | 37 | #define USE_PCI_DMA_API 1 |
0e87d2b0 DV |
38 | #else |
39 | #define USE_PCI_DMA_API 0 | |
f51b7662 DV |
40 | #endif |
41 | ||
1a997ff2 DV |
42 | struct intel_gtt_driver { |
43 | unsigned int gen : 8; | |
44 | unsigned int is_g33 : 1; | |
45 | unsigned int is_pineview : 1; | |
46 | unsigned int is_ironlake : 1; | |
100519e2 | 47 | unsigned int has_pgtbl_enable : 1; |
22533b49 | 48 | unsigned int dma_mask_size : 8; |
73800422 DV |
49 | /* Chipset specific GTT setup */ |
50 | int (*setup)(void); | |
ae83dd5c DV |
51 | /* This should undo anything done in ->setup() save the unmapping |
52 | * of the mmio register file, that's done in the generic code. */ | |
53 | void (*cleanup)(void); | |
351bb278 DV |
54 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
55 | /* Flags is a more or less chipset specific opaque value. | |
56 | * For chipsets that need to support old ums (non-gem) code, this | |
57 | * needs to be identical to the various supported agp memory types! */ | |
5cbecafc | 58 | bool (*check_flags)(unsigned int flags); |
1b263f24 | 59 | void (*chipset_flush)(void); |
1a997ff2 DV |
60 | }; |
61 | ||
f51b7662 | 62 | static struct _intel_private { |
1a997ff2 | 63 | const struct intel_gtt_driver *driver; |
f51b7662 | 64 | struct pci_dev *pcidev; /* device one */ |
d7cca2f7 | 65 | struct pci_dev *bridge_dev; |
f51b7662 | 66 | u8 __iomem *registers; |
5acc4ce4 | 67 | phys_addr_t gtt_phys_addr; |
b3eafc5a | 68 | u32 PGETBL_save; |
f51b7662 | 69 | u32 __iomem *gtt; /* I915G */ |
bee4a186 | 70 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
f51b7662 | 71 | int num_dcache_entries; |
bdb8b975 | 72 | void __iomem *i9xx_flush_page; |
820647b9 | 73 | char *i81x_gtt_table; |
f51b7662 DV |
74 | struct resource ifp_resource; |
75 | int resource_valid; | |
0e87d2b0 | 76 | struct page *scratch_page; |
9c61a32d | 77 | phys_addr_t scratch_page_dma; |
14be93dd | 78 | int refcount; |
8d2e6308 BW |
79 | /* Whether i915 needs to use the dmar apis or not. */ |
80 | unsigned int needs_dmar : 1; | |
e5c65377 | 81 | phys_addr_t gma_bus_addr; |
a54c0c27 | 82 | /* Size of memory reserved for graphics by the BIOS */ |
b7128ef1 | 83 | resource_size_t stolen_size; |
a54c0c27 BW |
84 | /* Total number of gtt entries. */ |
85 | unsigned int gtt_total_entries; | |
86 | /* Part of the gtt that is mappable by the cpu, for those chips where | |
87 | * this is not the full gtt. */ | |
88 | unsigned int gtt_mappable_entries; | |
f51b7662 DV |
89 | } intel_private; |
90 | ||
1a997ff2 DV |
91 | #define INTEL_GTT_GEN intel_private.driver->gen |
92 | #define IS_G33 intel_private.driver->is_g33 | |
93 | #define IS_PINEVIEW intel_private.driver->is_pineview | |
94 | #define IS_IRONLAKE intel_private.driver->is_ironlake | |
100519e2 | 95 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
1a997ff2 | 96 | |
00fe639a | 97 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
9da3da66 CW |
98 | static int intel_gtt_map_memory(struct page **pages, |
99 | unsigned int num_entries, | |
100 | struct sg_table *st) | |
f51b7662 | 101 | { |
f51b7662 DV |
102 | struct scatterlist *sg; |
103 | int i; | |
104 | ||
4080775b | 105 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
f51b7662 | 106 | |
9da3da66 | 107 | if (sg_alloc_table(st, num_entries, GFP_KERNEL)) |
831cd445 | 108 | goto err; |
f51b7662 | 109 | |
9da3da66 | 110 | for_each_sg(st->sgl, sg, num_entries, i) |
4080775b | 111 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); |
f51b7662 | 112 | |
9da3da66 CW |
113 | if (!pci_map_sg(intel_private.pcidev, |
114 | st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) | |
831cd445 CW |
115 | goto err; |
116 | ||
f51b7662 | 117 | return 0; |
831cd445 CW |
118 | |
119 | err: | |
9da3da66 | 120 | sg_free_table(st); |
831cd445 | 121 | return -ENOMEM; |
f51b7662 DV |
122 | } |
123 | ||
9da3da66 | 124 | static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
f51b7662 | 125 | { |
4080775b | 126 | struct sg_table st; |
f51b7662 DV |
127 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
128 | ||
4080775b DV |
129 | pci_unmap_sg(intel_private.pcidev, sg_list, |
130 | num_sg, PCI_DMA_BIDIRECTIONAL); | |
131 | ||
132 | st.sgl = sg_list; | |
133 | st.orig_nents = st.nents = num_sg; | |
134 | ||
135 | sg_free_table(&st); | |
f51b7662 DV |
136 | } |
137 | ||
ffdd7510 | 138 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
f51b7662 DV |
139 | { |
140 | return; | |
141 | } | |
142 | ||
143 | /* Exists to support ARGB cursors */ | |
144 | static struct page *i8xx_alloc_pages(void) | |
145 | { | |
146 | struct page *page; | |
147 | ||
148 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); | |
149 | if (page == NULL) | |
150 | return NULL; | |
151 | ||
152 | if (set_pages_uc(page, 4) < 0) { | |
153 | set_pages_wb(page, 4); | |
154 | __free_pages(page, 2); | |
155 | return NULL; | |
156 | } | |
f51b7662 DV |
157 | atomic_inc(&agp_bridge->current_memory_agp); |
158 | return page; | |
159 | } | |
160 | ||
161 | static void i8xx_destroy_pages(struct page *page) | |
162 | { | |
163 | if (page == NULL) | |
164 | return; | |
165 | ||
166 | set_pages_wb(page, 4); | |
f51b7662 DV |
167 | __free_pages(page, 2); |
168 | atomic_dec(&agp_bridge->current_memory_agp); | |
169 | } | |
00fe639a | 170 | #endif |
f51b7662 | 171 | |
820647b9 DV |
172 | #define I810_GTT_ORDER 4 |
173 | static int i810_setup(void) | |
174 | { | |
d3572532 | 175 | phys_addr_t reg_addr; |
820647b9 DV |
176 | char *gtt_table; |
177 | ||
178 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ | |
179 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); | |
180 | if (gtt_table == NULL) | |
181 | return -ENOMEM; | |
182 | intel_private.i81x_gtt_table = gtt_table; | |
183 | ||
d3572532 | 184 | reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); |
820647b9 DV |
185 | |
186 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
187 | if (!intel_private.registers) | |
188 | return -ENOMEM; | |
189 | ||
190 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, | |
191 | intel_private.registers+I810_PGETBL_CTL); | |
192 | ||
5acc4ce4 | 193 | intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; |
820647b9 DV |
194 | |
195 | if ((readl(intel_private.registers+I810_DRAM_CTL) | |
196 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { | |
197 | dev_info(&intel_private.pcidev->dev, | |
198 | "detected 4MB dedicated video ram\n"); | |
199 | intel_private.num_dcache_entries = 1024; | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static void i810_cleanup(void) | |
206 | { | |
207 | writel(0, intel_private.registers+I810_PGETBL_CTL); | |
208 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); | |
209 | } | |
210 | ||
00fe639a | 211 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
ff26860f DV |
212 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
213 | int type) | |
f51b7662 | 214 | { |
625dd9d3 | 215 | int i; |
f51b7662 | 216 | |
ff26860f DV |
217 | if ((pg_start + mem->page_count) |
218 | > intel_private.num_dcache_entries) | |
219 | return -EINVAL; | |
625dd9d3 | 220 | |
ff26860f DV |
221 | if (!mem->is_flushed) |
222 | global_cache_flush(); | |
f51b7662 | 223 | |
ff26860f DV |
224 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
225 | dma_addr_t addr = i << PAGE_SHIFT; | |
226 | intel_private.driver->write_entry(addr, | |
227 | i, type); | |
f51b7662 | 228 | } |
983d308c | 229 | wmb(); |
f51b7662 | 230 | |
ff26860f | 231 | return 0; |
f51b7662 DV |
232 | } |
233 | ||
234 | /* | |
235 | * The i810/i830 requires a physical address to program its mouse | |
236 | * pointer into hardware. | |
237 | * However the Xserver still writes to it through the agp aperture. | |
238 | */ | |
239 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
240 | { | |
241 | struct agp_memory *new; | |
242 | struct page *page; | |
243 | ||
244 | switch (pg_count) { | |
245 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
246 | break; | |
247 | case 4: | |
248 | /* kludge to get 4 physical pages for ARGB cursor */ | |
249 | page = i8xx_alloc_pages(); | |
250 | break; | |
251 | default: | |
252 | return NULL; | |
253 | } | |
254 | ||
255 | if (page == NULL) | |
256 | return NULL; | |
257 | ||
258 | new = agp_create_memory(pg_count); | |
259 | if (new == NULL) | |
260 | return NULL; | |
261 | ||
262 | new->pages[0] = page; | |
263 | if (pg_count == 4) { | |
264 | /* kludge to get 4 physical pages for ARGB cursor */ | |
265 | new->pages[1] = new->pages[0] + 1; | |
266 | new->pages[2] = new->pages[1] + 1; | |
267 | new->pages[3] = new->pages[2] + 1; | |
268 | } | |
269 | new->page_count = pg_count; | |
270 | new->num_scratch_pages = pg_count; | |
271 | new->type = AGP_PHYS_MEMORY; | |
272 | new->physical = page_to_phys(new->pages[0]); | |
273 | return new; | |
274 | } | |
275 | ||
f51b7662 DV |
276 | static void intel_i810_free_by_type(struct agp_memory *curr) |
277 | { | |
278 | agp_free_key(curr->key); | |
279 | if (curr->type == AGP_PHYS_MEMORY) { | |
280 | if (curr->page_count == 4) | |
281 | i8xx_destroy_pages(curr->pages[0]); | |
282 | else { | |
283 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
284 | AGP_PAGE_DESTROY_UNMAP); | |
285 | agp_bridge->driver->agp_destroy_page(curr->pages[0], | |
286 | AGP_PAGE_DESTROY_FREE); | |
287 | } | |
288 | agp_free_page_array(curr); | |
289 | } | |
290 | kfree(curr); | |
291 | } | |
00fe639a | 292 | #endif |
f51b7662 | 293 | |
0e87d2b0 DV |
294 | static int intel_gtt_setup_scratch_page(void) |
295 | { | |
296 | struct page *page; | |
297 | dma_addr_t dma_addr; | |
298 | ||
299 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
300 | if (page == NULL) | |
301 | return -ENOMEM; | |
0e87d2b0 DV |
302 | set_pages_uc(page, 1); |
303 | ||
8d2e6308 | 304 | if (intel_private.needs_dmar) { |
0e87d2b0 DV |
305 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
306 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
307 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) | |
308 | return -EINVAL; | |
309 | ||
9c61a32d | 310 | intel_private.scratch_page_dma = dma_addr; |
0e87d2b0 | 311 | } else |
9c61a32d | 312 | intel_private.scratch_page_dma = page_to_phys(page); |
0e87d2b0 DV |
313 | |
314 | intel_private.scratch_page = page; | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
625dd9d3 DV |
319 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
320 | unsigned int flags) | |
321 | { | |
322 | u32 pte_flags = I810_PTE_VALID; | |
323 | ||
324 | switch (flags) { | |
325 | case AGP_DCACHE_MEMORY: | |
326 | pte_flags |= I810_PTE_LOCAL; | |
327 | break; | |
328 | case AGP_USER_CACHED_MEMORY: | |
329 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
330 | break; | |
331 | } | |
332 | ||
983d308c | 333 | writel_relaxed(addr | pte_flags, intel_private.gtt + entry); |
625dd9d3 DV |
334 | } |
335 | ||
b7128ef1 | 336 | static resource_size_t intel_gtt_stolen_size(void) |
f51b7662 DV |
337 | { |
338 | u16 gmch_ctrl; | |
f51b7662 DV |
339 | u8 rdct; |
340 | int local = 0; | |
341 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
b7128ef1 | 342 | resource_size_t stolen_size = 0; |
f51b7662 | 343 | |
820647b9 DV |
344 | if (INTEL_GTT_GEN == 1) |
345 | return 0; /* no stolen mem on i81x */ | |
346 | ||
d7cca2f7 DV |
347 | pci_read_config_word(intel_private.bridge_dev, |
348 | I830_GMCH_CTRL, &gmch_ctrl); | |
f51b7662 | 349 | |
d7cca2f7 DV |
350 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
351 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
f51b7662 DV |
352 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
353 | case I830_GMCH_GMS_STOLEN_512: | |
d8d9abcd | 354 | stolen_size = KB(512); |
f51b7662 DV |
355 | break; |
356 | case I830_GMCH_GMS_STOLEN_1024: | |
d8d9abcd | 357 | stolen_size = MB(1); |
f51b7662 DV |
358 | break; |
359 | case I830_GMCH_GMS_STOLEN_8192: | |
d8d9abcd | 360 | stolen_size = MB(8); |
f51b7662 DV |
361 | break; |
362 | case I830_GMCH_GMS_LOCAL: | |
363 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); | |
d8d9abcd | 364 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
f51b7662 DV |
365 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
366 | local = 1; | |
367 | break; | |
368 | default: | |
d8d9abcd | 369 | stolen_size = 0; |
f51b7662 DV |
370 | break; |
371 | } | |
f51b7662 DV |
372 | } else { |
373 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { | |
374 | case I855_GMCH_GMS_STOLEN_1M: | |
d8d9abcd | 375 | stolen_size = MB(1); |
f51b7662 DV |
376 | break; |
377 | case I855_GMCH_GMS_STOLEN_4M: | |
d8d9abcd | 378 | stolen_size = MB(4); |
f51b7662 DV |
379 | break; |
380 | case I855_GMCH_GMS_STOLEN_8M: | |
d8d9abcd | 381 | stolen_size = MB(8); |
f51b7662 DV |
382 | break; |
383 | case I855_GMCH_GMS_STOLEN_16M: | |
d8d9abcd | 384 | stolen_size = MB(16); |
f51b7662 DV |
385 | break; |
386 | case I855_GMCH_GMS_STOLEN_32M: | |
d8d9abcd | 387 | stolen_size = MB(32); |
f51b7662 DV |
388 | break; |
389 | case I915_GMCH_GMS_STOLEN_48M: | |
77ad498e | 390 | stolen_size = MB(48); |
f51b7662 DV |
391 | break; |
392 | case I915_GMCH_GMS_STOLEN_64M: | |
77ad498e | 393 | stolen_size = MB(64); |
f51b7662 DV |
394 | break; |
395 | case G33_GMCH_GMS_STOLEN_128M: | |
77ad498e | 396 | stolen_size = MB(128); |
f51b7662 DV |
397 | break; |
398 | case G33_GMCH_GMS_STOLEN_256M: | |
77ad498e | 399 | stolen_size = MB(256); |
f51b7662 DV |
400 | break; |
401 | case INTEL_GMCH_GMS_STOLEN_96M: | |
77ad498e | 402 | stolen_size = MB(96); |
f51b7662 DV |
403 | break; |
404 | case INTEL_GMCH_GMS_STOLEN_160M: | |
77ad498e | 405 | stolen_size = MB(160); |
f51b7662 DV |
406 | break; |
407 | case INTEL_GMCH_GMS_STOLEN_224M: | |
77ad498e | 408 | stolen_size = MB(224); |
f51b7662 DV |
409 | break; |
410 | case INTEL_GMCH_GMS_STOLEN_352M: | |
77ad498e | 411 | stolen_size = MB(352); |
f51b7662 DV |
412 | break; |
413 | default: | |
d8d9abcd | 414 | stolen_size = 0; |
f51b7662 DV |
415 | break; |
416 | } | |
417 | } | |
1784a5fb | 418 | |
1b6064d7 | 419 | if (stolen_size > 0) { |
b7128ef1 MA |
420 | dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n", |
421 | (u64)stolen_size / KB(1), local ? "local" : "stolen"); | |
f51b7662 | 422 | } else { |
d7cca2f7 | 423 | dev_info(&intel_private.bridge_dev->dev, |
f51b7662 | 424 | "no pre-allocated video memory detected\n"); |
d8d9abcd | 425 | stolen_size = 0; |
f51b7662 DV |
426 | } |
427 | ||
c64f7ba5 | 428 | return stolen_size; |
f51b7662 DV |
429 | } |
430 | ||
20172842 DV |
431 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
432 | { | |
433 | u32 pgetbl_ctl, pgetbl_ctl2; | |
434 | ||
435 | /* ensure that ppgtt is disabled */ | |
436 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); | |
437 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; | |
438 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); | |
439 | ||
440 | /* write the new ggtt size */ | |
441 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); | |
442 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; | |
443 | pgetbl_ctl |= size_flag; | |
444 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); | |
445 | } | |
446 | ||
447 | static unsigned int i965_gtt_total_entries(void) | |
fbe40783 DV |
448 | { |
449 | int size; | |
20172842 DV |
450 | u32 pgetbl_ctl; |
451 | u16 gmch_ctl; | |
fbe40783 | 452 | |
20172842 DV |
453 | pci_read_config_word(intel_private.bridge_dev, |
454 | I830_GMCH_CTRL, &gmch_ctl); | |
fbe40783 | 455 | |
20172842 DV |
456 | if (INTEL_GTT_GEN == 5) { |
457 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { | |
458 | case G4x_GMCH_SIZE_1M: | |
459 | case G4x_GMCH_SIZE_VT_1M: | |
460 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); | |
fbe40783 | 461 | break; |
20172842 DV |
462 | case G4x_GMCH_SIZE_VT_1_5M: |
463 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); | |
fbe40783 | 464 | break; |
20172842 DV |
465 | case G4x_GMCH_SIZE_2M: |
466 | case G4x_GMCH_SIZE_VT_2M: | |
467 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); | |
fbe40783 | 468 | break; |
fbe40783 | 469 | } |
20172842 | 470 | } |
e5e408fc | 471 | |
20172842 DV |
472 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
473 | ||
474 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
475 | case I965_PGETBL_SIZE_128KB: | |
476 | size = KB(128); | |
477 | break; | |
478 | case I965_PGETBL_SIZE_256KB: | |
479 | size = KB(256); | |
480 | break; | |
481 | case I965_PGETBL_SIZE_512KB: | |
482 | size = KB(512); | |
483 | break; | |
484 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ | |
485 | case I965_PGETBL_SIZE_1MB: | |
486 | size = KB(1024); | |
487 | break; | |
488 | case I965_PGETBL_SIZE_2MB: | |
489 | size = KB(2048); | |
490 | break; | |
491 | case I965_PGETBL_SIZE_1_5MB: | |
492 | size = KB(1024 + 512); | |
493 | break; | |
494 | default: | |
495 | dev_info(&intel_private.pcidev->dev, | |
496 | "unknown page table size, assuming 512KB\n"); | |
497 | size = KB(512); | |
498 | } | |
499 | ||
500 | return size/4; | |
501 | } | |
502 | ||
503 | static unsigned int intel_gtt_total_entries(void) | |
504 | { | |
20172842 DV |
505 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
506 | return i965_gtt_total_entries(); | |
009946f8 | 507 | else { |
fbe40783 DV |
508 | /* On previous hardware, the GTT size was just what was |
509 | * required to map the aperture. | |
510 | */ | |
a54c0c27 | 511 | return intel_private.gtt_mappable_entries; |
fbe40783 | 512 | } |
fbe40783 | 513 | } |
fbe40783 | 514 | |
1784a5fb DV |
515 | static unsigned int intel_gtt_mappable_entries(void) |
516 | { | |
517 | unsigned int aperture_size; | |
1784a5fb | 518 | |
820647b9 DV |
519 | if (INTEL_GTT_GEN == 1) { |
520 | u32 smram_miscc; | |
521 | ||
522 | pci_read_config_dword(intel_private.bridge_dev, | |
523 | I810_SMRAM_MISCC, &smram_miscc); | |
524 | ||
525 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) | |
526 | == I810_GFX_MEM_WIN_32M) | |
527 | aperture_size = MB(32); | |
528 | else | |
529 | aperture_size = MB(64); | |
530 | } else if (INTEL_GTT_GEN == 2) { | |
b1c5b0f8 | 531 | u16 gmch_ctrl; |
1784a5fb | 532 | |
b1c5b0f8 CW |
533 | pci_read_config_word(intel_private.bridge_dev, |
534 | I830_GMCH_CTRL, &gmch_ctrl); | |
1784a5fb | 535 | |
1784a5fb | 536 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
b1c5b0f8 | 537 | aperture_size = MB(64); |
1784a5fb | 538 | else |
b1c5b0f8 | 539 | aperture_size = MB(128); |
239918f7 | 540 | } else { |
1784a5fb DV |
541 | /* 9xx supports large sizes, just look at the length */ |
542 | aperture_size = pci_resource_len(intel_private.pcidev, 2); | |
1784a5fb DV |
543 | } |
544 | ||
545 | return aperture_size >> PAGE_SHIFT; | |
546 | } | |
547 | ||
0e87d2b0 DV |
548 | static void intel_gtt_teardown_scratch_page(void) |
549 | { | |
550 | set_pages_wb(intel_private.scratch_page, 1); | |
9f5ac8ed DV |
551 | if (intel_private.needs_dmar) |
552 | pci_unmap_page(intel_private.pcidev, | |
553 | intel_private.scratch_page_dma, | |
554 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
0e87d2b0 DV |
555 | __free_page(intel_private.scratch_page); |
556 | } | |
557 | ||
558 | static void intel_gtt_cleanup(void) | |
559 | { | |
ae83dd5c DV |
560 | intel_private.driver->cleanup(); |
561 | ||
0e87d2b0 DV |
562 | iounmap(intel_private.gtt); |
563 | iounmap(intel_private.registers); | |
625dd9d3 | 564 | |
0e87d2b0 DV |
565 | intel_gtt_teardown_scratch_page(); |
566 | } | |
567 | ||
da88a5f7 CW |
568 | /* Certain Gen5 chipsets require require idling the GPU before |
569 | * unmapping anything from the GTT when VT-d is enabled. | |
570 | */ | |
571 | static inline int needs_ilk_vtd_wa(void) | |
572 | { | |
573 | #ifdef CONFIG_INTEL_IOMMU | |
574 | const unsigned short gpu_devid = intel_private.pcidev->device; | |
575 | ||
576 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
577 | * was loaded first. | |
578 | */ | |
8b572a42 | 579 | if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG || |
da88a5f7 CW |
580 | gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && |
581 | intel_iommu_gfx_mapped) | |
582 | return 1; | |
583 | #endif | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static bool intel_gtt_can_wc(void) | |
588 | { | |
589 | if (INTEL_GTT_GEN <= 2) | |
590 | return false; | |
591 | ||
592 | if (INTEL_GTT_GEN >= 6) | |
593 | return false; | |
594 | ||
595 | /* Reports of major corruption with ILK vt'd enabled */ | |
596 | if (needs_ilk_vtd_wa()) | |
597 | return false; | |
598 | ||
599 | return true; | |
600 | } | |
601 | ||
1784a5fb DV |
602 | static int intel_gtt_init(void) |
603 | { | |
f67eab66 | 604 | u32 gtt_map_size; |
545b0a74 | 605 | int ret, bar; |
3b15a9d7 | 606 | |
3b15a9d7 DV |
607 | ret = intel_private.driver->setup(); |
608 | if (ret != 0) | |
609 | return ret; | |
f67eab66 | 610 | |
a54c0c27 BW |
611 | intel_private.gtt_mappable_entries = intel_gtt_mappable_entries(); |
612 | intel_private.gtt_total_entries = intel_gtt_total_entries(); | |
f67eab66 | 613 | |
b3eafc5a DV |
614 | /* save the PGETBL reg for resume */ |
615 | intel_private.PGETBL_save = | |
616 | readl(intel_private.registers+I810_PGETBL_CTL) | |
617 | & ~I810_PGETBL_ENABLED; | |
100519e2 CW |
618 | /* we only ever restore the register when enabling the PGTBL... */ |
619 | if (HAS_PGTBL_EN) | |
620 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; | |
b3eafc5a | 621 | |
0af9e92e DV |
622 | dev_info(&intel_private.bridge_dev->dev, |
623 | "detected gtt size: %dK total, %dK mappable\n", | |
a54c0c27 BW |
624 | intel_private.gtt_total_entries * 4, |
625 | intel_private.gtt_mappable_entries * 4); | |
0af9e92e | 626 | |
a54c0c27 | 627 | gtt_map_size = intel_private.gtt_total_entries * 4; |
f67eab66 | 628 | |
edef7e68 | 629 | intel_private.gtt = NULL; |
da88a5f7 | 630 | if (intel_gtt_can_wc()) |
5acc4ce4 | 631 | intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr, |
edef7e68 CW |
632 | gtt_map_size); |
633 | if (intel_private.gtt == NULL) | |
5acc4ce4 | 634 | intel_private.gtt = ioremap(intel_private.gtt_phys_addr, |
edef7e68 CW |
635 | gtt_map_size); |
636 | if (intel_private.gtt == NULL) { | |
ae83dd5c | 637 | intel_private.driver->cleanup(); |
f67eab66 DV |
638 | iounmap(intel_private.registers); |
639 | return -ENOMEM; | |
640 | } | |
641 | ||
00fe639a | 642 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
f67eab66 | 643 | global_cache_flush(); /* FIXME: ? */ |
00fe639a | 644 | #endif |
f67eab66 | 645 | |
a54c0c27 | 646 | intel_private.stolen_size = intel_gtt_stolen_size(); |
1784a5fb | 647 | |
8d2e6308 | 648 | intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
a46f3108 | 649 | |
0e87d2b0 DV |
650 | ret = intel_gtt_setup_scratch_page(); |
651 | if (ret != 0) { | |
652 | intel_gtt_cleanup(); | |
653 | return ret; | |
654 | } | |
655 | ||
32e3cd6e | 656 | if (INTEL_GTT_GEN <= 2) |
545b0a74 | 657 | bar = I810_GMADR_BAR; |
32e3cd6e | 658 | else |
545b0a74 | 659 | bar = I915_GMADR_BAR; |
32e3cd6e | 660 | |
545b0a74 | 661 | intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar); |
1784a5fb DV |
662 | return 0; |
663 | } | |
664 | ||
00fe639a | 665 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
62fa0ce2 CW |
666 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
667 | {32, 8192, 3}, | |
668 | {64, 16384, 4}, | |
669 | {128, 32768, 5}, | |
670 | {256, 65536, 6}, | |
671 | {512, 131072, 7}, | |
672 | }; | |
673 | ||
3e921f98 DV |
674 | static int intel_fake_agp_fetch_size(void) |
675 | { | |
9e76e7b8 | 676 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
3e921f98 DV |
677 | unsigned int aper_size; |
678 | int i; | |
3e921f98 | 679 | |
a54c0c27 | 680 | aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1); |
3e921f98 DV |
681 | |
682 | for (i = 0; i < num_sizes; i++) { | |
ffdd7510 | 683 | if (aper_size == intel_fake_agp_sizes[i].size) { |
9e76e7b8 CW |
684 | agp_bridge->current_size = |
685 | (void *) (intel_fake_agp_sizes + i); | |
3e921f98 DV |
686 | return aper_size; |
687 | } | |
688 | } | |
689 | ||
690 | return 0; | |
691 | } | |
00fe639a | 692 | #endif |
3e921f98 | 693 | |
ae83dd5c | 694 | static void i830_cleanup(void) |
f51b7662 | 695 | { |
f51b7662 DV |
696 | } |
697 | ||
698 | /* The chipset_flush interface needs to get data that has already been | |
699 | * flushed out of the CPU all the way out to main memory, because the GPU | |
700 | * doesn't snoop those buffers. | |
701 | * | |
702 | * The 8xx series doesn't have the same lovely interface for flushing the | |
703 | * chipset write buffers that the later chips do. According to the 865 | |
704 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
705 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
706 | * that it'll push whatever was in there out. It appears to work. | |
707 | */ | |
1b263f24 | 708 | static void i830_chipset_flush(void) |
f51b7662 | 709 | { |
bdb8b975 CW |
710 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
711 | ||
712 | /* Forcibly evict everything from the CPU write buffers. | |
713 | * clflush appears to be insufficient. | |
714 | */ | |
715 | wbinvd_on_all_cpus(); | |
716 | ||
717 | /* Now we've only seen documents for this magic bit on 855GM, | |
718 | * we hope it exists for the other gen2 chipsets... | |
719 | * | |
720 | * Also works as advertised on my 845G. | |
721 | */ | |
722 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), | |
723 | intel_private.registers+I830_HIC); | |
f51b7662 | 724 | |
bdb8b975 CW |
725 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
726 | if (time_after(jiffies, timeout)) | |
727 | break; | |
f51b7662 | 728 | |
bdb8b975 CW |
729 | udelay(50); |
730 | } | |
f51b7662 DV |
731 | } |
732 | ||
351bb278 DV |
733 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
734 | unsigned int flags) | |
735 | { | |
736 | u32 pte_flags = I810_PTE_VALID; | |
625dd9d3 | 737 | |
b47cf66f | 738 | if (flags == AGP_USER_CACHED_MEMORY) |
351bb278 | 739 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
351bb278 | 740 | |
983d308c | 741 | writel_relaxed(addr | pte_flags, intel_private.gtt + entry); |
351bb278 DV |
742 | } |
743 | ||
8ecd1a66 | 744 | bool intel_enable_gtt(void) |
f51b7662 | 745 | { |
e380f60b | 746 | u8 __iomem *reg; |
f51b7662 | 747 | |
100519e2 CW |
748 | if (INTEL_GTT_GEN == 2) { |
749 | u16 gmch_ctrl; | |
73800422 | 750 | |
100519e2 CW |
751 | pci_read_config_word(intel_private.bridge_dev, |
752 | I830_GMCH_CTRL, &gmch_ctrl); | |
753 | gmch_ctrl |= I830_GMCH_ENABLED; | |
754 | pci_write_config_word(intel_private.bridge_dev, | |
755 | I830_GMCH_CTRL, gmch_ctrl); | |
756 | ||
757 | pci_read_config_word(intel_private.bridge_dev, | |
758 | I830_GMCH_CTRL, &gmch_ctrl); | |
759 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { | |
760 | dev_err(&intel_private.pcidev->dev, | |
761 | "failed to enable the GTT: GMCH_CTRL=%x\n", | |
762 | gmch_ctrl); | |
763 | return false; | |
764 | } | |
e380f60b CW |
765 | } |
766 | ||
c97689d8 CW |
767 | /* On the resume path we may be adjusting the PGTBL value, so |
768 | * be paranoid and flush all chipset write buffers... | |
769 | */ | |
770 | if (INTEL_GTT_GEN >= 3) | |
771 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
772 | ||
e380f60b | 773 | reg = intel_private.registers+I810_PGETBL_CTL; |
100519e2 CW |
774 | writel(intel_private.PGETBL_save, reg); |
775 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { | |
e380f60b | 776 | dev_err(&intel_private.pcidev->dev, |
100519e2 | 777 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
e380f60b CW |
778 | readl(reg), intel_private.PGETBL_save); |
779 | return false; | |
780 | } | |
781 | ||
c97689d8 CW |
782 | if (INTEL_GTT_GEN >= 3) |
783 | writel(0, intel_private.registers+GFX_FLSH_CNTL); | |
784 | ||
e380f60b | 785 | return true; |
73800422 | 786 | } |
8ecd1a66 | 787 | EXPORT_SYMBOL(intel_enable_gtt); |
73800422 DV |
788 | |
789 | static int i830_setup(void) | |
790 | { | |
d3572532 | 791 | phys_addr_t reg_addr; |
73800422 | 792 | |
d3572532 | 793 | reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR); |
73800422 DV |
794 | |
795 | intel_private.registers = ioremap(reg_addr, KB(64)); | |
f51b7662 DV |
796 | if (!intel_private.registers) |
797 | return -ENOMEM; | |
798 | ||
5acc4ce4 | 799 | intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE; |
73800422 | 800 | |
73800422 DV |
801 | return 0; |
802 | } | |
803 | ||
00fe639a | 804 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
3b15a9d7 | 805 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
73800422 | 806 | { |
73800422 | 807 | agp_bridge->gatt_table_real = NULL; |
f51b7662 | 808 | agp_bridge->gatt_table = NULL; |
73800422 | 809 | agp_bridge->gatt_bus_addr = 0; |
f51b7662 DV |
810 | |
811 | return 0; | |
812 | } | |
813 | ||
ffdd7510 | 814 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
f51b7662 DV |
815 | { |
816 | return 0; | |
817 | } | |
818 | ||
351bb278 | 819 | static int intel_fake_agp_configure(void) |
f51b7662 | 820 | { |
e380f60b CW |
821 | if (!intel_enable_gtt()) |
822 | return -EIO; | |
f51b7662 | 823 | |
bee4a186 | 824 | intel_private.clear_fake_agp = true; |
e5c65377 | 825 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
f51b7662 | 826 | |
f51b7662 DV |
827 | return 0; |
828 | } | |
00fe639a | 829 | #endif |
f51b7662 | 830 | |
5cbecafc | 831 | static bool i830_check_flags(unsigned int flags) |
f51b7662 | 832 | { |
5cbecafc DV |
833 | switch (flags) { |
834 | case 0: | |
835 | case AGP_PHYS_MEMORY: | |
836 | case AGP_USER_CACHED_MEMORY: | |
837 | case AGP_USER_MEMORY: | |
838 | return true; | |
839 | } | |
840 | ||
841 | return false; | |
842 | } | |
843 | ||
d6473f56 CW |
844 | void intel_gtt_insert_page(dma_addr_t addr, |
845 | unsigned int pg, | |
846 | unsigned int flags) | |
847 | { | |
848 | intel_private.driver->write_entry(addr, pg, flags); | |
3497971a CW |
849 | if (intel_private.driver->chipset_flush) |
850 | intel_private.driver->chipset_flush(); | |
d6473f56 CW |
851 | } |
852 | EXPORT_SYMBOL(intel_gtt_insert_page); | |
853 | ||
9da3da66 | 854 | void intel_gtt_insert_sg_entries(struct sg_table *st, |
4080775b DV |
855 | unsigned int pg_start, |
856 | unsigned int flags) | |
fefaa70f DV |
857 | { |
858 | struct scatterlist *sg; | |
859 | unsigned int len, m; | |
860 | int i, j; | |
861 | ||
862 | j = pg_start; | |
863 | ||
864 | /* sg may merge pages, but we have to separate | |
865 | * per-page addr for GTT */ | |
9da3da66 | 866 | for_each_sg(st->sgl, sg, st->nents, i) { |
fefaa70f DV |
867 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
868 | for (m = 0; m < len; m++) { | |
869 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); | |
9da3da66 | 870 | intel_private.driver->write_entry(addr, j, flags); |
fefaa70f DV |
871 | j++; |
872 | } | |
873 | } | |
983d308c | 874 | wmb(); |
8516673a CW |
875 | if (intel_private.driver->chipset_flush) |
876 | intel_private.driver->chipset_flush(); | |
fefaa70f | 877 | } |
4080775b DV |
878 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
879 | ||
00fe639a | 880 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
9da3da66 CW |
881 | static void intel_gtt_insert_pages(unsigned int first_entry, |
882 | unsigned int num_entries, | |
883 | struct page **pages, | |
884 | unsigned int flags) | |
4080775b DV |
885 | { |
886 | int i, j; | |
887 | ||
888 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { | |
889 | dma_addr_t addr = page_to_phys(pages[i]); | |
890 | intel_private.driver->write_entry(addr, | |
891 | j, flags); | |
892 | } | |
983d308c | 893 | wmb(); |
4080775b | 894 | } |
fefaa70f | 895 | |
5cbecafc DV |
896 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
897 | off_t pg_start, int type) | |
898 | { | |
f51b7662 | 899 | int ret = -EINVAL; |
f51b7662 | 900 | |
bee4a186 | 901 | if (intel_private.clear_fake_agp) { |
a54c0c27 BW |
902 | int start = intel_private.stolen_size / PAGE_SIZE; |
903 | int end = intel_private.gtt_mappable_entries; | |
bee4a186 CW |
904 | intel_gtt_clear_range(start, end - start); |
905 | intel_private.clear_fake_agp = false; | |
906 | } | |
907 | ||
ff26860f DV |
908 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
909 | return i810_insert_dcache_entries(mem, pg_start, type); | |
910 | ||
f51b7662 DV |
911 | if (mem->page_count == 0) |
912 | goto out; | |
913 | ||
a54c0c27 | 914 | if (pg_start + mem->page_count > intel_private.gtt_total_entries) |
f51b7662 DV |
915 | goto out_err; |
916 | ||
f51b7662 DV |
917 | if (type != mem->type) |
918 | goto out_err; | |
919 | ||
5cbecafc | 920 | if (!intel_private.driver->check_flags(type)) |
f51b7662 DV |
921 | goto out_err; |
922 | ||
923 | if (!mem->is_flushed) | |
924 | global_cache_flush(); | |
925 | ||
8d2e6308 | 926 | if (intel_private.needs_dmar) { |
9da3da66 CW |
927 | struct sg_table st; |
928 | ||
929 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); | |
fefaa70f DV |
930 | if (ret != 0) |
931 | return ret; | |
932 | ||
9da3da66 CW |
933 | intel_gtt_insert_sg_entries(&st, pg_start, type); |
934 | mem->sg_list = st.sgl; | |
935 | mem->num_sg = st.nents; | |
4080775b DV |
936 | } else |
937 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, | |
938 | type); | |
f51b7662 DV |
939 | |
940 | out: | |
941 | ret = 0; | |
942 | out_err: | |
943 | mem->is_flushed = true; | |
944 | return ret; | |
945 | } | |
00fe639a | 946 | #endif |
f51b7662 | 947 | |
4080775b DV |
948 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
949 | { | |
950 | unsigned int i; | |
951 | ||
952 | for (i = first_entry; i < (first_entry + num_entries); i++) { | |
9c61a32d | 953 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
4080775b DV |
954 | i, 0); |
955 | } | |
983d308c | 956 | wmb(); |
4080775b DV |
957 | } |
958 | EXPORT_SYMBOL(intel_gtt_clear_range); | |
959 | ||
00fe639a | 960 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
5cbecafc DV |
961 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
962 | off_t pg_start, int type) | |
f51b7662 | 963 | { |
f51b7662 DV |
964 | if (mem->page_count == 0) |
965 | return 0; | |
966 | ||
d15eda5c DA |
967 | intel_gtt_clear_range(pg_start, mem->page_count); |
968 | ||
8d2e6308 | 969 | if (intel_private.needs_dmar) { |
4080775b DV |
970 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); |
971 | mem->sg_list = NULL; | |
972 | mem->num_sg = 0; | |
f51b7662 | 973 | } |
4080775b | 974 | |
f51b7662 DV |
975 | return 0; |
976 | } | |
977 | ||
ffdd7510 DV |
978 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
979 | int type) | |
f51b7662 | 980 | { |
625dd9d3 DV |
981 | struct agp_memory *new; |
982 | ||
983 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { | |
984 | if (pg_count != intel_private.num_dcache_entries) | |
985 | return NULL; | |
986 | ||
987 | new = agp_create_memory(1); | |
988 | if (new == NULL) | |
989 | return NULL; | |
990 | ||
991 | new->type = AGP_DCACHE_MEMORY; | |
992 | new->page_count = pg_count; | |
993 | new->num_scratch_pages = 0; | |
994 | agp_free_page_array(new); | |
995 | return new; | |
996 | } | |
f51b7662 DV |
997 | if (type == AGP_PHYS_MEMORY) |
998 | return alloc_agpphysmem_i8xx(pg_count, type); | |
999 | /* always return NULL for other allocation types for now */ | |
1000 | return NULL; | |
1001 | } | |
00fe639a | 1002 | #endif |
f51b7662 DV |
1003 | |
1004 | static int intel_alloc_chipset_flush_resource(void) | |
1005 | { | |
1006 | int ret; | |
d7cca2f7 | 1007 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
f51b7662 | 1008 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
d7cca2f7 | 1009 | pcibios_align_resource, intel_private.bridge_dev); |
f51b7662 DV |
1010 | |
1011 | return ret; | |
1012 | } | |
1013 | ||
1014 | static void intel_i915_setup_chipset_flush(void) | |
1015 | { | |
1016 | int ret; | |
1017 | u32 temp; | |
1018 | ||
d7cca2f7 | 1019 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
f51b7662 DV |
1020 | if (!(temp & 0x1)) { |
1021 | intel_alloc_chipset_flush_resource(); | |
1022 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1023 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1024 | } else { |
1025 | temp &= ~1; | |
1026 | ||
1027 | intel_private.resource_valid = 1; | |
1028 | intel_private.ifp_resource.start = temp; | |
1029 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1030 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1031 | /* some BIOSes reserve this area in a pnp some don't */ | |
1032 | if (ret) | |
1033 | intel_private.resource_valid = 0; | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | static void intel_i965_g33_setup_chipset_flush(void) | |
1038 | { | |
1039 | u32 temp_hi, temp_lo; | |
1040 | int ret; | |
1041 | ||
d7cca2f7 DV |
1042 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
1043 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); | |
f51b7662 DV |
1044 | |
1045 | if (!(temp_lo & 0x1)) { | |
1046 | ||
1047 | intel_alloc_chipset_flush_resource(); | |
1048 | ||
1049 | intel_private.resource_valid = 1; | |
d7cca2f7 | 1050 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
f51b7662 | 1051 | upper_32_bits(intel_private.ifp_resource.start)); |
d7cca2f7 | 1052 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
f51b7662 DV |
1053 | } else { |
1054 | u64 l64; | |
1055 | ||
1056 | temp_lo &= ~0x1; | |
1057 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1058 | ||
1059 | intel_private.resource_valid = 1; | |
1060 | intel_private.ifp_resource.start = l64; | |
1061 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1062 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
1063 | /* some BIOSes reserve this area in a pnp some don't */ | |
1064 | if (ret) | |
1065 | intel_private.resource_valid = 0; | |
1066 | } | |
1067 | } | |
1068 | ||
1069 | static void intel_i9xx_setup_flush(void) | |
1070 | { | |
1071 | /* return if already configured */ | |
1072 | if (intel_private.ifp_resource.start) | |
1073 | return; | |
1074 | ||
1a997ff2 | 1075 | if (INTEL_GTT_GEN == 6) |
f51b7662 DV |
1076 | return; |
1077 | ||
1078 | /* setup a resource for this object */ | |
1079 | intel_private.ifp_resource.name = "Intel Flush Page"; | |
1080 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1081 | ||
1082 | /* Setup chipset flush for 915 */ | |
1a997ff2 | 1083 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
f51b7662 DV |
1084 | intel_i965_g33_setup_chipset_flush(); |
1085 | } else { | |
1086 | intel_i915_setup_chipset_flush(); | |
1087 | } | |
1088 | ||
df51e7aa | 1089 | if (intel_private.ifp_resource.start) |
f51b7662 | 1090 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
df51e7aa CW |
1091 | if (!intel_private.i9xx_flush_page) |
1092 | dev_err(&intel_private.pcidev->dev, | |
1093 | "can't ioremap flush page - no chipset flushing\n"); | |
f51b7662 DV |
1094 | } |
1095 | ||
ae83dd5c DV |
1096 | static void i9xx_cleanup(void) |
1097 | { | |
1098 | if (intel_private.i9xx_flush_page) | |
1099 | iounmap(intel_private.i9xx_flush_page); | |
1100 | if (intel_private.resource_valid) | |
1101 | release_resource(&intel_private.ifp_resource); | |
1102 | intel_private.ifp_resource.start = 0; | |
1103 | intel_private.resource_valid = 0; | |
1104 | } | |
1105 | ||
1b263f24 | 1106 | static void i9xx_chipset_flush(void) |
f51b7662 DV |
1107 | { |
1108 | if (intel_private.i9xx_flush_page) | |
1109 | writel(1, intel_private.i9xx_flush_page); | |
1110 | } | |
1111 | ||
71f45660 CW |
1112 | static void i965_write_entry(dma_addr_t addr, |
1113 | unsigned int entry, | |
a6963596 DV |
1114 | unsigned int flags) |
1115 | { | |
71f45660 CW |
1116 | u32 pte_flags; |
1117 | ||
1118 | pte_flags = I810_PTE_VALID; | |
1119 | if (flags == AGP_USER_CACHED_MEMORY) | |
1120 | pte_flags |= I830_PTE_SYSTEM_CACHED; | |
1121 | ||
a6963596 DV |
1122 | /* Shift high bits down */ |
1123 | addr |= (addr >> 28) & 0xf0; | |
983d308c | 1124 | writel_relaxed(addr | pte_flags, intel_private.gtt + entry); |
a6963596 DV |
1125 | } |
1126 | ||
2d2430cf | 1127 | static int i9xx_setup(void) |
f51b7662 | 1128 | { |
d3572532 | 1129 | phys_addr_t reg_addr; |
4b60d29e | 1130 | int size = KB(512); |
f51b7662 | 1131 | |
d3572532 | 1132 | reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR); |
f1befe71 | 1133 | |
4b60d29e | 1134 | intel_private.registers = ioremap(reg_addr, size); |
ccc4e67b | 1135 | if (!intel_private.registers) |
f51b7662 DV |
1136 | return -ENOMEM; |
1137 | ||
009946f8 BW |
1138 | switch (INTEL_GTT_GEN) { |
1139 | case 3: | |
b5e350f9 | 1140 | intel_private.gtt_phys_addr = |
d3572532 | 1141 | pci_resource_start(intel_private.pcidev, I915_PTE_BAR); |
009946f8 BW |
1142 | break; |
1143 | case 5: | |
5acc4ce4 | 1144 | intel_private.gtt_phys_addr = reg_addr + MB(2); |
009946f8 BW |
1145 | break; |
1146 | default: | |
5acc4ce4 | 1147 | intel_private.gtt_phys_addr = reg_addr + KB(512); |
009946f8 | 1148 | break; |
2d2430cf DV |
1149 | } |
1150 | ||
1151 | intel_i9xx_setup_flush(); | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
00fe639a | 1156 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
e9b1cc81 | 1157 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
f51b7662 | 1158 | .owner = THIS_MODULE, |
f51b7662 | 1159 | .size_type = FIXED_APER_SIZE, |
9e76e7b8 CW |
1160 | .aperture_sizes = intel_fake_agp_sizes, |
1161 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), | |
a6963596 | 1162 | .configure = intel_fake_agp_configure, |
3e921f98 | 1163 | .fetch_size = intel_fake_agp_fetch_size, |
fdfb58a9 | 1164 | .cleanup = intel_gtt_cleanup, |
ffdd7510 | 1165 | .agp_enable = intel_fake_agp_enable, |
f51b7662 | 1166 | .cache_flush = global_cache_flush, |
3b15a9d7 | 1167 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
ffdd7510 | 1168 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
450f2b3d DV |
1169 | .insert_memory = intel_fake_agp_insert_entries, |
1170 | .remove_memory = intel_fake_agp_remove_entries, | |
ffdd7510 | 1171 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
f51b7662 DV |
1172 | .free_by_type = intel_i810_free_by_type, |
1173 | .agp_alloc_page = agp_generic_alloc_page, | |
1174 | .agp_alloc_pages = agp_generic_alloc_pages, | |
1175 | .agp_destroy_page = agp_generic_destroy_page, | |
1176 | .agp_destroy_pages = agp_generic_destroy_pages, | |
f51b7662 | 1177 | }; |
00fe639a | 1178 | #endif |
02c026ce | 1179 | |
bdd30729 DV |
1180 | static const struct intel_gtt_driver i81x_gtt_driver = { |
1181 | .gen = 1, | |
820647b9 | 1182 | .has_pgtbl_enable = 1, |
22533b49 | 1183 | .dma_mask_size = 32, |
820647b9 DV |
1184 | .setup = i810_setup, |
1185 | .cleanup = i810_cleanup, | |
625dd9d3 DV |
1186 | .check_flags = i830_check_flags, |
1187 | .write_entry = i810_write_entry, | |
bdd30729 | 1188 | }; |
1a997ff2 DV |
1189 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
1190 | .gen = 2, | |
100519e2 | 1191 | .has_pgtbl_enable = 1, |
73800422 | 1192 | .setup = i830_setup, |
ae83dd5c | 1193 | .cleanup = i830_cleanup, |
351bb278 | 1194 | .write_entry = i830_write_entry, |
22533b49 | 1195 | .dma_mask_size = 32, |
5cbecafc | 1196 | .check_flags = i830_check_flags, |
1b263f24 | 1197 | .chipset_flush = i830_chipset_flush, |
1a997ff2 DV |
1198 | }; |
1199 | static const struct intel_gtt_driver i915_gtt_driver = { | |
1200 | .gen = 3, | |
100519e2 | 1201 | .has_pgtbl_enable = 1, |
2d2430cf | 1202 | .setup = i9xx_setup, |
ae83dd5c | 1203 | .cleanup = i9xx_cleanup, |
351bb278 | 1204 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
625dd9d3 | 1205 | .write_entry = i830_write_entry, |
22533b49 | 1206 | .dma_mask_size = 32, |
fefaa70f | 1207 | .check_flags = i830_check_flags, |
1b263f24 | 1208 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1209 | }; |
1210 | static const struct intel_gtt_driver g33_gtt_driver = { | |
1211 | .gen = 3, | |
1212 | .is_g33 = 1, | |
2d2430cf | 1213 | .setup = i9xx_setup, |
ae83dd5c | 1214 | .cleanup = i9xx_cleanup, |
a6963596 | 1215 | .write_entry = i965_write_entry, |
22533b49 | 1216 | .dma_mask_size = 36, |
450f2b3d | 1217 | .check_flags = i830_check_flags, |
1b263f24 | 1218 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1219 | }; |
1220 | static const struct intel_gtt_driver pineview_gtt_driver = { | |
1221 | .gen = 3, | |
1222 | .is_pineview = 1, .is_g33 = 1, | |
2d2430cf | 1223 | .setup = i9xx_setup, |
ae83dd5c | 1224 | .cleanup = i9xx_cleanup, |
a6963596 | 1225 | .write_entry = i965_write_entry, |
22533b49 | 1226 | .dma_mask_size = 36, |
450f2b3d | 1227 | .check_flags = i830_check_flags, |
1b263f24 | 1228 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1229 | }; |
1230 | static const struct intel_gtt_driver i965_gtt_driver = { | |
1231 | .gen = 4, | |
100519e2 | 1232 | .has_pgtbl_enable = 1, |
2d2430cf | 1233 | .setup = i9xx_setup, |
ae83dd5c | 1234 | .cleanup = i9xx_cleanup, |
a6963596 | 1235 | .write_entry = i965_write_entry, |
22533b49 | 1236 | .dma_mask_size = 36, |
450f2b3d | 1237 | .check_flags = i830_check_flags, |
1b263f24 | 1238 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1239 | }; |
1240 | static const struct intel_gtt_driver g4x_gtt_driver = { | |
1241 | .gen = 5, | |
2d2430cf | 1242 | .setup = i9xx_setup, |
ae83dd5c | 1243 | .cleanup = i9xx_cleanup, |
a6963596 | 1244 | .write_entry = i965_write_entry, |
22533b49 | 1245 | .dma_mask_size = 36, |
450f2b3d | 1246 | .check_flags = i830_check_flags, |
1b263f24 | 1247 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 DV |
1248 | }; |
1249 | static const struct intel_gtt_driver ironlake_gtt_driver = { | |
1250 | .gen = 5, | |
1251 | .is_ironlake = 1, | |
2d2430cf | 1252 | .setup = i9xx_setup, |
ae83dd5c | 1253 | .cleanup = i9xx_cleanup, |
a6963596 | 1254 | .write_entry = i965_write_entry, |
22533b49 | 1255 | .dma_mask_size = 36, |
450f2b3d | 1256 | .check_flags = i830_check_flags, |
1b263f24 | 1257 | .chipset_flush = i9xx_chipset_flush, |
1a997ff2 | 1258 | }; |
1a997ff2 | 1259 | |
02c026ce DV |
1260 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
1261 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
1262 | * which one should be used if a gmch_chip_id is present. | |
1263 | */ | |
1264 | static const struct intel_gtt_driver_description { | |
1265 | unsigned int gmch_chip_id; | |
1266 | char *name; | |
1a997ff2 | 1267 | const struct intel_gtt_driver *gtt_driver; |
02c026ce | 1268 | } intel_gtt_chipsets[] = { |
ff26860f | 1269 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
bdd30729 | 1270 | &i81x_gtt_driver}, |
ff26860f | 1271 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
bdd30729 | 1272 | &i81x_gtt_driver}, |
ff26860f | 1273 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
bdd30729 | 1274 | &i81x_gtt_driver}, |
ff26860f | 1275 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
bdd30729 | 1276 | &i81x_gtt_driver}, |
1a997ff2 | 1277 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
ff26860f | 1278 | &i8xx_gtt_driver}, |
53371eda | 1279 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
ff26860f | 1280 | &i8xx_gtt_driver}, |
1a997ff2 | 1281 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
ff26860f | 1282 | &i8xx_gtt_driver}, |
1a997ff2 | 1283 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
ff26860f | 1284 | &i8xx_gtt_driver}, |
1a997ff2 | 1285 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
ff26860f | 1286 | &i8xx_gtt_driver}, |
1a997ff2 | 1287 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
ff26860f | 1288 | &i915_gtt_driver }, |
1a997ff2 | 1289 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
ff26860f | 1290 | &i915_gtt_driver }, |
1a997ff2 | 1291 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
ff26860f | 1292 | &i915_gtt_driver }, |
1a997ff2 | 1293 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
ff26860f | 1294 | &i915_gtt_driver }, |
1a997ff2 | 1295 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
ff26860f | 1296 | &i915_gtt_driver }, |
1a997ff2 | 1297 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
ff26860f | 1298 | &i915_gtt_driver }, |
1a997ff2 | 1299 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
ff26860f | 1300 | &i965_gtt_driver }, |
1a997ff2 | 1301 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
ff26860f | 1302 | &i965_gtt_driver }, |
1a997ff2 | 1303 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
ff26860f | 1304 | &i965_gtt_driver }, |
1a997ff2 | 1305 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
ff26860f | 1306 | &i965_gtt_driver }, |
1a997ff2 | 1307 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
ff26860f | 1308 | &i965_gtt_driver }, |
1a997ff2 | 1309 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
ff26860f | 1310 | &i965_gtt_driver }, |
1a997ff2 | 1311 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
ff26860f | 1312 | &g33_gtt_driver }, |
1a997ff2 | 1313 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
ff26860f | 1314 | &g33_gtt_driver }, |
1a997ff2 | 1315 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
ff26860f | 1316 | &g33_gtt_driver }, |
1a997ff2 | 1317 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
ff26860f | 1318 | &pineview_gtt_driver }, |
1a997ff2 | 1319 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
ff26860f | 1320 | &pineview_gtt_driver }, |
1a997ff2 | 1321 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
ff26860f | 1322 | &g4x_gtt_driver }, |
1a997ff2 | 1323 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
ff26860f | 1324 | &g4x_gtt_driver }, |
1a997ff2 | 1325 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
ff26860f | 1326 | &g4x_gtt_driver }, |
1a997ff2 | 1327 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
ff26860f | 1328 | &g4x_gtt_driver }, |
1a997ff2 | 1329 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
ff26860f | 1330 | &g4x_gtt_driver }, |
e9e5f8e8 | 1331 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
ff26860f | 1332 | &g4x_gtt_driver }, |
1a997ff2 | 1333 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
ff26860f | 1334 | &g4x_gtt_driver }, |
02c026ce | 1335 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
ff26860f | 1336 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce | 1337 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
ff26860f | 1338 | "HD Graphics", &ironlake_gtt_driver }, |
02c026ce DV |
1339 | { 0, NULL, NULL } |
1340 | }; | |
1341 | ||
1342 | static int find_gmch(u16 device) | |
1343 | { | |
1344 | struct pci_dev *gmch_device; | |
1345 | ||
1346 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); | |
1347 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
1348 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
1349 | device, gmch_device); | |
1350 | } | |
1351 | ||
1352 | if (!gmch_device) | |
1353 | return 0; | |
1354 | ||
1355 | intel_private.pcidev = gmch_device; | |
1356 | return 1; | |
1357 | } | |
1358 | ||
14be93dd DV |
1359 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
1360 | struct agp_bridge_data *bridge) | |
02c026ce DV |
1361 | { |
1362 | int i, mask; | |
14be93dd | 1363 | |
02c026ce | 1364 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
14be93dd DV |
1365 | if (gpu_pdev) { |
1366 | if (gpu_pdev->device == | |
1367 | intel_gtt_chipsets[i].gmch_chip_id) { | |
1368 | intel_private.pcidev = pci_dev_get(gpu_pdev); | |
1369 | intel_private.driver = | |
1370 | intel_gtt_chipsets[i].gtt_driver; | |
1371 | ||
1372 | break; | |
1373 | } | |
1374 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { | |
625dd9d3 | 1375 | intel_private.driver = |
1a997ff2 | 1376 | intel_gtt_chipsets[i].gtt_driver; |
02c026ce DV |
1377 | break; |
1378 | } | |
1379 | } | |
1380 | ||
ff26860f | 1381 | if (!intel_private.driver) |
02c026ce DV |
1382 | return 0; |
1383 | ||
00fe639a | 1384 | #if IS_ENABLED(CONFIG_AGP_INTEL) |
7e8f6306 | 1385 | if (bridge) { |
ebb7c78d DV |
1386 | if (INTEL_GTT_GEN > 1) |
1387 | return 0; | |
1388 | ||
7e8f6306 DV |
1389 | bridge->driver = &intel_fake_agp_driver; |
1390 | bridge->dev_private_data = &intel_private; | |
14be93dd | 1391 | bridge->dev = bridge_pdev; |
7e8f6306 | 1392 | } |
00fe639a | 1393 | #endif |
02c026ce | 1394 | |
ebb7c78d DV |
1395 | |
1396 | /* | |
1397 | * Can be called from the fake agp driver but also directly from | |
1398 | * drm/i915.ko. Hence we need to check whether everything is set up | |
1399 | * already. | |
1400 | */ | |
1401 | if (intel_private.refcount++) | |
1402 | return 1; | |
1403 | ||
14be93dd | 1404 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
d7cca2f7 | 1405 | |
14be93dd | 1406 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
02c026ce | 1407 | |
22533b49 | 1408 | mask = intel_private.driver->dma_mask_size; |
02c026ce DV |
1409 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
1410 | dev_err(&intel_private.pcidev->dev, | |
1411 | "set gfx device dma mask %d-bit failed!\n", mask); | |
1412 | else | |
1413 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
1414 | DMA_BIT_MASK(mask)); | |
1415 | ||
14be93dd DV |
1416 | if (intel_gtt_init() != 0) { |
1417 | intel_gmch_remove(); | |
1418 | ||
3b15a9d7 | 1419 | return 0; |
14be93dd | 1420 | } |
1784a5fb | 1421 | |
02c026ce DV |
1422 | return 1; |
1423 | } | |
e2404e7c | 1424 | EXPORT_SYMBOL(intel_gmch_probe); |
02c026ce | 1425 | |
edd1f2fe | 1426 | void intel_gtt_get(u64 *gtt_total, |
edd1f2fe | 1427 | phys_addr_t *mappable_base, |
b7128ef1 | 1428 | resource_size_t *mappable_end) |
19966754 | 1429 | { |
a54c0c27 | 1430 | *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT; |
41907ddc BW |
1431 | *mappable_base = intel_private.gma_bus_addr; |
1432 | *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT; | |
19966754 DV |
1433 | } |
1434 | EXPORT_SYMBOL(intel_gtt_get); | |
1435 | ||
40ce6575 DV |
1436 | void intel_gtt_chipset_flush(void) |
1437 | { | |
1438 | if (intel_private.driver->chipset_flush) | |
1439 | intel_private.driver->chipset_flush(); | |
1440 | } | |
1441 | EXPORT_SYMBOL(intel_gtt_chipset_flush); | |
1442 | ||
14be93dd | 1443 | void intel_gmch_remove(void) |
02c026ce | 1444 | { |
14be93dd DV |
1445 | if (--intel_private.refcount) |
1446 | return; | |
1447 | ||
9f5ac8ed DV |
1448 | if (intel_private.scratch_page) |
1449 | intel_gtt_teardown_scratch_page(); | |
02c026ce DV |
1450 | if (intel_private.pcidev) |
1451 | pci_dev_put(intel_private.pcidev); | |
d7cca2f7 DV |
1452 | if (intel_private.bridge_dev) |
1453 | pci_dev_put(intel_private.bridge_dev); | |
14be93dd | 1454 | intel_private.driver = NULL; |
02c026ce | 1455 | } |
e2404e7c DV |
1456 | EXPORT_SYMBOL(intel_gmch_remove); |
1457 | ||
bd8136d3 | 1458 | MODULE_AUTHOR("Dave Jones, Various @Intel"); |
e2404e7c | 1459 | MODULE_LICENSE("GPL and additional rights"); |