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agp: add chipset flushing support to AGP interface
[linux-block.git] / drivers / char / agp / intel-agp.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel AGPGART routines.
3 */
4
1da177e4
LT		 5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/init.h>
1eaf122c 8#include <linux/kernel.h>
1da177e4
LT		 9#include <linux/pagemap.h>
10#include <linux/agp_backend.h>
11#include "agp.h"
12
e914a36a
CM		 13#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
65c25aad
EA		 15#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17#define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980
18#define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982
19#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
4598af33
WZ		 23#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
dde47876 25#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
c8eebfd6 26#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
dde47876 27#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
df80b148 28#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
874808c6
WZ		 29#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
65c25aad
EA		 35
36#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
37 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
38 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
4598af33 39 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
dde47876
ZW		 40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
41 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
65c25aad 42
874808c6
WZ		 43#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
44 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
45 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
65c25aad 46
a030ce44
TH		 47extern int agp_memory_reserved;
48
49
1da177e4
LT		 50/* Intel 815 register */
51#define INTEL_815_APCONT 0x51
52#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
53
54/* Intel i820 registers */
55#define INTEL_I820_RDCR 0x51
56#define INTEL_I820_ERRSTS 0xc8
57
58/* Intel i840 registers */
59#define INTEL_I840_MCHCFG 0x50
60#define INTEL_I840_ERRSTS 0xc8
61
62/* Intel i850 registers */
63#define INTEL_I850_MCHCFG 0x50
64#define INTEL_I850_ERRSTS 0xc8
65
66/* intel 915G registers */
67#define I915_GMADDR 0x18
68#define I915_MMADDR 0x10
69#define I915_PTEADDR 0x1C
70#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
71#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
874808c6
WZ		 72#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
73#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
1da177e4 74
65c25aad
EA		 75/* Intel 965G registers */
76#define I965_MSAC 0x62
1da177e4
LT		 77
78/* Intel 7505 registers */
79#define INTEL_I7505_APSIZE 0x74
80#define INTEL_I7505_NCAPID 0x60
81#define INTEL_I7505_NISTAT 0x6c
82#define INTEL_I7505_ATTBASE 0x78
83#define INTEL_I7505_ERRSTS 0x42
84#define INTEL_I7505_AGPCTRL 0x70
85#define INTEL_I7505_MCHCFG 0x50
86
e5524f35 87static const struct aper_size_info_fixed intel_i810_sizes[] =
1da177e4
LT		 88{
89 {64, 16384, 4},
90 /* The 32M mode still requires a 64k gatt */
91 {32, 8192, 4}
92};
93
94#define AGP_DCACHE_MEMORY 1
95#define AGP_PHYS_MEMORY 2
a030ce44 96#define INTEL_AGP_CACHED_MEMORY 3
1da177e4
LT		 97
98static struct gatt_mask intel_i810_masks[] =
99{
100 {.mask = I810_PTE_VALID, .type = 0},
101 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
a030ce44
TH		 102 {.mask = I810_PTE_VALID, .type = 0},
103 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
104 .type = INTEL_AGP_CACHED_MEMORY}
1da177e4
LT		 105};
106
c4ca8817
WZ		 107static struct _intel_private {
108 struct pci_dev *pcidev; /* device one */
109 u8 __iomem *registers;
110 u32 __iomem *gtt; /* I915G */
1da177e4 111 int num_dcache_entries;
c4ca8817
WZ		 112 /* gtt_entries is the number of gtt entries that are already mapped
113 * to stolen memory. Stolen memory is larger than the memory mapped
114 * through gtt_entries, as it includes some reserved space for the BIOS
115 * popup and for the GTT.
116 */
117 int gtt_entries; /* i830+ */
118} intel_private;
1da177e4
LT		 119
120static int intel_i810_fetch_size(void)
121{
122 u32 smram_miscc;
123 struct aper_size_info_fixed *values;
124
125 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
126 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
127
128 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
129 printk(KERN_WARNING PFX "i810 is disabled\n");
130 return 0;
131 }
132 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
133 agp_bridge->previous_size =
134 agp_bridge->current_size = (void *) (values + 1);
135 agp_bridge->aperture_size_idx = 1;
136 return values[1].size;
137 } else {
138 agp_bridge->previous_size =
139 agp_bridge->current_size = (void *) (values);
140 agp_bridge->aperture_size_idx = 0;
141 return values[0].size;
142 }
143
144 return 0;
145}
146
147static int intel_i810_configure(void)
148{
149 struct aper_size_info_fixed *current_size;
150 u32 temp;
151 int i;
152
153 current_size = A_SIZE_FIX(agp_bridge->current_size);
154
c4ca8817
WZ		 155 if (!intel_private.registers) {
156 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
e4ac5e4f
DJ		 157 temp &= 0xfff80000;
158
c4ca8817
WZ		 159 intel_private.registers = ioremap(temp, 128 * 4096);
160 if (!intel_private.registers) {
e4ac5e4f
DJ		 161 printk(KERN_ERR PFX "Unable to remap memory.\n");
162 return -ENOMEM;
163 }
1da177e4
LT		 164 }
165
c4ca8817 166 if ((readl(intel_private.registers+I810_DRAM_CTL)
1da177e4
LT		 167 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
168 /* This will need to be dynamically assigned */
169 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
c4ca8817 170 intel_private.num_dcache_entries = 1024;
1da177e4 171 }
c4ca8817 172 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
1da177e4 173 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
c4ca8817
WZ		 174 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
175 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1da177e4
LT		 176
177 if (agp_bridge->driver->needs_scratch_page) {
178 for (i = 0; i < current_size->num_entries; i++) {
c4ca8817
WZ		 179 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
180 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
1da177e4
LT		 181 }
182 }
183 global_cache_flush();
184 return 0;
185}
186
187static void intel_i810_cleanup(void)
188{
c4ca8817
WZ		 189 writel(0, intel_private.registers+I810_PGETBL_CTL);
190 readl(intel_private.registers); /* PCI Posting. */
191 iounmap(intel_private.registers);
1da177e4
LT		 192}
193
194static void intel_i810_tlbflush(struct agp_memory *mem)
195{
196 return;
197}
198
199static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
200{
201 return;
202}
203
204/* Exists to support ARGB cursors */
205static void *i8xx_alloc_pages(void)
206{
207 struct page * page;
208
66c669ba 209 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
1da177e4
LT		 210 if (page == NULL)
211 return NULL;
212
6d238cc4
AV		 213 if (set_pages_uc(page, 4) < 0) {
214 set_pages_wb(page, 4);
89cf7ccc 215 __free_pages(page, 2);
1da177e4
LT		 216 return NULL;
217 }
1da177e4 218 get_page(page);
1da177e4
LT		 219 atomic_inc(&agp_bridge->current_memory_agp);
220 return page_address(page);
221}
222
223static void i8xx_destroy_pages(void *addr)
224{
225 struct page *page;
226
227 if (addr == NULL)
228 return;
229
230 page = virt_to_page(addr);
6d238cc4 231 set_pages_wb(page, 4);
1da177e4 232 put_page(page);
89cf7ccc 233 __free_pages(page, 2);
1da177e4
LT		 234 atomic_dec(&agp_bridge->current_memory_agp);
235}
236
a030ce44
TH		 237static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
238 int type)
239{
240 if (type < AGP_USER_TYPES)
241 return type;
242 else if (type == AGP_USER_CACHED_MEMORY)
243 return INTEL_AGP_CACHED_MEMORY;
244 else
245 return 0;
246}
247
1da177e4
LT		 248static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
249 int type)
250{
251 int i, j, num_entries;
252 void *temp;
a030ce44
TH		 253 int ret = -EINVAL;
254 int mask_type;
1da177e4 255
5aa80c72 256 if (mem->page_count == 0)
a030ce44 257 goto out;
5aa80c72 258
1da177e4
LT		 259 temp = agp_bridge->current_size;
260 num_entries = A_SIZE_FIX(temp)->num_entries;
261
6a92a4e0 262 if ((pg_start + mem->page_count) > num_entries)
a030ce44 263 goto out_err;
6a92a4e0 264
1da177e4 265
a030ce44
TH		 266 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
267 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
268 ret = -EBUSY;
269 goto out_err;
1da177e4 270 }
1da177e4
LT		 271 }
272
a030ce44
TH		 273 if (type != mem->type)
274 goto out_err;
5aa80c72 275
a030ce44
TH		 276 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
277
278 switch (mask_type) {
279 case AGP_DCACHE_MEMORY:
280 if (!mem->is_flushed)
281 global_cache_flush();
282 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
283 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
c4ca8817 284 intel_private.registers+I810_PTE_BASE+(i*4));
a030ce44 285 }
c4ca8817 286 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
a030ce44
TH		 287 break;
288 case AGP_PHYS_MEMORY:
289 case AGP_NORMAL_MEMORY:
290 if (!mem->is_flushed)
291 global_cache_flush();
292 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
293 writel(agp_bridge->driver->mask_memory(agp_bridge,
294 mem->memory[i],
295 mask_type),
c4ca8817 296 intel_private.registers+I810_PTE_BASE+(j*4));
a030ce44 297 }
c4ca8817 298 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
a030ce44
TH		 299 break;
300 default:
301 goto out_err;
1da177e4 302 }
1da177e4
LT		 303
304 agp_bridge->driver->tlb_flush(mem);
a030ce44
TH		 305out:
306 ret = 0;
307out_err:
308 mem->is_flushed = 1;
309 return ret;
1da177e4
LT		 310}
311
312static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
313 int type)
314{
315 int i;
316
5aa80c72
TH		 317 if (mem->page_count == 0)
318 return 0;
319
1da177e4 320 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
c4ca8817 321 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1da177e4 322 }
c4ca8817 323 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1da177e4 324
1da177e4
LT		 325 agp_bridge->driver->tlb_flush(mem);
326 return 0;
327}
328
329/*
330 * The i810/i830 requires a physical address to program its mouse
331 * pointer into hardware.
332 * However the Xserver still writes to it through the agp aperture.
333 */
334static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
335{
336 struct agp_memory *new;
337 void *addr;
338
1da177e4
LT		 339 switch (pg_count) {
340 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
341 break;
342 case 4:
343 /* kludge to get 4 physical pages for ARGB cursor */
344 addr = i8xx_alloc_pages();
345 break;
346 default:
347 return NULL;
348 }
349
350 if (addr == NULL)
351 return NULL;
352
353 new = agp_create_memory(pg_count);
354 if (new == NULL)
355 return NULL;
356
07eee78e 357 new->memory[0] = virt_to_gart(addr);
1da177e4
LT		 358 if (pg_count == 4) {
359 /* kludge to get 4 physical pages for ARGB cursor */
360 new->memory[1] = new->memory[0] + PAGE_SIZE;
361 new->memory[2] = new->memory[1] + PAGE_SIZE;
362 new->memory[3] = new->memory[2] + PAGE_SIZE;
363 }
364 new->page_count = pg_count;
365 new->num_scratch_pages = pg_count;
366 new->type = AGP_PHYS_MEMORY;
367 new->physical = new->memory[0];
368 return new;
369}
370
371static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
372{
373 struct agp_memory *new;
374
375 if (type == AGP_DCACHE_MEMORY) {
c4ca8817 376 if (pg_count != intel_private.num_dcache_entries)
1da177e4
LT		 377 return NULL;
378
379 new = agp_create_memory(1);
380 if (new == NULL)
381 return NULL;
382
383 new->type = AGP_DCACHE_MEMORY;
384 new->page_count = pg_count;
385 new->num_scratch_pages = 0;
a030ce44 386 agp_free_page_array(new);
1da177e4
LT		 387 return new;
388 }
389 if (type == AGP_PHYS_MEMORY)
390 return alloc_agpphysmem_i8xx(pg_count, type);
1da177e4
LT		 391 return NULL;
392}
393
394static void intel_i810_free_by_type(struct agp_memory *curr)
395{
396 agp_free_key(curr->key);
6a92a4e0 397 if (curr->type == AGP_PHYS_MEMORY) {
1da177e4 398 if (curr->page_count == 4)
07eee78e 399 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
88d51967 400 else {
a2721e99
DA		 401 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
402 AGP_PAGE_DESTROY_UNMAP);
a2721e99
DA		 403 agp_bridge->driver->agp_destroy_page(gart_to_virt(curr->memory[0]),
404 AGP_PAGE_DESTROY_FREE);
88d51967 405 }
a030ce44 406 agp_free_page_array(curr);
1da177e4
LT		 407 }
408 kfree(curr);
409}
410
411static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
412 unsigned long addr, int type)
413{
414 /* Type checking must be done elsewhere */
415 return addr | bridge->driver->masks[type].mask;
416}
417
418static struct aper_size_info_fixed intel_i830_sizes[] =
419{
420 {128, 32768, 5},
421 /* The 64M mode still requires a 128k gatt */
422 {64, 16384, 5},
423 {256, 65536, 6},
65c25aad 424 {512, 131072, 7},
1da177e4
LT		 425};
426
1da177e4
LT		 427static void intel_i830_init_gtt_entries(void)
428{
429 u16 gmch_ctrl;
430 int gtt_entries;
431 u8 rdct;
432 int local = 0;
433 static const int ddt[4] = { 0, 16, 32, 64 };
c41e0deb 434 int size; /* reserved space (in kb) at the top of stolen memory */
1da177e4
LT		 435
436 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
437
c41e0deb
EA		 438 if (IS_I965) {
439 u32 pgetbl_ctl;
c4ca8817 440 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
c41e0deb 441
c41e0deb
EA		 442 /* The 965 has a field telling us the size of the GTT,
443 * which may be larger than what is necessary to map the
444 * aperture.
445 */
446 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
447 case I965_PGETBL_SIZE_128KB:
448 size = 128;
449 break;
450 case I965_PGETBL_SIZE_256KB:
451 size = 256;
452 break;
453 case I965_PGETBL_SIZE_512KB:
454 size = 512;
455 break;
456 default:
457 printk(KERN_INFO PFX "Unknown page table size, "
458 "assuming 512KB\n");
459 size = 512;
460 }
461 size += 4; /* add in BIOS popup space */
874808c6
WZ		 462 } else if (IS_G33) {
463 /* G33's GTT size defined in gmch_ctrl */
464 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
465 case G33_PGETBL_SIZE_1M:
466 size = 1024;
467 break;
468 case G33_PGETBL_SIZE_2M:
469 size = 2048;
470 break;
471 default:
472 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
473 "assuming 512KB\n",
474 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
475 size = 512;
476 }
477 size += 4;
c41e0deb
EA		 478 } else {
479 /* On previous hardware, the GTT size was just what was
480 * required to map the aperture.
481 */
482 size = agp_bridge->driver->fetch_size() + 4;
483 }
1da177e4
LT		 484
485 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
486 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
487 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
488 case I830_GMCH_GMS_STOLEN_512:
489 gtt_entries = KB(512) - KB(size);
490 break;
491 case I830_GMCH_GMS_STOLEN_1024:
492 gtt_entries = MB(1) - KB(size);
493 break;
494 case I830_GMCH_GMS_STOLEN_8192:
495 gtt_entries = MB(8) - KB(size);
496 break;
497 case I830_GMCH_GMS_LOCAL:
c4ca8817 498 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
1da177e4
LT		 499 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
500 MB(ddt[I830_RDRAM_DDT(rdct)]);
501 local = 1;
502 break;
503 default:
504 gtt_entries = 0;
505 break;
506 }
507 } else {
e67aa27a 508 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
1da177e4
LT		 509 case I855_GMCH_GMS_STOLEN_1M:
510 gtt_entries = MB(1) - KB(size);
511 break;
512 case I855_GMCH_GMS_STOLEN_4M:
513 gtt_entries = MB(4) - KB(size);
514 break;
515 case I855_GMCH_GMS_STOLEN_8M:
516 gtt_entries = MB(8) - KB(size);
517 break;
518 case I855_GMCH_GMS_STOLEN_16M:
519 gtt_entries = MB(16) - KB(size);
520 break;
521 case I855_GMCH_GMS_STOLEN_32M:
522 gtt_entries = MB(32) - KB(size);
523 break;
524 case I915_GMCH_GMS_STOLEN_48M:
525 /* Check it's really I915G */
e914a36a
CM		 526 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
527 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
d0de98fa 528 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
3b0e8ead 529 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
874808c6 530 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
dde47876 531 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
874808c6 532 IS_I965 || IS_G33)
1da177e4
LT		 533 gtt_entries = MB(48) - KB(size);
534 else
535 gtt_entries = 0;
536 break;
537 case I915_GMCH_GMS_STOLEN_64M:
538 /* Check it's really I915G */
e914a36a
CM		 539 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB ||
540 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
d0de98fa 541 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
3b0e8ead 542 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
874808c6 543 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
dde47876 544 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
874808c6 545 IS_I965 || IS_G33)
1da177e4
LT		 546 gtt_entries = MB(64) - KB(size);
547 else
548 gtt_entries = 0;
874808c6
WZ		 549 break;
550 case G33_GMCH_GMS_STOLEN_128M:
551 if (IS_G33)
552 gtt_entries = MB(128) - KB(size);
553 else
554 gtt_entries = 0;
555 break;
556 case G33_GMCH_GMS_STOLEN_256M:
557 if (IS_G33)
558 gtt_entries = MB(256) - KB(size);
559 else
560 gtt_entries = 0;
561 break;
1da177e4
LT		 562 default:
563 gtt_entries = 0;
564 break;
565 }
566 }
567 if (gtt_entries > 0)
568 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
569 gtt_entries / KB(1), local ? "local" : "stolen");
570 else
571 printk(KERN_INFO PFX
572 "No pre-allocated video memory detected.\n");
573 gtt_entries /= KB(4);
574
c4ca8817 575 intel_private.gtt_entries = gtt_entries;
1da177e4
LT		 576}
577
578/* The intel i830 automatically initializes the agp aperture during POST.
579 * Use the memory already set aside for in the GTT.
580 */
581static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
582{
583 int page_order;
584 struct aper_size_info_fixed *size;
585 int num_entries;
586 u32 temp;
587
588 size = agp_bridge->current_size;
589 page_order = size->page_order;
590 num_entries = size->num_entries;
591 agp_bridge->gatt_table_real = NULL;
592
c4ca8817 593 pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
1da177e4
LT		 594 temp &= 0xfff80000;
595
c4ca8817
WZ		 596 intel_private.registers = ioremap(temp,128 * 4096);
597 if (!intel_private.registers)
1da177e4
LT		 598 return -ENOMEM;
599
c4ca8817 600 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1da177e4
LT		 601 global_cache_flush(); /* FIXME: ?? */
602
603 /* we have to call this as early as possible after the MMIO base address is known */
604 intel_i830_init_gtt_entries();
605
606 agp_bridge->gatt_table = NULL;
607
608 agp_bridge->gatt_bus_addr = temp;
609
610 return 0;
611}
612
613/* Return the gatt table to a sane state. Use the top of stolen
614 * memory for the GTT.
615 */
616static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
617{
618 return 0;
619}
620
621static int intel_i830_fetch_size(void)
622{
623 u16 gmch_ctrl;
624 struct aper_size_info_fixed *values;
625
626 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
627
628 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
629 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
630 /* 855GM/852GM/865G has 128MB aperture size */
631 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
632 agp_bridge->aperture_size_idx = 0;
633 return values[0].size;
634 }
635
636 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
637
638 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
639 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
640 agp_bridge->aperture_size_idx = 0;
641 return values[0].size;
642 } else {
643 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
644 agp_bridge->aperture_size_idx = 1;
645 return values[1].size;
646 }
647
648 return 0;
649}
650
651static int intel_i830_configure(void)
652{
653 struct aper_size_info_fixed *current_size;
654 u32 temp;
655 u16 gmch_ctrl;
656 int i;
657
658 current_size = A_SIZE_FIX(agp_bridge->current_size);
659
c4ca8817 660 pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
1da177e4
LT		 661 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
662
663 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
664 gmch_ctrl |= I830_GMCH_ENABLED;
665 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
666
c4ca8817
WZ		 667 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
668 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1da177e4
LT		 669
670 if (agp_bridge->driver->needs_scratch_page) {
c4ca8817
WZ		 671 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
672 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
673 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
1da177e4
LT		 674 }
675 }
676
677 global_cache_flush();
678 return 0;
679}
680
681static void intel_i830_cleanup(void)
682{
c4ca8817 683 iounmap(intel_private.registers);
1da177e4
LT		 684}
685
686static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
687{
688 int i,j,num_entries;
689 void *temp;
a030ce44
TH		 690 int ret = -EINVAL;
691 int mask_type;
1da177e4 692
5aa80c72 693 if (mem->page_count == 0)
a030ce44 694 goto out;
5aa80c72 695
1da177e4
LT		 696 temp = agp_bridge->current_size;
697 num_entries = A_SIZE_FIX(temp)->num_entries;
698
c4ca8817
WZ		 699 if (pg_start < intel_private.gtt_entries) {
700 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
701 pg_start,intel_private.gtt_entries);
1da177e4
LT		 702
703 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
a030ce44 704 goto out_err;
1da177e4
LT		 705 }
706
707 if ((pg_start + mem->page_count) > num_entries)
a030ce44 708 goto out_err;
1da177e4
LT		 709
710 /* The i830 can't check the GTT for entries since its read only,
711 * depend on the caller to make the correct offset decisions.
712 */
713
a030ce44
TH		 714 if (type != mem->type)
715 goto out_err;
716
717 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1da177e4 718
a030ce44
TH		 719 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
720 mask_type != INTEL_AGP_CACHED_MEMORY)
721 goto out_err;
722
723 if (!mem->is_flushed)
5aa80c72 724 global_cache_flush();
1da177e4
LT		 725
726 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
727 writel(agp_bridge->driver->mask_memory(agp_bridge,
a030ce44 728 mem->memory[i], mask_type),
c4ca8817 729 intel_private.registers+I810_PTE_BASE+(j*4));
1da177e4 730 }
c4ca8817 731 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1da177e4 732 agp_bridge->driver->tlb_flush(mem);
a030ce44
TH		 733
734out:
735 ret = 0;
736out_err:
737 mem->is_flushed = 1;
738 return ret;
1da177e4
LT		 739}
740
741static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
742 int type)
743{
744 int i;
745
5aa80c72
TH		 746 if (mem->page_count == 0)
747 return 0;
1da177e4 748
c4ca8817 749 if (pg_start < intel_private.gtt_entries) {
1da177e4
LT		 750 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
751 return -EINVAL;
752 }
753
754 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
c4ca8817 755 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1da177e4 756 }
c4ca8817 757 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1da177e4 758
1da177e4
LT		 759 agp_bridge->driver->tlb_flush(mem);
760 return 0;
761}
762
763static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
764{
765 if (type == AGP_PHYS_MEMORY)
766 return alloc_agpphysmem_i8xx(pg_count, type);
1da177e4
LT		 767 /* always return NULL for other allocation types for now */
768 return NULL;
769}
770
771static int intel_i915_configure(void)
772{
773 struct aper_size_info_fixed *current_size;
774 u32 temp;
775 u16 gmch_ctrl;
776 int i;
777
778 current_size = A_SIZE_FIX(agp_bridge->current_size);
779
c4ca8817 780 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1da177e4
LT		 781
782 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
783
784 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
785 gmch_ctrl |= I830_GMCH_ENABLED;
786 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
787
c4ca8817
WZ		 788 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
789 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1da177e4
LT		 790
791 if (agp_bridge->driver->needs_scratch_page) {
c4ca8817
WZ		 792 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
793 writel(agp_bridge->scratch_page, intel_private.gtt+i);
794 readl(intel_private.gtt+i); /* PCI Posting. */
1da177e4
LT		 795 }
796 }
797
798 global_cache_flush();
799 return 0;
800}
801
802static void intel_i915_cleanup(void)
803{
c4ca8817
WZ		 804 iounmap(intel_private.gtt);
805 iounmap(intel_private.registers);
1da177e4
LT		 806}
807
808static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
809 int type)
810{
811 int i,j,num_entries;
812 void *temp;
a030ce44
TH		 813 int ret = -EINVAL;
814 int mask_type;
1da177e4 815
5aa80c72 816 if (mem->page_count == 0)
a030ce44 817 goto out;
5aa80c72 818
1da177e4
LT		 819 temp = agp_bridge->current_size;
820 num_entries = A_SIZE_FIX(temp)->num_entries;
821
c4ca8817
WZ		 822 if (pg_start < intel_private.gtt_entries) {
823 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
824 pg_start,intel_private.gtt_entries);
1da177e4
LT		 825
826 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
a030ce44 827 goto out_err;
1da177e4
LT		 828 }
829
830 if ((pg_start + mem->page_count) > num_entries)
a030ce44 831 goto out_err;
1da177e4 832
a030ce44 833 /* The i915 can't check the GTT for entries since its read only,
1da177e4
LT		 834 * depend on the caller to make the correct offset decisions.
835 */
836
a030ce44
TH		 837 if (type != mem->type)
838 goto out_err;
839
840 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1da177e4 841
a030ce44
TH		 842 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
843 mask_type != INTEL_AGP_CACHED_MEMORY)
844 goto out_err;
845
846 if (!mem->is_flushed)
5aa80c72 847 global_cache_flush();
1da177e4
LT		 848
849 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
850 writel(agp_bridge->driver->mask_memory(agp_bridge,
c4ca8817 851 mem->memory[i], mask_type), intel_private.gtt+j);
1da177e4
LT		 852 }
853
c4ca8817 854 readl(intel_private.gtt+j-1);
1da177e4 855 agp_bridge->driver->tlb_flush(mem);
a030ce44
TH		 856
857 out:
858 ret = 0;
859 out_err:
860 mem->is_flushed = 1;
861 return ret;
1da177e4
LT		 862}
863
864static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
865 int type)
866{
867 int i;
868
5aa80c72
TH		 869 if (mem->page_count == 0)
870 return 0;
1da177e4 871
c4ca8817 872 if (pg_start < intel_private.gtt_entries) {
1da177e4
LT		 873 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
874 return -EINVAL;
875 }
876
877 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
c4ca8817 878 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1da177e4 879 }
c4ca8817 880 readl(intel_private.gtt+i-1);
1da177e4 881
1da177e4
LT		 882 agp_bridge->driver->tlb_flush(mem);
883 return 0;
884}
885
c41e0deb
EA		 886/* Return the aperture size by just checking the resource length. The effect
887 * described in the spec of the MSAC registers is just changing of the
888 * resource size.
889 */
890static int intel_i9xx_fetch_size(void)
1da177e4 891{
1eaf122c 892 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
c41e0deb
EA		 893 int aper_size; /* size in megabytes */
894 int i;
1da177e4 895
c4ca8817 896 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1da177e4 897
c41e0deb
EA		 898 for (i = 0; i < num_sizes; i++) {
899 if (aper_size == intel_i830_sizes[i].size) {
900 agp_bridge->current_size = intel_i830_sizes + i;
901 agp_bridge->previous_size = agp_bridge->current_size;
902 return aper_size;
903 }
904 }
1da177e4 905
c41e0deb 906 return 0;
1da177e4
LT		 907}
908
909/* The intel i915 automatically initializes the agp aperture during POST.
910 * Use the memory already set aside for in the GTT.
911 */
912static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
913{
914 int page_order;
915 struct aper_size_info_fixed *size;
916 int num_entries;
917 u32 temp, temp2;
4740622c 918 int gtt_map_size = 256 * 1024;
1da177e4
LT		 919
920 size = agp_bridge->current_size;
921 page_order = size->page_order;
922 num_entries = size->num_entries;
923 agp_bridge->gatt_table_real = NULL;
924
c4ca8817
WZ		 925 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
926 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
1da177e4 927
4740622c
ZW		 928 if (IS_G33)
929 gtt_map_size = 1024 * 1024; /* 1M on G33 */
930 intel_private.gtt = ioremap(temp2, gtt_map_size);
c4ca8817 931 if (!intel_private.gtt)
1da177e4
LT		 932 return -ENOMEM;
933
934 temp &= 0xfff80000;
935
c4ca8817 936 intel_private.registers = ioremap(temp,128 * 4096);
5bdbc7dc
ST		 937 if (!intel_private.registers) {
938 iounmap(intel_private.gtt);
1da177e4 939 return -ENOMEM;
5bdbc7dc 940 }
1da177e4 941
c4ca8817 942 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1da177e4
LT		 943 global_cache_flush(); /* FIXME: ? */
944
945 /* we have to call this as early as possible after the MMIO base address is known */
946 intel_i830_init_gtt_entries();
947
948 agp_bridge->gatt_table = NULL;
949
950 agp_bridge->gatt_bus_addr = temp;
951
952 return 0;
953}
7d915a38
LT		 954
955/*
956 * The i965 supports 36-bit physical addresses, but to keep
957 * the format of the GTT the same, the bits that don't fit
958 * in a 32-bit word are shifted down to bits 4..7.
959 *
960 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
961 * is always zero on 32-bit architectures, so no need to make
962 * this conditional.
963 */
964static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
965 unsigned long addr, int type)
966{
967 /* Shift high bits down */
968 addr |= (addr >> 28) & 0xf0;
969
970 /* Type checking must be done elsewhere */
971 return addr | bridge->driver->masks[type].mask;
972}
973
65c25aad 974/* The intel i965 automatically initializes the agp aperture during POST.
c41e0deb
EA		 975 * Use the memory already set aside for in the GTT.
976 */
65c25aad
EA		 977static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
978{
979 int page_order;
980 struct aper_size_info_fixed *size;
981 int num_entries;
982 u32 temp;
983
984 size = agp_bridge->current_size;
985 page_order = size->page_order;
986 num_entries = size->num_entries;
987 agp_bridge->gatt_table_real = NULL;
988
c4ca8817 989 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
65c25aad
EA		 990
991 temp &= 0xfff00000;
c4ca8817 992 intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
65c25aad 993
5bdbc7dc
ST		 994 if (!intel_private.gtt)
995 return -ENOMEM;
65c25aad
EA		 996
997
c4ca8817 998 intel_private.registers = ioremap(temp,128 * 4096);
5bdbc7dc
ST		 999 if (!intel_private.registers) {
1000 iounmap(intel_private.gtt);
1001 return -ENOMEM;
1002 }
65c25aad 1003
c4ca8817 1004 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
65c25aad
EA		 1005 global_cache_flush(); /* FIXME: ? */
1006
1007 /* we have to call this as early as possible after the MMIO base address is known */
1008 intel_i830_init_gtt_entries();
1009
1010 agp_bridge->gatt_table = NULL;
1011
1012 agp_bridge->gatt_bus_addr = temp;
1013
1014 return 0;
1015}
1016
1da177e4
LT		 1017
1018static int intel_fetch_size(void)
1019{
1020 int i;
1021 u16 temp;
1022 struct aper_size_info_16 *values;
1023
1024 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1025 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1026
1027 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1028 if (temp == values[i].size_value) {
1029 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1030 agp_bridge->aperture_size_idx = i;
1031 return values[i].size;
1032 }
1033 }
1034
1035 return 0;
1036}
1037
1038static int __intel_8xx_fetch_size(u8 temp)
1039{
1040 int i;
1041 struct aper_size_info_8 *values;
1042
1043 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1044
1045 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1046 if (temp == values[i].size_value) {
1047 agp_bridge->previous_size =
1048 agp_bridge->current_size = (void *) (values + i);
1049 agp_bridge->aperture_size_idx = i;
1050 return values[i].size;
1051 }
1052 }
1053 return 0;
1054}
1055
1056static int intel_8xx_fetch_size(void)
1057{
1058 u8 temp;
1059
1060 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1061 return __intel_8xx_fetch_size(temp);
1062}
1063
1064static int intel_815_fetch_size(void)
1065{
1066 u8 temp;
1067
1068 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1069 * one non-reserved bit, so mask the others out ... */
1070 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1071 temp &= (1 << 3);
1072
1073 return __intel_8xx_fetch_size(temp);
1074}
1075
1076static void intel_tlbflush(struct agp_memory *mem)
1077{
1078 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1079 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1080}
1081
1082
1083static void intel_8xx_tlbflush(struct agp_memory *mem)
1084{
1085 u32 temp;
1086 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1087 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1088 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1089 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1090}
1091
1092
1093static void intel_cleanup(void)
1094{
1095 u16 temp;
1096 struct aper_size_info_16 *previous_size;
1097
1098 previous_size = A_SIZE_16(agp_bridge->previous_size);
1099 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1100 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1101 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1102}
1103
1104
1105static void intel_8xx_cleanup(void)
1106{
1107 u16 temp;
1108 struct aper_size_info_8 *previous_size;
1109
1110 previous_size = A_SIZE_8(agp_bridge->previous_size);
1111 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1112 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1113 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1114}
1115
1116
1117static int intel_configure(void)
1118{
1119 u32 temp;
1120 u16 temp2;
1121 struct aper_size_info_16 *current_size;
1122
1123 current_size = A_SIZE_16(agp_bridge->current_size);
1124
1125 /* aperture size */
1126 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1127
1128 /* address to map to */
1129 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1130 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1131
1132 /* attbase - aperture base */
1133 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1134
1135 /* agpctrl */
1136 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1137
1138 /* paccfg/nbxcfg */
1139 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1140 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1141 (temp2 & ~(1 << 10)) | (1 << 9));
1142 /* clear any possible error conditions */
1143 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1144 return 0;
1145}
1146
1147static int intel_815_configure(void)
1148{
1149 u32 temp, addr;
1150 u8 temp2;
1151 struct aper_size_info_8 *current_size;
1152
1153 /* attbase - aperture base */
1154 /* the Intel 815 chipset spec. says that bits 29-31 in the
1155 * ATTBASE register are reserved -> try not to write them */
1156 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1157 printk (KERN_EMERG PFX "gatt bus addr too high");
1158 return -EINVAL;
1159 }
1160
1161 current_size = A_SIZE_8(agp_bridge->current_size);
1162
1163 /* aperture size */
1164 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1165 current_size->size_value);
1166
1167 /* address to map to */
1168 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1169 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1170
1171 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1172 addr &= INTEL_815_ATTBASE_MASK;
1173 addr |= agp_bridge->gatt_bus_addr;
1174 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1175
1176 /* agpctrl */
1177 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1178
1179 /* apcont */
1180 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1181 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1182
1183 /* clear any possible error conditions */
1184 /* Oddness : this chipset seems to have no ERRSTS register ! */
1185 return 0;
1186}
1187
1188static void intel_820_tlbflush(struct agp_memory *mem)
1189{
1190 return;
1191}
1192
1193static void intel_820_cleanup(void)
1194{
1195 u8 temp;
1196 struct aper_size_info_8 *previous_size;
1197
1198 previous_size = A_SIZE_8(agp_bridge->previous_size);
1199 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1200 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1201 temp & ~(1 << 1));
1202 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1203 previous_size->size_value);
1204}
1205
1206
1207static int intel_820_configure(void)
1208{
1209 u32 temp;
1210 u8 temp2;
1211 struct aper_size_info_8 *current_size;
1212
1213 current_size = A_SIZE_8(agp_bridge->current_size);
1214
1215 /* aperture size */
1216 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1217
1218 /* address to map to */
1219 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1220 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1221
1222 /* attbase - aperture base */
1223 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1224
1225 /* agpctrl */
1226 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1227
1228 /* global enable aperture access */
1229 /* This flag is not accessed through MCHCFG register as in */
1230 /* i850 chipset. */
1231 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1232 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1233 /* clear any possible AGP-related error conditions */
1234 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1235 return 0;
1236}
1237
1238static int intel_840_configure(void)
1239{
1240 u32 temp;
1241 u16 temp2;
1242 struct aper_size_info_8 *current_size;
1243
1244 current_size = A_SIZE_8(agp_bridge->current_size);
1245
1246 /* aperture size */
1247 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1248
1249 /* address to map to */
1250 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1251 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1252
1253 /* attbase - aperture base */
1254 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1255
1256 /* agpctrl */
1257 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1258
1259 /* mcgcfg */
1260 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1261 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1262 /* clear any possible error conditions */
1263 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1264 return 0;
1265}
1266
1267static int intel_845_configure(void)
1268{
1269 u32 temp;
1270 u8 temp2;
1271 struct aper_size_info_8 *current_size;
1272
1273 current_size = A_SIZE_8(agp_bridge->current_size);
1274
1275 /* aperture size */
1276 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1277
b0825488
MG		 1278 if (agp_bridge->apbase_config != 0) {
1279 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1280 agp_bridge->apbase_config);
1281 } else {
1282 /* address to map to */
1283 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1284 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1285 agp_bridge->apbase_config = temp;
1286 }
1da177e4
LT		 1287
1288 /* attbase - aperture base */
1289 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1290
1291 /* agpctrl */
1292 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1293
1294 /* agpm */
1295 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1296 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1297 /* clear any possible error conditions */
1298 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1299 return 0;
1300}
1301
1302static int intel_850_configure(void)
1303{
1304 u32 temp;
1305 u16 temp2;
1306 struct aper_size_info_8 *current_size;
1307
1308 current_size = A_SIZE_8(agp_bridge->current_size);
1309
1310 /* aperture size */
1311 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1312
1313 /* address to map to */
1314 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1315 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1316
1317 /* attbase - aperture base */
1318 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1319
1320 /* agpctrl */
1321 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1322
1323 /* mcgcfg */
1324 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1325 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1326 /* clear any possible AGP-related error conditions */
1327 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1328 return 0;
1329}
1330
1331static int intel_860_configure(void)
1332{
1333 u32 temp;
1334 u16 temp2;
1335 struct aper_size_info_8 *current_size;
1336
1337 current_size = A_SIZE_8(agp_bridge->current_size);
1338
1339 /* aperture size */
1340 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1341
1342 /* address to map to */
1343 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1344 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1345
1346 /* attbase - aperture base */
1347 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1348
1349 /* agpctrl */
1350 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1351
1352 /* mcgcfg */
1353 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1354 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1355 /* clear any possible AGP-related error conditions */
1356 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1357 return 0;
1358}
1359
1360static int intel_830mp_configure(void)
1361{
1362 u32 temp;
1363 u16 temp2;
1364 struct aper_size_info_8 *current_size;
1365
1366 current_size = A_SIZE_8(agp_bridge->current_size);
1367
1368 /* aperture size */
1369 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1370
1371 /* address to map to */
1372 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1373 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1374
1375 /* attbase - aperture base */
1376 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1377
1378 /* agpctrl */
1379 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1380
1381 /* gmch */
1382 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1383 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1384 /* clear any possible AGP-related error conditions */
1385 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1386 return 0;
1387}
1388
1389static int intel_7505_configure(void)
1390{
1391 u32 temp;
1392 u16 temp2;
1393 struct aper_size_info_8 *current_size;
1394
1395 current_size = A_SIZE_8(agp_bridge->current_size);
1396
1397 /* aperture size */
1398 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1399
1400 /* address to map to */
1401 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1402 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1403
1404 /* attbase - aperture base */
1405 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1406
1407 /* agpctrl */
1408 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1409
1410 /* mchcfg */
1411 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1412 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1413
1414 return 0;
1415}
1416
1417/* Setup function */
e5524f35 1418static const struct gatt_mask intel_generic_masks[] =
1da177e4
LT		 1419{
1420 {.mask = 0x00000017, .type = 0}
1421};
1422
e5524f35 1423static const struct aper_size_info_8 intel_815_sizes[2] =
1da177e4
LT		 1424{
1425 {64, 16384, 4, 0},
1426 {32, 8192, 3, 8},
1427};
1428
e5524f35 1429static const struct aper_size_info_8 intel_8xx_sizes[7] =
1da177e4
LT		 1430{
1431 {256, 65536, 6, 0},
1432 {128, 32768, 5, 32},
1433 {64, 16384, 4, 48},
1434 {32, 8192, 3, 56},
1435 {16, 4096, 2, 60},
1436 {8, 2048, 1, 62},
1437 {4, 1024, 0, 63}
1438};
1439
e5524f35 1440static const struct aper_size_info_16 intel_generic_sizes[7] =
1da177e4
LT		 1441{
1442 {256, 65536, 6, 0},
1443 {128, 32768, 5, 32},
1444 {64, 16384, 4, 48},
1445 {32, 8192, 3, 56},
1446 {16, 4096, 2, 60},
1447 {8, 2048, 1, 62},
1448 {4, 1024, 0, 63}
1449};
1450
e5524f35 1451static const struct aper_size_info_8 intel_830mp_sizes[4] =
1da177e4
LT		 1452{
1453 {256, 65536, 6, 0},
1454 {128, 32768, 5, 32},
1455 {64, 16384, 4, 48},
1456 {32, 8192, 3, 56}
1457};
1458
e5524f35 1459static const struct agp_bridge_driver intel_generic_driver = {
1da177e4
LT		 1460 .owner = THIS_MODULE,
1461 .aperture_sizes = intel_generic_sizes,
1462 .size_type = U16_APER_SIZE,
1463 .num_aperture_sizes = 7,
1464 .configure = intel_configure,
1465 .fetch_size = intel_fetch_size,
1466 .cleanup = intel_cleanup,
1467 .tlb_flush = intel_tlbflush,
1468 .mask_memory = agp_generic_mask_memory,
1469 .masks = intel_generic_masks,
1470 .agp_enable = agp_generic_enable,
1471 .cache_flush = global_cache_flush,
1472 .create_gatt_table = agp_generic_create_gatt_table,
1473 .free_gatt_table = agp_generic_free_gatt_table,
1474 .insert_memory = agp_generic_insert_memory,
1475 .remove_memory = agp_generic_remove_memory,
1476 .alloc_by_type = agp_generic_alloc_by_type,
1477 .free_by_type = agp_generic_free_by_type,
1478 .agp_alloc_page = agp_generic_alloc_page,
1479 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1480 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1481};
1482
e5524f35 1483static const struct agp_bridge_driver intel_810_driver = {
1da177e4
LT		 1484 .owner = THIS_MODULE,
1485 .aperture_sizes = intel_i810_sizes,
1486 .size_type = FIXED_APER_SIZE,
1487 .num_aperture_sizes = 2,
1488 .needs_scratch_page = TRUE,
1489 .configure = intel_i810_configure,
1490 .fetch_size = intel_i810_fetch_size,
1491 .cleanup = intel_i810_cleanup,
1492 .tlb_flush = intel_i810_tlbflush,
1493 .mask_memory = intel_i810_mask_memory,
1494 .masks = intel_i810_masks,
1495 .agp_enable = intel_i810_agp_enable,
1496 .cache_flush = global_cache_flush,
1497 .create_gatt_table = agp_generic_create_gatt_table,
1498 .free_gatt_table = agp_generic_free_gatt_table,
1499 .insert_memory = intel_i810_insert_entries,
1500 .remove_memory = intel_i810_remove_entries,
1501 .alloc_by_type = intel_i810_alloc_by_type,
1502 .free_by_type = intel_i810_free_by_type,
1503 .agp_alloc_page = agp_generic_alloc_page,
1504 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1505 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1506};
1507
e5524f35 1508static const struct agp_bridge_driver intel_815_driver = {
1da177e4
LT		 1509 .owner = THIS_MODULE,
1510 .aperture_sizes = intel_815_sizes,
1511 .size_type = U8_APER_SIZE,
1512 .num_aperture_sizes = 2,
1513 .configure = intel_815_configure,
1514 .fetch_size = intel_815_fetch_size,
1515 .cleanup = intel_8xx_cleanup,
1516 .tlb_flush = intel_8xx_tlbflush,
1517 .mask_memory = agp_generic_mask_memory,
1518 .masks = intel_generic_masks,
1519 .agp_enable = agp_generic_enable,
1520 .cache_flush = global_cache_flush,
1521 .create_gatt_table = agp_generic_create_gatt_table,
1522 .free_gatt_table = agp_generic_free_gatt_table,
1523 .insert_memory = agp_generic_insert_memory,
1524 .remove_memory = agp_generic_remove_memory,
1525 .alloc_by_type = agp_generic_alloc_by_type,
1526 .free_by_type = agp_generic_free_by_type,
1527 .agp_alloc_page = agp_generic_alloc_page,
1528 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1529 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1530};
1531
e5524f35 1532static const struct agp_bridge_driver intel_830_driver = {
1da177e4
LT		 1533 .owner = THIS_MODULE,
1534 .aperture_sizes = intel_i830_sizes,
1535 .size_type = FIXED_APER_SIZE,
c14635eb 1536 .num_aperture_sizes = 4,
1da177e4
LT		 1537 .needs_scratch_page = TRUE,
1538 .configure = intel_i830_configure,
1539 .fetch_size = intel_i830_fetch_size,
1540 .cleanup = intel_i830_cleanup,
1541 .tlb_flush = intel_i810_tlbflush,
1542 .mask_memory = intel_i810_mask_memory,
1543 .masks = intel_i810_masks,
1544 .agp_enable = intel_i810_agp_enable,
1545 .cache_flush = global_cache_flush,
1546 .create_gatt_table = intel_i830_create_gatt_table,
1547 .free_gatt_table = intel_i830_free_gatt_table,
1548 .insert_memory = intel_i830_insert_entries,
1549 .remove_memory = intel_i830_remove_entries,
1550 .alloc_by_type = intel_i830_alloc_by_type,
1551 .free_by_type = intel_i810_free_by_type,
1552 .agp_alloc_page = agp_generic_alloc_page,
1553 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1554 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1da177e4
LT		 1555};
1556
e5524f35 1557static const struct agp_bridge_driver intel_820_driver = {
1da177e4
LT		 1558 .owner = THIS_MODULE,
1559 .aperture_sizes = intel_8xx_sizes,
1560 .size_type = U8_APER_SIZE,
1561 .num_aperture_sizes = 7,
1562 .configure = intel_820_configure,
1563 .fetch_size = intel_8xx_fetch_size,
1564 .cleanup = intel_820_cleanup,
1565 .tlb_flush = intel_820_tlbflush,
1566 .mask_memory = agp_generic_mask_memory,
1567 .masks = intel_generic_masks,
1568 .agp_enable = agp_generic_enable,
1569 .cache_flush = global_cache_flush,
1570 .create_gatt_table = agp_generic_create_gatt_table,
1571 .free_gatt_table = agp_generic_free_gatt_table,
1572 .insert_memory = agp_generic_insert_memory,
1573 .remove_memory = agp_generic_remove_memory,
1574 .alloc_by_type = agp_generic_alloc_by_type,
1575 .free_by_type = agp_generic_free_by_type,
1576 .agp_alloc_page = agp_generic_alloc_page,
1577 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1578 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1579};
1580
e5524f35 1581static const struct agp_bridge_driver intel_830mp_driver = {
1da177e4
LT		 1582 .owner = THIS_MODULE,
1583 .aperture_sizes = intel_830mp_sizes,
1584 .size_type = U8_APER_SIZE,
1585 .num_aperture_sizes = 4,
1586 .configure = intel_830mp_configure,
1587 .fetch_size = intel_8xx_fetch_size,
1588 .cleanup = intel_8xx_cleanup,
1589 .tlb_flush = intel_8xx_tlbflush,
1590 .mask_memory = agp_generic_mask_memory,
1591 .masks = intel_generic_masks,
1592 .agp_enable = agp_generic_enable,
1593 .cache_flush = global_cache_flush,
1594 .create_gatt_table = agp_generic_create_gatt_table,
1595 .free_gatt_table = agp_generic_free_gatt_table,
1596 .insert_memory = agp_generic_insert_memory,
1597 .remove_memory = agp_generic_remove_memory,
1598 .alloc_by_type = agp_generic_alloc_by_type,
1599 .free_by_type = agp_generic_free_by_type,
1600 .agp_alloc_page = agp_generic_alloc_page,
1601 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1602 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1603};
1604
e5524f35 1605static const struct agp_bridge_driver intel_840_driver = {
1da177e4
LT		 1606 .owner = THIS_MODULE,
1607 .aperture_sizes = intel_8xx_sizes,
1608 .size_type = U8_APER_SIZE,
1609 .num_aperture_sizes = 7,
1610 .configure = intel_840_configure,
1611 .fetch_size = intel_8xx_fetch_size,
1612 .cleanup = intel_8xx_cleanup,
1613 .tlb_flush = intel_8xx_tlbflush,
1614 .mask_memory = agp_generic_mask_memory,
1615 .masks = intel_generic_masks,
1616 .agp_enable = agp_generic_enable,
1617 .cache_flush = global_cache_flush,
1618 .create_gatt_table = agp_generic_create_gatt_table,
1619 .free_gatt_table = agp_generic_free_gatt_table,
1620 .insert_memory = agp_generic_insert_memory,
1621 .remove_memory = agp_generic_remove_memory,
1622 .alloc_by_type = agp_generic_alloc_by_type,
1623 .free_by_type = agp_generic_free_by_type,
1624 .agp_alloc_page = agp_generic_alloc_page,
1625 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1626 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1627};
1628
e5524f35 1629static const struct agp_bridge_driver intel_845_driver = {
1da177e4
LT		 1630 .owner = THIS_MODULE,
1631 .aperture_sizes = intel_8xx_sizes,
1632 .size_type = U8_APER_SIZE,
1633 .num_aperture_sizes = 7,
1634 .configure = intel_845_configure,
1635 .fetch_size = intel_8xx_fetch_size,
1636 .cleanup = intel_8xx_cleanup,
1637 .tlb_flush = intel_8xx_tlbflush,
1638 .mask_memory = agp_generic_mask_memory,
1639 .masks = intel_generic_masks,
1640 .agp_enable = agp_generic_enable,
1641 .cache_flush = global_cache_flush,
1642 .create_gatt_table = agp_generic_create_gatt_table,
1643 .free_gatt_table = agp_generic_free_gatt_table,
1644 .insert_memory = agp_generic_insert_memory,
1645 .remove_memory = agp_generic_remove_memory,
1646 .alloc_by_type = agp_generic_alloc_by_type,
1647 .free_by_type = agp_generic_free_by_type,
1648 .agp_alloc_page = agp_generic_alloc_page,
1649 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1650 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1651};
1652
e5524f35 1653static const struct agp_bridge_driver intel_850_driver = {
1da177e4
LT		 1654 .owner = THIS_MODULE,
1655 .aperture_sizes = intel_8xx_sizes,
1656 .size_type = U8_APER_SIZE,
1657 .num_aperture_sizes = 7,
1658 .configure = intel_850_configure,
1659 .fetch_size = intel_8xx_fetch_size,
1660 .cleanup = intel_8xx_cleanup,
1661 .tlb_flush = intel_8xx_tlbflush,
1662 .mask_memory = agp_generic_mask_memory,
1663 .masks = intel_generic_masks,
1664 .agp_enable = agp_generic_enable,
1665 .cache_flush = global_cache_flush,
1666 .create_gatt_table = agp_generic_create_gatt_table,
1667 .free_gatt_table = agp_generic_free_gatt_table,
1668 .insert_memory = agp_generic_insert_memory,
1669 .remove_memory = agp_generic_remove_memory,
1670 .alloc_by_type = agp_generic_alloc_by_type,
1671 .free_by_type = agp_generic_free_by_type,
1672 .agp_alloc_page = agp_generic_alloc_page,
1673 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1674 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1675};
1676
e5524f35 1677static const struct agp_bridge_driver intel_860_driver = {
1da177e4
LT		 1678 .owner = THIS_MODULE,
1679 .aperture_sizes = intel_8xx_sizes,
1680 .size_type = U8_APER_SIZE,
1681 .num_aperture_sizes = 7,
1682 .configure = intel_860_configure,
1683 .fetch_size = intel_8xx_fetch_size,
1684 .cleanup = intel_8xx_cleanup,
1685 .tlb_flush = intel_8xx_tlbflush,
1686 .mask_memory = agp_generic_mask_memory,
1687 .masks = intel_generic_masks,
1688 .agp_enable = agp_generic_enable,
1689 .cache_flush = global_cache_flush,
1690 .create_gatt_table = agp_generic_create_gatt_table,
1691 .free_gatt_table = agp_generic_free_gatt_table,
1692 .insert_memory = agp_generic_insert_memory,
1693 .remove_memory = agp_generic_remove_memory,
1694 .alloc_by_type = agp_generic_alloc_by_type,
1695 .free_by_type = agp_generic_free_by_type,
1696 .agp_alloc_page = agp_generic_alloc_page,
1697 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1698 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1699};
1700
e5524f35 1701static const struct agp_bridge_driver intel_915_driver = {
1da177e4
LT		 1702 .owner = THIS_MODULE,
1703 .aperture_sizes = intel_i830_sizes,
1704 .size_type = FIXED_APER_SIZE,
c14635eb 1705 .num_aperture_sizes = 4,
1da177e4
LT		 1706 .needs_scratch_page = TRUE,
1707 .configure = intel_i915_configure,
c41e0deb 1708 .fetch_size = intel_i9xx_fetch_size,
1da177e4
LT		 1709 .cleanup = intel_i915_cleanup,
1710 .tlb_flush = intel_i810_tlbflush,
1711 .mask_memory = intel_i810_mask_memory,
1712 .masks = intel_i810_masks,
1713 .agp_enable = intel_i810_agp_enable,
1714 .cache_flush = global_cache_flush,
1715 .create_gatt_table = intel_i915_create_gatt_table,
1716 .free_gatt_table = intel_i830_free_gatt_table,
1717 .insert_memory = intel_i915_insert_entries,
1718 .remove_memory = intel_i915_remove_entries,
1719 .alloc_by_type = intel_i830_alloc_by_type,
1720 .free_by_type = intel_i810_free_by_type,
1721 .agp_alloc_page = agp_generic_alloc_page,
1722 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1723 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1da177e4
LT		 1724};
1725
e5524f35 1726static const struct agp_bridge_driver intel_i965_driver = {
65c25aad
EA		 1727 .owner = THIS_MODULE,
1728 .aperture_sizes = intel_i830_sizes,
1729 .size_type = FIXED_APER_SIZE,
1730 .num_aperture_sizes = 4,
1731 .needs_scratch_page = TRUE,
1732 .configure = intel_i915_configure,
c41e0deb 1733 .fetch_size = intel_i9xx_fetch_size,
65c25aad
EA		 1734 .cleanup = intel_i915_cleanup,
1735 .tlb_flush = intel_i810_tlbflush,
7d915a38 1736 .mask_memory = intel_i965_mask_memory,
65c25aad
EA		 1737 .masks = intel_i810_masks,
1738 .agp_enable = intel_i810_agp_enable,
1739 .cache_flush = global_cache_flush,
1740 .create_gatt_table = intel_i965_create_gatt_table,
1741 .free_gatt_table = intel_i830_free_gatt_table,
1742 .insert_memory = intel_i915_insert_entries,
1743 .remove_memory = intel_i915_remove_entries,
1744 .alloc_by_type = intel_i830_alloc_by_type,
1745 .free_by_type = intel_i810_free_by_type,
1746 .agp_alloc_page = agp_generic_alloc_page,
1747 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1748 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
65c25aad 1749};
1da177e4 1750
e5524f35 1751static const struct agp_bridge_driver intel_7505_driver = {
1da177e4
LT		 1752 .owner = THIS_MODULE,
1753 .aperture_sizes = intel_8xx_sizes,
1754 .size_type = U8_APER_SIZE,
1755 .num_aperture_sizes = 7,
1756 .configure = intel_7505_configure,
1757 .fetch_size = intel_8xx_fetch_size,
1758 .cleanup = intel_8xx_cleanup,
1759 .tlb_flush = intel_8xx_tlbflush,
1760 .mask_memory = agp_generic_mask_memory,
1761 .masks = intel_generic_masks,
1762 .agp_enable = agp_generic_enable,
1763 .cache_flush = global_cache_flush,
1764 .create_gatt_table = agp_generic_create_gatt_table,
1765 .free_gatt_table = agp_generic_free_gatt_table,
1766 .insert_memory = agp_generic_insert_memory,
1767 .remove_memory = agp_generic_remove_memory,
1768 .alloc_by_type = agp_generic_alloc_by_type,
1769 .free_by_type = agp_generic_free_by_type,
1770 .agp_alloc_page = agp_generic_alloc_page,
1771 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1772 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1773};
1774
874808c6
WZ		 1775static const struct agp_bridge_driver intel_g33_driver = {
1776 .owner = THIS_MODULE,
1777 .aperture_sizes = intel_i830_sizes,
1778 .size_type = FIXED_APER_SIZE,
1779 .num_aperture_sizes = 4,
1780 .needs_scratch_page = TRUE,
1781 .configure = intel_i915_configure,
1782 .fetch_size = intel_i9xx_fetch_size,
1783 .cleanup = intel_i915_cleanup,
1784 .tlb_flush = intel_i810_tlbflush,
1785 .mask_memory = intel_i965_mask_memory,
1786 .masks = intel_i810_masks,
1787 .agp_enable = intel_i810_agp_enable,
1788 .cache_flush = global_cache_flush,
1789 .create_gatt_table = intel_i915_create_gatt_table,
1790 .free_gatt_table = intel_i830_free_gatt_table,
1791 .insert_memory = intel_i915_insert_entries,
1792 .remove_memory = intel_i915_remove_entries,
1793 .alloc_by_type = intel_i830_alloc_by_type,
1794 .free_by_type = intel_i810_free_by_type,
1795 .agp_alloc_page = agp_generic_alloc_page,
1796 .agp_destroy_page = agp_generic_destroy_page,
1797 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1798};
1da177e4 1799
9614ece1 1800static int find_gmch(u16 device)
1da177e4 1801{
9614ece1 1802 struct pci_dev *gmch_device;
1da177e4 1803
9614ece1
WZ		 1804 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1805 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1806 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1807 device, gmch_device);
1da177e4
LT		 1808 }
1809
9614ece1 1810 if (!gmch_device)
1da177e4
LT		 1811 return 0;
1812
9614ece1 1813 intel_private.pcidev = gmch_device;
1da177e4
LT		 1814 return 1;
1815}
1816
9614ece1
WZ		 1817/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1818 * driver and gmch_driver must be non-null, and find_gmch will determine
1819 * which one should be used if a gmch_chip_id is present.
1820 */
1821static const struct intel_driver_description {
1822 unsigned int chip_id;
1823 unsigned int gmch_chip_id;
88889851 1824 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
9614ece1
WZ		 1825 char *name;
1826 const struct agp_bridge_driver *driver;
1827 const struct agp_bridge_driver *gmch_driver;
1828} intel_agp_chipsets[] = {
88889851
WZ		 1829 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1830 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1831 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1832 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
9614ece1 1833 NULL, &intel_810_driver },
88889851 1834 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
9614ece1 1835 NULL, &intel_810_driver },
88889851 1836 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
9614ece1 1837 NULL, &intel_810_driver },
88889851
WZ		 1838 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1839 &intel_815_driver, &intel_810_driver },
1840 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1841 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1842 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
9614ece1 1843 &intel_830mp_driver, &intel_830_driver },
88889851
WZ		 1844 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1845 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1846 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
9614ece1 1847 &intel_845_driver, &intel_830_driver },
88889851
WZ		 1848 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1849 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1850 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
9614ece1 1851 &intel_845_driver, &intel_830_driver },
88889851
WZ		 1852 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1853 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
9614ece1 1854 &intel_845_driver, &intel_830_driver },
88889851 1855 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
e914a36a
CM		 1856 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
1857 NULL, &intel_915_driver },
88889851 1858 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
47d46379 1859 NULL, &intel_915_driver },
88889851 1860 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
47d46379 1861 NULL, &intel_915_driver },
88889851 1862 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
47d46379 1863 NULL, &intel_915_driver },
dde47876 1864 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
47d46379 1865 NULL, &intel_915_driver },
dde47876 1866 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
47d46379 1867 NULL, &intel_915_driver },
88889851 1868 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
47d46379 1869 NULL, &intel_i965_driver },
88889851 1870 { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
47d46379 1871 NULL, &intel_i965_driver },
88889851 1872 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
47d46379 1873 NULL, &intel_i965_driver },
88889851 1874 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
47d46379 1875 NULL, &intel_i965_driver },
dde47876 1876 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
47d46379 1877 NULL, &intel_i965_driver },
dde47876 1878 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
47d46379 1879 NULL, &intel_i965_driver },
88889851
WZ		 1880 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1881 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1882 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
47d46379 1883 NULL, &intel_g33_driver },
88889851 1884 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
47d46379 1885 NULL, &intel_g33_driver },
88889851 1886 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
47d46379 1887 NULL, &intel_g33_driver },
88889851 1888 { 0, 0, 0, NULL, NULL, NULL }
9614ece1
WZ		 1889};
1890
1da177e4
LT		 1891static int __devinit agp_intel_probe(struct pci_dev *pdev,
1892 const struct pci_device_id *ent)
1893{
1894 struct agp_bridge_data *bridge;
1da177e4
LT		 1895 u8 cap_ptr = 0;
1896 struct resource *r;
9614ece1 1897 int i;
1da177e4
LT		 1898
1899 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1900
1901 bridge = agp_alloc_bridge();
1902 if (!bridge)
1903 return -ENOMEM;
1904
9614ece1
WZ		 1905 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1906 /* In case that multiple models of gfx chip may
1907 stand on same host bridge type, this can be
1908 sure we detect the right IGD. */
88889851
WZ		 1909 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1910 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1911 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1912 bridge->driver =
1913 intel_agp_chipsets[i].gmch_driver;
1914 break;
1915 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1916 continue;
1917 } else {
1918 bridge->driver = intel_agp_chipsets[i].driver;
1919 break;
1920 }
1921 }
9614ece1
WZ		 1922 }
1923
1924 if (intel_agp_chipsets[i].name == NULL) {
1da177e4 1925 if (cap_ptr)
9614ece1
WZ		 1926 printk(KERN_WARNING PFX "Unsupported Intel chipset"
1927 "(device id: %04x)\n", pdev->device);
1928 agp_put_bridge(bridge);
1929 return -ENODEV;
1930 }
1931
9614ece1 1932 if (bridge->driver == NULL) {
47d46379
WZ		 1933 /* bridge has no AGP and no IGD detected */
1934 if (cap_ptr)
1935 printk(KERN_WARNING PFX "Failed to find bridge device "
1936 "(chip_id: %04x)\n",
1937 intel_agp_chipsets[i].gmch_chip_id);
1da177e4
LT		 1938 agp_put_bridge(bridge);
1939 return -ENODEV;
9614ece1 1940 }
1da177e4
LT		 1941
1942 bridge->dev = pdev;
1943 bridge->capndx = cap_ptr;
c4ca8817 1944 bridge->dev_private_data = &intel_private;
1da177e4 1945
9614ece1
WZ		 1946 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1947 intel_agp_chipsets[i].name);
1da177e4
LT		 1948
1949 /*
1950 * The following fixes the case where the BIOS has "forgotten" to
1951 * provide an address range for the GART.
1952 * 20030610 - hamish@zot.org
1953 */
1954 r = &pdev->resource[0];
1955 if (!r->start && r->end) {
6a92a4e0 1956 if (pci_assign_resource(pdev, 0)) {
1da177e4
LT		 1957 printk(KERN_ERR PFX "could not assign resource 0\n");
1958 agp_put_bridge(bridge);
1959 return -ENODEV;
1960 }
1961 }
1962
1963 /*
1964 * If the device has not been properly setup, the following will catch
1965 * the problem and should stop the system from crashing.
1966 * 20030610 - hamish@zot.org
1967 */
1968 if (pci_enable_device(pdev)) {
1969 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1970 agp_put_bridge(bridge);
1971 return -ENODEV;
1972 }
1973
1974 /* Fill in the mode register */
1975 if (cap_ptr) {
1976 pci_read_config_dword(pdev,
1977 bridge->capndx+PCI_AGP_STATUS,
1978 &bridge->mode);
1979 }
1980
1981 pci_set_drvdata(pdev, bridge);
1982 return agp_add_bridge(bridge);
1da177e4
LT		 1983}
1984
1985static void __devexit agp_intel_remove(struct pci_dev *pdev)
1986{
1987 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1988
1989 agp_remove_bridge(bridge);
1990
c4ca8817
WZ		 1991 if (intel_private.pcidev)
1992 pci_dev_put(intel_private.pcidev);
1da177e4
LT		 1993
1994 agp_put_bridge(bridge);
1995}
1996
85be7d60 1997#ifdef CONFIG_PM
1da177e4
LT		 1998static int agp_intel_resume(struct pci_dev *pdev)
1999{
2000 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2001
2002 pci_restore_state(pdev);
2003
4b95320f
WZ		 2004 /* We should restore our graphics device's config space,
2005 * as host bridge (00:00) resumes before graphics device (02:00),
2006 * then our access to its pci space can work right.
2007 */
c4ca8817
WZ		 2008 if (intel_private.pcidev)
2009 pci_restore_state(intel_private.pcidev);
4b95320f 2010
1da177e4
LT		 2011 if (bridge->driver == &intel_generic_driver)
2012 intel_configure();
2013 else if (bridge->driver == &intel_850_driver)
2014 intel_850_configure();
2015 else if (bridge->driver == &intel_845_driver)
2016 intel_845_configure();
2017 else if (bridge->driver == &intel_830mp_driver)
2018 intel_830mp_configure();
2019 else if (bridge->driver == &intel_915_driver)
2020 intel_i915_configure();
2021 else if (bridge->driver == &intel_830_driver)
2022 intel_i830_configure();
2023 else if (bridge->driver == &intel_810_driver)
2024 intel_i810_configure();
08da3f41
DJ		 2025 else if (bridge->driver == &intel_i965_driver)
2026 intel_i915_configure();
1da177e4
LT		 2027
2028 return 0;
2029}
85be7d60 2030#endif
1da177e4
LT		 2031
2032static struct pci_device_id agp_intel_pci_table[] = {
2033#define ID(x) \
2034 { \
2035 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2036 .class_mask = ~0, \
2037 .vendor = PCI_VENDOR_ID_INTEL, \
2038 .device = x, \
2039 .subvendor = PCI_ANY_ID, \
2040 .subdevice = PCI_ANY_ID, \
2041 }
2042 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2043 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2044 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2045 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2046 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2047 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2048 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2049 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2050 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2051 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2052 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2053 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2054 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2055 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2056 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2057 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2058 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2059 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2060 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2061 ID(PCI_DEVICE_ID_INTEL_7505_0),
2062 ID(PCI_DEVICE_ID_INTEL_7205_0),
e914a36a 2063 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
1da177e4
LT		 2064 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2065 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
d0de98fa 2066 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
3b0e8ead 2067 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
dde47876 2068 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
65c25aad
EA		 2069 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2070 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2071 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2072 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
4598af33 2073 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
dde47876 2074 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
874808c6
WZ		 2075 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2076 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2077 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
1da177e4
LT		 2078 { }
2079};
2080
2081MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2082
2083static struct pci_driver agp_intel_pci_driver = {
2084 .name = "agpgart-intel",
2085 .id_table = agp_intel_pci_table,
2086 .probe = agp_intel_probe,
2087 .remove = __devexit_p(agp_intel_remove),
85be7d60 2088#ifdef CONFIG_PM
1da177e4 2089 .resume = agp_intel_resume,
85be7d60 2090#endif
1da177e4
LT		 2091};
2092
2093static int __init agp_intel_init(void)
2094{
2095 if (agp_off)
2096 return -EINVAL;
2097 return pci_register_driver(&agp_intel_pci_driver);
2098}
2099
2100static void __exit agp_intel_cleanup(void)
2101{
2102 pci_unregister_driver(&agp_intel_pci_driver);
2103}
2104
2105module_init(agp_intel_init);
2106module_exit(agp_intel_cleanup);
2107
2108MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2109MODULE_LICENSE("GPL and additional rights");
Linux 6.x block layer and io_uring tree(s)