Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
e914a36a CM |
13 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
14 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
15 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
16 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
9119f85a ZW |
17 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
18 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
65c25aad EA |
19 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
20 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
21 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
22 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
23 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
24 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 25 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 26 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 27 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 28 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
874808c6 WZ |
29 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
30 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
31 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
32 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
33 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
34 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
99d32bd5 ZW |
35 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
36 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
25ce77ab ZW |
37 | #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00 |
38 | #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02 | |
39 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
40 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
41 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
42 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
65c25aad | 43 | |
f011ae74 DA |
44 | /* cover 915 and 945 variants */ |
45 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
46 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
47 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
48 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
49 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
50 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
51 | ||
65c25aad | 52 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ |
f011ae74 DA |
53 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ |
54 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
55 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
56 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
4e8b6e25 | 57 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \ |
99d32bd5 | 58 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB) |
65c25aad | 59 | |
874808c6 WZ |
60 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
61 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
62 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB) | |
65c25aad | 63 | |
25ce77ab ZW |
64 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \ |
65 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | |
66 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB) | |
67 | ||
a030ce44 TH |
68 | extern int agp_memory_reserved; |
69 | ||
70 | ||
1da177e4 LT |
71 | /* Intel 815 register */ |
72 | #define INTEL_815_APCONT 0x51 | |
73 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
74 | ||
75 | /* Intel i820 registers */ | |
76 | #define INTEL_I820_RDCR 0x51 | |
77 | #define INTEL_I820_ERRSTS 0xc8 | |
78 | ||
79 | /* Intel i840 registers */ | |
80 | #define INTEL_I840_MCHCFG 0x50 | |
81 | #define INTEL_I840_ERRSTS 0xc8 | |
82 | ||
83 | /* Intel i850 registers */ | |
84 | #define INTEL_I850_MCHCFG 0x50 | |
85 | #define INTEL_I850_ERRSTS 0xc8 | |
86 | ||
87 | /* intel 915G registers */ | |
88 | #define I915_GMADDR 0x18 | |
89 | #define I915_MMADDR 0x10 | |
90 | #define I915_PTEADDR 0x1C | |
91 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
92 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
25ce77ab ZW |
93 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
94 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
95 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
96 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
97 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
98 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
99 | ||
6c00a61e | 100 | #define I915_IFPADDR 0x60 |
1da177e4 | 101 | |
65c25aad EA |
102 | /* Intel 965G registers */ |
103 | #define I965_MSAC 0x62 | |
6c00a61e | 104 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
105 | |
106 | /* Intel 7505 registers */ | |
107 | #define INTEL_I7505_APSIZE 0x74 | |
108 | #define INTEL_I7505_NCAPID 0x60 | |
109 | #define INTEL_I7505_NISTAT 0x6c | |
110 | #define INTEL_I7505_ATTBASE 0x78 | |
111 | #define INTEL_I7505_ERRSTS 0x42 | |
112 | #define INTEL_I7505_AGPCTRL 0x70 | |
113 | #define INTEL_I7505_MCHCFG 0x50 | |
114 | ||
e5524f35 | 115 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
116 | { |
117 | {64, 16384, 4}, | |
118 | /* The 32M mode still requires a 64k gatt */ | |
119 | {32, 8192, 4} | |
120 | }; | |
121 | ||
122 | #define AGP_DCACHE_MEMORY 1 | |
123 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 124 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
125 | |
126 | static struct gatt_mask intel_i810_masks[] = | |
127 | { | |
128 | {.mask = I810_PTE_VALID, .type = 0}, | |
129 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
130 | {.mask = I810_PTE_VALID, .type = 0}, |
131 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
132 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
133 | }; |
134 | ||
c4ca8817 WZ |
135 | static struct _intel_private { |
136 | struct pci_dev *pcidev; /* device one */ | |
137 | u8 __iomem *registers; | |
138 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 139 | int num_dcache_entries; |
c4ca8817 WZ |
140 | /* gtt_entries is the number of gtt entries that are already mapped |
141 | * to stolen memory. Stolen memory is larger than the memory mapped | |
142 | * through gtt_entries, as it includes some reserved space for the BIOS | |
143 | * popup and for the GTT. | |
144 | */ | |
145 | int gtt_entries; /* i830+ */ | |
2162e6a2 DA |
146 | union { |
147 | void __iomem *i9xx_flush_page; | |
148 | void *i8xx_flush_page; | |
149 | }; | |
150 | struct page *i8xx_page; | |
6c00a61e | 151 | struct resource ifp_resource; |
4d64dd9e | 152 | int resource_valid; |
c4ca8817 | 153 | } intel_private; |
1da177e4 LT |
154 | |
155 | static int intel_i810_fetch_size(void) | |
156 | { | |
157 | u32 smram_miscc; | |
158 | struct aper_size_info_fixed *values; | |
159 | ||
160 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
161 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
162 | ||
163 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
164 | printk(KERN_WARNING PFX "i810 is disabled\n"); | |
165 | return 0; | |
166 | } | |
167 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
168 | agp_bridge->previous_size = | |
169 | agp_bridge->current_size = (void *) (values + 1); | |
170 | agp_bridge->aperture_size_idx = 1; | |
171 | return values[1].size; | |
172 | } else { | |
173 | agp_bridge->previous_size = | |
174 | agp_bridge->current_size = (void *) (values); | |
175 | agp_bridge->aperture_size_idx = 0; | |
176 | return values[0].size; | |
177 | } | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static int intel_i810_configure(void) | |
183 | { | |
184 | struct aper_size_info_fixed *current_size; | |
185 | u32 temp; | |
186 | int i; | |
187 | ||
188 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
189 | ||
c4ca8817 WZ |
190 | if (!intel_private.registers) { |
191 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
192 | temp &= 0xfff80000; |
193 | ||
c4ca8817 WZ |
194 | intel_private.registers = ioremap(temp, 128 * 4096); |
195 | if (!intel_private.registers) { | |
e4ac5e4f DJ |
196 | printk(KERN_ERR PFX "Unable to remap memory.\n"); |
197 | return -ENOMEM; | |
198 | } | |
1da177e4 LT |
199 | } |
200 | ||
c4ca8817 | 201 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
202 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
203 | /* This will need to be dynamically assigned */ | |
204 | printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); | |
c4ca8817 | 205 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 206 | } |
c4ca8817 | 207 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 208 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
209 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
210 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
211 | |
212 | if (agp_bridge->driver->needs_scratch_page) { | |
213 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 WZ |
214 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
215 | readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ | |
1da177e4 LT |
216 | } |
217 | } | |
218 | global_cache_flush(); | |
219 | return 0; | |
220 | } | |
221 | ||
222 | static void intel_i810_cleanup(void) | |
223 | { | |
c4ca8817 WZ |
224 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
225 | readl(intel_private.registers); /* PCI Posting. */ | |
226 | iounmap(intel_private.registers); | |
1da177e4 LT |
227 | } |
228 | ||
229 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
230 | { | |
231 | return; | |
232 | } | |
233 | ||
234 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
235 | { | |
236 | return; | |
237 | } | |
238 | ||
239 | /* Exists to support ARGB cursors */ | |
240 | static void *i8xx_alloc_pages(void) | |
241 | { | |
f011ae74 | 242 | struct page *page; |
1da177e4 | 243 | |
66c669ba | 244 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
245 | if (page == NULL) |
246 | return NULL; | |
247 | ||
6d238cc4 AV |
248 | if (set_pages_uc(page, 4) < 0) { |
249 | set_pages_wb(page, 4); | |
89cf7ccc | 250 | __free_pages(page, 2); |
1da177e4 LT |
251 | return NULL; |
252 | } | |
1da177e4 | 253 | get_page(page); |
1da177e4 LT |
254 | atomic_inc(&agp_bridge->current_memory_agp); |
255 | return page_address(page); | |
256 | } | |
257 | ||
258 | static void i8xx_destroy_pages(void *addr) | |
259 | { | |
260 | struct page *page; | |
261 | ||
262 | if (addr == NULL) | |
263 | return; | |
264 | ||
265 | page = virt_to_page(addr); | |
6d238cc4 | 266 | set_pages_wb(page, 4); |
1da177e4 | 267 | put_page(page); |
89cf7ccc | 268 | __free_pages(page, 2); |
1da177e4 LT |
269 | atomic_dec(&agp_bridge->current_memory_agp); |
270 | } | |
271 | ||
a030ce44 TH |
272 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
273 | int type) | |
274 | { | |
275 | if (type < AGP_USER_TYPES) | |
276 | return type; | |
277 | else if (type == AGP_USER_CACHED_MEMORY) | |
278 | return INTEL_AGP_CACHED_MEMORY; | |
279 | else | |
280 | return 0; | |
281 | } | |
282 | ||
1da177e4 LT |
283 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
284 | int type) | |
285 | { | |
286 | int i, j, num_entries; | |
287 | void *temp; | |
a030ce44 TH |
288 | int ret = -EINVAL; |
289 | int mask_type; | |
1da177e4 | 290 | |
5aa80c72 | 291 | if (mem->page_count == 0) |
a030ce44 | 292 | goto out; |
5aa80c72 | 293 | |
1da177e4 LT |
294 | temp = agp_bridge->current_size; |
295 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
296 | ||
6a92a4e0 | 297 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 298 | goto out_err; |
6a92a4e0 | 299 | |
1da177e4 | 300 | |
a030ce44 TH |
301 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
302 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
303 | ret = -EBUSY; | |
304 | goto out_err; | |
1da177e4 | 305 | } |
1da177e4 LT |
306 | } |
307 | ||
a030ce44 TH |
308 | if (type != mem->type) |
309 | goto out_err; | |
5aa80c72 | 310 | |
a030ce44 TH |
311 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
312 | ||
313 | switch (mask_type) { | |
314 | case AGP_DCACHE_MEMORY: | |
315 | if (!mem->is_flushed) | |
316 | global_cache_flush(); | |
317 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
318 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 319 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 320 | } |
c4ca8817 | 321 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
322 | break; |
323 | case AGP_PHYS_MEMORY: | |
324 | case AGP_NORMAL_MEMORY: | |
325 | if (!mem->is_flushed) | |
326 | global_cache_flush(); | |
327 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
328 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
329 | mem->memory[i], | |
330 | mask_type), | |
c4ca8817 | 331 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 332 | } |
c4ca8817 | 333 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
334 | break; |
335 | default: | |
336 | goto out_err; | |
1da177e4 | 337 | } |
1da177e4 LT |
338 | |
339 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
340 | out: |
341 | ret = 0; | |
342 | out_err: | |
9516b030 | 343 | mem->is_flushed = true; |
a030ce44 | 344 | return ret; |
1da177e4 LT |
345 | } |
346 | ||
347 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
348 | int type) | |
349 | { | |
350 | int i; | |
351 | ||
5aa80c72 TH |
352 | if (mem->page_count == 0) |
353 | return 0; | |
354 | ||
1da177e4 | 355 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 356 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 357 | } |
c4ca8817 | 358 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 359 | |
1da177e4 LT |
360 | agp_bridge->driver->tlb_flush(mem); |
361 | return 0; | |
362 | } | |
363 | ||
364 | /* | |
365 | * The i810/i830 requires a physical address to program its mouse | |
366 | * pointer into hardware. | |
367 | * However the Xserver still writes to it through the agp aperture. | |
368 | */ | |
369 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
370 | { | |
371 | struct agp_memory *new; | |
372 | void *addr; | |
373 | ||
1da177e4 LT |
374 | switch (pg_count) { |
375 | case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); | |
376 | break; | |
377 | case 4: | |
378 | /* kludge to get 4 physical pages for ARGB cursor */ | |
379 | addr = i8xx_alloc_pages(); | |
380 | break; | |
381 | default: | |
382 | return NULL; | |
383 | } | |
384 | ||
385 | if (addr == NULL) | |
386 | return NULL; | |
387 | ||
388 | new = agp_create_memory(pg_count); | |
389 | if (new == NULL) | |
390 | return NULL; | |
391 | ||
07eee78e | 392 | new->memory[0] = virt_to_gart(addr); |
1da177e4 LT |
393 | if (pg_count == 4) { |
394 | /* kludge to get 4 physical pages for ARGB cursor */ | |
395 | new->memory[1] = new->memory[0] + PAGE_SIZE; | |
396 | new->memory[2] = new->memory[1] + PAGE_SIZE; | |
397 | new->memory[3] = new->memory[2] + PAGE_SIZE; | |
398 | } | |
399 | new->page_count = pg_count; | |
400 | new->num_scratch_pages = pg_count; | |
401 | new->type = AGP_PHYS_MEMORY; | |
402 | new->physical = new->memory[0]; | |
403 | return new; | |
404 | } | |
405 | ||
406 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
407 | { | |
408 | struct agp_memory *new; | |
409 | ||
410 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 411 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
412 | return NULL; |
413 | ||
414 | new = agp_create_memory(1); | |
415 | if (new == NULL) | |
416 | return NULL; | |
417 | ||
418 | new->type = AGP_DCACHE_MEMORY; | |
419 | new->page_count = pg_count; | |
420 | new->num_scratch_pages = 0; | |
a030ce44 | 421 | agp_free_page_array(new); |
1da177e4 LT |
422 | return new; |
423 | } | |
424 | if (type == AGP_PHYS_MEMORY) | |
425 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
426 | return NULL; |
427 | } | |
428 | ||
429 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
430 | { | |
431 | agp_free_key(curr->key); | |
6a92a4e0 | 432 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 433 | if (curr->page_count == 4) |
07eee78e | 434 | i8xx_destroy_pages(gart_to_virt(curr->memory[0])); |
88d51967 | 435 | else { |
da503fa6 JB |
436 | void *va = gart_to_virt(curr->memory[0]); |
437 | ||
438 | agp_bridge->driver->agp_destroy_page(va, | |
a2721e99 | 439 | AGP_PAGE_DESTROY_UNMAP); |
da503fa6 | 440 | agp_bridge->driver->agp_destroy_page(va, |
a2721e99 | 441 | AGP_PAGE_DESTROY_FREE); |
88d51967 | 442 | } |
a030ce44 | 443 | agp_free_page_array(curr); |
1da177e4 LT |
444 | } |
445 | kfree(curr); | |
446 | } | |
447 | ||
448 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
449 | unsigned long addr, int type) | |
450 | { | |
451 | /* Type checking must be done elsewhere */ | |
452 | return addr | bridge->driver->masks[type].mask; | |
453 | } | |
454 | ||
455 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
456 | { | |
457 | {128, 32768, 5}, | |
458 | /* The 64M mode still requires a 128k gatt */ | |
459 | {64, 16384, 5}, | |
460 | {256, 65536, 6}, | |
65c25aad | 461 | {512, 131072, 7}, |
1da177e4 LT |
462 | }; |
463 | ||
1da177e4 LT |
464 | static void intel_i830_init_gtt_entries(void) |
465 | { | |
466 | u16 gmch_ctrl; | |
467 | int gtt_entries; | |
468 | u8 rdct; | |
469 | int local = 0; | |
470 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 471 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 | 472 | |
f011ae74 | 473 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 474 | |
c41e0deb EA |
475 | if (IS_I965) { |
476 | u32 pgetbl_ctl; | |
c4ca8817 | 477 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 478 | |
c41e0deb EA |
479 | /* The 965 has a field telling us the size of the GTT, |
480 | * which may be larger than what is necessary to map the | |
481 | * aperture. | |
482 | */ | |
483 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
484 | case I965_PGETBL_SIZE_128KB: | |
485 | size = 128; | |
486 | break; | |
487 | case I965_PGETBL_SIZE_256KB: | |
488 | size = 256; | |
489 | break; | |
490 | case I965_PGETBL_SIZE_512KB: | |
491 | size = 512; | |
492 | break; | |
4e8b6e25 ZW |
493 | case I965_PGETBL_SIZE_1MB: |
494 | size = 1024; | |
495 | break; | |
496 | case I965_PGETBL_SIZE_2MB: | |
497 | size = 2048; | |
498 | break; | |
499 | case I965_PGETBL_SIZE_1_5MB: | |
500 | size = 1024 + 512; | |
501 | break; | |
c41e0deb EA |
502 | default: |
503 | printk(KERN_INFO PFX "Unknown page table size, " | |
504 | "assuming 512KB\n"); | |
505 | size = 512; | |
506 | } | |
507 | size += 4; /* add in BIOS popup space */ | |
874808c6 WZ |
508 | } else if (IS_G33) { |
509 | /* G33's GTT size defined in gmch_ctrl */ | |
510 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
511 | case G33_PGETBL_SIZE_1M: | |
512 | size = 1024; | |
513 | break; | |
514 | case G33_PGETBL_SIZE_2M: | |
515 | size = 2048; | |
516 | break; | |
517 | default: | |
518 | printk(KERN_INFO PFX "Unknown page table size 0x%x, " | |
519 | "assuming 512KB\n", | |
520 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); | |
521 | size = 512; | |
522 | } | |
523 | size += 4; | |
25ce77ab ZW |
524 | } else if (IS_G4X) { |
525 | /* On 4 series hardware, GTT stolen is separate from graphics | |
526 | * stolen, ignore it in stolen gtt entries counting */ | |
527 | size = 0; | |
c41e0deb EA |
528 | } else { |
529 | /* On previous hardware, the GTT size was just what was | |
530 | * required to map the aperture. | |
531 | */ | |
532 | size = agp_bridge->driver->fetch_size() + 4; | |
533 | } | |
1da177e4 LT |
534 | |
535 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
536 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
537 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
538 | case I830_GMCH_GMS_STOLEN_512: | |
539 | gtt_entries = KB(512) - KB(size); | |
540 | break; | |
541 | case I830_GMCH_GMS_STOLEN_1024: | |
542 | gtt_entries = MB(1) - KB(size); | |
543 | break; | |
544 | case I830_GMCH_GMS_STOLEN_8192: | |
545 | gtt_entries = MB(8) - KB(size); | |
546 | break; | |
547 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 548 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
549 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
550 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
551 | local = 1; | |
552 | break; | |
553 | default: | |
554 | gtt_entries = 0; | |
555 | break; | |
556 | } | |
557 | } else { | |
e67aa27a | 558 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
559 | case I855_GMCH_GMS_STOLEN_1M: |
560 | gtt_entries = MB(1) - KB(size); | |
561 | break; | |
562 | case I855_GMCH_GMS_STOLEN_4M: | |
563 | gtt_entries = MB(4) - KB(size); | |
564 | break; | |
565 | case I855_GMCH_GMS_STOLEN_8M: | |
566 | gtt_entries = MB(8) - KB(size); | |
567 | break; | |
568 | case I855_GMCH_GMS_STOLEN_16M: | |
569 | gtt_entries = MB(16) - KB(size); | |
570 | break; | |
571 | case I855_GMCH_GMS_STOLEN_32M: | |
572 | gtt_entries = MB(32) - KB(size); | |
573 | break; | |
574 | case I915_GMCH_GMS_STOLEN_48M: | |
575 | /* Check it's really I915G */ | |
25ce77ab | 576 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
577 | gtt_entries = MB(48) - KB(size); |
578 | else | |
579 | gtt_entries = 0; | |
580 | break; | |
581 | case I915_GMCH_GMS_STOLEN_64M: | |
582 | /* Check it's really I915G */ | |
25ce77ab | 583 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
584 | gtt_entries = MB(64) - KB(size); |
585 | else | |
586 | gtt_entries = 0; | |
874808c6 WZ |
587 | break; |
588 | case G33_GMCH_GMS_STOLEN_128M: | |
25ce77ab | 589 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
590 | gtt_entries = MB(128) - KB(size); |
591 | else | |
592 | gtt_entries = 0; | |
593 | break; | |
594 | case G33_GMCH_GMS_STOLEN_256M: | |
25ce77ab | 595 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
596 | gtt_entries = MB(256) - KB(size); |
597 | else | |
598 | gtt_entries = 0; | |
599 | break; | |
25ce77ab ZW |
600 | case INTEL_GMCH_GMS_STOLEN_96M: |
601 | if (IS_I965 || IS_G4X) | |
602 | gtt_entries = MB(96) - KB(size); | |
603 | else | |
604 | gtt_entries = 0; | |
605 | break; | |
606 | case INTEL_GMCH_GMS_STOLEN_160M: | |
607 | if (IS_I965 || IS_G4X) | |
608 | gtt_entries = MB(160) - KB(size); | |
609 | else | |
610 | gtt_entries = 0; | |
611 | break; | |
612 | case INTEL_GMCH_GMS_STOLEN_224M: | |
613 | if (IS_I965 || IS_G4X) | |
614 | gtt_entries = MB(224) - KB(size); | |
615 | else | |
616 | gtt_entries = 0; | |
617 | break; | |
618 | case INTEL_GMCH_GMS_STOLEN_352M: | |
619 | if (IS_I965 || IS_G4X) | |
620 | gtt_entries = MB(352) - KB(size); | |
621 | else | |
622 | gtt_entries = 0; | |
623 | break; | |
1da177e4 LT |
624 | default: |
625 | gtt_entries = 0; | |
626 | break; | |
627 | } | |
628 | } | |
629 | if (gtt_entries > 0) | |
630 | printk(KERN_INFO PFX "Detected %dK %s memory.\n", | |
631 | gtt_entries / KB(1), local ? "local" : "stolen"); | |
632 | else | |
633 | printk(KERN_INFO PFX | |
634 | "No pre-allocated video memory detected.\n"); | |
635 | gtt_entries /= KB(4); | |
636 | ||
c4ca8817 | 637 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
638 | } |
639 | ||
2162e6a2 DA |
640 | static void intel_i830_fini_flush(void) |
641 | { | |
642 | kunmap(intel_private.i8xx_page); | |
643 | intel_private.i8xx_flush_page = NULL; | |
644 | unmap_page_from_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
645 | |
646 | __free_page(intel_private.i8xx_page); | |
4d64dd9e | 647 | intel_private.i8xx_page = NULL; |
2162e6a2 DA |
648 | } |
649 | ||
650 | static void intel_i830_setup_flush(void) | |
651 | { | |
4d64dd9e DA |
652 | /* return if we've already set the flush mechanism up */ |
653 | if (intel_private.i8xx_page) | |
654 | return; | |
2162e6a2 DA |
655 | |
656 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
f011ae74 | 657 | if (!intel_private.i8xx_page) |
2162e6a2 | 658 | return; |
2162e6a2 DA |
659 | |
660 | /* make page uncached */ | |
661 | map_page_into_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
662 | |
663 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); | |
664 | if (!intel_private.i8xx_flush_page) | |
665 | intel_i830_fini_flush(); | |
666 | } | |
667 | ||
668 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) | |
669 | { | |
670 | unsigned int *pg = intel_private.i8xx_flush_page; | |
671 | int i; | |
672 | ||
f011ae74 | 673 | for (i = 0; i < 256; i += 2) |
2162e6a2 | 674 | *(pg + i) = i; |
f011ae74 | 675 | |
2162e6a2 DA |
676 | wmb(); |
677 | } | |
678 | ||
1da177e4 LT |
679 | /* The intel i830 automatically initializes the agp aperture during POST. |
680 | * Use the memory already set aside for in the GTT. | |
681 | */ | |
682 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
683 | { | |
684 | int page_order; | |
685 | struct aper_size_info_fixed *size; | |
686 | int num_entries; | |
687 | u32 temp; | |
688 | ||
689 | size = agp_bridge->current_size; | |
690 | page_order = size->page_order; | |
691 | num_entries = size->num_entries; | |
692 | agp_bridge->gatt_table_real = NULL; | |
693 | ||
f011ae74 | 694 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
1da177e4 LT |
695 | temp &= 0xfff80000; |
696 | ||
f011ae74 | 697 | intel_private.registers = ioremap(temp, 128 * 4096); |
c4ca8817 | 698 | if (!intel_private.registers) |
1da177e4 LT |
699 | return -ENOMEM; |
700 | ||
c4ca8817 | 701 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
702 | global_cache_flush(); /* FIXME: ?? */ |
703 | ||
704 | /* we have to call this as early as possible after the MMIO base address is known */ | |
705 | intel_i830_init_gtt_entries(); | |
706 | ||
707 | agp_bridge->gatt_table = NULL; | |
708 | ||
709 | agp_bridge->gatt_bus_addr = temp; | |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | /* Return the gatt table to a sane state. Use the top of stolen | |
715 | * memory for the GTT. | |
716 | */ | |
717 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
718 | { | |
719 | return 0; | |
720 | } | |
721 | ||
722 | static int intel_i830_fetch_size(void) | |
723 | { | |
724 | u16 gmch_ctrl; | |
725 | struct aper_size_info_fixed *values; | |
726 | ||
727 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
728 | ||
729 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
730 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
731 | /* 855GM/852GM/865G has 128MB aperture size */ | |
732 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
733 | agp_bridge->aperture_size_idx = 0; | |
734 | return values[0].size; | |
735 | } | |
736 | ||
f011ae74 | 737 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 LT |
738 | |
739 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
740 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
741 | agp_bridge->aperture_size_idx = 0; | |
742 | return values[0].size; | |
743 | } else { | |
744 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
745 | agp_bridge->aperture_size_idx = 1; | |
746 | return values[1].size; | |
747 | } | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static int intel_i830_configure(void) | |
753 | { | |
754 | struct aper_size_info_fixed *current_size; | |
755 | u32 temp; | |
756 | u16 gmch_ctrl; | |
757 | int i; | |
758 | ||
759 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
760 | ||
f011ae74 | 761 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 LT |
762 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
763 | ||
f011ae74 | 764 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 765 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 766 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 767 | |
c4ca8817 WZ |
768 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
769 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
770 | |
771 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
772 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
773 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
774 | readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ | |
1da177e4 LT |
775 | } |
776 | } | |
777 | ||
778 | global_cache_flush(); | |
2162e6a2 DA |
779 | |
780 | intel_i830_setup_flush(); | |
1da177e4 LT |
781 | return 0; |
782 | } | |
783 | ||
784 | static void intel_i830_cleanup(void) | |
785 | { | |
c4ca8817 | 786 | iounmap(intel_private.registers); |
1da177e4 LT |
787 | } |
788 | ||
f011ae74 DA |
789 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
790 | int type) | |
1da177e4 | 791 | { |
f011ae74 | 792 | int i, j, num_entries; |
1da177e4 | 793 | void *temp; |
a030ce44 TH |
794 | int ret = -EINVAL; |
795 | int mask_type; | |
1da177e4 | 796 | |
5aa80c72 | 797 | if (mem->page_count == 0) |
a030ce44 | 798 | goto out; |
5aa80c72 | 799 | |
1da177e4 LT |
800 | temp = agp_bridge->current_size; |
801 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
802 | ||
c4ca8817 | 803 | if (pg_start < intel_private.gtt_entries) { |
f011ae74 DA |
804 | printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", |
805 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 806 | |
f011ae74 | 807 | printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n"); |
a030ce44 | 808 | goto out_err; |
1da177e4 LT |
809 | } |
810 | ||
811 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 812 | goto out_err; |
1da177e4 LT |
813 | |
814 | /* The i830 can't check the GTT for entries since its read only, | |
815 | * depend on the caller to make the correct offset decisions. | |
816 | */ | |
817 | ||
a030ce44 TH |
818 | if (type != mem->type) |
819 | goto out_err; | |
820 | ||
821 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 822 | |
a030ce44 TH |
823 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
824 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
825 | goto out_err; | |
826 | ||
827 | if (!mem->is_flushed) | |
5aa80c72 | 828 | global_cache_flush(); |
1da177e4 LT |
829 | |
830 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
831 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
a030ce44 | 832 | mem->memory[i], mask_type), |
c4ca8817 | 833 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 834 | } |
c4ca8817 | 835 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 836 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
837 | |
838 | out: | |
839 | ret = 0; | |
840 | out_err: | |
9516b030 | 841 | mem->is_flushed = true; |
a030ce44 | 842 | return ret; |
1da177e4 LT |
843 | } |
844 | ||
f011ae74 DA |
845 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, |
846 | int type) | |
1da177e4 LT |
847 | { |
848 | int i; | |
849 | ||
5aa80c72 TH |
850 | if (mem->page_count == 0) |
851 | return 0; | |
1da177e4 | 852 | |
c4ca8817 | 853 | if (pg_start < intel_private.gtt_entries) { |
f011ae74 | 854 | printk(KERN_INFO PFX "Trying to disable local/stolen memory\n"); |
1da177e4 LT |
855 | return -EINVAL; |
856 | } | |
857 | ||
858 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 859 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 860 | } |
c4ca8817 | 861 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 862 | |
1da177e4 LT |
863 | agp_bridge->driver->tlb_flush(mem); |
864 | return 0; | |
865 | } | |
866 | ||
f011ae74 | 867 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) |
1da177e4 LT |
868 | { |
869 | if (type == AGP_PHYS_MEMORY) | |
870 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
871 | /* always return NULL for other allocation types for now */ |
872 | return NULL; | |
873 | } | |
874 | ||
6c00a61e DA |
875 | static int intel_alloc_chipset_flush_resource(void) |
876 | { | |
877 | int ret; | |
878 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
879 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
880 | pcibios_align_resource, agp_bridge->dev); | |
6c00a61e | 881 | |
2162e6a2 | 882 | return ret; |
6c00a61e DA |
883 | } |
884 | ||
885 | static void intel_i915_setup_chipset_flush(void) | |
886 | { | |
887 | int ret; | |
888 | u32 temp; | |
889 | ||
890 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
891 | if (!(temp & 0x1)) { | |
892 | intel_alloc_chipset_flush_resource(); | |
4d64dd9e | 893 | intel_private.resource_valid = 1; |
6c00a61e DA |
894 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
895 | } else { | |
896 | temp &= ~1; | |
897 | ||
4d64dd9e | 898 | intel_private.resource_valid = 1; |
6c00a61e DA |
899 | intel_private.ifp_resource.start = temp; |
900 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
901 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
902 | /* some BIOSes reserve this area in a pnp some don't */ |
903 | if (ret) | |
904 | intel_private.resource_valid = 0; | |
6c00a61e DA |
905 | } |
906 | } | |
907 | ||
908 | static void intel_i965_g33_setup_chipset_flush(void) | |
909 | { | |
910 | u32 temp_hi, temp_lo; | |
911 | int ret; | |
912 | ||
913 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
914 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
915 | ||
916 | if (!(temp_lo & 0x1)) { | |
917 | ||
918 | intel_alloc_chipset_flush_resource(); | |
919 | ||
4d64dd9e | 920 | intel_private.resource_valid = 1; |
1fa4db7d AM |
921 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, |
922 | upper_32_bits(intel_private.ifp_resource.start)); | |
6c00a61e | 923 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
6c00a61e DA |
924 | } else { |
925 | u64 l64; | |
f011ae74 | 926 | |
6c00a61e DA |
927 | temp_lo &= ~0x1; |
928 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
929 | ||
4d64dd9e | 930 | intel_private.resource_valid = 1; |
6c00a61e DA |
931 | intel_private.ifp_resource.start = l64; |
932 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
933 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
934 | /* some BIOSes reserve this area in a pnp some don't */ |
935 | if (ret) | |
936 | intel_private.resource_valid = 0; | |
6c00a61e DA |
937 | } |
938 | } | |
939 | ||
2162e6a2 DA |
940 | static void intel_i9xx_setup_flush(void) |
941 | { | |
4d64dd9e DA |
942 | /* return if already configured */ |
943 | if (intel_private.ifp_resource.start) | |
944 | return; | |
2162e6a2 | 945 | |
4d64dd9e | 946 | /* setup a resource for this object */ |
2162e6a2 DA |
947 | intel_private.ifp_resource.name = "Intel Flush Page"; |
948 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
949 | ||
950 | /* Setup chipset flush for 915 */ | |
7d15ddf7 | 951 | if (IS_I965 || IS_G33 || IS_G4X) { |
2162e6a2 DA |
952 | intel_i965_g33_setup_chipset_flush(); |
953 | } else { | |
954 | intel_i915_setup_chipset_flush(); | |
955 | } | |
956 | ||
957 | if (intel_private.ifp_resource.start) { | |
958 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
959 | if (!intel_private.i9xx_flush_page) | |
f011ae74 | 960 | printk(KERN_INFO "unable to ioremap flush page - no chipset flushing"); |
2162e6a2 DA |
961 | } |
962 | } | |
963 | ||
1da177e4 LT |
964 | static int intel_i915_configure(void) |
965 | { | |
966 | struct aper_size_info_fixed *current_size; | |
967 | u32 temp; | |
968 | u16 gmch_ctrl; | |
969 | int i; | |
970 | ||
971 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
972 | ||
c4ca8817 | 973 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
974 | |
975 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
976 | ||
f011ae74 | 977 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 978 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 979 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 980 | |
c4ca8817 WZ |
981 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
982 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
983 | |
984 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
985 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
986 | writel(agp_bridge->scratch_page, intel_private.gtt+i); | |
987 | readl(intel_private.gtt+i); /* PCI Posting. */ | |
1da177e4 LT |
988 | } |
989 | } | |
990 | ||
991 | global_cache_flush(); | |
6c00a61e | 992 | |
2162e6a2 | 993 | intel_i9xx_setup_flush(); |
f011ae74 | 994 | |
1da177e4 LT |
995 | return 0; |
996 | } | |
997 | ||
998 | static void intel_i915_cleanup(void) | |
999 | { | |
2162e6a2 DA |
1000 | if (intel_private.i9xx_flush_page) |
1001 | iounmap(intel_private.i9xx_flush_page); | |
4d64dd9e DA |
1002 | if (intel_private.resource_valid) |
1003 | release_resource(&intel_private.ifp_resource); | |
1004 | intel_private.ifp_resource.start = 0; | |
1005 | intel_private.resource_valid = 0; | |
c4ca8817 WZ |
1006 | iounmap(intel_private.gtt); |
1007 | iounmap(intel_private.registers); | |
1da177e4 LT |
1008 | } |
1009 | ||
6c00a61e DA |
1010 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
1011 | { | |
2162e6a2 DA |
1012 | if (intel_private.i9xx_flush_page) |
1013 | writel(1, intel_private.i9xx_flush_page); | |
6c00a61e DA |
1014 | } |
1015 | ||
f011ae74 DA |
1016 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, |
1017 | int type) | |
1da177e4 | 1018 | { |
f011ae74 | 1019 | int i, j, num_entries; |
1da177e4 | 1020 | void *temp; |
a030ce44 TH |
1021 | int ret = -EINVAL; |
1022 | int mask_type; | |
1da177e4 | 1023 | |
5aa80c72 | 1024 | if (mem->page_count == 0) |
a030ce44 | 1025 | goto out; |
5aa80c72 | 1026 | |
1da177e4 LT |
1027 | temp = agp_bridge->current_size; |
1028 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1029 | ||
c4ca8817 | 1030 | if (pg_start < intel_private.gtt_entries) { |
f011ae74 DA |
1031 | printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n", |
1032 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1033 | |
f011ae74 | 1034 | printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n"); |
a030ce44 | 1035 | goto out_err; |
1da177e4 LT |
1036 | } |
1037 | ||
1038 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1039 | goto out_err; |
1da177e4 | 1040 | |
a030ce44 | 1041 | /* The i915 can't check the GTT for entries since its read only, |
1da177e4 LT |
1042 | * depend on the caller to make the correct offset decisions. |
1043 | */ | |
1044 | ||
a030ce44 TH |
1045 | if (type != mem->type) |
1046 | goto out_err; | |
1047 | ||
1048 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1049 | |
a030ce44 TH |
1050 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1051 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1052 | goto out_err; | |
1053 | ||
1054 | if (!mem->is_flushed) | |
5aa80c72 | 1055 | global_cache_flush(); |
1da177e4 LT |
1056 | |
1057 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1058 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
c4ca8817 | 1059 | mem->memory[i], mask_type), intel_private.gtt+j); |
1da177e4 LT |
1060 | } |
1061 | ||
c4ca8817 | 1062 | readl(intel_private.gtt+j-1); |
1da177e4 | 1063 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1064 | |
1065 | out: | |
1066 | ret = 0; | |
1067 | out_err: | |
9516b030 | 1068 | mem->is_flushed = true; |
a030ce44 | 1069 | return ret; |
1da177e4 LT |
1070 | } |
1071 | ||
f011ae74 DA |
1072 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, |
1073 | int type) | |
1da177e4 LT |
1074 | { |
1075 | int i; | |
1076 | ||
5aa80c72 TH |
1077 | if (mem->page_count == 0) |
1078 | return 0; | |
1da177e4 | 1079 | |
c4ca8817 | 1080 | if (pg_start < intel_private.gtt_entries) { |
f011ae74 | 1081 | printk(KERN_INFO PFX "Trying to disable local/stolen memory\n"); |
1da177e4 LT |
1082 | return -EINVAL; |
1083 | } | |
1084 | ||
f011ae74 | 1085 | for (i = pg_start; i < (mem->page_count + pg_start); i++) |
c4ca8817 | 1086 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f011ae74 | 1087 | |
c4ca8817 | 1088 | readl(intel_private.gtt+i-1); |
1da177e4 | 1089 | |
1da177e4 LT |
1090 | agp_bridge->driver->tlb_flush(mem); |
1091 | return 0; | |
1092 | } | |
1093 | ||
c41e0deb EA |
1094 | /* Return the aperture size by just checking the resource length. The effect |
1095 | * described in the spec of the MSAC registers is just changing of the | |
1096 | * resource size. | |
1097 | */ | |
1098 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 1099 | { |
1eaf122c | 1100 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
1101 | int aper_size; /* size in megabytes */ |
1102 | int i; | |
1da177e4 | 1103 | |
c4ca8817 | 1104 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 1105 | |
c41e0deb EA |
1106 | for (i = 0; i < num_sizes; i++) { |
1107 | if (aper_size == intel_i830_sizes[i].size) { | |
1108 | agp_bridge->current_size = intel_i830_sizes + i; | |
1109 | agp_bridge->previous_size = agp_bridge->current_size; | |
1110 | return aper_size; | |
1111 | } | |
1112 | } | |
1da177e4 | 1113 | |
c41e0deb | 1114 | return 0; |
1da177e4 LT |
1115 | } |
1116 | ||
1117 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1118 | * Use the memory already set aside for in the GTT. | |
1119 | */ | |
1120 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1121 | { | |
1122 | int page_order; | |
1123 | struct aper_size_info_fixed *size; | |
1124 | int num_entries; | |
1125 | u32 temp, temp2; | |
4740622c | 1126 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1127 | |
1128 | size = agp_bridge->current_size; | |
1129 | page_order = size->page_order; | |
1130 | num_entries = size->num_entries; | |
1131 | agp_bridge->gatt_table_real = NULL; | |
1132 | ||
c4ca8817 | 1133 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
f011ae74 | 1134 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); |
1da177e4 | 1135 | |
4740622c ZW |
1136 | if (IS_G33) |
1137 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1138 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1139 | if (!intel_private.gtt) |
1da177e4 LT |
1140 | return -ENOMEM; |
1141 | ||
1142 | temp &= 0xfff80000; | |
1143 | ||
f011ae74 | 1144 | intel_private.registers = ioremap(temp, 128 * 4096); |
5bdbc7dc ST |
1145 | if (!intel_private.registers) { |
1146 | iounmap(intel_private.gtt); | |
1da177e4 | 1147 | return -ENOMEM; |
5bdbc7dc | 1148 | } |
1da177e4 | 1149 | |
c4ca8817 | 1150 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1151 | global_cache_flush(); /* FIXME: ? */ |
1152 | ||
1153 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1154 | intel_i830_init_gtt_entries(); | |
1155 | ||
1156 | agp_bridge->gatt_table = NULL; | |
1157 | ||
1158 | agp_bridge->gatt_bus_addr = temp; | |
1159 | ||
1160 | return 0; | |
1161 | } | |
7d915a38 LT |
1162 | |
1163 | /* | |
1164 | * The i965 supports 36-bit physical addresses, but to keep | |
1165 | * the format of the GTT the same, the bits that don't fit | |
1166 | * in a 32-bit word are shifted down to bits 4..7. | |
1167 | * | |
1168 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1169 | * is always zero on 32-bit architectures, so no need to make | |
1170 | * this conditional. | |
1171 | */ | |
1172 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
1173 | unsigned long addr, int type) | |
1174 | { | |
1175 | /* Shift high bits down */ | |
1176 | addr |= (addr >> 28) & 0xf0; | |
1177 | ||
1178 | /* Type checking must be done elsewhere */ | |
1179 | return addr | bridge->driver->masks[type].mask; | |
1180 | } | |
1181 | ||
25ce77ab ZW |
1182 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1183 | { | |
1184 | switch (agp_bridge->dev->device) { | |
99d32bd5 | 1185 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
25ce77ab ZW |
1186 | case PCI_DEVICE_ID_INTEL_IGD_E_HB: |
1187 | case PCI_DEVICE_ID_INTEL_Q45_HB: | |
1188 | case PCI_DEVICE_ID_INTEL_G45_HB: | |
1189 | *gtt_offset = *gtt_size = MB(2); | |
1190 | break; | |
1191 | default: | |
1192 | *gtt_offset = *gtt_size = KB(512); | |
1193 | } | |
1194 | } | |
1195 | ||
65c25aad | 1196 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1197 | * Use the memory already set aside for in the GTT. |
1198 | */ | |
65c25aad EA |
1199 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1200 | { | |
62c96b9d DA |
1201 | int page_order; |
1202 | struct aper_size_info_fixed *size; | |
1203 | int num_entries; | |
1204 | u32 temp; | |
1205 | int gtt_offset, gtt_size; | |
65c25aad | 1206 | |
62c96b9d DA |
1207 | size = agp_bridge->current_size; |
1208 | page_order = size->page_order; | |
1209 | num_entries = size->num_entries; | |
1210 | agp_bridge->gatt_table_real = NULL; | |
65c25aad | 1211 | |
62c96b9d | 1212 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad | 1213 | |
62c96b9d | 1214 | temp &= 0xfff00000; |
65c25aad | 1215 | |
25ce77ab | 1216 | intel_i965_get_gtt_range(>t_offset, >t_size); |
4e8b6e25 | 1217 | |
62c96b9d | 1218 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
65c25aad | 1219 | |
62c96b9d DA |
1220 | if (!intel_private.gtt) |
1221 | return -ENOMEM; | |
65c25aad | 1222 | |
62c96b9d DA |
1223 | intel_private.registers = ioremap(temp, 128 * 4096); |
1224 | if (!intel_private.registers) { | |
5bdbc7dc ST |
1225 | iounmap(intel_private.gtt); |
1226 | return -ENOMEM; | |
1227 | } | |
65c25aad | 1228 | |
62c96b9d DA |
1229 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1230 | global_cache_flush(); /* FIXME: ? */ | |
65c25aad | 1231 | |
62c96b9d DA |
1232 | /* we have to call this as early as possible after the MMIO base address is known */ |
1233 | intel_i830_init_gtt_entries(); | |
65c25aad | 1234 | |
62c96b9d | 1235 | agp_bridge->gatt_table = NULL; |
65c25aad | 1236 | |
62c96b9d | 1237 | agp_bridge->gatt_bus_addr = temp; |
65c25aad | 1238 | |
62c96b9d | 1239 | return 0; |
65c25aad EA |
1240 | } |
1241 | ||
1da177e4 LT |
1242 | |
1243 | static int intel_fetch_size(void) | |
1244 | { | |
1245 | int i; | |
1246 | u16 temp; | |
1247 | struct aper_size_info_16 *values; | |
1248 | ||
1249 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1250 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1251 | ||
1252 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1253 | if (temp == values[i].size_value) { | |
1254 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1255 | agp_bridge->aperture_size_idx = i; | |
1256 | return values[i].size; | |
1257 | } | |
1258 | } | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | static int __intel_8xx_fetch_size(u8 temp) | |
1264 | { | |
1265 | int i; | |
1266 | struct aper_size_info_8 *values; | |
1267 | ||
1268 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1269 | ||
1270 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1271 | if (temp == values[i].size_value) { | |
1272 | agp_bridge->previous_size = | |
1273 | agp_bridge->current_size = (void *) (values + i); | |
1274 | agp_bridge->aperture_size_idx = i; | |
1275 | return values[i].size; | |
1276 | } | |
1277 | } | |
1278 | return 0; | |
1279 | } | |
1280 | ||
1281 | static int intel_8xx_fetch_size(void) | |
1282 | { | |
1283 | u8 temp; | |
1284 | ||
1285 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1286 | return __intel_8xx_fetch_size(temp); | |
1287 | } | |
1288 | ||
1289 | static int intel_815_fetch_size(void) | |
1290 | { | |
1291 | u8 temp; | |
1292 | ||
1293 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1294 | * one non-reserved bit, so mask the others out ... */ | |
1295 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1296 | temp &= (1 << 3); | |
1297 | ||
1298 | return __intel_8xx_fetch_size(temp); | |
1299 | } | |
1300 | ||
1301 | static void intel_tlbflush(struct agp_memory *mem) | |
1302 | { | |
1303 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1304 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1305 | } | |
1306 | ||
1307 | ||
1308 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1309 | { | |
1310 | u32 temp; | |
1311 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1312 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1313 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1314 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1315 | } | |
1316 | ||
1317 | ||
1318 | static void intel_cleanup(void) | |
1319 | { | |
1320 | u16 temp; | |
1321 | struct aper_size_info_16 *previous_size; | |
1322 | ||
1323 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1324 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1325 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1326 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1327 | } | |
1328 | ||
1329 | ||
1330 | static void intel_8xx_cleanup(void) | |
1331 | { | |
1332 | u16 temp; | |
1333 | struct aper_size_info_8 *previous_size; | |
1334 | ||
1335 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1336 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1337 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1338 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1339 | } | |
1340 | ||
1341 | ||
1342 | static int intel_configure(void) | |
1343 | { | |
1344 | u32 temp; | |
1345 | u16 temp2; | |
1346 | struct aper_size_info_16 *current_size; | |
1347 | ||
1348 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1349 | ||
1350 | /* aperture size */ | |
1351 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1352 | ||
1353 | /* address to map to */ | |
1354 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1355 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1356 | ||
1357 | /* attbase - aperture base */ | |
1358 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1359 | ||
1360 | /* agpctrl */ | |
1361 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1362 | ||
1363 | /* paccfg/nbxcfg */ | |
1364 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1365 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1366 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1367 | /* clear any possible error conditions */ | |
1368 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | static int intel_815_configure(void) | |
1373 | { | |
1374 | u32 temp, addr; | |
1375 | u8 temp2; | |
1376 | struct aper_size_info_8 *current_size; | |
1377 | ||
1378 | /* attbase - aperture base */ | |
1379 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1380 | * ATTBASE register are reserved -> try not to write them */ | |
1381 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
f011ae74 | 1382 | printk(KERN_EMERG PFX "gatt bus addr too high"); |
1da177e4 LT |
1383 | return -EINVAL; |
1384 | } | |
1385 | ||
1386 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1387 | ||
1388 | /* aperture size */ | |
1389 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1390 | current_size->size_value); | |
1391 | ||
1392 | /* address to map to */ | |
1393 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1394 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1395 | ||
1396 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1397 | addr &= INTEL_815_ATTBASE_MASK; | |
1398 | addr |= agp_bridge->gatt_bus_addr; | |
1399 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1400 | ||
1401 | /* agpctrl */ | |
1402 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1403 | ||
1404 | /* apcont */ | |
1405 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1406 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1407 | ||
1408 | /* clear any possible error conditions */ | |
1409 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1414 | { | |
1415 | return; | |
1416 | } | |
1417 | ||
1418 | static void intel_820_cleanup(void) | |
1419 | { | |
1420 | u8 temp; | |
1421 | struct aper_size_info_8 *previous_size; | |
1422 | ||
1423 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1424 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1425 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1426 | temp & ~(1 << 1)); | |
1427 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1428 | previous_size->size_value); | |
1429 | } | |
1430 | ||
1431 | ||
1432 | static int intel_820_configure(void) | |
1433 | { | |
1434 | u32 temp; | |
1435 | u8 temp2; | |
1436 | struct aper_size_info_8 *current_size; | |
1437 | ||
1438 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1439 | ||
1440 | /* aperture size */ | |
1441 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1442 | ||
1443 | /* address to map to */ | |
1444 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1445 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1446 | ||
1447 | /* attbase - aperture base */ | |
1448 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1449 | ||
1450 | /* agpctrl */ | |
1451 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1452 | ||
1453 | /* global enable aperture access */ | |
1454 | /* This flag is not accessed through MCHCFG register as in */ | |
1455 | /* i850 chipset. */ | |
1456 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1457 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1458 | /* clear any possible AGP-related error conditions */ | |
1459 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1460 | return 0; | |
1461 | } | |
1462 | ||
1463 | static int intel_840_configure(void) | |
1464 | { | |
1465 | u32 temp; | |
1466 | u16 temp2; | |
1467 | struct aper_size_info_8 *current_size; | |
1468 | ||
1469 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1470 | ||
1471 | /* aperture size */ | |
1472 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1473 | ||
1474 | /* address to map to */ | |
1475 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1476 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1477 | ||
1478 | /* attbase - aperture base */ | |
1479 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1480 | ||
1481 | /* agpctrl */ | |
1482 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1483 | ||
1484 | /* mcgcfg */ | |
1485 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1486 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1487 | /* clear any possible error conditions */ | |
1488 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1489 | return 0; | |
1490 | } | |
1491 | ||
1492 | static int intel_845_configure(void) | |
1493 | { | |
1494 | u32 temp; | |
1495 | u8 temp2; | |
1496 | struct aper_size_info_8 *current_size; | |
1497 | ||
1498 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1499 | ||
1500 | /* aperture size */ | |
1501 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1502 | ||
b0825488 MG |
1503 | if (agp_bridge->apbase_config != 0) { |
1504 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1505 | agp_bridge->apbase_config); | |
1506 | } else { | |
1507 | /* address to map to */ | |
1508 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1509 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1510 | agp_bridge->apbase_config = temp; | |
1511 | } | |
1da177e4 LT |
1512 | |
1513 | /* attbase - aperture base */ | |
1514 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1515 | ||
1516 | /* agpctrl */ | |
1517 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1518 | ||
1519 | /* agpm */ | |
1520 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1521 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1522 | /* clear any possible error conditions */ | |
1523 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
2162e6a2 DA |
1524 | |
1525 | intel_i830_setup_flush(); | |
1da177e4 LT |
1526 | return 0; |
1527 | } | |
1528 | ||
1529 | static int intel_850_configure(void) | |
1530 | { | |
1531 | u32 temp; | |
1532 | u16 temp2; | |
1533 | struct aper_size_info_8 *current_size; | |
1534 | ||
1535 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1536 | ||
1537 | /* aperture size */ | |
1538 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1539 | ||
1540 | /* address to map to */ | |
1541 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1542 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1543 | ||
1544 | /* attbase - aperture base */ | |
1545 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1546 | ||
1547 | /* agpctrl */ | |
1548 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1549 | ||
1550 | /* mcgcfg */ | |
1551 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1552 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1553 | /* clear any possible AGP-related error conditions */ | |
1554 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | static int intel_860_configure(void) | |
1559 | { | |
1560 | u32 temp; | |
1561 | u16 temp2; | |
1562 | struct aper_size_info_8 *current_size; | |
1563 | ||
1564 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1565 | ||
1566 | /* aperture size */ | |
1567 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1568 | ||
1569 | /* address to map to */ | |
1570 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1571 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1572 | ||
1573 | /* attbase - aperture base */ | |
1574 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1575 | ||
1576 | /* agpctrl */ | |
1577 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1578 | ||
1579 | /* mcgcfg */ | |
1580 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1581 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1582 | /* clear any possible AGP-related error conditions */ | |
1583 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | static int intel_830mp_configure(void) | |
1588 | { | |
1589 | u32 temp; | |
1590 | u16 temp2; | |
1591 | struct aper_size_info_8 *current_size; | |
1592 | ||
1593 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1594 | ||
1595 | /* aperture size */ | |
1596 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1597 | ||
1598 | /* address to map to */ | |
1599 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1600 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1601 | ||
1602 | /* attbase - aperture base */ | |
1603 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1604 | ||
1605 | /* agpctrl */ | |
1606 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1607 | ||
1608 | /* gmch */ | |
1609 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1610 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1611 | /* clear any possible AGP-related error conditions */ | |
1612 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static int intel_7505_configure(void) | |
1617 | { | |
1618 | u32 temp; | |
1619 | u16 temp2; | |
1620 | struct aper_size_info_8 *current_size; | |
1621 | ||
1622 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1623 | ||
1624 | /* aperture size */ | |
1625 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1626 | ||
1627 | /* address to map to */ | |
1628 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1629 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1630 | ||
1631 | /* attbase - aperture base */ | |
1632 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1633 | ||
1634 | /* agpctrl */ | |
1635 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1636 | ||
1637 | /* mchcfg */ | |
1638 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1639 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
1644 | /* Setup function */ | |
e5524f35 | 1645 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1646 | { |
1647 | {.mask = 0x00000017, .type = 0} | |
1648 | }; | |
1649 | ||
e5524f35 | 1650 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1651 | { |
1652 | {64, 16384, 4, 0}, | |
1653 | {32, 8192, 3, 8}, | |
1654 | }; | |
1655 | ||
e5524f35 | 1656 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1657 | { |
1658 | {256, 65536, 6, 0}, | |
1659 | {128, 32768, 5, 32}, | |
1660 | {64, 16384, 4, 48}, | |
1661 | {32, 8192, 3, 56}, | |
1662 | {16, 4096, 2, 60}, | |
1663 | {8, 2048, 1, 62}, | |
1664 | {4, 1024, 0, 63} | |
1665 | }; | |
1666 | ||
e5524f35 | 1667 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1668 | { |
1669 | {256, 65536, 6, 0}, | |
1670 | {128, 32768, 5, 32}, | |
1671 | {64, 16384, 4, 48}, | |
1672 | {32, 8192, 3, 56}, | |
1673 | {16, 4096, 2, 60}, | |
1674 | {8, 2048, 1, 62}, | |
1675 | {4, 1024, 0, 63} | |
1676 | }; | |
1677 | ||
e5524f35 | 1678 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1679 | { |
1680 | {256, 65536, 6, 0}, | |
1681 | {128, 32768, 5, 32}, | |
1682 | {64, 16384, 4, 48}, | |
1683 | {32, 8192, 3, 56} | |
1684 | }; | |
1685 | ||
e5524f35 | 1686 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1687 | .owner = THIS_MODULE, |
1688 | .aperture_sizes = intel_generic_sizes, | |
1689 | .size_type = U16_APER_SIZE, | |
1690 | .num_aperture_sizes = 7, | |
1691 | .configure = intel_configure, | |
1692 | .fetch_size = intel_fetch_size, | |
1693 | .cleanup = intel_cleanup, | |
1694 | .tlb_flush = intel_tlbflush, | |
1695 | .mask_memory = agp_generic_mask_memory, | |
1696 | .masks = intel_generic_masks, | |
1697 | .agp_enable = agp_generic_enable, | |
1698 | .cache_flush = global_cache_flush, | |
1699 | .create_gatt_table = agp_generic_create_gatt_table, | |
1700 | .free_gatt_table = agp_generic_free_gatt_table, | |
1701 | .insert_memory = agp_generic_insert_memory, | |
1702 | .remove_memory = agp_generic_remove_memory, | |
1703 | .alloc_by_type = agp_generic_alloc_by_type, | |
1704 | .free_by_type = agp_generic_free_by_type, | |
1705 | .agp_alloc_page = agp_generic_alloc_page, | |
1706 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1707 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1708 | }; |
1709 | ||
e5524f35 | 1710 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1711 | .owner = THIS_MODULE, |
1712 | .aperture_sizes = intel_i810_sizes, | |
1713 | .size_type = FIXED_APER_SIZE, | |
1714 | .num_aperture_sizes = 2, | |
c7258012 | 1715 | .needs_scratch_page = true, |
1da177e4 LT |
1716 | .configure = intel_i810_configure, |
1717 | .fetch_size = intel_i810_fetch_size, | |
1718 | .cleanup = intel_i810_cleanup, | |
1719 | .tlb_flush = intel_i810_tlbflush, | |
1720 | .mask_memory = intel_i810_mask_memory, | |
1721 | .masks = intel_i810_masks, | |
1722 | .agp_enable = intel_i810_agp_enable, | |
1723 | .cache_flush = global_cache_flush, | |
1724 | .create_gatt_table = agp_generic_create_gatt_table, | |
1725 | .free_gatt_table = agp_generic_free_gatt_table, | |
1726 | .insert_memory = intel_i810_insert_entries, | |
1727 | .remove_memory = intel_i810_remove_entries, | |
1728 | .alloc_by_type = intel_i810_alloc_by_type, | |
1729 | .free_by_type = intel_i810_free_by_type, | |
1730 | .agp_alloc_page = agp_generic_alloc_page, | |
1731 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1732 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1733 | }; |
1734 | ||
e5524f35 | 1735 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
1736 | .owner = THIS_MODULE, |
1737 | .aperture_sizes = intel_815_sizes, | |
1738 | .size_type = U8_APER_SIZE, | |
1739 | .num_aperture_sizes = 2, | |
1740 | .configure = intel_815_configure, | |
1741 | .fetch_size = intel_815_fetch_size, | |
1742 | .cleanup = intel_8xx_cleanup, | |
1743 | .tlb_flush = intel_8xx_tlbflush, | |
1744 | .mask_memory = agp_generic_mask_memory, | |
1745 | .masks = intel_generic_masks, | |
1746 | .agp_enable = agp_generic_enable, | |
1747 | .cache_flush = global_cache_flush, | |
1748 | .create_gatt_table = agp_generic_create_gatt_table, | |
1749 | .free_gatt_table = agp_generic_free_gatt_table, | |
1750 | .insert_memory = agp_generic_insert_memory, | |
1751 | .remove_memory = agp_generic_remove_memory, | |
1752 | .alloc_by_type = agp_generic_alloc_by_type, | |
1753 | .free_by_type = agp_generic_free_by_type, | |
1754 | .agp_alloc_page = agp_generic_alloc_page, | |
1755 | .agp_destroy_page = agp_generic_destroy_page, | |
62c96b9d | 1756 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1757 | }; |
1758 | ||
e5524f35 | 1759 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
1760 | .owner = THIS_MODULE, |
1761 | .aperture_sizes = intel_i830_sizes, | |
1762 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1763 | .num_aperture_sizes = 4, |
c7258012 | 1764 | .needs_scratch_page = true, |
1da177e4 LT |
1765 | .configure = intel_i830_configure, |
1766 | .fetch_size = intel_i830_fetch_size, | |
1767 | .cleanup = intel_i830_cleanup, | |
1768 | .tlb_flush = intel_i810_tlbflush, | |
1769 | .mask_memory = intel_i810_mask_memory, | |
1770 | .masks = intel_i810_masks, | |
1771 | .agp_enable = intel_i810_agp_enable, | |
1772 | .cache_flush = global_cache_flush, | |
1773 | .create_gatt_table = intel_i830_create_gatt_table, | |
1774 | .free_gatt_table = intel_i830_free_gatt_table, | |
1775 | .insert_memory = intel_i830_insert_entries, | |
1776 | .remove_memory = intel_i830_remove_entries, | |
1777 | .alloc_by_type = intel_i830_alloc_by_type, | |
1778 | .free_by_type = intel_i810_free_by_type, | |
1779 | .agp_alloc_page = agp_generic_alloc_page, | |
1780 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1781 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
2162e6a2 | 1782 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
1783 | }; |
1784 | ||
e5524f35 | 1785 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
1786 | .owner = THIS_MODULE, |
1787 | .aperture_sizes = intel_8xx_sizes, | |
1788 | .size_type = U8_APER_SIZE, | |
1789 | .num_aperture_sizes = 7, | |
1790 | .configure = intel_820_configure, | |
1791 | .fetch_size = intel_8xx_fetch_size, | |
1792 | .cleanup = intel_820_cleanup, | |
1793 | .tlb_flush = intel_820_tlbflush, | |
1794 | .mask_memory = agp_generic_mask_memory, | |
1795 | .masks = intel_generic_masks, | |
1796 | .agp_enable = agp_generic_enable, | |
1797 | .cache_flush = global_cache_flush, | |
1798 | .create_gatt_table = agp_generic_create_gatt_table, | |
1799 | .free_gatt_table = agp_generic_free_gatt_table, | |
1800 | .insert_memory = agp_generic_insert_memory, | |
1801 | .remove_memory = agp_generic_remove_memory, | |
1802 | .alloc_by_type = agp_generic_alloc_by_type, | |
1803 | .free_by_type = agp_generic_free_by_type, | |
1804 | .agp_alloc_page = agp_generic_alloc_page, | |
1805 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1806 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1807 | }; |
1808 | ||
e5524f35 | 1809 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
1810 | .owner = THIS_MODULE, |
1811 | .aperture_sizes = intel_830mp_sizes, | |
1812 | .size_type = U8_APER_SIZE, | |
1813 | .num_aperture_sizes = 4, | |
1814 | .configure = intel_830mp_configure, | |
1815 | .fetch_size = intel_8xx_fetch_size, | |
1816 | .cleanup = intel_8xx_cleanup, | |
1817 | .tlb_flush = intel_8xx_tlbflush, | |
1818 | .mask_memory = agp_generic_mask_memory, | |
1819 | .masks = intel_generic_masks, | |
1820 | .agp_enable = agp_generic_enable, | |
1821 | .cache_flush = global_cache_flush, | |
1822 | .create_gatt_table = agp_generic_create_gatt_table, | |
1823 | .free_gatt_table = agp_generic_free_gatt_table, | |
1824 | .insert_memory = agp_generic_insert_memory, | |
1825 | .remove_memory = agp_generic_remove_memory, | |
1826 | .alloc_by_type = agp_generic_alloc_by_type, | |
1827 | .free_by_type = agp_generic_free_by_type, | |
1828 | .agp_alloc_page = agp_generic_alloc_page, | |
1829 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1830 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1831 | }; |
1832 | ||
e5524f35 | 1833 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
1834 | .owner = THIS_MODULE, |
1835 | .aperture_sizes = intel_8xx_sizes, | |
1836 | .size_type = U8_APER_SIZE, | |
1837 | .num_aperture_sizes = 7, | |
1838 | .configure = intel_840_configure, | |
1839 | .fetch_size = intel_8xx_fetch_size, | |
1840 | .cleanup = intel_8xx_cleanup, | |
1841 | .tlb_flush = intel_8xx_tlbflush, | |
1842 | .mask_memory = agp_generic_mask_memory, | |
1843 | .masks = intel_generic_masks, | |
1844 | .agp_enable = agp_generic_enable, | |
1845 | .cache_flush = global_cache_flush, | |
1846 | .create_gatt_table = agp_generic_create_gatt_table, | |
1847 | .free_gatt_table = agp_generic_free_gatt_table, | |
1848 | .insert_memory = agp_generic_insert_memory, | |
1849 | .remove_memory = agp_generic_remove_memory, | |
1850 | .alloc_by_type = agp_generic_alloc_by_type, | |
1851 | .free_by_type = agp_generic_free_by_type, | |
1852 | .agp_alloc_page = agp_generic_alloc_page, | |
1853 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1854 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1855 | }; |
1856 | ||
e5524f35 | 1857 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
1858 | .owner = THIS_MODULE, |
1859 | .aperture_sizes = intel_8xx_sizes, | |
1860 | .size_type = U8_APER_SIZE, | |
1861 | .num_aperture_sizes = 7, | |
1862 | .configure = intel_845_configure, | |
1863 | .fetch_size = intel_8xx_fetch_size, | |
1864 | .cleanup = intel_8xx_cleanup, | |
1865 | .tlb_flush = intel_8xx_tlbflush, | |
1866 | .mask_memory = agp_generic_mask_memory, | |
1867 | .masks = intel_generic_masks, | |
1868 | .agp_enable = agp_generic_enable, | |
1869 | .cache_flush = global_cache_flush, | |
1870 | .create_gatt_table = agp_generic_create_gatt_table, | |
1871 | .free_gatt_table = agp_generic_free_gatt_table, | |
1872 | .insert_memory = agp_generic_insert_memory, | |
1873 | .remove_memory = agp_generic_remove_memory, | |
1874 | .alloc_by_type = agp_generic_alloc_by_type, | |
1875 | .free_by_type = agp_generic_free_by_type, | |
1876 | .agp_alloc_page = agp_generic_alloc_page, | |
1877 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1878 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
2162e6a2 | 1879 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
1880 | }; |
1881 | ||
e5524f35 | 1882 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
1883 | .owner = THIS_MODULE, |
1884 | .aperture_sizes = intel_8xx_sizes, | |
1885 | .size_type = U8_APER_SIZE, | |
1886 | .num_aperture_sizes = 7, | |
1887 | .configure = intel_850_configure, | |
1888 | .fetch_size = intel_8xx_fetch_size, | |
1889 | .cleanup = intel_8xx_cleanup, | |
1890 | .tlb_flush = intel_8xx_tlbflush, | |
1891 | .mask_memory = agp_generic_mask_memory, | |
1892 | .masks = intel_generic_masks, | |
1893 | .agp_enable = agp_generic_enable, | |
1894 | .cache_flush = global_cache_flush, | |
1895 | .create_gatt_table = agp_generic_create_gatt_table, | |
1896 | .free_gatt_table = agp_generic_free_gatt_table, | |
1897 | .insert_memory = agp_generic_insert_memory, | |
1898 | .remove_memory = agp_generic_remove_memory, | |
1899 | .alloc_by_type = agp_generic_alloc_by_type, | |
1900 | .free_by_type = agp_generic_free_by_type, | |
1901 | .agp_alloc_page = agp_generic_alloc_page, | |
1902 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1903 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1904 | }; |
1905 | ||
e5524f35 | 1906 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
1907 | .owner = THIS_MODULE, |
1908 | .aperture_sizes = intel_8xx_sizes, | |
1909 | .size_type = U8_APER_SIZE, | |
1910 | .num_aperture_sizes = 7, | |
1911 | .configure = intel_860_configure, | |
1912 | .fetch_size = intel_8xx_fetch_size, | |
1913 | .cleanup = intel_8xx_cleanup, | |
1914 | .tlb_flush = intel_8xx_tlbflush, | |
1915 | .mask_memory = agp_generic_mask_memory, | |
1916 | .masks = intel_generic_masks, | |
1917 | .agp_enable = agp_generic_enable, | |
1918 | .cache_flush = global_cache_flush, | |
1919 | .create_gatt_table = agp_generic_create_gatt_table, | |
1920 | .free_gatt_table = agp_generic_free_gatt_table, | |
1921 | .insert_memory = agp_generic_insert_memory, | |
1922 | .remove_memory = agp_generic_remove_memory, | |
1923 | .alloc_by_type = agp_generic_alloc_by_type, | |
1924 | .free_by_type = agp_generic_free_by_type, | |
1925 | .agp_alloc_page = agp_generic_alloc_page, | |
1926 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1927 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1928 | }; |
1929 | ||
e5524f35 | 1930 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
1931 | .owner = THIS_MODULE, |
1932 | .aperture_sizes = intel_i830_sizes, | |
1933 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 1934 | .num_aperture_sizes = 4, |
c7258012 | 1935 | .needs_scratch_page = true, |
1da177e4 | 1936 | .configure = intel_i915_configure, |
c41e0deb | 1937 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
1938 | .cleanup = intel_i915_cleanup, |
1939 | .tlb_flush = intel_i810_tlbflush, | |
1940 | .mask_memory = intel_i810_mask_memory, | |
1941 | .masks = intel_i810_masks, | |
1942 | .agp_enable = intel_i810_agp_enable, | |
1943 | .cache_flush = global_cache_flush, | |
1944 | .create_gatt_table = intel_i915_create_gatt_table, | |
1945 | .free_gatt_table = intel_i830_free_gatt_table, | |
1946 | .insert_memory = intel_i915_insert_entries, | |
1947 | .remove_memory = intel_i915_remove_entries, | |
1948 | .alloc_by_type = intel_i830_alloc_by_type, | |
1949 | .free_by_type = intel_i810_free_by_type, | |
1950 | .agp_alloc_page = agp_generic_alloc_page, | |
1951 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 1952 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 1953 | .chipset_flush = intel_i915_chipset_flush, |
1da177e4 LT |
1954 | }; |
1955 | ||
e5524f35 | 1956 | static const struct agp_bridge_driver intel_i965_driver = { |
62c96b9d DA |
1957 | .owner = THIS_MODULE, |
1958 | .aperture_sizes = intel_i830_sizes, | |
1959 | .size_type = FIXED_APER_SIZE, | |
1960 | .num_aperture_sizes = 4, | |
1961 | .needs_scratch_page = true, | |
0e480e5f DA |
1962 | .configure = intel_i915_configure, |
1963 | .fetch_size = intel_i9xx_fetch_size, | |
62c96b9d DA |
1964 | .cleanup = intel_i915_cleanup, |
1965 | .tlb_flush = intel_i810_tlbflush, | |
1966 | .mask_memory = intel_i965_mask_memory, | |
1967 | .masks = intel_i810_masks, | |
1968 | .agp_enable = intel_i810_agp_enable, | |
1969 | .cache_flush = global_cache_flush, | |
1970 | .create_gatt_table = intel_i965_create_gatt_table, | |
1971 | .free_gatt_table = intel_i830_free_gatt_table, | |
1972 | .insert_memory = intel_i915_insert_entries, | |
1973 | .remove_memory = intel_i915_remove_entries, | |
1974 | .alloc_by_type = intel_i830_alloc_by_type, | |
1975 | .free_by_type = intel_i810_free_by_type, | |
1976 | .agp_alloc_page = agp_generic_alloc_page, | |
1977 | .agp_destroy_page = agp_generic_destroy_page, | |
1978 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
6c00a61e | 1979 | .chipset_flush = intel_i915_chipset_flush, |
65c25aad | 1980 | }; |
1da177e4 | 1981 | |
e5524f35 | 1982 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
1983 | .owner = THIS_MODULE, |
1984 | .aperture_sizes = intel_8xx_sizes, | |
1985 | .size_type = U8_APER_SIZE, | |
1986 | .num_aperture_sizes = 7, | |
1987 | .configure = intel_7505_configure, | |
1988 | .fetch_size = intel_8xx_fetch_size, | |
1989 | .cleanup = intel_8xx_cleanup, | |
1990 | .tlb_flush = intel_8xx_tlbflush, | |
1991 | .mask_memory = agp_generic_mask_memory, | |
1992 | .masks = intel_generic_masks, | |
1993 | .agp_enable = agp_generic_enable, | |
1994 | .cache_flush = global_cache_flush, | |
1995 | .create_gatt_table = agp_generic_create_gatt_table, | |
1996 | .free_gatt_table = agp_generic_free_gatt_table, | |
1997 | .insert_memory = agp_generic_insert_memory, | |
1998 | .remove_memory = agp_generic_remove_memory, | |
1999 | .alloc_by_type = agp_generic_alloc_by_type, | |
2000 | .free_by_type = agp_generic_free_by_type, | |
2001 | .agp_alloc_page = agp_generic_alloc_page, | |
2002 | .agp_destroy_page = agp_generic_destroy_page, | |
a030ce44 | 2003 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2004 | }; |
2005 | ||
874808c6 | 2006 | static const struct agp_bridge_driver intel_g33_driver = { |
62c96b9d DA |
2007 | .owner = THIS_MODULE, |
2008 | .aperture_sizes = intel_i830_sizes, | |
2009 | .size_type = FIXED_APER_SIZE, | |
2010 | .num_aperture_sizes = 4, | |
2011 | .needs_scratch_page = true, | |
2012 | .configure = intel_i915_configure, | |
2013 | .fetch_size = intel_i9xx_fetch_size, | |
2014 | .cleanup = intel_i915_cleanup, | |
2015 | .tlb_flush = intel_i810_tlbflush, | |
2016 | .mask_memory = intel_i965_mask_memory, | |
2017 | .masks = intel_i810_masks, | |
2018 | .agp_enable = intel_i810_agp_enable, | |
2019 | .cache_flush = global_cache_flush, | |
2020 | .create_gatt_table = intel_i915_create_gatt_table, | |
2021 | .free_gatt_table = intel_i830_free_gatt_table, | |
2022 | .insert_memory = intel_i915_insert_entries, | |
2023 | .remove_memory = intel_i915_remove_entries, | |
2024 | .alloc_by_type = intel_i830_alloc_by_type, | |
2025 | .free_by_type = intel_i810_free_by_type, | |
2026 | .agp_alloc_page = agp_generic_alloc_page, | |
2027 | .agp_destroy_page = agp_generic_destroy_page, | |
2028 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, | |
6c00a61e | 2029 | .chipset_flush = intel_i915_chipset_flush, |
874808c6 | 2030 | }; |
1da177e4 | 2031 | |
9614ece1 | 2032 | static int find_gmch(u16 device) |
1da177e4 | 2033 | { |
9614ece1 | 2034 | struct pci_dev *gmch_device; |
1da177e4 | 2035 | |
9614ece1 WZ |
2036 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
2037 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
2038 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
f011ae74 | 2039 | device, gmch_device); |
1da177e4 LT |
2040 | } |
2041 | ||
9614ece1 | 2042 | if (!gmch_device) |
1da177e4 LT |
2043 | return 0; |
2044 | ||
9614ece1 | 2045 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
2046 | return 1; |
2047 | } | |
2048 | ||
9614ece1 WZ |
2049 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
2050 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
2051 | * which one should be used if a gmch_chip_id is present. | |
2052 | */ | |
2053 | static const struct intel_driver_description { | |
2054 | unsigned int chip_id; | |
2055 | unsigned int gmch_chip_id; | |
88889851 | 2056 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
2057 | char *name; |
2058 | const struct agp_bridge_driver *driver; | |
2059 | const struct agp_bridge_driver *gmch_driver; | |
2060 | } intel_agp_chipsets[] = { | |
88889851 WZ |
2061 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
2062 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
2063 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
2064 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 2065 | NULL, &intel_810_driver }, |
88889851 | 2066 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 2067 | NULL, &intel_810_driver }, |
88889851 | 2068 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 2069 | NULL, &intel_810_driver }, |
88889851 WZ |
2070 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
2071 | &intel_815_driver, &intel_810_driver }, | |
2072 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2073 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2074 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 2075 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
2076 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
2077 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
2078 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 2079 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2080 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
2081 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, | |
2082 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 2083 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2084 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
2085 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 2086 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2087 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
2088 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
2089 | NULL, &intel_915_driver }, | |
88889851 | 2090 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 2091 | NULL, &intel_915_driver }, |
88889851 | 2092 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 2093 | NULL, &intel_915_driver }, |
88889851 | 2094 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 2095 | NULL, &intel_915_driver }, |
dde47876 | 2096 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 2097 | NULL, &intel_915_driver }, |
dde47876 | 2098 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 2099 | NULL, &intel_915_driver }, |
88889851 | 2100 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 2101 | NULL, &intel_i965_driver }, |
9119f85a | 2102 | { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", |
47d46379 | 2103 | NULL, &intel_i965_driver }, |
88889851 | 2104 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 2105 | NULL, &intel_i965_driver }, |
88889851 | 2106 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 2107 | NULL, &intel_i965_driver }, |
dde47876 | 2108 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 2109 | NULL, &intel_i965_driver }, |
dde47876 | 2110 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 2111 | NULL, &intel_i965_driver }, |
88889851 WZ |
2112 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
2113 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
2114 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 2115 | NULL, &intel_g33_driver }, |
88889851 | 2116 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 2117 | NULL, &intel_g33_driver }, |
88889851 | 2118 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 2119 | NULL, &intel_g33_driver }, |
99d32bd5 ZW |
2120 | { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, |
2121 | "Mobile Intel? GM45 Express", NULL, &intel_i965_driver }, | |
25ce77ab ZW |
2122 | { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0, |
2123 | "Intel Integrated Graphics Device", NULL, &intel_i965_driver }, | |
2124 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, | |
2125 | "Q45/Q43", NULL, &intel_i965_driver }, | |
2126 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | |
2127 | "G45/G43", NULL, &intel_i965_driver }, | |
88889851 | 2128 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
2129 | }; |
2130 | ||
1da177e4 LT |
2131 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
2132 | const struct pci_device_id *ent) | |
2133 | { | |
2134 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
2135 | u8 cap_ptr = 0; |
2136 | struct resource *r; | |
9614ece1 | 2137 | int i; |
1da177e4 LT |
2138 | |
2139 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2140 | ||
2141 | bridge = agp_alloc_bridge(); | |
2142 | if (!bridge) | |
2143 | return -ENOMEM; | |
2144 | ||
9614ece1 WZ |
2145 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2146 | /* In case that multiple models of gfx chip may | |
2147 | stand on same host bridge type, this can be | |
2148 | sure we detect the right IGD. */ | |
88889851 WZ |
2149 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2150 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2151 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2152 | bridge->driver = | |
2153 | intel_agp_chipsets[i].gmch_driver; | |
2154 | break; | |
2155 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2156 | continue; | |
2157 | } else { | |
2158 | bridge->driver = intel_agp_chipsets[i].driver; | |
2159 | break; | |
2160 | } | |
2161 | } | |
9614ece1 WZ |
2162 | } |
2163 | ||
2164 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2165 | if (cap_ptr) |
9614ece1 | 2166 | printk(KERN_WARNING PFX "Unsupported Intel chipset" |
f011ae74 | 2167 | "(device id: %04x)\n", pdev->device); |
9614ece1 WZ |
2168 | agp_put_bridge(bridge); |
2169 | return -ENODEV; | |
2170 | } | |
2171 | ||
9614ece1 | 2172 | if (bridge->driver == NULL) { |
47d46379 WZ |
2173 | /* bridge has no AGP and no IGD detected */ |
2174 | if (cap_ptr) | |
2175 | printk(KERN_WARNING PFX "Failed to find bridge device " | |
2176 | "(chip_id: %04x)\n", | |
2177 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2178 | agp_put_bridge(bridge); |
2179 | return -ENODEV; | |
f011ae74 | 2180 | } |
1da177e4 LT |
2181 | |
2182 | bridge->dev = pdev; | |
2183 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2184 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2185 | |
9614ece1 WZ |
2186 | printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", |
2187 | intel_agp_chipsets[i].name); | |
1da177e4 LT |
2188 | |
2189 | /* | |
2190 | * The following fixes the case where the BIOS has "forgotten" to | |
2191 | * provide an address range for the GART. | |
2192 | * 20030610 - hamish@zot.org | |
2193 | */ | |
2194 | r = &pdev->resource[0]; | |
2195 | if (!r->start && r->end) { | |
6a92a4e0 | 2196 | if (pci_assign_resource(pdev, 0)) { |
1da177e4 LT |
2197 | printk(KERN_ERR PFX "could not assign resource 0\n"); |
2198 | agp_put_bridge(bridge); | |
2199 | return -ENODEV; | |
2200 | } | |
2201 | } | |
2202 | ||
2203 | /* | |
2204 | * If the device has not been properly setup, the following will catch | |
2205 | * the problem and should stop the system from crashing. | |
2206 | * 20030610 - hamish@zot.org | |
2207 | */ | |
2208 | if (pci_enable_device(pdev)) { | |
2209 | printk(KERN_ERR PFX "Unable to Enable PCI device\n"); | |
2210 | agp_put_bridge(bridge); | |
2211 | return -ENODEV; | |
2212 | } | |
2213 | ||
2214 | /* Fill in the mode register */ | |
2215 | if (cap_ptr) { | |
2216 | pci_read_config_dword(pdev, | |
2217 | bridge->capndx+PCI_AGP_STATUS, | |
2218 | &bridge->mode); | |
2219 | } | |
2220 | ||
2221 | pci_set_drvdata(pdev, bridge); | |
2222 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2223 | } |
2224 | ||
2225 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2226 | { | |
2227 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2228 | ||
2229 | agp_remove_bridge(bridge); | |
2230 | ||
c4ca8817 WZ |
2231 | if (intel_private.pcidev) |
2232 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2233 | |
2234 | agp_put_bridge(bridge); | |
2235 | } | |
2236 | ||
85be7d60 | 2237 | #ifdef CONFIG_PM |
1da177e4 LT |
2238 | static int agp_intel_resume(struct pci_dev *pdev) |
2239 | { | |
2240 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2241 | ||
2242 | pci_restore_state(pdev); | |
2243 | ||
4b95320f WZ |
2244 | /* We should restore our graphics device's config space, |
2245 | * as host bridge (00:00) resumes before graphics device (02:00), | |
2246 | * then our access to its pci space can work right. | |
2247 | */ | |
c4ca8817 WZ |
2248 | if (intel_private.pcidev) |
2249 | pci_restore_state(intel_private.pcidev); | |
4b95320f | 2250 | |
1da177e4 LT |
2251 | if (bridge->driver == &intel_generic_driver) |
2252 | intel_configure(); | |
2253 | else if (bridge->driver == &intel_850_driver) | |
2254 | intel_850_configure(); | |
2255 | else if (bridge->driver == &intel_845_driver) | |
2256 | intel_845_configure(); | |
2257 | else if (bridge->driver == &intel_830mp_driver) | |
2258 | intel_830mp_configure(); | |
2259 | else if (bridge->driver == &intel_915_driver) | |
2260 | intel_i915_configure(); | |
2261 | else if (bridge->driver == &intel_830_driver) | |
2262 | intel_i830_configure(); | |
2263 | else if (bridge->driver == &intel_810_driver) | |
2264 | intel_i810_configure(); | |
08da3f41 DJ |
2265 | else if (bridge->driver == &intel_i965_driver) |
2266 | intel_i915_configure(); | |
1da177e4 LT |
2267 | |
2268 | return 0; | |
2269 | } | |
85be7d60 | 2270 | #endif |
1da177e4 LT |
2271 | |
2272 | static struct pci_device_id agp_intel_pci_table[] = { | |
2273 | #define ID(x) \ | |
2274 | { \ | |
2275 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2276 | .class_mask = ~0, \ | |
2277 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2278 | .device = x, \ | |
2279 | .subvendor = PCI_ANY_ID, \ | |
2280 | .subdevice = PCI_ANY_ID, \ | |
2281 | } | |
2282 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2283 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2284 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2285 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2286 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2287 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2288 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2289 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2290 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2291 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2292 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2293 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2294 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2295 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
2296 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), | |
2297 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2298 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2299 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2300 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2301 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2302 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2303 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2304 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2305 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2306 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2307 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2308 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
65c25aad | 2309 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
9119f85a | 2310 | ID(PCI_DEVICE_ID_INTEL_82G35_HB), |
65c25aad EA |
2311 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), |
2312 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2313 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2314 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2315 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2316 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2317 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
99d32bd5 | 2318 | ID(PCI_DEVICE_ID_INTEL_GM45_HB), |
25ce77ab ZW |
2319 | ID(PCI_DEVICE_ID_INTEL_IGD_E_HB), |
2320 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), | |
2321 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | |
1da177e4 LT |
2322 | { } |
2323 | }; | |
2324 | ||
2325 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2326 | ||
2327 | static struct pci_driver agp_intel_pci_driver = { | |
2328 | .name = "agpgart-intel", | |
2329 | .id_table = agp_intel_pci_table, | |
2330 | .probe = agp_intel_probe, | |
2331 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2332 | #ifdef CONFIG_PM |
1da177e4 | 2333 | .resume = agp_intel_resume, |
85be7d60 | 2334 | #endif |
1da177e4 LT |
2335 | }; |
2336 | ||
2337 | static int __init agp_intel_init(void) | |
2338 | { | |
2339 | if (agp_off) | |
2340 | return -EINVAL; | |
2341 | return pci_register_driver(&agp_intel_pci_driver); | |
2342 | } | |
2343 | ||
2344 | static void __exit agp_intel_cleanup(void) | |
2345 | { | |
2346 | pci_unregister_driver(&agp_intel_pci_driver); | |
2347 | } | |
2348 | ||
2349 | module_init(agp_intel_init); | |
2350 | module_exit(agp_intel_cleanup); | |
2351 | ||
2352 | MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); | |
2353 | MODULE_LICENSE("GPL and additional rights"); |