[linux-2.6-block.git] / drivers / char / agp / i460-agp.c

/*
 * For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
 * the "Intel 460GTX Chipset Software Developer's Manual":
 * http://developer.intel.com/design/itanium/downloads/24870401s.htm
 */
/*
 * 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
 * Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com>
 */
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/agp_backend.h>

#include "agp.h"

#define INTEL_I460_BAPBASE		0x98
#define INTEL_I460_GXBCTL		0xa0
#define INTEL_I460_AGPSIZ		0xa2
#define INTEL_I460_ATTBASE		0xfe200000
#define INTEL_I460_GATT_VALID		(1UL << 24)
#define INTEL_I460_GATT_COHERENT	(1UL << 25)

/*
 * The i460 can operate with large (4MB) pages, but there is no sane way to support this
 * within the current kernel/DRM environment, so we disable the relevant code for now.
 * See also comments in ia64_alloc_page()...
 */
#define I460_LARGE_IO_PAGES		0

#if I460_LARGE_IO_PAGES
# define I460_IO_PAGE_SHIFT		i460.io_page_shift
#else
# define I460_IO_PAGE_SHIFT		12
#endif

#define I460_IOPAGES_PER_KPAGE		(PAGE_SIZE >> I460_IO_PAGE_SHIFT)
#define I460_KPAGES_PER_IOPAGE		(1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT))
#define I460_SRAM_IO_DISABLE		(1 << 4)
#define I460_BAPBASE_ENABLE		(1 << 3)
#define I460_AGPSIZ_MASK		0x7
#define I460_4M_PS			(1 << 1)

/* Control bits for Out-Of-GART coherency and Burst Write Combining */
#define I460_GXBCTL_OOG		(1UL << 0)
#define I460_GXBCTL_BWC		(1UL << 2)

/*
 * gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the
 * gatt_table and gatt_table_real pointers a "void *"...
 */
#define RD_GATT(index)		readl((u32 *) i460.gatt + (index))
#define WR_GATT(index, val)	writel((val), (u32 *) i460.gatt + (index))
/*
 * The 460 spec says we have to read the last location written to make sure that all
 * writes have taken effect
 */
#define WR_FLUSH_GATT(index)	RD_GATT(index)

#define log2(x)			ffz(~(x))

static struct {
	void *gatt;				/* ioremap'd GATT area */

	/* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
	u8 io_page_shift;

	/* BIOS configures chipset to one of 2 possible apbase values: */
	u8 dynamic_apbase;

	/* structure for tracking partial use of 4MB GART pages: */
	struct lp_desc {
		unsigned long *alloced_map;	/* bitmap of kernel-pages in use */
		int refcount;			/* number of kernel pages using the large page */
		u64 paddr;			/* physical address of large page */
	} *lp_desc;
} i460;

static struct aper_size_info_8 i460_sizes[3] =
{
	/*
	 * The 32GB aperture is only available with a 4M GART page size.  Due to the
	 * dynamic GART page size, we can't figure out page_order or num_entries until
	 * runtime.
	 */
	{32768, 0, 0, 4},
	{1024, 0, 0, 2},
	{256, 0, 0, 1}
};

static struct gatt_mask i460_masks[] =
{
	{
	  .mask = INTEL_I460_GATT_VALID | INTEL_I460_GATT_COHERENT,
	  .type = 0
	}
};

static int i460_fetch_size (void)
{
	int i;
	u8 temp;
	struct aper_size_info_8 *values;

	/* Determine the GART page size */
	pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
	i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
	pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);

	if (i460.io_page_shift != I460_IO_PAGE_SHIFT) {
		printk(KERN_ERR PFX
			"I/O (GART) page-size %luKB doesn't match expected "
				"size %luKB\n",
			1UL << (i460.io_page_shift - 10),
			1UL << (I460_IO_PAGE_SHIFT));
		return 0;
	}

	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);

	pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);

	/* Exit now if the IO drivers for the GART SRAMS are turned off */
	if (temp & I460_SRAM_IO_DISABLE) {
		printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n");
		printk(KERN_ERR PFX "AGPGART operation not possible\n");
		return 0;
	}

	/* Make sure we don't try to create an 2 ^ 23 entry GATT */
	if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
		printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n");
		return 0;
	}

	/* Determine the proper APBASE register */
	if (temp & I460_BAPBASE_ENABLE)
		i460.dynamic_apbase = INTEL_I460_BAPBASE;
	else
		i460.dynamic_apbase = AGP_APBASE;

	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		/*
		 * Dynamically calculate the proper num_entries and page_order values for
		 * the define aperture sizes. Take care not to shift off the end of
		 * values[i].size.
		 */
		values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12);
		values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
	}

	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		/* Neglect control bits when matching up size_value */
		if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
			agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}

	return 0;
}

/* There isn't anything to do here since 460 has no GART TLB. */
static void i460_tlb_flush (struct agp_memory *mem)
{
	return;
}

/*
 * This utility function is needed to prevent corruption of the control bits
 * which are stored along with the aperture size in 460's AGPSIZ register
 */
static void i460_write_agpsiz (u8 size_value)
{
	u8 temp;

	pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
	pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
			      ((temp & ~I460_AGPSIZ_MASK) | size_value));
}

static void i460_cleanup (void)
{
	struct aper_size_info_8 *previous_size;

	previous_size = A_SIZE_8(agp_bridge->previous_size);
	i460_write_agpsiz(previous_size->size_value);

	if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
		kfree(i460.lp_desc);
}

static int i460_configure (void)
{
	union {
		u32 small[2];
		u64 large;
	} temp;
	size_t size;
	u8 scratch;
	struct aper_size_info_8 *current_size;

	temp.large = 0;

	current_size = A_SIZE_8(agp_bridge->current_size);
	i460_write_agpsiz(current_size->size_value);

	/*
	 * Do the necessary rigmarole to read all eight bytes of APBASE.
	 * This has to be done since the AGP aperture can be above 4GB on
	 * 460 based systems.
	 */
	pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
	pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));

	/* Clear BAR control bits */
	agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);

	pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
	pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
			      (scratch & 0x02) | I460_GXBCTL_OOG | I460_GXBCTL_BWC);

	/*
	 * Initialize partial allocation trackers if a GART page is bigger than a kernel
	 * page.
	 */
	if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {
		size = current_size->num_entries * sizeof(i460.lp_desc[0]);
		i460.lp_desc = kzalloc(size, GFP_KERNEL);
		if (!i460.lp_desc)
			return -ENOMEM;
	}
	return 0;
}

static int i460_create_gatt_table (struct agp_bridge_data *bridge)
{
	int page_order, num_entries, i;
	void *temp;

	/*
	 * Load up the fixed address of the GART SRAMS which hold our GATT table.
	 */
	temp = agp_bridge->current_size;
	page_order = A_SIZE_8(temp)->page_order;
	num_entries = A_SIZE_8(temp)->num_entries;

	i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);

	/* These are no good, the should be removed from the agp_bridge strucure... */
	agp_bridge->gatt_table_real = NULL;
	agp_bridge->gatt_table = NULL;
	agp_bridge->gatt_bus_addr = 0;

	for (i = 0; i < num_entries; ++i)
		WR_GATT(i, 0);
	WR_FLUSH_GATT(i - 1);
	return 0;
}

static int i460_free_gatt_table (struct agp_bridge_data *bridge)
{
	int num_entries, i;
	void *temp;

	temp = agp_bridge->current_size;

	num_entries = A_SIZE_8(temp)->num_entries;

	for (i = 0; i < num_entries; ++i)
		WR_GATT(i, 0);
	WR_FLUSH_GATT(num_entries - 1);

	iounmap(i460.gatt);
	return 0;
}

/*
 * The following functions are called when the I/O (GART) page size is smaller than
 * PAGE_SIZE.
 */

static int i460_insert_memory_small_io_page (struct agp_memory *mem,
				off_t pg_start, int type)
{
	unsigned long paddr, io_pg_start, io_page_size;
	int i, j, k, num_entries;
	void *temp;

	pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n",
		 mem, pg_start, type, mem->memory[0]);

	if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)
		return -EINVAL;

	io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;

	temp = agp_bridge->current_size;
	num_entries = A_SIZE_8(temp)->num_entries;

	if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
		printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
		return -EINVAL;
	}

	j = io_pg_start;
	while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
		if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
			pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
				 j, RD_GATT(j));
			return -EBUSY;
		}
		j++;
	}

	io_page_size = 1UL << I460_IO_PAGE_SHIFT;
	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
		paddr = mem->memory[i];
		for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
			WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge,
				paddr, mem->type));
	}
	WR_FLUSH_GATT(j - 1);
	return 0;
}

static int i460_remove_memory_small_io_page(struct agp_memory *mem,
				off_t pg_start, int type)
{
	int i;

	pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n",
		 mem, pg_start, type);

	pg_start = I460_IOPAGES_PER_KPAGE * pg_start;

	for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++)
		WR_GATT(i, 0);
	WR_FLUSH_GATT(i - 1);
	return 0;
}

#if I460_LARGE_IO_PAGES

/*
 * These functions are called when the I/O (GART) page size exceeds PAGE_SIZE.
 *
 * This situation is interesting since AGP memory allocations that are smaller than a
 * single GART page are possible.  The i460.lp_desc array tracks partial allocation of the
 * large GART pages to work around this issue.
 *
 * i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page
 * pg_num.  i460.lp_desc[pg_num].paddr is the physical address of the large page and
 * i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated).
 */

static int i460_alloc_large_page (struct lp_desc *lp)
{
	unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT;
	size_t map_size;
	void *lpage;

	lpage = (void *) __get_free_pages(GFP_KERNEL, order);
	if (!lpage) {
		printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n");
		return -ENOMEM;
	}

	map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8;
	lp->alloced_map = kzalloc(map_size, GFP_KERNEL);
	if (!lp->alloced_map) {
		free_pages((unsigned long) lpage, order);
		printk(KERN_ERR PFX "Out of memory, we're in trouble...\n");
		return -ENOMEM;
	}

	lp->paddr = virt_to_gart(lpage);
	lp->refcount = 0;
	atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
	return 0;
}

static void i460_free_large_page (struct lp_desc *lp)
{
	kfree(lp->alloced_map);
	lp->alloced_map = NULL;

	free_pages((unsigned long) gart_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
	atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
}

static int i460_insert_memory_large_io_page (struct agp_memory *mem,
				off_t pg_start, int type)
{
	int i, start_offset, end_offset, idx, pg, num_entries;
	struct lp_desc *start, *end, *lp;
	void *temp;

	if (type >= AGP_USER_TYPES || mem->type >= AGP_USER_TYPES)
		return -EINVAL;

	temp = agp_bridge->current_size;
	num_entries = A_SIZE_8(temp)->num_entries;

	/* Figure out what pg_start means in terms of our large GART pages */
	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;

	if (end > i460.lp_desc + num_entries) {
		printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
		return -EINVAL;
	}

	/* Check if the requested region of the aperture is free */
	for (lp = start; lp <= end; ++lp) {
		if (!lp->alloced_map)
			continue;	/* OK, the entire large page is available... */

		for (idx = ((lp == start) ? start_offset : 0);
		     idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
		     idx++)
		{
			if (test_bit(idx, lp->alloced_map))
				return -EBUSY;
		}
	}

	for (lp = start, i = 0; lp <= end; ++lp) {
		if (!lp->alloced_map) {
			/* Allocate new GART pages... */
			if (i460_alloc_large_page(lp) < 0)
				return -ENOMEM;
			pg = lp - i460.lp_desc;
			WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge,
				lp->paddr, 0));
			WR_FLUSH_GATT(pg);
		}

		for (idx = ((lp == start) ? start_offset : 0);
		     idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
		     idx++, i++)
		{
			mem->memory[i] = lp->paddr + idx*PAGE_SIZE;
			__set_bit(idx, lp->alloced_map);
			++lp->refcount;
		}
	}
	return 0;
}

static int i460_remove_memory_large_io_page (struct agp_memory *mem,
				off_t pg_start, int type)
{
	int i, pg, start_offset, end_offset, idx, num_entries;
	struct lp_desc *start, *end, *lp;
	void *temp;

	temp = agp_bridge->driver->current_size;
	num_entries = A_SIZE_8(temp)->num_entries;

	/* Figure out what pg_start means in terms of our large GART pages */
	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;

	for (i = 0, lp = start; lp <= end; ++lp) {
		for (idx = ((lp == start) ? start_offset : 0);
		     idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
		     idx++, i++)
		{
			mem->memory[i] = 0;
			__clear_bit(idx, lp->alloced_map);
			--lp->refcount;
		}

		/* Free GART pages if they are unused */
		if (lp->refcount == 0) {
			pg = lp - i460.lp_desc;
			WR_GATT(pg, 0);
			WR_FLUSH_GATT(pg);
			i460_free_large_page(lp);
		}
	}
	return 0;
}

/* Wrapper routines to call the approriate {small_io_page,large_io_page} function */

static int i460_insert_memory (struct agp_memory *mem,
				off_t pg_start, int type)
{
	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
		return i460_insert_memory_small_io_page(mem, pg_start, type);
	else
		return i460_insert_memory_large_io_page(mem, pg_start, type);
}

static int i460_remove_memory (struct agp_memory *mem,
				off_t pg_start, int type)
{
	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
		return i460_remove_memory_small_io_page(mem, pg_start, type);
	else
		return i460_remove_memory_large_io_page(mem, pg_start, type);
}

/*
 * If the I/O (GART) page size is bigger than the kernel page size, we don't want to
 * allocate memory until we know where it is to be bound in the aperture (a
 * multi-kernel-page alloc might fit inside of an already allocated GART page).
 *
 * Let's just hope nobody counts on the allocated AGP memory being there before bind time
 * (I don't think current drivers do)...
 */
static void *i460_alloc_page (struct agp_bridge_data *bridge)
{
	void *page;

	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
		page = agp_generic_alloc_page(agp_bridge);
		global_flush_tlb();
	} else
		/* Returning NULL would cause problems */
		/* AK: really dubious code. */
		page = (void *)~0UL;
	return page;
}

static void i460_destroy_page (void *page)
{
	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
		agp_generic_destroy_page(page);
		global_flush_tlb();
	}
}

#endif /* I460_LARGE_IO_PAGES */

static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
	unsigned long addr, int type)
{
	/* Make sure the returned address is a valid GATT entry */
	return bridge->driver->masks[0].mask
		| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xfffff000) >> 12);
}

struct agp_bridge_driver intel_i460_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= i460_sizes,
	.size_type		= U8_APER_SIZE,
	.num_aperture_sizes	= 3,
	.configure		= i460_configure,
	.fetch_size		= i460_fetch_size,
	.cleanup		= i460_cleanup,
	.tlb_flush		= i460_tlb_flush,
	.mask_memory		= i460_mask_memory,
	.masks			= i460_masks,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= i460_create_gatt_table,
	.free_gatt_table	= i460_free_gatt_table,
#if I460_LARGE_IO_PAGES
	.insert_memory		= i460_insert_memory,
	.remove_memory		= i460_remove_memory,
	.agp_alloc_page		= i460_alloc_page,
	.agp_destroy_page	= i460_destroy_page,
#else
	.insert_memory		= i460_insert_memory_small_io_page,
	.remove_memory		= i460_remove_memory_small_io_page,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_destroy_page	= agp_generic_destroy_page,
#endif
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
	.cant_use_aperture	= 1,
};

static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
					  const struct pci_device_id *ent)
{
	struct agp_bridge_data *bridge;
	u8 cap_ptr;

	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	if (!cap_ptr)
		return -ENODEV;

	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

	bridge->driver = &intel_i460_driver;
	bridge->dev = pdev;
	bridge->capndx = cap_ptr;

	printk(KERN_INFO PFX "Detected Intel 460GX chipset\n");

	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
}

static void __devexit agp_intel_i460_remove(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
}

static struct pci_device_id agp_intel_i460_pci_table[] = {
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_INTEL,
	.device		= PCI_DEVICE_ID_INTEL_84460GX,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{ }
};

MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);

static struct pci_driver agp_intel_i460_pci_driver = {
	.name		= "agpgart-intel-i460",
	.id_table	= agp_intel_i460_pci_table,
	.probe		= agp_intel_i460_probe,
	.remove		= __devexit_p(agp_intel_i460_remove),
};

static int __init agp_intel_i460_init(void)
{
	if (agp_off)
		return -EINVAL;
	return pci_register_driver(&agp_intel_i460_pci_driver);
}

static void __exit agp_intel_i460_cleanup(void)
{
	pci_unregister_driver(&agp_intel_i460_pci_driver);
}

module_init(agp_intel_i460_init);
module_exit(agp_intel_i460_cleanup);

MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* For documentation on the i460 AGP interface, see Chapter 7 (AGP Subsystem) of
	3	* the "Intel 460GTX Chipset Software Developer's Manual":
	4	* http://developer.intel.com/design/itanium/downloads/24870401s.htm
	5	*/
	6	/*
	7	* 460GX support by Chris Ahna <christopher.j.ahna@intel.com>
	8	* Clean up & simplification by David Mosberger-Tang <davidm@hpl.hp.com>
	9	*/
	10	#include <linux/module.h>
	11	#include <linux/pci.h>
	12	#include <linux/init.h>
4e57b681 TS	13	#include <linux/string.h>
4e57b681 TS	14	#include <linux/slab.h>
1da177e4 LT	15	#include <linux/agp_backend.h>
	16
	17	#include "agp.h"
	18
	19	#define INTEL_I460_BAPBASE 0x98
	20	#define INTEL_I460_GXBCTL 0xa0
	21	#define INTEL_I460_AGPSIZ 0xa2
	22	#define INTEL_I460_ATTBASE 0xfe200000
	23	#define INTEL_I460_GATT_VALID (1UL << 24)
	24	#define INTEL_I460_GATT_COHERENT (1UL << 25)
	25
	26	/*
	27	* The i460 can operate with large (4MB) pages, but there is no sane way to support this
	28	* within the current kernel/DRM environment, so we disable the relevant code for now.
	29	* See also comments in ia64_alloc_page()...
	30	*/
	31	#define I460_LARGE_IO_PAGES 0
	32
	33	#if I460_LARGE_IO_PAGES
	34	# define I460_IO_PAGE_SHIFT i460.io_page_shift
	35	#else
	36	# define I460_IO_PAGE_SHIFT 12
	37	#endif
	38
	39	#define I460_IOPAGES_PER_KPAGE (PAGE_SIZE >> I460_IO_PAGE_SHIFT)
	40	#define I460_KPAGES_PER_IOPAGE (1 << (I460_IO_PAGE_SHIFT - PAGE_SHIFT))
	41	#define I460_SRAM_IO_DISABLE (1 << 4)
	42	#define I460_BAPBASE_ENABLE (1 << 3)
	43	#define I460_AGPSIZ_MASK 0x7
	44	#define I460_4M_PS (1 << 1)
	45
	46	/* Control bits for Out-Of-GART coherency and Burst Write Combining */
	47	#define I460_GXBCTL_OOG (1UL << 0)
	48	#define I460_GXBCTL_BWC (1UL << 2)
	49
	50	/*
	51	* gatt_table entries are 32-bits wide on the i460; the generic code ought to declare the
	52	* gatt_table and gatt_table_real pointers a "void *"...
	53	*/
	54	#define RD_GATT(index) readl((u32 *) i460.gatt + (index))
	55	#define WR_GATT(index, val) writel((val), (u32 *) i460.gatt + (index))
	56	/*
	57	* The 460 spec says we have to read the last location written to make sure that all
	58	* writes have taken effect
	59	*/
	60	#define WR_FLUSH_GATT(index) RD_GATT(index)
	61
	62	#define log2(x) ffz(~(x))
	63
	64	static struct {
	65	void gatt; / ioremap'd GATT area */
	66
	67	/* i460 supports multiple GART page sizes, so GART pageshift is dynamic: */
	68	u8 io_page_shift;
	69
	70	/* BIOS configures chipset to one of 2 possible apbase values: */
	71	u8 dynamic_apbase;
	72
	73	/* structure for tracking partial use of 4MB GART pages: */
	74	struct lp_desc {
	75	unsigned long alloced_map; / bitmap of kernel-pages in use */
	76	int refcount; /* number of kernel pages using the large page */
	77	u64 paddr; /* physical address of large page */
	78	} *lp_desc;
79	} i460;
80
81	static struct aper_size_info_8 i460_sizes[3] =
82	{
83	/*
84	* The 32GB aperture is only available with a 4M GART page size. Due to the
85	* dynamic GART page size, we can't figure out page_order or num_entries until
86	* runtime.
87	*/
88	{32768, 0, 0, 4},
89	{1024, 0, 0, 2},
90	{256, 0, 0, 1}
91	};
92
93	static struct gatt_mask i460_masks[] =
94	{
95	{
96	.mask = INTEL_I460_GATT_VALID \| INTEL_I460_GATT_COHERENT,
97	.type = 0
98	}
99	};
100
101	static int i460_fetch_size (void)
102	{
103	int i;
104	u8 temp;
105	struct aper_size_info_8 *values;
106
107	/* Determine the GART page size */
108	pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &temp);
109	i460.io_page_shift = (temp & I460_4M_PS) ? 22 : 12;
110	pr_debug("i460_fetch_size: io_page_shift=%d\n", i460.io_page_shift);
111
112	if (i460.io_page_shift != I460_IO_PAGE_SHIFT) {
113	printk(KERN_ERR PFX
49ebd7c6 AM	114	"I/O (GART) page-size %luKB doesn't match expected "
	115	"size %luKB\n",
	116	1UL << (i460.io_page_shift - 10),
	117	1UL << (I460_IO_PAGE_SHIFT));
1da177e4 LT	118	return 0;
	119	}
	120
	121	values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
	122
	123	pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
	124
	125	/* Exit now if the IO drivers for the GART SRAMS are turned off */
	126	if (temp & I460_SRAM_IO_DISABLE) {
	127	printk(KERN_ERR PFX "GART SRAMS disabled on 460GX chipset\n");
	128	printk(KERN_ERR PFX "AGPGART operation not possible\n");
	129	return 0;
	130	}
	131
	132	/* Make sure we don't try to create an 2 ^ 23 entry GATT */
	133	if ((i460.io_page_shift == 0) && ((temp & I460_AGPSIZ_MASK) == 4)) {
	134	printk(KERN_ERR PFX "We can't have a 32GB aperture with 4KB GART pages\n");
	135	return 0;
	136	}
	137
	138	/* Determine the proper APBASE register */
	139	if (temp & I460_BAPBASE_ENABLE)
	140	i460.dynamic_apbase = INTEL_I460_BAPBASE;
	141	else
	142	i460.dynamic_apbase = AGP_APBASE;
	143
	144	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	145	/*
	146	* Dynamically calculate the proper num_entries and page_order values for
	147	* the define aperture sizes. Take care not to shift off the end of
	148	* values[i].size.
	149	*/
	150	values[i].num_entries = (values[i].size << 8) >> (I460_IO_PAGE_SHIFT - 12);
	151	values[i].page_order = log2((sizeof(u32)*values[i].num_entries) >> PAGE_SHIFT);
	152	}
	153
	154	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	155	/* Neglect control bits when matching up size_value */
	156	if ((temp & I460_AGPSIZ_MASK) == values[i].size_value) {
	157	agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
	158	agp_bridge->aperture_size_idx = i;
	159	return values[i].size;
	160	}
	161	}
	162
	163	return 0;
	164	}
	165
	166	/* There isn't anything to do here since 460 has no GART TLB. */
	167	static void i460_tlb_flush (struct agp_memory *mem)
	168	{
	169	return;
	170	}
	171
	172	/*
	173	* This utility function is needed to prevent corruption of the control bits
	174	* which are stored along with the aperture size in 460's AGPSIZ register
	175	*/
	176	static void i460_write_agpsiz (u8 size_value)
	177	{
	178	u8 temp;
	179
	180	pci_read_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ, &temp);
	181	pci_write_config_byte(agp_bridge->dev, INTEL_I460_AGPSIZ,
182	((temp & ~I460_AGPSIZ_MASK) \| size_value));
183	}
184
185	static void i460_cleanup (void)
186	{
187	struct aper_size_info_8 *previous_size;
188
189	previous_size = A_SIZE_8(agp_bridge->previous_size);
190	i460_write_agpsiz(previous_size->size_value);
191
192	if (I460_IO_PAGE_SHIFT > PAGE_SHIFT)
193	kfree(i460.lp_desc);
194	}
195
196	static int i460_configure (void)
197	{
198	union {
199	u32 small[2];
200	u64 large;
201	} temp;
202	size_t size;
203	u8 scratch;
204	struct aper_size_info_8 *current_size;
205
206	temp.large = 0;
207
208	current_size = A_SIZE_8(agp_bridge->current_size);
209	i460_write_agpsiz(current_size->size_value);
210
211	/*
212	* Do the necessary rigmarole to read all eight bytes of APBASE.
213	* This has to be done since the AGP aperture can be above 4GB on
214	* 460 based systems.
215	*/
216	pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase, &(temp.small[0]));
217	pci_read_config_dword(agp_bridge->dev, i460.dynamic_apbase + 4, &(temp.small[1]));
218
219	/* Clear BAR control bits */
220	agp_bridge->gart_bus_addr = temp.large & ~((1UL << 3) - 1);
221
222	pci_read_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL, &scratch);
223	pci_write_config_byte(agp_bridge->dev, INTEL_I460_GXBCTL,
224	(scratch & 0x02) \| I460_GXBCTL_OOG \| I460_GXBCTL_BWC);
225
226	/*
227	* Initialize partial allocation trackers if a GART page is bigger than a kernel
228	* page.
229	*/
230	if (I460_IO_PAGE_SHIFT > PAGE_SHIFT) {
231	size = current_size->num_entries * sizeof(i460.lp_desc[0]);
0ea27d9f	232	i460.lp_desc = kzalloc(size, GFP_KERNEL);
1da177e4 LT	233	if (!i460.lp_desc)
1da177e4 LT	234	return -ENOMEM;
1da177e4 LT	235	}
	236	return 0;
	237	}
	238
	239	static int i460_create_gatt_table (struct agp_bridge_data *bridge)
	240	{
	241	int page_order, num_entries, i;
	242	void *temp;
	243
	244	/*
	245	* Load up the fixed address of the GART SRAMS which hold our GATT table.
	246	*/
	247	temp = agp_bridge->current_size;
	248	page_order = A_SIZE_8(temp)->page_order;
	249	num_entries = A_SIZE_8(temp)->num_entries;
	250
	251	i460.gatt = ioremap(INTEL_I460_ATTBASE, PAGE_SIZE << page_order);
	252
	253	/* These are no good, the should be removed from the agp_bridge strucure... */
	254	agp_bridge->gatt_table_real = NULL;
	255	agp_bridge->gatt_table = NULL;
	256	agp_bridge->gatt_bus_addr = 0;
	257
	258	for (i = 0; i < num_entries; ++i)
	259	WR_GATT(i, 0);
	260	WR_FLUSH_GATT(i - 1);
	261	return 0;
	262	}
	263
	264	static int i460_free_gatt_table (struct agp_bridge_data *bridge)
	265	{
	266	int num_entries, i;
	267	void *temp;
	268
	269	temp = agp_bridge->current_size;
	270
	271	num_entries = A_SIZE_8(temp)->num_entries;
	272
	273	for (i = 0; i < num_entries; ++i)
	274	WR_GATT(i, 0);
	275	WR_FLUSH_GATT(num_entries - 1);
	276
	277	iounmap(i460.gatt);
	278	return 0;
	279	}
	280
	281	/*
	282	* The following functions are called when the I/O (GART) page size is smaller than
	283	* PAGE_SIZE.
	284	*/
	285
	286	static int i460_insert_memory_small_io_page (struct agp_memory *mem,
	287	off_t pg_start, int type)
	288	{
	289	unsigned long paddr, io_pg_start, io_page_size;
	290	int i, j, k, num_entries;
	291	void *temp;
	292
	293	pr_debug("i460_insert_memory_small_io_page(mem=%p, pg_start=%ld, type=%d, paddr0=0x%lx)\n",
	294	mem, pg_start, type, mem->memory[0]);
	295
a030ce44 TH	296	if (type >= AGP_USER_TYPES \|\| mem->type >= AGP_USER_TYPES)
	297	return -EINVAL;
	298
1da177e4 LT	299	io_pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
	300
	301	temp = agp_bridge->current_size;
	302	num_entries = A_SIZE_8(temp)->num_entries;
	303
	304	if ((io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count) > num_entries) {
	305	printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
	306	return -EINVAL;
	307	}
	308
	309	j = io_pg_start;
	310	while (j < (io_pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count)) {
	311	if (!PGE_EMPTY(agp_bridge, RD_GATT(j))) {
	312	pr_debug("i460_insert_memory_small_io_page: GATT[%d]=0x%x is busy\n",
	313	j, RD_GATT(j));
	314	return -EBUSY;
	315	}
	316	j++;
	317	}
	318
	319	io_page_size = 1UL << I460_IO_PAGE_SHIFT;
	320	for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
	321	paddr = mem->memory[i];
	322	for (k = 0; k < I460_IOPAGES_PER_KPAGE; k++, j++, paddr += io_page_size)
	323	WR_GATT(j, agp_bridge->driver->mask_memory(agp_bridge,
	324	paddr, mem->type));
	325	}
	326	WR_FLUSH_GATT(j - 1);
	327	return 0;
	328	}
	329
	330	static int i460_remove_memory_small_io_page(struct agp_memory *mem,
	331	off_t pg_start, int type)
	332	{
	333	int i;
	334
	335	pr_debug("i460_remove_memory_small_io_page(mem=%p, pg_start=%ld, type=%d)\n",
	336	mem, pg_start, type);
	337
	338	pg_start = I460_IOPAGES_PER_KPAGE * pg_start;
	339
	340	for (i = pg_start; i < (pg_start + I460_IOPAGES_PER_KPAGE * mem->page_count); i++)
	341	WR_GATT(i, 0);
	342	WR_FLUSH_GATT(i - 1);
	343	return 0;
	344	}
	345
	346	#if I460_LARGE_IO_PAGES
	347
	348	/*
	349	* These functions are called when the I/O (GART) page size exceeds PAGE_SIZE.
	350	*
	351	* This situation is interesting since AGP memory allocations that are smaller than a
	352	* single GART page are possible. The i460.lp_desc array tracks partial allocation of the
	353	* large GART pages to work around this issue.
	354	*
	355	* i460.lp_desc[pg_num].refcount tracks the number of kernel pages in use within GART page
	356	* pg_num. i460.lp_desc[pg_num].paddr is the physical address of the large page and
	357	* i460.lp_desc[pg_num].alloced_map is a bitmap of kernel pages that are in use (allocated).
	358	*/
	359
	360	static int i460_alloc_large_page (struct lp_desc *lp)
	361	{
	362	unsigned long order = I460_IO_PAGE_SHIFT - PAGE_SHIFT;
363	size_t map_size;
364	void *lpage;
365
366	lpage = (void *) __get_free_pages(GFP_KERNEL, order);
367	if (!lpage) {
368	printk(KERN_ERR PFX "Couldn't alloc 4M GART page...\n");
369	return -ENOMEM;
370	}
371
372	map_size = ((I460_KPAGES_PER_IOPAGE + BITS_PER_LONG - 1) & -BITS_PER_LONG)/8;
0ea27d9f	373	lp->alloced_map = kzalloc(map_size, GFP_KERNEL);
1da177e4 LT	374	if (!lp->alloced_map) {
	375	free_pages((unsigned long) lpage, order);
	376	printk(KERN_ERR PFX "Out of memory, we're in trouble...\n");
	377	return -ENOMEM;
	378	}
1da177e4	379
07eee78e	380	lp->paddr = virt_to_gart(lpage);
1da177e4 LT	381	lp->refcount = 0;
	382	atomic_add(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
	383	return 0;
	384	}
	385
	386	static void i460_free_large_page (struct lp_desc *lp)
	387	{
	388	kfree(lp->alloced_map);
	389	lp->alloced_map = NULL;
	390
07eee78e	391	free_pages((unsigned long) gart_to_virt(lp->paddr), I460_IO_PAGE_SHIFT - PAGE_SHIFT);
1da177e4 LT	392	atomic_sub(I460_KPAGES_PER_IOPAGE, &agp_bridge->current_memory_agp);
	393	}
	394
	395	static int i460_insert_memory_large_io_page (struct agp_memory *mem,
	396	off_t pg_start, int type)
	397	{
	398	int i, start_offset, end_offset, idx, pg, num_entries;
	399	struct lp_desc start, end, *lp;
	400	void *temp;
	401
a030ce44 TH	402	if (type >= AGP_USER_TYPES \|\| mem->type >= AGP_USER_TYPES)
	403	return -EINVAL;
	404
1da177e4 LT	405	temp = agp_bridge->current_size;
	406	num_entries = A_SIZE_8(temp)->num_entries;
	407
	408	/* Figure out what pg_start means in terms of our large GART pages */
6a92a4e0 DJ	409	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
	410	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
	411	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
	412	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
1da177e4 LT	413
	414	if (end > i460.lp_desc + num_entries) {
	415	printk(KERN_ERR PFX "Looks like we're out of AGP memory\n");
	416	return -EINVAL;
	417	}
	418
	419	/* Check if the requested region of the aperture is free */
	420	for (lp = start; lp <= end; ++lp) {
	421	if (!lp->alloced_map)
	422	continue; /* OK, the entire large page is available... */
	423
	424	for (idx = ((lp == start) ? start_offset : 0);
	425	idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
	426	idx++)
	427	{
	428	if (test_bit(idx, lp->alloced_map))
	429	return -EBUSY;
	430	}
	431	}
	432
	433	for (lp = start, i = 0; lp <= end; ++lp) {
	434	if (!lp->alloced_map) {
	435	/* Allocate new GART pages... */
	436	if (i460_alloc_large_page(lp) < 0)
	437	return -ENOMEM;
	438	pg = lp - i460.lp_desc;
	439	WR_GATT(pg, agp_bridge->driver->mask_memory(agp_bridge,
	440	lp->paddr, 0));
	441	WR_FLUSH_GATT(pg);
	442	}
	443
	444	for (idx = ((lp == start) ? start_offset : 0);
	445	idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
	446	idx++, i++)
	447	{
	448	mem->memory[i] = lp->paddr + idx*PAGE_SIZE;
	449	__set_bit(idx, lp->alloced_map);
	450	++lp->refcount;
	451	}
	452	}
	453	return 0;
	454	}
	455
	456	static int i460_remove_memory_large_io_page (struct agp_memory *mem,
	457	off_t pg_start, int type)
	458	{
	459	int i, pg, start_offset, end_offset, idx, num_entries;
	460	struct lp_desc start, end, *lp;
	461	void *temp;
	462
	463	temp = agp_bridge->driver->current_size;
	464	num_entries = A_SIZE_8(temp)->num_entries;
	465
	466	/* Figure out what pg_start means in terms of our large GART pages */
6a92a4e0 DJ	467	start = &i460.lp_desc[pg_start / I460_KPAGES_PER_IOPAGE];
	468	end = &i460.lp_desc[(pg_start + mem->page_count - 1) / I460_KPAGES_PER_IOPAGE];
	469	start_offset = pg_start % I460_KPAGES_PER_IOPAGE;
	470	end_offset = (pg_start + mem->page_count - 1) % I460_KPAGES_PER_IOPAGE;
1da177e4 LT	471
	472	for (i = 0, lp = start; lp <= end; ++lp) {
	473	for (idx = ((lp == start) ? start_offset : 0);
	474	idx < ((lp == end) ? (end_offset + 1) : I460_KPAGES_PER_IOPAGE);
	475	idx++, i++)
	476	{
	477	mem->memory[i] = 0;
	478	__clear_bit(idx, lp->alloced_map);
	479	--lp->refcount;
	480	}
	481
	482	/* Free GART pages if they are unused */
	483	if (lp->refcount == 0) {
	484	pg = lp - i460.lp_desc;
	485	WR_GATT(pg, 0);
	486	WR_FLUSH_GATT(pg);
	487	i460_free_large_page(lp);
	488	}
	489	}
	490	return 0;
	491	}
	492
	493	/* Wrapper routines to call the approriate {small_io_page,large_io_page} function */
	494
	495	static int i460_insert_memory (struct agp_memory *mem,
	496	off_t pg_start, int type)
	497	{
	498	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
	499	return i460_insert_memory_small_io_page(mem, pg_start, type);
	500	else
	501	return i460_insert_memory_large_io_page(mem, pg_start, type);
	502	}
	503
	504	static int i460_remove_memory (struct agp_memory *mem,
	505	off_t pg_start, int type)
	506	{
	507	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT)
	508	return i460_remove_memory_small_io_page(mem, pg_start, type);
	509	else
	510	return i460_remove_memory_large_io_page(mem, pg_start, type);
	511	}
	512
	513	/*
	514	* If the I/O (GART) page size is bigger than the kernel page size, we don't want to
	515	* allocate memory until we know where it is to be bound in the aperture (a
	516	* multi-kernel-page alloc might fit inside of an already allocated GART page).
	517	*
	518	* Let's just hope nobody counts on the allocated AGP memory being there before bind time
	519	* (I don't think current drivers do)...
	520	*/
	521	static void i460_alloc_page (struct agp_bridge_data bridge)
	522	{
	523	void *page;
	524
88d51967	525	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
1da177e4	526	page = agp_generic_alloc_page(agp_bridge);
88d51967 AH	527	global_flush_tlb();
88d51967 AH	528	} else
1da177e4 LT	529	/* Returning NULL would cause problems */
	530	/* AK: really dubious code. */
	531	page = (void *)~0UL;
	532	return page;
	533	}
	534
	535	static void i460_destroy_page (void *page)
	536	{
88d51967	537	if (I460_IO_PAGE_SHIFT <= PAGE_SHIFT) {
1da177e4	538	agp_generic_destroy_page(page);
88d51967 AH	539	global_flush_tlb();
88d51967 AH	540	}
1da177e4 LT	541	}
	542
	543	#endif /* I460_LARGE_IO_PAGES */
	544
	545	static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
	546	unsigned long addr, int type)
	547	{
	548	/* Make sure the returned address is a valid GATT entry */
	549	return bridge->driver->masks[0].mask
49ebd7c6	550	\| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xfffff000) >> 12);
1da177e4 LT	551	}
	552
	553	struct agp_bridge_driver intel_i460_driver = {
	554	.owner = THIS_MODULE,
	555	.aperture_sizes = i460_sizes,
	556	.size_type = U8_APER_SIZE,
	557	.num_aperture_sizes = 3,
	558	.configure = i460_configure,
	559	.fetch_size = i460_fetch_size,
	560	.cleanup = i460_cleanup,
	561	.tlb_flush = i460_tlb_flush,
	562	.mask_memory = i460_mask_memory,
	563	.masks = i460_masks,
	564	.agp_enable = agp_generic_enable,
	565	.cache_flush = global_cache_flush,
	566	.create_gatt_table = i460_create_gatt_table,
	567	.free_gatt_table = i460_free_gatt_table,
	568	#if I460_LARGE_IO_PAGES
	569	.insert_memory = i460_insert_memory,
	570	.remove_memory = i460_remove_memory,
	571	.agp_alloc_page = i460_alloc_page,
	572	.agp_destroy_page = i460_destroy_page,
	573	#else
	574	.insert_memory = i460_insert_memory_small_io_page,
	575	.remove_memory = i460_remove_memory_small_io_page,
	576	.agp_alloc_page = agp_generic_alloc_page,
	577	.agp_destroy_page = agp_generic_destroy_page,
	578	#endif
	579	.alloc_by_type = agp_generic_alloc_by_type,
	580	.free_by_type = agp_generic_free_by_type,
a030ce44	581	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	582	.cant_use_aperture = 1,
	583	};
	584
	585	static int __devinit agp_intel_i460_probe(struct pci_dev *pdev,
	586	const struct pci_device_id *ent)
	587	{
	588	struct agp_bridge_data *bridge;
	589	u8 cap_ptr;
	590
	591	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	592	if (!cap_ptr)
	593	return -ENODEV;
	594
	595	bridge = agp_alloc_bridge();
	596	if (!bridge)
	597	return -ENOMEM;
	598
	599	bridge->driver = &intel_i460_driver;
	600	bridge->dev = pdev;
	601	bridge->capndx = cap_ptr;
	602
	603	printk(KERN_INFO PFX "Detected Intel 460GX chipset\n");
	604
	605	pci_set_drvdata(pdev, bridge);
	606	return agp_add_bridge(bridge);
	607	}
	608
	609	static void __devexit agp_intel_i460_remove(struct pci_dev *pdev)
	610	{
	611	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
	612
	613	agp_remove_bridge(bridge);
	614	agp_put_bridge(bridge);
	615	}
	616
	617	static struct pci_device_id agp_intel_i460_pci_table[] = {
	618	{
	619	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	620	.class_mask = ~0,
	621	.vendor = PCI_VENDOR_ID_INTEL,
	622	.device = PCI_DEVICE_ID_INTEL_84460GX,
	623	.subvendor = PCI_ANY_ID,
	624	.subdevice = PCI_ANY_ID,
	625	},
	626	{ }
	627	};
	628
	629	MODULE_DEVICE_TABLE(pci, agp_intel_i460_pci_table);
	630
	631	static struct pci_driver agp_intel_i460_pci_driver = {
	632	.name = "agpgart-intel-i460",
	633	.id_table = agp_intel_i460_pci_table,
	634	.probe = agp_intel_i460_probe,
	635	.remove = __devexit_p(agp_intel_i460_remove),
	636	};
	637
	638	static int __init agp_intel_i460_init(void)
	639	{
	640	if (agp_off)
	641	return -EINVAL;
	642	return pci_register_driver(&agp_intel_i460_pci_driver);
	643	}
	644
	645	static void __exit agp_intel_i460_cleanup(void)
646	{
647	pci_unregister_driver(&agp_intel_i460_pci_driver);
648	}
649
650	module_init(agp_intel_i460_init);
651	module_exit(agp_intel_i460_cleanup);
652
653	MODULE_AUTHOR("Chris Ahna <Christopher.J.Ahna@intel.com>");
654	MODULE_LICENSE("GPL and additional rights");