Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * AMD K7 AGPGART routines. | |
3 | */ | |
4 | ||
5 | #include <linux/module.h> | |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
8 | #include <linux/agp_backend.h> | |
9 | #include <linux/gfp.h> | |
10 | #include <linux/page-flags.h> | |
11 | #include <linux/mm.h> | |
12 | #include "agp.h" | |
13 | ||
14 | #define AMD_MMBASE 0x14 | |
15 | #define AMD_APSIZE 0xac | |
16 | #define AMD_MODECNTL 0xb0 | |
17 | #define AMD_MODECNTL2 0xb2 | |
18 | #define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */ | |
19 | #define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */ | |
20 | #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */ | |
21 | #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */ | |
22 | ||
23 | static struct pci_device_id agp_amdk7_pci_table[]; | |
24 | ||
25 | struct amd_page_map { | |
26 | unsigned long *real; | |
27 | unsigned long __iomem *remapped; | |
28 | }; | |
29 | ||
30 | static struct _amd_irongate_private { | |
31 | volatile u8 __iomem *registers; | |
32 | struct amd_page_map **gatt_pages; | |
33 | int num_tables; | |
34 | } amd_irongate_private; | |
35 | ||
36 | static int amd_create_page_map(struct amd_page_map *page_map) | |
37 | { | |
38 | int i; | |
39 | ||
40 | page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); | |
41 | if (page_map->real == NULL) | |
42 | return -ENOMEM; | |
43 | ||
44 | SetPageReserved(virt_to_page(page_map->real)); | |
45 | global_cache_flush(); | |
46 | page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real), | |
47 | PAGE_SIZE); | |
48 | if (page_map->remapped == NULL) { | |
49 | ClearPageReserved(virt_to_page(page_map->real)); | |
50 | free_page((unsigned long) page_map->real); | |
51 | page_map->real = NULL; | |
52 | return -ENOMEM; | |
53 | } | |
54 | global_cache_flush(); | |
55 | ||
56 | for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) { | |
57 | writel(agp_bridge->scratch_page, page_map->remapped+i); | |
58 | readl(page_map->remapped+i); /* PCI Posting. */ | |
59 | } | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
64 | static void amd_free_page_map(struct amd_page_map *page_map) | |
65 | { | |
66 | iounmap(page_map->remapped); | |
67 | ClearPageReserved(virt_to_page(page_map->real)); | |
68 | free_page((unsigned long) page_map->real); | |
69 | } | |
70 | ||
71 | static void amd_free_gatt_pages(void) | |
72 | { | |
73 | int i; | |
74 | struct amd_page_map **tables; | |
75 | struct amd_page_map *entry; | |
76 | ||
77 | tables = amd_irongate_private.gatt_pages; | |
78 | for (i = 0; i < amd_irongate_private.num_tables; i++) { | |
79 | entry = tables[i]; | |
80 | if (entry != NULL) { | |
81 | if (entry->real != NULL) | |
82 | amd_free_page_map(entry); | |
83 | kfree(entry); | |
84 | } | |
85 | } | |
86 | kfree(tables); | |
87 | amd_irongate_private.gatt_pages = NULL; | |
88 | } | |
89 | ||
90 | static int amd_create_gatt_pages(int nr_tables) | |
91 | { | |
92 | struct amd_page_map **tables; | |
93 | struct amd_page_map *entry; | |
94 | int retval = 0; | |
95 | int i; | |
96 | ||
97 | tables = kmalloc((nr_tables + 1) * sizeof(struct amd_page_map *), | |
98 | GFP_KERNEL); | |
99 | if (tables == NULL) | |
100 | return -ENOMEM; | |
101 | ||
102 | memset (tables, 0, sizeof(struct amd_page_map *) * (nr_tables + 1)); | |
103 | for (i = 0; i < nr_tables; i++) { | |
104 | entry = kmalloc(sizeof(struct amd_page_map), GFP_KERNEL); | |
105 | if (entry == NULL) { | |
106 | retval = -ENOMEM; | |
107 | break; | |
108 | } | |
109 | memset (entry, 0, sizeof(struct amd_page_map)); | |
110 | tables[i] = entry; | |
111 | retval = amd_create_page_map(entry); | |
112 | if (retval != 0) | |
113 | break; | |
114 | } | |
115 | amd_irongate_private.num_tables = nr_tables; | |
116 | amd_irongate_private.gatt_pages = tables; | |
117 | ||
118 | if (retval != 0) | |
119 | amd_free_gatt_pages(); | |
120 | ||
121 | return retval; | |
122 | } | |
123 | ||
124 | /* Since we don't need contigious memory we just try | |
125 | * to get the gatt table once | |
126 | */ | |
127 | ||
128 | #define GET_PAGE_DIR_OFF(addr) (addr >> 22) | |
129 | #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ | |
130 | GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) | |
131 | #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) | |
132 | #define GET_GATT(addr) (amd_irongate_private.gatt_pages[\ | |
133 | GET_PAGE_DIR_IDX(addr)]->remapped) | |
134 | ||
135 | static int amd_create_gatt_table(struct agp_bridge_data *bridge) | |
136 | { | |
137 | struct aper_size_info_lvl2 *value; | |
138 | struct amd_page_map page_dir; | |
139 | unsigned long addr; | |
140 | int retval; | |
141 | u32 temp; | |
142 | int i; | |
143 | ||
144 | value = A_SIZE_LVL2(agp_bridge->current_size); | |
145 | retval = amd_create_page_map(&page_dir); | |
146 | if (retval != 0) | |
147 | return retval; | |
148 | ||
149 | retval = amd_create_gatt_pages(value->num_entries / 1024); | |
150 | if (retval != 0) { | |
151 | amd_free_page_map(&page_dir); | |
152 | return retval; | |
153 | } | |
154 | ||
155 | agp_bridge->gatt_table_real = (u32 *)page_dir.real; | |
156 | agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped; | |
157 | agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); | |
158 | ||
159 | /* Get the address for the gart region. | |
160 | * This is a bus address even on the alpha, b/c its | |
161 | * used to program the agp master not the cpu | |
162 | */ | |
163 | ||
164 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
165 | addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
166 | agp_bridge->gart_bus_addr = addr; | |
167 | ||
168 | /* Calculate the agp offset */ | |
169 | for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) { | |
170 | writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1, | |
171 | page_dir.remapped+GET_PAGE_DIR_OFF(addr)); | |
172 | readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */ | |
173 | } | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | static int amd_free_gatt_table(struct agp_bridge_data *bridge) | |
179 | { | |
180 | struct amd_page_map page_dir; | |
181 | ||
182 | page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; | |
183 | page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table; | |
184 | ||
185 | amd_free_gatt_pages(); | |
186 | amd_free_page_map(&page_dir); | |
187 | return 0; | |
188 | } | |
189 | ||
190 | static int amd_irongate_fetch_size(void) | |
191 | { | |
192 | int i; | |
193 | u32 temp; | |
194 | struct aper_size_info_lvl2 *values; | |
195 | ||
196 | pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); | |
197 | temp = (temp & 0x0000000e); | |
198 | values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); | |
199 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
200 | if (temp == values[i].size_value) { | |
201 | agp_bridge->previous_size = | |
202 | agp_bridge->current_size = (void *) (values + i); | |
203 | ||
204 | agp_bridge->aperture_size_idx = i; | |
205 | return values[i].size; | |
206 | } | |
207 | } | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int amd_irongate_configure(void) | |
213 | { | |
214 | struct aper_size_info_lvl2 *current_size; | |
215 | u32 temp; | |
216 | u16 enable_reg; | |
217 | ||
218 | current_size = A_SIZE_LVL2(agp_bridge->current_size); | |
219 | ||
220 | /* Get the memory mapped registers */ | |
221 | pci_read_config_dword(agp_bridge->dev, AMD_MMBASE, &temp); | |
222 | temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
223 | amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); | |
224 | ||
225 | /* Write out the address of the gatt table */ | |
226 | writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); | |
227 | readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ | |
228 | ||
229 | /* Write the Sync register */ | |
230 | pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80); | |
231 | ||
232 | /* Set indexing mode */ | |
233 | pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00); | |
234 | ||
235 | /* Write the enable register */ | |
236 | enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); | |
237 | enable_reg = (enable_reg | 0x0004); | |
238 | writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); | |
239 | readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ | |
240 | ||
241 | /* Write out the size register */ | |
242 | pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); | |
243 | temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1); | |
244 | pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); | |
245 | ||
246 | /* Flush the tlb */ | |
247 | writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); | |
248 | readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/ | |
249 | return 0; | |
250 | } | |
251 | ||
252 | static void amd_irongate_cleanup(void) | |
253 | { | |
254 | struct aper_size_info_lvl2 *previous_size; | |
255 | u32 temp; | |
256 | u16 enable_reg; | |
257 | ||
258 | previous_size = A_SIZE_LVL2(agp_bridge->previous_size); | |
259 | ||
260 | enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); | |
261 | enable_reg = (enable_reg & ~(0x0004)); | |
262 | writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); | |
263 | readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ | |
264 | ||
265 | /* Write back the previous size and disable gart translation */ | |
266 | pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp); | |
267 | temp = ((temp & ~(0x0000000f)) | previous_size->size_value); | |
268 | pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp); | |
269 | iounmap((void __iomem *) amd_irongate_private.registers); | |
270 | } | |
271 | ||
272 | /* | |
273 | * This routine could be implemented by taking the addresses | |
274 | * written to the GATT, and flushing them individually. However | |
275 | * currently it just flushes the whole table. Which is probably | |
276 | * more efficent, since agp_memory blocks can be a large number of | |
277 | * entries. | |
278 | */ | |
279 | ||
280 | static void amd_irongate_tlbflush(struct agp_memory *temp) | |
281 | { | |
282 | writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); | |
283 | readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */ | |
284 | } | |
285 | ||
286 | static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type) | |
287 | { | |
288 | int i, j, num_entries; | |
289 | unsigned long __iomem *cur_gatt; | |
290 | unsigned long addr; | |
291 | ||
292 | num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; | |
293 | ||
294 | if (type != 0 || mem->type != 0) | |
295 | return -EINVAL; | |
296 | ||
297 | if ((pg_start + mem->page_count) > num_entries) | |
298 | return -EINVAL; | |
299 | ||
300 | j = pg_start; | |
301 | while (j < (pg_start + mem->page_count)) { | |
302 | addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; | |
303 | cur_gatt = GET_GATT(addr); | |
304 | if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr)))) | |
305 | return -EBUSY; | |
306 | j++; | |
307 | } | |
308 | ||
309 | if (mem->is_flushed == FALSE) { | |
310 | global_cache_flush(); | |
311 | mem->is_flushed = TRUE; | |
312 | } | |
313 | ||
314 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
315 | addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; | |
316 | cur_gatt = GET_GATT(addr); | |
317 | writel(agp_generic_mask_memory(agp_bridge, | |
318 | mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr)); | |
319 | readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ | |
320 | } | |
321 | amd_irongate_tlbflush(mem); | |
322 | return 0; | |
323 | } | |
324 | ||
325 | static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type) | |
326 | { | |
327 | int i; | |
328 | unsigned long __iomem *cur_gatt; | |
329 | unsigned long addr; | |
330 | ||
331 | if (type != 0 || mem->type != 0) | |
332 | return -EINVAL; | |
333 | ||
334 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
335 | addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; | |
336 | cur_gatt = GET_GATT(addr); | |
337 | writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); | |
338 | readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */ | |
339 | } | |
340 | ||
341 | amd_irongate_tlbflush(mem); | |
342 | return 0; | |
343 | } | |
344 | ||
345 | static struct aper_size_info_lvl2 amd_irongate_sizes[7] = | |
346 | { | |
347 | {2048, 524288, 0x0000000c}, | |
348 | {1024, 262144, 0x0000000a}, | |
349 | {512, 131072, 0x00000008}, | |
350 | {256, 65536, 0x00000006}, | |
351 | {128, 32768, 0x00000004}, | |
352 | {64, 16384, 0x00000002}, | |
353 | {32, 8192, 0x00000000} | |
354 | }; | |
355 | ||
356 | static struct gatt_mask amd_irongate_masks[] = | |
357 | { | |
358 | {.mask = 1, .type = 0} | |
359 | }; | |
360 | ||
408b664a | 361 | static struct agp_bridge_driver amd_irongate_driver = { |
1da177e4 LT |
362 | .owner = THIS_MODULE, |
363 | .aperture_sizes = amd_irongate_sizes, | |
364 | .size_type = LVL2_APER_SIZE, | |
365 | .num_aperture_sizes = 7, | |
366 | .configure = amd_irongate_configure, | |
367 | .fetch_size = amd_irongate_fetch_size, | |
368 | .cleanup = amd_irongate_cleanup, | |
369 | .tlb_flush = amd_irongate_tlbflush, | |
370 | .mask_memory = agp_generic_mask_memory, | |
371 | .masks = amd_irongate_masks, | |
372 | .agp_enable = agp_generic_enable, | |
373 | .cache_flush = global_cache_flush, | |
374 | .create_gatt_table = amd_create_gatt_table, | |
375 | .free_gatt_table = amd_free_gatt_table, | |
376 | .insert_memory = amd_insert_memory, | |
377 | .remove_memory = amd_remove_memory, | |
378 | .alloc_by_type = agp_generic_alloc_by_type, | |
379 | .free_by_type = agp_generic_free_by_type, | |
380 | .agp_alloc_page = agp_generic_alloc_page, | |
381 | .agp_destroy_page = agp_generic_destroy_page, | |
382 | }; | |
383 | ||
384 | static struct agp_device_ids amd_agp_device_ids[] __devinitdata = | |
385 | { | |
386 | { | |
387 | .device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006, | |
388 | .chipset_name = "Irongate", | |
389 | }, | |
390 | { | |
391 | .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E, | |
392 | .chipset_name = "761", | |
393 | }, | |
394 | { | |
395 | .device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C, | |
396 | .chipset_name = "760MP", | |
397 | }, | |
398 | { }, /* dummy final entry, always present */ | |
399 | }; | |
400 | ||
401 | static int __devinit agp_amdk7_probe(struct pci_dev *pdev, | |
402 | const struct pci_device_id *ent) | |
403 | { | |
404 | struct agp_bridge_data *bridge; | |
405 | u8 cap_ptr; | |
406 | int j; | |
407 | ||
408 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
409 | if (!cap_ptr) | |
410 | return -ENODEV; | |
411 | ||
412 | j = ent - agp_amdk7_pci_table; | |
413 | printk(KERN_INFO PFX "Detected AMD %s chipset\n", | |
414 | amd_agp_device_ids[j].chipset_name); | |
415 | ||
416 | bridge = agp_alloc_bridge(); | |
417 | if (!bridge) | |
418 | return -ENOMEM; | |
419 | ||
420 | bridge->driver = &amd_irongate_driver; | |
421 | bridge->dev_private_data = &amd_irongate_private, | |
422 | bridge->dev = pdev; | |
423 | bridge->capndx = cap_ptr; | |
424 | ||
425 | /* 751 Errata (22564_B-1.PDF) | |
426 | erratum 20: strobe glitch with Nvidia NV10 GeForce cards. | |
427 | system controller may experience noise due to strong drive strengths | |
428 | */ | |
429 | if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) { | |
430 | u8 cap_ptr=0; | |
431 | struct pci_dev *gfxcard=NULL; | |
432 | while (!cap_ptr) { | |
433 | gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard); | |
434 | if (!gfxcard) { | |
435 | printk (KERN_INFO PFX "Couldn't find an AGP VGA controller.\n"); | |
436 | return -ENODEV; | |
437 | } | |
438 | cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP); | |
439 | if (!cap_ptr) { | |
440 | pci_dev_put(gfxcard); | |
441 | continue; | |
442 | } | |
443 | } | |
444 | ||
445 | /* With so many variants of NVidia cards, it's simpler just | |
446 | to blacklist them all, and then whitelist them as needed | |
447 | (if necessary at all). */ | |
448 | if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) { | |
449 | agp_bridge->flags |= AGP_ERRATA_1X; | |
450 | printk (KERN_INFO PFX "AMD 751 chipset with NVidia GeForce detected. Forcing to 1X due to errata.\n"); | |
451 | } | |
452 | pci_dev_put(gfxcard); | |
453 | } | |
454 | ||
455 | /* 761 Errata (23613_F.pdf) | |
456 | * Revisions B0/B1 were a disaster. | |
457 | * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X | |
458 | * erratum 45: Timing problem prevents fast writes -- Disable fast write. | |
459 | * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing. | |
460 | * With this lot disabled, we should prevent lockups. */ | |
461 | if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) { | |
462 | u8 revision=0; | |
463 | pci_read_config_byte(pdev, PCI_REVISION_ID, &revision); | |
464 | if (revision == 0x10 || revision == 0x11) { | |
465 | agp_bridge->flags = AGP_ERRATA_FASTWRITES; | |
466 | agp_bridge->flags |= AGP_ERRATA_SBA; | |
467 | agp_bridge->flags |= AGP_ERRATA_1X; | |
468 | printk (KERN_INFO PFX "AMD 761 chipset with errata detected - disabling AGP fast writes & SBA and forcing to 1X.\n"); | |
469 | } | |
470 | } | |
471 | ||
472 | /* Fill in the mode register */ | |
473 | pci_read_config_dword(pdev, | |
474 | bridge->capndx+PCI_AGP_STATUS, | |
475 | &bridge->mode); | |
476 | ||
477 | pci_set_drvdata(pdev, bridge); | |
478 | return agp_add_bridge(bridge); | |
479 | } | |
480 | ||
481 | static void __devexit agp_amdk7_remove(struct pci_dev *pdev) | |
482 | { | |
483 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
484 | ||
485 | agp_remove_bridge(bridge); | |
486 | agp_put_bridge(bridge); | |
487 | } | |
488 | ||
489 | /* must be the same order as name table above */ | |
490 | static struct pci_device_id agp_amdk7_pci_table[] = { | |
491 | { | |
492 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
493 | .class_mask = ~0, | |
494 | .vendor = PCI_VENDOR_ID_AMD, | |
495 | .device = PCI_DEVICE_ID_AMD_FE_GATE_7006, | |
496 | .subvendor = PCI_ANY_ID, | |
497 | .subdevice = PCI_ANY_ID, | |
498 | }, | |
499 | { | |
500 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
501 | .class_mask = ~0, | |
502 | .vendor = PCI_VENDOR_ID_AMD, | |
503 | .device = PCI_DEVICE_ID_AMD_FE_GATE_700E, | |
504 | .subvendor = PCI_ANY_ID, | |
505 | .subdevice = PCI_ANY_ID, | |
506 | }, | |
507 | { | |
508 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
509 | .class_mask = ~0, | |
510 | .vendor = PCI_VENDOR_ID_AMD, | |
511 | .device = PCI_DEVICE_ID_AMD_FE_GATE_700C, | |
512 | .subvendor = PCI_ANY_ID, | |
513 | .subdevice = PCI_ANY_ID, | |
514 | }, | |
515 | { } | |
516 | }; | |
517 | ||
518 | MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table); | |
519 | ||
520 | static struct pci_driver agp_amdk7_pci_driver = { | |
521 | .name = "agpgart-amdk7", | |
522 | .id_table = agp_amdk7_pci_table, | |
523 | .probe = agp_amdk7_probe, | |
524 | .remove = agp_amdk7_remove, | |
525 | }; | |
526 | ||
527 | static int __init agp_amdk7_init(void) | |
528 | { | |
529 | if (agp_off) | |
530 | return -EINVAL; | |
531 | return pci_register_driver(&agp_amdk7_pci_driver); | |
532 | } | |
533 | ||
534 | static void __exit agp_amdk7_cleanup(void) | |
535 | { | |
536 | pci_unregister_driver(&agp_amdk7_pci_driver); | |
537 | } | |
538 | ||
539 | module_init(agp_amdk7_init); | |
540 | module_exit(agp_amdk7_cleanup); | |
541 | ||
542 | MODULE_LICENSE("GPL and additional rights"); |