[linux-2.6-block.git] / drivers / char / agp / amd-k7-agp.c

/*
 * AMD K7 AGPGART routines.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/agp_backend.h>
#include <linux/page-flags.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <asm/set_memory.h>
#include "agp.h"

#define AMD_MMBASE_BAR	1
#define AMD_APSIZE	0xac
#define AMD_MODECNTL	0xb0
#define AMD_MODECNTL2	0xb2
#define AMD_GARTENABLE	0x02	/* In mmio region (16-bit register) */
#define AMD_ATTBASE	0x04	/* In mmio region (32-bit register) */
#define AMD_TLBFLUSH	0x0c	/* In mmio region (32-bit register) */
#define AMD_CACHEENTRY	0x10	/* In mmio region (32-bit register) */

static const struct pci_device_id agp_amdk7_pci_table[];

struct amd_page_map {
	unsigned long *real;
	unsigned long __iomem *remapped;
};

static struct _amd_irongate_private {
	volatile u8 __iomem *registers;
	struct amd_page_map **gatt_pages;
	int num_tables;
} amd_irongate_private;

static int amd_create_page_map(struct amd_page_map *page_map)
{
	int i;

	page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
	if (page_map->real == NULL)
		return -ENOMEM;

	set_memory_uc((unsigned long)page_map->real, 1);
	page_map->remapped = page_map->real;

	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
		writel(agp_bridge->scratch_page, page_map->remapped+i);
		readl(page_map->remapped+i);	/* PCI Posting. */
	}

	return 0;
}

static void amd_free_page_map(struct amd_page_map *page_map)
{
	set_memory_wb((unsigned long)page_map->real, 1);
	free_page((unsigned long) page_map->real);
}

static void amd_free_gatt_pages(void)
{
	int i;
	struct amd_page_map **tables;
	struct amd_page_map *entry;

	tables = amd_irongate_private.gatt_pages;
	for (i = 0; i < amd_irongate_private.num_tables; i++) {
		entry = tables[i];
		if (entry != NULL) {
			if (entry->real != NULL)
				amd_free_page_map(entry);
			kfree(entry);
		}
	}
	kfree(tables);
	amd_irongate_private.gatt_pages = NULL;
}

static int amd_create_gatt_pages(int nr_tables)
{
	struct amd_page_map **tables;
	struct amd_page_map *entry;
	int retval = 0;
	int i;

	tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
	if (tables == NULL)
		return -ENOMEM;

	for (i = 0; i < nr_tables; i++) {
		entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
		tables[i] = entry;
		if (entry == NULL) {
			retval = -ENOMEM;
			break;
		}
		retval = amd_create_page_map(entry);
		if (retval != 0)
			break;
	}
	amd_irongate_private.num_tables = i;
	amd_irongate_private.gatt_pages = tables;

	if (retval != 0)
		amd_free_gatt_pages();

	return retval;
}

/* Since we don't need contiguous memory we just try
 * to get the gatt table once
 */

#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
	GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
	GET_PAGE_DIR_IDX(addr)]->remapped)

static int amd_create_gatt_table(struct agp_bridge_data *bridge)
{
	struct aper_size_info_lvl2 *value;
	struct amd_page_map page_dir;
	unsigned long __iomem *cur_gatt;
	unsigned long addr;
	int retval;
	int i;

	value = A_SIZE_LVL2(agp_bridge->current_size);
	retval = amd_create_page_map(&page_dir);
	if (retval != 0)
		return retval;

	retval = amd_create_gatt_pages(value->num_entries / 1024);
	if (retval != 0) {
		amd_free_page_map(&page_dir);
		return retval;
	}

	agp_bridge->gatt_table_real = (u32 *)page_dir.real;
	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
	agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);

	/* Get the address for the gart region.
	 * This is a bus address even on the alpha, b/c its
	 * used to program the agp master not the cpu
	 */

	addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
	agp_bridge->gart_bus_addr = addr;

	/* Calculate the agp offset */
	for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
		writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) | 1,
			page_dir.remapped+GET_PAGE_DIR_OFF(addr));
		readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr));	/* PCI Posting. */
	}

	for (i = 0; i < value->num_entries; i++) {
		addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = GET_GATT(addr);
		writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
		readl(cur_gatt+GET_GATT_OFF(addr));	/* PCI Posting. */
	}

	return 0;
}

static int amd_free_gatt_table(struct agp_bridge_data *bridge)
{
	struct amd_page_map page_dir;

	page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
	page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;

	amd_free_gatt_pages();
	amd_free_page_map(&page_dir);
	return 0;
}

static int amd_irongate_fetch_size(void)
{
	int i;
	u32 temp;
	struct aper_size_info_lvl2 *values;

	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
	temp = (temp & 0x0000000e);
	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
		if (temp == values[i].size_value) {
			agp_bridge->previous_size =
			    agp_bridge->current_size = (void *) (values + i);

			agp_bridge->aperture_size_idx = i;
			return values[i].size;
		}
	}

	return 0;
}

static int amd_irongate_configure(void)
{
	struct aper_size_info_lvl2 *current_size;
	phys_addr_t reg;
	u32 temp;
	u16 enable_reg;

	current_size = A_SIZE_LVL2(agp_bridge->current_size);

	if (!amd_irongate_private.registers) {
		/* Get the memory mapped registers */
		reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
		amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
		if (!amd_irongate_private.registers)
			return -ENOMEM;
	}

	/* Write out the address of the gatt table */
	writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
	readl(amd_irongate_private.registers+AMD_ATTBASE);	/* PCI Posting. */

	/* Write the Sync register */
	pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);

	/* Set indexing mode */
	pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);

	/* Write the enable register */
	enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
	enable_reg = (enable_reg | 0x0004);
	writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
	readw(amd_irongate_private.registers+AMD_GARTENABLE);	/* PCI Posting. */

	/* Write out the size register */
	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
	temp = (((temp & ~(0x0000000e)) | current_size->size_value) | 1);
	pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);

	/* Flush the tlb */
	writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
	readl(amd_irongate_private.registers+AMD_TLBFLUSH);	/* PCI Posting.*/
	return 0;
}

static void amd_irongate_cleanup(void)
{
	struct aper_size_info_lvl2 *previous_size;
	u32 temp;
	u16 enable_reg;

	previous_size = A_SIZE_LVL2(agp_bridge->previous_size);

	enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
	enable_reg = (enable_reg & ~(0x0004));
	writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
	readw(amd_irongate_private.registers+AMD_GARTENABLE);	/* PCI Posting. */

	/* Write back the previous size and disable gart translation */
	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
	temp = ((temp & ~(0x0000000f)) | previous_size->size_value);
	pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
	iounmap((void __iomem *) amd_irongate_private.registers);
}

/*
 * This routine could be implemented by taking the addresses
 * written to the GATT, and flushing them individually.  However
 * currently it just flushes the whole table.  Which is probably
 * more efficient, since agp_memory blocks can be a large number of
 * entries.
 */

static void amd_irongate_tlbflush(struct agp_memory *temp)
{
	writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
	readl(amd_irongate_private.registers+AMD_TLBFLUSH);	/* PCI Posting. */
}

static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
{
	int i, j, num_entries;
	unsigned long __iomem *cur_gatt;
	unsigned long addr;

	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;

	if (type != mem->type ||
	    agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
		return -EINVAL;

	if ((pg_start + mem->page_count) > num_entries)
		return -EINVAL;

	j = pg_start;
	while (j < (pg_start + mem->page_count)) {
		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = GET_GATT(addr);
		if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
			return -EBUSY;
		j++;
	}

	if (!mem->is_flushed) {
		global_cache_flush();
		mem->is_flushed = true;
	}

	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = GET_GATT(addr);
		writel(agp_generic_mask_memory(agp_bridge,
					       page_to_phys(mem->pages[i]),
					       mem->type),
		       cur_gatt+GET_GATT_OFF(addr));
		readl(cur_gatt+GET_GATT_OFF(addr));	/* PCI Posting. */
	}
	amd_irongate_tlbflush(mem);
	return 0;
}

static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
{
	int i;
	unsigned long __iomem *cur_gatt;
	unsigned long addr;

	if (type != mem->type ||
	    agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
		return -EINVAL;

	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
		addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
		cur_gatt = GET_GATT(addr);
		writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
		readl(cur_gatt+GET_GATT_OFF(addr));	/* PCI Posting. */
	}

	amd_irongate_tlbflush(mem);
	return 0;
}

static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
{
	{2048, 524288, 0x0000000c},
	{1024, 262144, 0x0000000a},
	{512, 131072, 0x00000008},
	{256, 65536, 0x00000006},
	{128, 32768, 0x00000004},
	{64, 16384, 0x00000002},
	{32, 8192, 0x00000000}
};

static const struct gatt_mask amd_irongate_masks[] =
{
	{.mask = 1, .type = 0}
};

static const struct agp_bridge_driver amd_irongate_driver = {
	.owner			= THIS_MODULE,
	.aperture_sizes		= amd_irongate_sizes,
	.size_type		= LVL2_APER_SIZE,
	.num_aperture_sizes	= 7,
	.needs_scratch_page	= true,
	.configure		= amd_irongate_configure,
	.fetch_size		= amd_irongate_fetch_size,
	.cleanup		= amd_irongate_cleanup,
	.tlb_flush		= amd_irongate_tlbflush,
	.mask_memory		= agp_generic_mask_memory,
	.masks			= amd_irongate_masks,
	.agp_enable		= agp_generic_enable,
	.cache_flush		= global_cache_flush,
	.create_gatt_table	= amd_create_gatt_table,
	.free_gatt_table	= amd_free_gatt_table,
	.insert_memory		= amd_insert_memory,
	.remove_memory		= amd_remove_memory,
	.alloc_by_type		= agp_generic_alloc_by_type,
	.free_by_type		= agp_generic_free_by_type,
	.agp_alloc_page		= agp_generic_alloc_page,
	.agp_alloc_pages	= agp_generic_alloc_pages,
	.agp_destroy_page	= agp_generic_destroy_page,
	.agp_destroy_pages	= agp_generic_destroy_pages,
	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
};

static struct agp_device_ids amd_agp_device_ids[] =
{
	{
		.device_id	= PCI_DEVICE_ID_AMD_FE_GATE_7006,
		.chipset_name	= "Irongate",
	},
	{
		.device_id	= PCI_DEVICE_ID_AMD_FE_GATE_700E,
		.chipset_name	= "761",
	},
	{
		.device_id	= PCI_DEVICE_ID_AMD_FE_GATE_700C,
		.chipset_name	= "760MP",
	},
	{ }, /* dummy final entry, always present */
};

static int agp_amdk7_probe(struct pci_dev *pdev,
			   const struct pci_device_id *ent)
{
	struct agp_bridge_data *bridge;
	u8 cap_ptr;
	int j;

	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	if (!cap_ptr)
		return -ENODEV;

	j = ent - agp_amdk7_pci_table;
	dev_info(&pdev->dev, "AMD %s chipset\n",
		 amd_agp_device_ids[j].chipset_name);

	bridge = agp_alloc_bridge();
	if (!bridge)
		return -ENOMEM;

	bridge->driver = &amd_irongate_driver;
	bridge->dev_private_data = &amd_irongate_private,
	bridge->dev = pdev;
	bridge->capndx = cap_ptr;

	/* 751 Errata (22564_B-1.PDF)
	   erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
	   system controller may experience noise due to strong drive strengths
	 */
	if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
		struct pci_dev *gfxcard=NULL;

		cap_ptr = 0;
		while (!cap_ptr) {
			gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
			if (!gfxcard) {
				dev_info(&pdev->dev, "no AGP VGA controller\n");
				return -ENODEV;
			}
			cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
		}

		/* With so many variants of NVidia cards, it's simpler just
		   to blacklist them all, and then whitelist them as needed
		   (if necessary at all). */
		if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
			agp_bridge->flags |= AGP_ERRATA_1X;
			dev_info(&pdev->dev, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
		}
		pci_dev_put(gfxcard);
	}

	/* 761 Errata (23613_F.pdf)
	 * Revisions B0/B1 were a disaster.
	 * erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
	 * erratum 45: Timing problem prevents fast writes -- Disable fast write.
	 * erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
	 * With this lot disabled, we should prevent lockups. */
	if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
		if (pdev->revision == 0x10 || pdev->revision == 0x11) {
			agp_bridge->flags = AGP_ERRATA_FASTWRITES;
			agp_bridge->flags |= AGP_ERRATA_SBA;
			agp_bridge->flags |= AGP_ERRATA_1X;
			dev_info(&pdev->dev, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
		}
	}

	/* Fill in the mode register */
	pci_read_config_dword(pdev,
			bridge->capndx+PCI_AGP_STATUS,
			&bridge->mode);

	pci_set_drvdata(pdev, bridge);
	return agp_add_bridge(bridge);
}

static void agp_amdk7_remove(struct pci_dev *pdev)
{
	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);

	agp_remove_bridge(bridge);
	agp_put_bridge(bridge);
}

#ifdef CONFIG_PM

static int agp_amdk7_suspend(struct pci_dev *pdev, pm_message_t state)
{
	pci_save_state(pdev);
	pci_set_power_state(pdev, pci_choose_state(pdev, state));

	return 0;
}

static int agp_amdk7_resume(struct pci_dev *pdev)
{
	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);

	return amd_irongate_driver.configure();
}

#endif /* CONFIG_PM */

/* must be the same order as name table above */
static const struct pci_device_id agp_amdk7_pci_table[] = {
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_AMD,
	.device		= PCI_DEVICE_ID_AMD_FE_GATE_7006,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_AMD,
	.device		= PCI_DEVICE_ID_AMD_FE_GATE_700E,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{
	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
	.class_mask	= ~0,
	.vendor		= PCI_VENDOR_ID_AMD,
	.device		= PCI_DEVICE_ID_AMD_FE_GATE_700C,
	.subvendor	= PCI_ANY_ID,
	.subdevice	= PCI_ANY_ID,
	},
	{ }
};

MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);

static struct pci_driver agp_amdk7_pci_driver = {
	.name		= "agpgart-amdk7",
	.id_table	= agp_amdk7_pci_table,
	.probe		= agp_amdk7_probe,
	.remove		= agp_amdk7_remove,
#ifdef CONFIG_PM
	.suspend	= agp_amdk7_suspend,
	.resume		= agp_amdk7_resume,
#endif
};

static int __init agp_amdk7_init(void)
{
	if (agp_off)
		return -EINVAL;
	return pci_register_driver(&agp_amdk7_pci_driver);
}

static void __exit agp_amdk7_cleanup(void)
{
	pci_unregister_driver(&agp_amdk7_pci_driver);
}

module_init(agp_amdk7_init);
module_exit(agp_amdk7_cleanup);

MODULE_LICENSE("GPL and additional rights");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* AMD K7 AGPGART routines.
	3	*/
	4
	5	#include <linux/module.h>
	6	#include <linux/pci.h>
	7	#include <linux/init.h>
	8	#include <linux/agp_backend.h>
1da177e4 LT	9	#include <linux/page-flags.h>
1da177e4 LT	10	#include <linux/mm.h>
5a0e3ad6	11	#include <linux/slab.h>
e47036b4	12	#include <asm/set_memory.h>
1da177e4 LT	13	#include "agp.h"
1da177e4 LT	14
d68c5a27	15	#define AMD_MMBASE_BAR 1
1da177e4 LT	16	#define AMD_APSIZE 0xac
	17	#define AMD_MODECNTL 0xb0
	18	#define AMD_MODECNTL2 0xb2
	19	#define AMD_GARTENABLE 0x02 /* In mmio region (16-bit register) */
	20	#define AMD_ATTBASE 0x04 /* In mmio region (32-bit register) */
	21	#define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
	22	#define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
	23
b8ca53f4	24	static const struct pci_device_id agp_amdk7_pci_table[];
1da177e4 LT	25
	26	struct amd_page_map {
	27	unsigned long *real;
	28	unsigned long __iomem *remapped;
	29	};
	30
	31	static struct _amd_irongate_private {
	32	volatile u8 __iomem *registers;
	33	struct amd_page_map **gatt_pages;
	34	int num_tables;
	35	} amd_irongate_private;
	36
	37	static int amd_create_page_map(struct amd_page_map *page_map)
	38	{
	39	int i;
	40
	41	page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
	42	if (page_map->real == NULL)
	43	return -ENOMEM;
	44
44a207fc	45	set_memory_uc((unsigned long)page_map->real, 1);
fcea424d	46	page_map->remapped = page_map->real;
1da177e4 LT	47
	48	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
	49	writel(agp_bridge->scratch_page, page_map->remapped+i);
	50	readl(page_map->remapped+i); /* PCI Posting. */
	51	}
	52
	53	return 0;
	54	}
	55
	56	static void amd_free_page_map(struct amd_page_map *page_map)
	57	{
44a207fc	58	set_memory_wb((unsigned long)page_map->real, 1);
1da177e4 LT	59	free_page((unsigned long) page_map->real);
	60	}
	61
	62	static void amd_free_gatt_pages(void)
	63	{
	64	int i;
	65	struct amd_page_map **tables;
	66	struct amd_page_map *entry;
	67
	68	tables = amd_irongate_private.gatt_pages;
	69	for (i = 0; i < amd_irongate_private.num_tables; i++) {
	70	entry = tables[i];
	71	if (entry != NULL) {
	72	if (entry->real != NULL)
	73	amd_free_page_map(entry);
	74	kfree(entry);
	75	}
	76	}
	77	kfree(tables);
	78	amd_irongate_private.gatt_pages = NULL;
	79	}
	80
	81	static int amd_create_gatt_pages(int nr_tables)
	82	{
	83	struct amd_page_map **tables;
	84	struct amd_page_map *entry;
	85	int retval = 0;
	86	int i;
	87
0ea27d9f	88	tables = kzalloc((nr_tables + 1) * sizeof(struct amd_page_map *),GFP_KERNEL);
1da177e4 LT	89	if (tables == NULL)
	90	return -ENOMEM;
	91
1da177e4	92	for (i = 0; i < nr_tables; i++) {
0ea27d9f	93	entry = kzalloc(sizeof(struct amd_page_map), GFP_KERNEL);
bdc3e603	94	tables[i] = entry;
1da177e4 LT	95	if (entry == NULL) {
	96	retval = -ENOMEM;
	97	break;
	98	}
1da177e4 LT	99	retval = amd_create_page_map(entry);
	100	if (retval != 0)
	101	break;
	102	}
bdc3e603	103	amd_irongate_private.num_tables = i;
1da177e4 LT	104	amd_irongate_private.gatt_pages = tables;
	105
	106	if (retval != 0)
	107	amd_free_gatt_pages();
	108
	109	return retval;
	110	}
	111
d6e05edc	112	/* Since we don't need contiguous memory we just try
1da177e4 LT	113	* to get the gatt table once
	114	*/
	115
	116	#define GET_PAGE_DIR_OFF(addr) (addr >> 22)
	117	#define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
	118	GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
	119	#define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
	120	#define GET_GATT(addr) (amd_irongate_private.gatt_pages[\
	121	GET_PAGE_DIR_IDX(addr)]->remapped)
	122
	123	static int amd_create_gatt_table(struct agp_bridge_data *bridge)
	124	{
	125	struct aper_size_info_lvl2 *value;
	126	struct amd_page_map page_dir;
61cf0593	127	unsigned long __iomem *cur_gatt;
1da177e4 LT	128	unsigned long addr;
1da177e4 LT	129	int retval;
1da177e4 LT	130	int i;
	131
	132	value = A_SIZE_LVL2(agp_bridge->current_size);
	133	retval = amd_create_page_map(&page_dir);
	134	if (retval != 0)
	135	return retval;
	136
	137	retval = amd_create_gatt_pages(value->num_entries / 1024);
	138	if (retval != 0) {
	139	amd_free_page_map(&page_dir);
	140	return retval;
	141	}
	142
	143	agp_bridge->gatt_table_real = (u32 *)page_dir.real;
	144	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
6a12235c	145	agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
1da177e4 LT	146
	147	/* Get the address for the gart region.
	148	* This is a bus address even on the alpha, b/c its
	149	* used to program the agp master not the cpu
	150	*/
	151
e501b3d8	152	addr = pci_bus_address(agp_bridge->dev, AGP_APERTURE_BAR);
1da177e4 LT	153	agp_bridge->gart_bus_addr = addr;
	154
	155	/* Calculate the agp offset */
	156	for (i = 0; i < value->num_entries / 1024; i++, addr += 0x00400000) {
6a12235c	157	writel(virt_to_phys(amd_irongate_private.gatt_pages[i]->real) \| 1,
1da177e4 LT	158	page_dir.remapped+GET_PAGE_DIR_OFF(addr));
	159	readl(page_dir.remapped+GET_PAGE_DIR_OFF(addr)); /* PCI Posting. */
	160	}
	161
61cf0593 JG	162	for (i = 0; i < value->num_entries; i++) {
	163	addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
	164	cur_gatt = GET_GATT(addr);
	165	writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
	166	readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
	167	}
	168
1da177e4 LT	169	return 0;
	170	}
	171
	172	static int amd_free_gatt_table(struct agp_bridge_data *bridge)
	173	{
	174	struct amd_page_map page_dir;
	175
	176	page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
	177	page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
	178
	179	amd_free_gatt_pages();
	180	amd_free_page_map(&page_dir);
	181	return 0;
	182	}
	183
	184	static int amd_irongate_fetch_size(void)
	185	{
	186	int i;
	187	u32 temp;
	188	struct aper_size_info_lvl2 *values;
	189
	190	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
	191	temp = (temp & 0x0000000e);
	192	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
	193	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
	194	if (temp == values[i].size_value) {
	195	agp_bridge->previous_size =
	196	agp_bridge->current_size = (void *) (values + i);
	197
	198	agp_bridge->aperture_size_idx = i;
	199	return values[i].size;
	200	}
	201	}
	202
	203	return 0;
	204	}
	205
	206	static int amd_irongate_configure(void)
	207	{
	208	struct aper_size_info_lvl2 *current_size;
d68c5a27	209	phys_addr_t reg;
1da177e4 LT	210	u32 temp;
	211	u16 enable_reg;
	212
	213	current_size = A_SIZE_LVL2(agp_bridge->current_size);
	214
2a32c3c8 SB	215	if (!amd_irongate_private.registers) {
2a32c3c8 SB	216	/* Get the memory mapped registers */
d68c5a27 BH	217	reg = pci_resource_start(agp_bridge->dev, AMD_MMBASE_BAR);
d68c5a27 BH	218	amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096);
2a32c3c8 SB	219	if (!amd_irongate_private.registers)
	220	return -ENOMEM;
	221	}
1da177e4 LT	222
	223	/* Write out the address of the gatt table */
	224	writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE);
	225	readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */
	226
	227	/* Write the Sync register */
	228	pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL, 0x80);
	229
	230	/* Set indexing mode */
	231	pci_write_config_byte(agp_bridge->dev, AMD_MODECNTL2, 0x00);
	232
	233	/* Write the enable register */
	234	enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
	235	enable_reg = (enable_reg \| 0x0004);
	236	writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
	237	readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
	238
	239	/* Write out the size register */
	240	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
	241	temp = (((temp & ~(0x0000000e)) \| current_size->size_value) \| 1);
	242	pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
	243
	244	/* Flush the tlb */
	245	writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
	246	readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting.*/
	247	return 0;
	248	}
	249
	250	static void amd_irongate_cleanup(void)
	251	{
	252	struct aper_size_info_lvl2 *previous_size;
	253	u32 temp;
	254	u16 enable_reg;
	255
	256	previous_size = A_SIZE_LVL2(agp_bridge->previous_size);
	257
	258	enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE);
	259	enable_reg = (enable_reg & ~(0x0004));
	260	writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE);
	261	readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */
	262
	263	/* Write back the previous size and disable gart translation */
	264	pci_read_config_dword(agp_bridge->dev, AMD_APSIZE, &temp);
	265	temp = ((temp & ~(0x0000000f)) \| previous_size->size_value);
	266	pci_write_config_dword(agp_bridge->dev, AMD_APSIZE, temp);
	267	iounmap((void __iomem *) amd_irongate_private.registers);
	268	}
	269
	270	/*
	271	* This routine could be implemented by taking the addresses
	272	* written to the GATT, and flushing them individually. However
	273	* currently it just flushes the whole table. Which is probably
25985edc	274	* more efficient, since agp_memory blocks can be a large number of
1da177e4 LT	275	* entries.
	276	*/
	277
	278	static void amd_irongate_tlbflush(struct agp_memory *temp)
	279	{
	280	writel(1, amd_irongate_private.registers+AMD_TLBFLUSH);
	281	readl(amd_irongate_private.registers+AMD_TLBFLUSH); /* PCI Posting. */
	282	}
	283
	284	static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
	285	{
	286	int i, j, num_entries;
	287	unsigned long __iomem *cur_gatt;
	288	unsigned long addr;
	289
	290	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
	291
f6086134 FJ	292	if (type != mem->type \|\|
f6086134 FJ	293	agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
1da177e4 LT	294	return -EINVAL;
	295
	296	if ((pg_start + mem->page_count) > num_entries)
	297	return -EINVAL;
	298
	299	j = pg_start;
	300	while (j < (pg_start + mem->page_count)) {
	301	addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
	302	cur_gatt = GET_GATT(addr);
	303	if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
	304	return -EBUSY;
	305	j++;
	306	}
	307
c7258012	308	if (!mem->is_flushed) {
1da177e4	309	global_cache_flush();
c7258012	310	mem->is_flushed = true;
1da177e4 LT	311	}
	312
	313	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
	314	addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
	315	cur_gatt = GET_GATT(addr);
	316	writel(agp_generic_mask_memory(agp_bridge,
6a12235c	317	page_to_phys(mem->pages[i]),
2a4ceb6d DW	318	mem->type),
2a4ceb6d DW	319	cur_gatt+GET_GATT_OFF(addr));
1da177e4 LT	320	readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
	321	}
	322	amd_irongate_tlbflush(mem);
	323	return 0;
	324	}
	325
	326	static int amd_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
	327	{
	328	int i;
	329	unsigned long __iomem *cur_gatt;
	330	unsigned long addr;
	331
f6086134 FJ	332	if (type != mem->type \|\|
f6086134 FJ	333	agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type))
1da177e4 LT	334	return -EINVAL;
	335
	336	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
	337	addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
	338	cur_gatt = GET_GATT(addr);
	339	writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
	340	readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
	341	}
	342
	343	amd_irongate_tlbflush(mem);
	344	return 0;
	345	}
	346
e5524f35	347	static const struct aper_size_info_lvl2 amd_irongate_sizes[7] =
1da177e4 LT	348	{
	349	{2048, 524288, 0x0000000c},
	350	{1024, 262144, 0x0000000a},
	351	{512, 131072, 0x00000008},
	352	{256, 65536, 0x00000006},
	353	{128, 32768, 0x00000004},
	354	{64, 16384, 0x00000002},
	355	{32, 8192, 0x00000000}
	356	};
	357
e5524f35	358	static const struct gatt_mask amd_irongate_masks[] =
1da177e4 LT	359	{
	360	{.mask = 1, .type = 0}
	361	};
	362
e5524f35	363	static const struct agp_bridge_driver amd_irongate_driver = {
1da177e4 LT	364	.owner = THIS_MODULE,
	365	.aperture_sizes = amd_irongate_sizes,
	366	.size_type = LVL2_APER_SIZE,
	367	.num_aperture_sizes = 7,
61cf0593	368	.needs_scratch_page = true,
1da177e4 LT	369	.configure = amd_irongate_configure,
	370	.fetch_size = amd_irongate_fetch_size,
	371	.cleanup = amd_irongate_cleanup,
	372	.tlb_flush = amd_irongate_tlbflush,
	373	.mask_memory = agp_generic_mask_memory,
	374	.masks = amd_irongate_masks,
	375	.agp_enable = agp_generic_enable,
	376	.cache_flush = global_cache_flush,
	377	.create_gatt_table = amd_create_gatt_table,
	378	.free_gatt_table = amd_free_gatt_table,
	379	.insert_memory = amd_insert_memory,
	380	.remove_memory = amd_remove_memory,
	381	.alloc_by_type = agp_generic_alloc_by_type,
	382	.free_by_type = agp_generic_free_by_type,
	383	.agp_alloc_page = agp_generic_alloc_page,
5f310b63	384	.agp_alloc_pages = agp_generic_alloc_pages,
1da177e4	385	.agp_destroy_page = agp_generic_destroy_page,
5f310b63	386	.agp_destroy_pages = agp_generic_destroy_pages,
a030ce44	387	.agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4 LT	388	};
1da177e4 LT	389
0bbed20e	390	static struct agp_device_ids amd_agp_device_ids[] =
1da177e4 LT	391	{
	392	{
	393	.device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
	394	.chipset_name = "Irongate",
	395	},
	396	{
	397	.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700E,
	398	.chipset_name = "761",
	399	},
	400	{
	401	.device_id = PCI_DEVICE_ID_AMD_FE_GATE_700C,
	402	.chipset_name = "760MP",
	403	},
	404	{ }, /* dummy final entry, always present */
	405	};
	406
bcd2982a GKH	407	static int agp_amdk7_probe(struct pci_dev *pdev,
bcd2982a GKH	408	const struct pci_device_id *ent)
1da177e4 LT	409	{
	410	struct agp_bridge_data *bridge;
	411	u8 cap_ptr;
	412	int j;
	413
	414	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
	415	if (!cap_ptr)
	416	return -ENODEV;
	417
	418	j = ent - agp_amdk7_pci_table;
e3cf6951 BH	419	dev_info(&pdev->dev, "AMD %s chipset\n",
e3cf6951 BH	420	amd_agp_device_ids[j].chipset_name);
1da177e4 LT	421
	422	bridge = agp_alloc_bridge();
	423	if (!bridge)
	424	return -ENOMEM;
	425
	426	bridge->driver = &amd_irongate_driver;
	427	bridge->dev_private_data = &amd_irongate_private,
	428	bridge->dev = pdev;
	429	bridge->capndx = cap_ptr;
	430
	431	/* 751 Errata (22564_B-1.PDF)
	432	erratum 20: strobe glitch with Nvidia NV10 GeForce cards.
	433	system controller may experience noise due to strong drive strengths
	434	*/
	435	if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_7006) {
1da177e4	436	struct pci_dev *gfxcard=NULL;
4ab92bcf HH	437
4ab92bcf HH	438	cap_ptr = 0;
1da177e4 LT	439	while (!cap_ptr) {
	440	gfxcard = pci_get_class(PCI_CLASS_DISPLAY_VGA<<8, gfxcard);
	441	if (!gfxcard) {
e3cf6951	442	dev_info(&pdev->dev, "no AGP VGA controller\n");
1da177e4 LT	443	return -ENODEV;
	444	}
	445	cap_ptr = pci_find_capability(gfxcard, PCI_CAP_ID_AGP);
1da177e4 LT	446	}
	447
	448	/* With so many variants of NVidia cards, it's simpler just
	449	to blacklist them all, and then whitelist them as needed
	450	(if necessary at all). */
	451	if (gfxcard->vendor == PCI_VENDOR_ID_NVIDIA) {
	452	agp_bridge->flags \|= AGP_ERRATA_1X;
e3cf6951	453	dev_info(&pdev->dev, "AMD 751 chipset with NVidia GeForce; forcing 1X due to errata\n");
1da177e4 LT	454	}
	455	pci_dev_put(gfxcard);
	456	}
	457
	458	/* 761 Errata (23613_F.pdf)
	459	* Revisions B0/B1 were a disaster.
	460	* erratum 44: SYSCLK/AGPCLK skew causes 2X failures -- Force mode to 1X
	461	* erratum 45: Timing problem prevents fast writes -- Disable fast write.
	462	* erratum 46: Setup violation on AGP SBA pins - Disable side band addressing.
	463	* With this lot disabled, we should prevent lockups. */
	464	if (agp_bridge->dev->device == PCI_DEVICE_ID_AMD_FE_GATE_700E) {
44c10138	465	if (pdev->revision == 0x10 \|\| pdev->revision == 0x11) {
1da177e4 LT	466	agp_bridge->flags = AGP_ERRATA_FASTWRITES;
	467	agp_bridge->flags \|= AGP_ERRATA_SBA;
	468	agp_bridge->flags \|= AGP_ERRATA_1X;
e3cf6951	469	dev_info(&pdev->dev, "AMD 761 chipset with errata; disabling AGP fast writes & SBA and forcing to 1X\n");
1da177e4 LT	470	}
	471	}
	472
	473	/* Fill in the mode register */
	474	pci_read_config_dword(pdev,
	475	bridge->capndx+PCI_AGP_STATUS,
	476	&bridge->mode);
	477
	478	pci_set_drvdata(pdev, bridge);
	479	return agp_add_bridge(bridge);
	480	}
	481
39af33fc	482	static void agp_amdk7_remove(struct pci_dev *pdev)
1da177e4 LT	483	{
	484	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
	485
	486	agp_remove_bridge(bridge);
	487	agp_put_bridge(bridge);
	488	}
	489
2a32c3c8 SB	490	#ifdef CONFIG_PM
	491
	492	static int agp_amdk7_suspend(struct pci_dev *pdev, pm_message_t state)
	493	{
	494	pci_save_state(pdev);
	495	pci_set_power_state(pdev, pci_choose_state(pdev, state));
	496
	497	return 0;
	498	}
	499
	500	static int agp_amdk7_resume(struct pci_dev *pdev)
	501	{
	502	pci_set_power_state(pdev, PCI_D0);
	503	pci_restore_state(pdev);
	504
	505	return amd_irongate_driver.configure();
	506	}
	507
	508	#endif /* CONFIG_PM */
	509
1da177e4	510	/* must be the same order as name table above */
b8ca53f4	511	static const struct pci_device_id agp_amdk7_pci_table[] = {
1da177e4 LT	512	{
	513	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	514	.class_mask = ~0,
	515	.vendor = PCI_VENDOR_ID_AMD,
	516	.device = PCI_DEVICE_ID_AMD_FE_GATE_7006,
	517	.subvendor = PCI_ANY_ID,
	518	.subdevice = PCI_ANY_ID,
	519	},
	520	{
	521	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	522	.class_mask = ~0,
	523	.vendor = PCI_VENDOR_ID_AMD,
	524	.device = PCI_DEVICE_ID_AMD_FE_GATE_700E,
	525	.subvendor = PCI_ANY_ID,
	526	.subdevice = PCI_ANY_ID,
	527	},
	528	{
	529	.class = (PCI_CLASS_BRIDGE_HOST << 8),
	530	.class_mask = ~0,
	531	.vendor = PCI_VENDOR_ID_AMD,
	532	.device = PCI_DEVICE_ID_AMD_FE_GATE_700C,
	533	.subvendor = PCI_ANY_ID,
	534	.subdevice = PCI_ANY_ID,
	535	},
	536	{ }
	537	};
	538
	539	MODULE_DEVICE_TABLE(pci, agp_amdk7_pci_table);
	540
	541	static struct pci_driver agp_amdk7_pci_driver = {
	542	.name = "agpgart-amdk7",
	543	.id_table = agp_amdk7_pci_table,
	544	.probe = agp_amdk7_probe,
	545	.remove = agp_amdk7_remove,
2a32c3c8 SB	546	#ifdef CONFIG_PM
	547	.suspend = agp_amdk7_suspend,
	548	.resume = agp_amdk7_resume,
	549	#endif
1da177e4 LT	550	};
	551
	552	static int __init agp_amdk7_init(void)
	553	{
	554	if (agp_off)
	555	return -EINVAL;
	556	return pci_register_driver(&agp_amdk7_pci_driver);
	557	}
	558
	559	static void __exit agp_amdk7_cleanup(void)
	560	{
	561	pci_unregister_driver(&agp_amdk7_pci_driver);
	562	}
	563
	564	module_init(agp_amdk7_init);
	565	module_exit(agp_amdk7_cleanup);
	566
	567	MODULE_LICENSE("GPL and additional rights");