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c942fddf | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
4b7f48d3 MY |
2 | /* |
3 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> | |
4b7f48d3 MY |
4 | */ |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/log2.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/of.h> | |
10 | #include <linux/of_address.h> | |
11 | #include <linux/of_platform.h> | |
12 | #include <linux/platform_device.h> | |
13 | ||
14 | /* System Bus Controller registers */ | |
15 | #define UNIPHIER_SBC_BASE 0x100 /* base address of bank0 space */ | |
16 | #define UNIPHIER_SBC_BASE_BE BIT(0) /* bank_enable */ | |
17 | #define UNIPHIER_SBC_CTRL0 0x200 /* timing parameter 0 of bank0 */ | |
18 | #define UNIPHIER_SBC_CTRL1 0x204 /* timing parameter 1 of bank0 */ | |
19 | #define UNIPHIER_SBC_CTRL2 0x208 /* timing parameter 2 of bank0 */ | |
20 | #define UNIPHIER_SBC_CTRL3 0x20c /* timing parameter 3 of bank0 */ | |
21 | #define UNIPHIER_SBC_CTRL4 0x300 /* timing parameter 4 of bank0 */ | |
22 | ||
23 | #define UNIPHIER_SBC_STRIDE 0x10 /* register stride to next bank */ | |
24 | #define UNIPHIER_SBC_NR_BANKS 8 /* number of banks (chip select) */ | |
25 | #define UNIPHIER_SBC_BASE_DUMMY 0xffffffff /* data to squash bank 0, 1 */ | |
26 | ||
27 | struct uniphier_system_bus_bank { | |
28 | u32 base; | |
29 | u32 end; | |
30 | }; | |
31 | ||
32 | struct uniphier_system_bus_priv { | |
33 | struct device *dev; | |
34 | void __iomem *membase; | |
35 | struct uniphier_system_bus_bank bank[UNIPHIER_SBC_NR_BANKS]; | |
36 | }; | |
37 | ||
38 | static int uniphier_system_bus_add_bank(struct uniphier_system_bus_priv *priv, | |
39 | int bank, u32 addr, u64 paddr, u32 size) | |
40 | { | |
41 | u64 end, mask; | |
42 | ||
43 | dev_dbg(priv->dev, | |
44 | "range found: bank = %d, addr = %08x, paddr = %08llx, size = %08x\n", | |
45 | bank, addr, paddr, size); | |
46 | ||
47 | if (bank >= ARRAY_SIZE(priv->bank)) { | |
48 | dev_err(priv->dev, "unsupported bank number %d\n", bank); | |
49 | return -EINVAL; | |
50 | } | |
51 | ||
52 | if (priv->bank[bank].base || priv->bank[bank].end) { | |
53 | dev_err(priv->dev, | |
54 | "range for bank %d has already been specified\n", bank); | |
55 | return -EINVAL; | |
56 | } | |
57 | ||
58 | if (paddr > U32_MAX) { | |
59 | dev_err(priv->dev, "base address %llx is too high\n", paddr); | |
60 | return -EINVAL; | |
61 | } | |
62 | ||
63 | end = paddr + size; | |
64 | ||
65 | if (addr > paddr) { | |
66 | dev_err(priv->dev, | |
67 | "base %08x cannot be mapped to %08llx of parent\n", | |
68 | addr, paddr); | |
69 | return -EINVAL; | |
70 | } | |
71 | paddr -= addr; | |
72 | ||
73 | paddr = round_down(paddr, 0x00020000); | |
74 | end = round_up(end, 0x00020000); | |
75 | ||
76 | if (end > U32_MAX) { | |
77 | dev_err(priv->dev, "end address %08llx is too high\n", end); | |
78 | return -EINVAL; | |
79 | } | |
80 | mask = paddr ^ (end - 1); | |
81 | mask = roundup_pow_of_two(mask); | |
82 | ||
83 | paddr = round_down(paddr, mask); | |
84 | end = round_up(end, mask); | |
85 | ||
86 | priv->bank[bank].base = paddr; | |
87 | priv->bank[bank].end = end; | |
88 | ||
89 | dev_dbg(priv->dev, "range added: bank = %d, addr = %08x, end = %08x\n", | |
90 | bank, priv->bank[bank].base, priv->bank[bank].end); | |
91 | ||
92 | return 0; | |
93 | } | |
94 | ||
95 | static int uniphier_system_bus_check_overlap( | |
96 | const struct uniphier_system_bus_priv *priv) | |
97 | { | |
98 | int i, j; | |
99 | ||
100 | for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { | |
101 | for (j = i + 1; j < ARRAY_SIZE(priv->bank); j++) { | |
3de7beeb | 102 | if (priv->bank[i].end > priv->bank[j].base && |
4b7f48d3 MY |
103 | priv->bank[i].base < priv->bank[j].end) { |
104 | dev_err(priv->dev, | |
105 | "region overlap between bank%d and bank%d\n", | |
106 | i, j); | |
107 | return -EINVAL; | |
108 | } | |
109 | } | |
110 | } | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
115 | static void uniphier_system_bus_check_boot_swap( | |
116 | struct uniphier_system_bus_priv *priv) | |
117 | { | |
118 | void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; | |
119 | int is_swapped; | |
120 | ||
121 | is_swapped = !(readl(base_reg) & UNIPHIER_SBC_BASE_BE); | |
122 | ||
123 | dev_dbg(priv->dev, "Boot Swap: %s\n", is_swapped ? "on" : "off"); | |
124 | ||
125 | /* | |
126 | * If BOOT_SWAP was asserted on power-on-reset, the CS0 and CS1 are | |
127 | * swapped. In this case, bank0 and bank1 should be swapped as well. | |
128 | */ | |
129 | if (is_swapped) | |
130 | swap(priv->bank[0], priv->bank[1]); | |
131 | } | |
132 | ||
133 | static void uniphier_system_bus_set_reg( | |
134 | const struct uniphier_system_bus_priv *priv) | |
135 | { | |
136 | void __iomem *base_reg = priv->membase + UNIPHIER_SBC_BASE; | |
137 | u32 base, end, mask, val; | |
138 | int i; | |
139 | ||
140 | for (i = 0; i < ARRAY_SIZE(priv->bank); i++) { | |
141 | base = priv->bank[i].base; | |
142 | end = priv->bank[i].end; | |
143 | ||
144 | if (base == end) { | |
145 | /* | |
146 | * If SBC_BASE0 or SBC_BASE1 is set to zero, the access | |
147 | * to anywhere in the system bus space is routed to | |
148 | * bank 0 (if boot swap if off) or bank 1 (if boot swap | |
149 | * if on). It means that CPUs cannot get access to | |
150 | * bank 2 or later. In other words, bank 0/1 cannot | |
151 | * be disabled even if its bank_enable bits is cleared. | |
152 | * This seems odd, but it is how this hardware goes. | |
153 | * As a workaround, dummy data (0xffffffff) should be | |
154 | * set when the bank 0/1 is unused. As for bank 2 and | |
155 | * later, they can be simply disable by clearing the | |
156 | * bank_enable bit. | |
157 | */ | |
158 | if (i < 2) | |
159 | val = UNIPHIER_SBC_BASE_DUMMY; | |
160 | else | |
161 | val = 0; | |
162 | } else { | |
163 | mask = base ^ (end - 1); | |
164 | ||
165 | val = base & 0xfffe0000; | |
166 | val |= (~mask >> 16) & 0xfffe; | |
167 | val |= UNIPHIER_SBC_BASE_BE; | |
168 | } | |
169 | dev_dbg(priv->dev, "SBC_BASE[%d] = 0x%08x\n", i, val); | |
170 | ||
171 | writel(val, base_reg + UNIPHIER_SBC_STRIDE * i); | |
172 | } | |
173 | } | |
174 | ||
175 | static int uniphier_system_bus_probe(struct platform_device *pdev) | |
176 | { | |
177 | struct device *dev = &pdev->dev; | |
178 | struct uniphier_system_bus_priv *priv; | |
4b7f48d3 MY |
179 | const __be32 *ranges; |
180 | u32 cells, addr, size; | |
181 | u64 paddr; | |
182 | int pna, bank, rlen, rone, ret; | |
183 | ||
184 | priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); | |
185 | if (!priv) | |
186 | return -ENOMEM; | |
187 | ||
ef92bfda | 188 | priv->membase = devm_platform_ioremap_resource(pdev, 0); |
4b7f48d3 MY |
189 | if (IS_ERR(priv->membase)) |
190 | return PTR_ERR(priv->membase); | |
191 | ||
192 | priv->dev = dev; | |
193 | ||
194 | pna = of_n_addr_cells(dev->of_node); | |
195 | ||
196 | ret = of_property_read_u32(dev->of_node, "#address-cells", &cells); | |
197 | if (ret) { | |
198 | dev_err(dev, "failed to get #address-cells\n"); | |
199 | return ret; | |
200 | } | |
201 | if (cells != 2) { | |
202 | dev_err(dev, "#address-cells must be 2\n"); | |
203 | return -EINVAL; | |
204 | } | |
205 | ||
206 | ret = of_property_read_u32(dev->of_node, "#size-cells", &cells); | |
207 | if (ret) { | |
208 | dev_err(dev, "failed to get #size-cells\n"); | |
209 | return ret; | |
210 | } | |
211 | if (cells != 1) { | |
212 | dev_err(dev, "#size-cells must be 1\n"); | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
216 | ranges = of_get_property(dev->of_node, "ranges", &rlen); | |
217 | if (!ranges) { | |
218 | dev_err(dev, "failed to get ranges property\n"); | |
219 | return -ENOENT; | |
220 | } | |
221 | ||
222 | rlen /= sizeof(*ranges); | |
223 | rone = pna + 2; | |
224 | ||
225 | for (; rlen >= rone; rlen -= rone) { | |
226 | bank = be32_to_cpup(ranges++); | |
227 | addr = be32_to_cpup(ranges++); | |
228 | paddr = of_translate_address(dev->of_node, ranges); | |
229 | if (paddr == OF_BAD_ADDR) | |
230 | return -EINVAL; | |
231 | ranges += pna; | |
232 | size = be32_to_cpup(ranges++); | |
233 | ||
234 | ret = uniphier_system_bus_add_bank(priv, bank, addr, | |
235 | paddr, size); | |
236 | if (ret) | |
237 | return ret; | |
238 | } | |
239 | ||
240 | ret = uniphier_system_bus_check_overlap(priv); | |
241 | if (ret) | |
242 | return ret; | |
243 | ||
244 | uniphier_system_bus_check_boot_swap(priv); | |
245 | ||
246 | uniphier_system_bus_set_reg(priv); | |
247 | ||
2f4233ee MY |
248 | platform_set_drvdata(pdev, priv); |
249 | ||
4b7f48d3 | 250 | /* Now, the bus is configured. Populate platform_devices below it */ |
2cf66924 | 251 | return of_platform_default_populate(dev->of_node, NULL, dev); |
4b7f48d3 MY |
252 | } |
253 | ||
2f4233ee MY |
254 | static int __maybe_unused uniphier_system_bus_resume(struct device *dev) |
255 | { | |
256 | uniphier_system_bus_set_reg(dev_get_drvdata(dev)); | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static const struct dev_pm_ops uniphier_system_bus_pm_ops = { | |
262 | SET_SYSTEM_SLEEP_PM_OPS(NULL, uniphier_system_bus_resume) | |
263 | }; | |
264 | ||
4b7f48d3 MY |
265 | static const struct of_device_id uniphier_system_bus_match[] = { |
266 | { .compatible = "socionext,uniphier-system-bus" }, | |
267 | { /* sentinel */ } | |
268 | }; | |
269 | MODULE_DEVICE_TABLE(of, uniphier_system_bus_match); | |
270 | ||
271 | static struct platform_driver uniphier_system_bus_driver = { | |
272 | .probe = uniphier_system_bus_probe, | |
273 | .driver = { | |
274 | .name = "uniphier-system-bus", | |
275 | .of_match_table = uniphier_system_bus_match, | |
2f4233ee | 276 | .pm = &uniphier_system_bus_pm_ops, |
4b7f48d3 MY |
277 | }, |
278 | }; | |
279 | module_platform_driver(uniphier_system_bus_driver); | |
280 | ||
281 | MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>"); | |
282 | MODULE_DESCRIPTION("UniPhier System Bus driver"); | |
283 | MODULE_LICENSE("GPL"); |