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0eecc636 TL |
1 | /* |
2 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
9 | * kind, whether express or implied; without even the implied warranty | |
10 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | ||
14 | #include <linux/io.h> | |
15 | #include <linux/clk.h> | |
2c355ff6 | 16 | #include <linux/clkdev.h> |
a885f0fe | 17 | #include <linux/delay.h> |
0eecc636 TL |
18 | #include <linux/module.h> |
19 | #include <linux/platform_device.h> | |
a885f0fe | 20 | #include <linux/pm_domain.h> |
0eecc636 | 21 | #include <linux/pm_runtime.h> |
5062236e | 22 | #include <linux/reset.h> |
0eecc636 TL |
23 | #include <linux/of_address.h> |
24 | #include <linux/of_platform.h> | |
2c355ff6 TL |
25 | #include <linux/slab.h> |
26 | ||
70a65240 TL |
27 | #include <linux/platform_data/ti-sysc.h> |
28 | ||
29 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 30 | |
0eecc636 TL |
31 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; |
32 | ||
33 | enum sysc_clocks { | |
34 | SYSC_FCK, | |
35 | SYSC_ICK, | |
09dfe581 TL |
36 | SYSC_OPTFCK0, |
37 | SYSC_OPTFCK1, | |
38 | SYSC_OPTFCK2, | |
39 | SYSC_OPTFCK3, | |
40 | SYSC_OPTFCK4, | |
41 | SYSC_OPTFCK5, | |
42 | SYSC_OPTFCK6, | |
43 | SYSC_OPTFCK7, | |
0eecc636 TL |
44 | SYSC_MAX_CLOCKS, |
45 | }; | |
46 | ||
09dfe581 | 47 | static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", }; |
0eecc636 | 48 | |
c5a2de97 TL |
49 | #define SYSC_IDLEMODE_MASK 3 |
50 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
51 | ||
0eecc636 TL |
52 | /** |
53 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
54 | * @dev: struct device pointer | |
55 | * @module_pa: physical address of the interconnect target module | |
56 | * @module_size: size of the interconnect target module | |
57 | * @module_va: virtual address of the interconnect target module | |
58 | * @offsets: register offsets from module base | |
59 | * @clocks: clocks used by the interconnect target module | |
09dfe581 TL |
60 | * @clock_roles: clock role names for the found clocks |
61 | * @nr_clocks: number of clocks used by the interconnect target module | |
0eecc636 | 62 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
63 | * @cap: interconnect target module capabilities |
64 | * @cfg: interconnect target module configuration | |
566a9b05 TL |
65 | * @name: name if available |
66 | * @revision: interconnect target module revision | |
62020f23 | 67 | * @needs_resume: runtime resume needed on resume from suspend |
0eecc636 TL |
68 | */ |
69 | struct sysc { | |
70 | struct device *dev; | |
71 | u64 module_pa; | |
72 | u32 module_size; | |
73 | void __iomem *module_va; | |
74 | int offsets[SYSC_MAX_REGS]; | |
09dfe581 TL |
75 | struct clk **clocks; |
76 | const char **clock_roles; | |
77 | int nr_clocks; | |
5062236e | 78 | struct reset_control *rsts; |
0eecc636 | 79 | const char *legacy_mode; |
70a65240 TL |
80 | const struct sysc_capabilities *cap; |
81 | struct sysc_config cfg; | |
ef70b0bd | 82 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
83 | const char *name; |
84 | u32 revision; | |
62020f23 TL |
85 | bool enabled; |
86 | bool needs_resume; | |
a885f0fe | 87 | bool child_needs_resume; |
76f0f772 | 88 | struct delayed_work idle_work; |
0eecc636 TL |
89 | }; |
90 | ||
566a9b05 TL |
91 | static u32 sysc_read(struct sysc *ddata, int offset) |
92 | { | |
93 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
94 | u32 val; | |
95 | ||
96 | val = readw_relaxed(ddata->module_va + offset); | |
97 | val |= (readw_relaxed(ddata->module_va + offset + 4) << 16); | |
98 | ||
99 | return val; | |
100 | } | |
101 | ||
102 | return readl_relaxed(ddata->module_va + offset); | |
103 | } | |
104 | ||
09dfe581 TL |
105 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
106 | { | |
107 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
108 | } | |
109 | ||
0eecc636 TL |
110 | static u32 sysc_read_revision(struct sysc *ddata) |
111 | { | |
566a9b05 TL |
112 | int offset = ddata->offsets[SYSC_REVISION]; |
113 | ||
114 | if (offset < 0) | |
115 | return 0; | |
116 | ||
117 | return sysc_read(ddata, offset); | |
0eecc636 TL |
118 | } |
119 | ||
09dfe581 | 120 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 121 | { |
09dfe581 TL |
122 | int error, i, index = -ENODEV; |
123 | ||
124 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
125 | index = SYSC_FCK; | |
126 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
127 | index = SYSC_ICK; | |
128 | ||
129 | if (index < 0) { | |
130 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 131 | if (!ddata->clocks[i]) { |
09dfe581 TL |
132 | index = i; |
133 | break; | |
134 | } | |
135 | } | |
136 | } | |
0eecc636 | 137 | |
09dfe581 TL |
138 | if (index < 0) { |
139 | dev_err(ddata->dev, "clock %s not added\n", name); | |
140 | return index; | |
0eecc636 | 141 | } |
0eecc636 TL |
142 | |
143 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
144 | if (IS_ERR(ddata->clocks[index])) { | |
145 | if (PTR_ERR(ddata->clocks[index]) == -ENOENT) | |
146 | return 0; | |
147 | ||
148 | dev_err(ddata->dev, "clock get error for %s: %li\n", | |
149 | name, PTR_ERR(ddata->clocks[index])); | |
150 | ||
151 | return PTR_ERR(ddata->clocks[index]); | |
152 | } | |
153 | ||
154 | error = clk_prepare(ddata->clocks[index]); | |
155 | if (error) { | |
156 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
157 | name, error); | |
158 | ||
159 | return error; | |
160 | } | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static int sysc_get_clocks(struct sysc *ddata) | |
166 | { | |
09dfe581 TL |
167 | struct device_node *np = ddata->dev->of_node; |
168 | struct property *prop; | |
169 | const char *name; | |
170 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
171 | ||
20749051 | 172 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 173 | SYSC_MAX_CLOCKS, |
20749051 | 174 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
175 | GFP_KERNEL); |
176 | if (!ddata->clock_roles) | |
177 | return -ENOMEM; | |
178 | ||
179 | of_property_for_each_string(np, "clock-names", prop, name) { | |
180 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
181 | nr_fck++; | |
182 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
183 | nr_ick++; | |
184 | ddata->clock_roles[ddata->nr_clocks] = name; | |
185 | ddata->nr_clocks++; | |
186 | } | |
187 | ||
188 | if (ddata->nr_clocks < 1) | |
189 | return 0; | |
190 | ||
191 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { | |
192 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
193 | ||
194 | return -EINVAL; | |
195 | } | |
196 | ||
197 | if (nr_fck > 1 || nr_ick > 1) { | |
198 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 199 | |
09dfe581 TL |
200 | return -EINVAL; |
201 | } | |
202 | ||
20749051 KC |
203 | ddata->clocks = devm_kcalloc(ddata->dev, |
204 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
205 | GFP_KERNEL); |
206 | if (!ddata->clocks) | |
207 | return -ENOMEM; | |
208 | ||
209 | for (i = 0; i < ddata->nr_clocks; i++) { | |
210 | error = sysc_get_one_clock(ddata, ddata->clock_roles[i]); | |
0eecc636 TL |
211 | if (error && error != -ENOENT) |
212 | return error; | |
213 | } | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
5062236e TL |
218 | /** |
219 | * sysc_init_resets - reset module on init | |
220 | * @ddata: device driver data | |
221 | * | |
222 | * A module can have both OCP softreset control and external rstctrl. | |
223 | * If more complicated rstctrl resets are needed, please handle these | |
224 | * directly from the child device driver and map only the module reset | |
225 | * for the parent interconnect target module device. | |
226 | * | |
227 | * Automatic reset of the module on init can be skipped with the | |
228 | * "ti,no-reset-on-init" device tree property. | |
229 | */ | |
230 | static int sysc_init_resets(struct sysc *ddata) | |
231 | { | |
232 | int error; | |
233 | ||
234 | ddata->rsts = | |
235 | devm_reset_control_array_get_optional_exclusive(ddata->dev); | |
236 | if (IS_ERR(ddata->rsts)) | |
237 | return PTR_ERR(ddata->rsts); | |
238 | ||
239 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) | |
240 | goto deassert; | |
241 | ||
242 | error = reset_control_assert(ddata->rsts); | |
243 | if (error) | |
244 | return error; | |
245 | ||
246 | deassert: | |
247 | error = reset_control_deassert(ddata->rsts); | |
248 | if (error) | |
249 | return error; | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
0eecc636 TL |
254 | /** |
255 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
256 | * @ddata: device driver data | |
257 | * | |
258 | * In general we only need rev, syss, and sysc registers and not the whole | |
259 | * module range. But we do want the offsets for these registers from the | |
260 | * module base. This allows us to check them against the legacy hwmod | |
261 | * platform data. Let's also check the ranges are configured properly. | |
262 | */ | |
263 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
264 | { | |
265 | struct device_node *np = ddata->dev->of_node; | |
266 | const __be32 *ranges; | |
267 | u32 nr_addr, nr_size; | |
268 | int len, error; | |
269 | ||
270 | ranges = of_get_property(np, "ranges", &len); | |
271 | if (!ranges) { | |
272 | dev_err(ddata->dev, "missing ranges for %pOF\n", np); | |
273 | ||
274 | return -ENOENT; | |
275 | } | |
276 | ||
277 | len /= sizeof(*ranges); | |
278 | ||
279 | if (len < 3) { | |
280 | dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); | |
281 | ||
282 | return -EINVAL; | |
283 | } | |
284 | ||
285 | error = of_property_read_u32(np, "#address-cells", &nr_addr); | |
286 | if (error) | |
287 | return -ENOENT; | |
288 | ||
289 | error = of_property_read_u32(np, "#size-cells", &nr_size); | |
290 | if (error) | |
291 | return -ENOENT; | |
292 | ||
293 | if (nr_addr != 1 || nr_size != 1) { | |
294 | dev_err(ddata->dev, "invalid ranges for %pOF\n", np); | |
295 | ||
296 | return -EINVAL; | |
297 | } | |
298 | ||
299 | ranges++; | |
300 | ddata->module_pa = of_translate_address(np, ranges++); | |
301 | ddata->module_size = be32_to_cpup(ranges); | |
302 | ||
0eecc636 TL |
303 | return 0; |
304 | } | |
305 | ||
3bb37c8e TL |
306 | static struct device_node *stdout_path; |
307 | ||
308 | static void sysc_init_stdout_path(struct sysc *ddata) | |
309 | { | |
310 | struct device_node *np = NULL; | |
311 | const char *uart; | |
312 | ||
313 | if (IS_ERR(stdout_path)) | |
314 | return; | |
315 | ||
316 | if (stdout_path) | |
317 | return; | |
318 | ||
319 | np = of_find_node_by_path("/chosen"); | |
320 | if (!np) | |
321 | goto err; | |
322 | ||
323 | uart = of_get_property(np, "stdout-path", NULL); | |
324 | if (!uart) | |
325 | goto err; | |
326 | ||
327 | np = of_find_node_by_path(uart); | |
328 | if (!np) | |
329 | goto err; | |
330 | ||
331 | stdout_path = np; | |
332 | ||
333 | return; | |
334 | ||
335 | err: | |
336 | stdout_path = ERR_PTR(-ENODEV); | |
337 | } | |
338 | ||
339 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
340 | struct device_node *np) | |
341 | { | |
342 | sysc_init_stdout_path(ddata); | |
343 | if (np != stdout_path) | |
344 | return; | |
345 | ||
346 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
347 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
348 | } | |
349 | ||
0eecc636 TL |
350 | /** |
351 | * sysc_check_one_child - check child configuration | |
352 | * @ddata: device driver data | |
353 | * @np: child device node | |
354 | * | |
355 | * Let's avoid messy situations where we have new interconnect target | |
356 | * node but children have "ti,hwmods". These belong to the interconnect | |
357 | * target node and are managed by this driver. | |
358 | */ | |
359 | static int sysc_check_one_child(struct sysc *ddata, | |
360 | struct device_node *np) | |
361 | { | |
362 | const char *name; | |
363 | ||
364 | name = of_get_property(np, "ti,hwmods", NULL); | |
365 | if (name) | |
366 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); | |
367 | ||
3bb37c8e TL |
368 | sysc_check_quirk_stdout(ddata, np); |
369 | ||
0eecc636 TL |
370 | return 0; |
371 | } | |
372 | ||
373 | static int sysc_check_children(struct sysc *ddata) | |
374 | { | |
375 | struct device_node *child; | |
376 | int error; | |
377 | ||
378 | for_each_child_of_node(ddata->dev->of_node, child) { | |
379 | error = sysc_check_one_child(ddata, child); | |
380 | if (error) | |
381 | return error; | |
382 | } | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
a7199e2b TL |
387 | /* |
388 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
389 | * in two registers with stride of 4. We can detect this based on the rev | |
390 | * register size to configure things far enough to be able to properly read | |
391 | * the revision register. | |
392 | */ | |
393 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
394 | { | |
dd57ac1e | 395 | if (resource_size(res) == 8) |
a7199e2b | 396 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
397 | } |
398 | ||
0eecc636 TL |
399 | /** |
400 | * sysc_parse_one - parses the interconnect target module registers | |
401 | * @ddata: device driver data | |
402 | * @reg: register to parse | |
403 | */ | |
404 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
405 | { | |
406 | struct resource *res; | |
407 | const char *name; | |
408 | ||
409 | switch (reg) { | |
410 | case SYSC_REVISION: | |
411 | case SYSC_SYSCONFIG: | |
412 | case SYSC_SYSSTATUS: | |
413 | name = reg_names[reg]; | |
414 | break; | |
415 | default: | |
416 | return -EINVAL; | |
417 | } | |
418 | ||
419 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
420 | IORESOURCE_MEM, name); | |
421 | if (!res) { | |
0eecc636 TL |
422 | ddata->offsets[reg] = -ENODEV; |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
428 | if (reg == SYSC_REVISION) |
429 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
430 | |
431 | return 0; | |
432 | } | |
433 | ||
434 | static int sysc_parse_registers(struct sysc *ddata) | |
435 | { | |
436 | int i, error; | |
437 | ||
438 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
439 | error = sysc_parse_one(ddata, i); | |
440 | if (error) | |
441 | return error; | |
442 | } | |
443 | ||
444 | return 0; | |
445 | } | |
446 | ||
447 | /** | |
448 | * sysc_check_registers - check for misconfigured register overlaps | |
449 | * @ddata: device driver data | |
450 | */ | |
451 | static int sysc_check_registers(struct sysc *ddata) | |
452 | { | |
453 | int i, j, nr_regs = 0, nr_matches = 0; | |
454 | ||
455 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
456 | if (ddata->offsets[i] < 0) | |
457 | continue; | |
458 | ||
459 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
460 | dev_err(ddata->dev, "register outside module range"); | |
461 | ||
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
466 | if (ddata->offsets[j] < 0) | |
467 | continue; | |
468 | ||
469 | if (ddata->offsets[i] == ddata->offsets[j]) | |
470 | nr_matches++; | |
471 | } | |
472 | nr_regs++; | |
473 | } | |
474 | ||
475 | if (nr_regs < 1) { | |
476 | dev_err(ddata->dev, "missing registers\n"); | |
477 | ||
478 | return -EINVAL; | |
479 | } | |
480 | ||
481 | if (nr_matches > nr_regs) { | |
482 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
483 | nr_regs, nr_matches); | |
484 | ||
485 | return -EINVAL; | |
486 | } | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | /** | |
492 | * syc_ioremap - ioremap register space for the interconnect target module | |
493 | * @ddata: deviec driver data | |
494 | * | |
495 | * Note that the interconnect target module registers can be anywhere | |
496 | * within the first child device address space. For example, SGX has | |
497 | * them at offset 0x1fc00 in the 32MB module address space. We just | |
498 | * what we need around the interconnect target module registers. | |
499 | */ | |
500 | static int sysc_ioremap(struct sysc *ddata) | |
501 | { | |
502 | u32 size = 0; | |
503 | ||
504 | if (ddata->offsets[SYSC_SYSSTATUS] >= 0) | |
505 | size = ddata->offsets[SYSC_SYSSTATUS]; | |
506 | else if (ddata->offsets[SYSC_SYSCONFIG] >= 0) | |
507 | size = ddata->offsets[SYSC_SYSCONFIG]; | |
508 | else if (ddata->offsets[SYSC_REVISION] >= 0) | |
509 | size = ddata->offsets[SYSC_REVISION]; | |
510 | else | |
511 | return -EINVAL; | |
512 | ||
513 | size &= 0xfff00; | |
514 | size += SZ_256; | |
515 | ||
516 | ddata->module_va = devm_ioremap(ddata->dev, | |
517 | ddata->module_pa, | |
518 | size); | |
519 | if (!ddata->module_va) | |
520 | return -EIO; | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | /** | |
526 | * sysc_map_and_check_registers - ioremap and check device registers | |
527 | * @ddata: device driver data | |
528 | */ | |
529 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
530 | { | |
531 | int error; | |
532 | ||
533 | error = sysc_parse_and_check_child_range(ddata); | |
534 | if (error) | |
535 | return error; | |
536 | ||
537 | error = sysc_check_children(ddata); | |
538 | if (error) | |
539 | return error; | |
540 | ||
541 | error = sysc_parse_registers(ddata); | |
542 | if (error) | |
543 | return error; | |
544 | ||
545 | error = sysc_ioremap(ddata); | |
546 | if (error) | |
547 | return error; | |
548 | ||
549 | error = sysc_check_registers(ddata); | |
550 | if (error) | |
551 | return error; | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | /** | |
557 | * sysc_show_rev - read and show interconnect target module revision | |
558 | * @bufp: buffer to print the information to | |
559 | * @ddata: device driver data | |
560 | */ | |
561 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
562 | { | |
566a9b05 | 563 | int len; |
0eecc636 TL |
564 | |
565 | if (ddata->offsets[SYSC_REVISION] < 0) | |
566 | return sprintf(bufp, ":NA"); | |
567 | ||
566a9b05 | 568 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
569 | |
570 | return len; | |
571 | } | |
572 | ||
573 | static int sysc_show_reg(struct sysc *ddata, | |
574 | char *bufp, enum sysc_registers reg) | |
575 | { | |
576 | if (ddata->offsets[reg] < 0) | |
577 | return sprintf(bufp, ":NA"); | |
578 | ||
579 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
580 | } | |
581 | ||
a885f0fe TL |
582 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
583 | { | |
584 | if (!ddata->name) | |
585 | return 0; | |
586 | ||
587 | return sprintf(bufp, ":%s", ddata->name); | |
588 | } | |
589 | ||
0eecc636 TL |
590 | /** |
591 | * sysc_show_registers - show information about interconnect target module | |
592 | * @ddata: device driver data | |
593 | */ | |
594 | static void sysc_show_registers(struct sysc *ddata) | |
595 | { | |
596 | char buf[128]; | |
597 | char *bufp = buf; | |
598 | int i; | |
599 | ||
600 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
601 | bufp += sysc_show_reg(ddata, bufp, i); | |
602 | ||
603 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 604 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
605 | |
606 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
607 | ddata->module_pa, ddata->module_size, | |
608 | buf); | |
609 | } | |
610 | ||
a4a5d493 | 611 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) |
0eecc636 | 612 | { |
ef70b0bd | 613 | struct ti_sysc_platform_data *pdata; |
0eecc636 | 614 | struct sysc *ddata; |
ef70b0bd | 615 | int error = 0, i; |
0eecc636 TL |
616 | |
617 | ddata = dev_get_drvdata(dev); | |
618 | ||
ef70b0bd | 619 | if (!ddata->enabled) |
0eecc636 TL |
620 | return 0; |
621 | ||
ef70b0bd TL |
622 | if (ddata->legacy_mode) { |
623 | pdata = dev_get_platdata(ddata->dev); | |
624 | if (!pdata) | |
625 | return 0; | |
626 | ||
627 | if (!pdata->idle_module) | |
628 | return -ENODEV; | |
629 | ||
630 | error = pdata->idle_module(dev, &ddata->cookie); | |
631 | if (error) | |
632 | dev_err(dev, "%s: could not idle: %i\n", | |
633 | __func__, error); | |
634 | ||
635 | goto idled; | |
636 | } | |
637 | ||
09dfe581 | 638 | for (i = 0; i < ddata->nr_clocks; i++) { |
0eecc636 TL |
639 | if (IS_ERR_OR_NULL(ddata->clocks[i])) |
640 | continue; | |
09dfe581 TL |
641 | |
642 | if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata)) | |
643 | break; | |
644 | ||
0eecc636 TL |
645 | clk_disable(ddata->clocks[i]); |
646 | } | |
647 | ||
ef70b0bd TL |
648 | idled: |
649 | ddata->enabled = false; | |
650 | ||
651 | return error; | |
0eecc636 TL |
652 | } |
653 | ||
a4a5d493 | 654 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 | 655 | { |
ef70b0bd | 656 | struct ti_sysc_platform_data *pdata; |
0eecc636 | 657 | struct sysc *ddata; |
ef70b0bd | 658 | int error = 0, i; |
0eecc636 TL |
659 | |
660 | ddata = dev_get_drvdata(dev); | |
661 | ||
ef70b0bd | 662 | if (ddata->enabled) |
0eecc636 TL |
663 | return 0; |
664 | ||
ef70b0bd TL |
665 | if (ddata->legacy_mode) { |
666 | pdata = dev_get_platdata(ddata->dev); | |
667 | if (!pdata) | |
668 | return 0; | |
669 | ||
670 | if (!pdata->enable_module) | |
671 | return -ENODEV; | |
672 | ||
673 | error = pdata->enable_module(dev, &ddata->cookie); | |
674 | if (error) | |
675 | dev_err(dev, "%s: could not enable: %i\n", | |
676 | __func__, error); | |
677 | ||
678 | goto awake; | |
679 | } | |
680 | ||
09dfe581 | 681 | for (i = 0; i < ddata->nr_clocks; i++) { |
0eecc636 TL |
682 | if (IS_ERR_OR_NULL(ddata->clocks[i])) |
683 | continue; | |
09dfe581 TL |
684 | |
685 | if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata)) | |
686 | break; | |
687 | ||
0eecc636 TL |
688 | error = clk_enable(ddata->clocks[i]); |
689 | if (error) | |
690 | return error; | |
691 | } | |
692 | ||
ef70b0bd TL |
693 | awake: |
694 | ddata->enabled = true; | |
695 | ||
696 | return error; | |
0eecc636 TL |
697 | } |
698 | ||
62020f23 TL |
699 | #ifdef CONFIG_PM_SLEEP |
700 | static int sysc_suspend(struct device *dev) | |
701 | { | |
702 | struct sysc *ddata; | |
ef55f821 | 703 | int error; |
62020f23 TL |
704 | |
705 | ddata = dev_get_drvdata(dev); | |
706 | ||
e7420c2d TL |
707 | if (ddata->cfg.quirks & (SYSC_QUIRK_RESOURCE_PROVIDER | |
708 | SYSC_QUIRK_LEGACY_IDLE)) | |
709 | return 0; | |
710 | ||
62020f23 TL |
711 | if (!ddata->enabled) |
712 | return 0; | |
713 | ||
ef55f821 TL |
714 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
715 | ddata->name ? ddata->name : ""); | |
716 | ||
717 | error = pm_runtime_put_sync_suspend(dev); | |
718 | if (error < 0) { | |
719 | dev_warn(ddata->dev, "%s not idle %i %s\n", | |
720 | __func__, error, | |
721 | ddata->name ? ddata->name : ""); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
62020f23 TL |
726 | ddata->needs_resume = true; |
727 | ||
ef55f821 | 728 | return 0; |
62020f23 TL |
729 | } |
730 | ||
731 | static int sysc_resume(struct device *dev) | |
732 | { | |
733 | struct sysc *ddata; | |
ef55f821 | 734 | int error; |
62020f23 TL |
735 | |
736 | ddata = dev_get_drvdata(dev); | |
e7420c2d TL |
737 | |
738 | if (ddata->cfg.quirks & (SYSC_QUIRK_RESOURCE_PROVIDER | | |
739 | SYSC_QUIRK_LEGACY_IDLE)) | |
740 | return 0; | |
741 | ||
742 | if (ddata->needs_resume) { | |
743 | dev_dbg(ddata->dev, "%s %s\n", __func__, | |
744 | ddata->name ? ddata->name : ""); | |
745 | ||
ef55f821 TL |
746 | error = pm_runtime_get_sync(dev); |
747 | if (error < 0) { | |
748 | dev_err(ddata->dev, "%s error %i %s\n", | |
749 | __func__, error, | |
750 | ddata->name ? ddata->name : ""); | |
e7420c2d | 751 | |
ef55f821 TL |
752 | return error; |
753 | } | |
754 | ||
755 | ddata->needs_resume = false; | |
e7420c2d TL |
756 | } |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | static int sysc_noirq_suspend(struct device *dev) | |
762 | { | |
763 | struct sysc *ddata; | |
764 | ||
765 | ddata = dev_get_drvdata(dev); | |
766 | ||
767 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
768 | return 0; | |
769 | ||
770 | if (!(ddata->cfg.quirks & SYSC_QUIRK_RESOURCE_PROVIDER)) | |
771 | return 0; | |
772 | ||
773 | if (!ddata->enabled) | |
774 | return 0; | |
775 | ||
776 | dev_dbg(ddata->dev, "%s %s\n", __func__, | |
777 | ddata->name ? ddata->name : ""); | |
778 | ||
779 | ddata->needs_resume = true; | |
780 | ||
781 | return sysc_runtime_suspend(dev); | |
782 | } | |
783 | ||
784 | static int sysc_noirq_resume(struct device *dev) | |
785 | { | |
786 | struct sysc *ddata; | |
787 | ||
788 | ddata = dev_get_drvdata(dev); | |
789 | ||
790 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
791 | return 0; | |
792 | ||
793 | if (!(ddata->cfg.quirks & SYSC_QUIRK_RESOURCE_PROVIDER)) | |
794 | return 0; | |
795 | ||
62020f23 | 796 | if (ddata->needs_resume) { |
ef55f821 TL |
797 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
798 | ddata->name ? ddata->name : ""); | |
799 | ||
62020f23 TL |
800 | ddata->needs_resume = false; |
801 | ||
802 | return sysc_runtime_resume(dev); | |
803 | } | |
804 | ||
0eecc636 TL |
805 | return 0; |
806 | } | |
62020f23 | 807 | #endif |
0eecc636 TL |
808 | |
809 | static const struct dev_pm_ops sysc_pm_ops = { | |
62020f23 | 810 | SET_SYSTEM_SLEEP_PM_OPS(sysc_suspend, sysc_resume) |
e7420c2d | 811 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
812 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
813 | sysc_runtime_resume, | |
814 | NULL) | |
815 | }; | |
816 | ||
a885f0fe TL |
817 | /* Module revision register based quirks */ |
818 | struct sysc_revision_quirk { | |
819 | const char *name; | |
820 | u32 base; | |
821 | int rev_offset; | |
822 | int sysc_offset; | |
823 | int syss_offset; | |
824 | u32 revision; | |
825 | u32 revision_mask; | |
826 | u32 quirks; | |
827 | }; | |
828 | ||
829 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
830 | optrev_val, optrevmask, optquirkmask) \ | |
831 | { \ | |
832 | .name = (optname), \ | |
833 | .base = (optbase), \ | |
834 | .rev_offset = (optrev), \ | |
835 | .sysc_offset = (optsysc), \ | |
836 | .syss_offset = (optsyss), \ | |
837 | .revision = (optrev_val), \ | |
838 | .revision_mask = (optrevmask), \ | |
839 | .quirks = (optquirkmask), \ | |
840 | } | |
841 | ||
842 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
e7420c2d TL |
843 | /* These need to use noirq_suspend */ |
844 | SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, | |
845 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
846 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xffffffff, | |
847 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
848 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffffffff, | |
849 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
850 | SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, | |
851 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
852 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xffffffff, | |
853 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
854 | SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, | |
855 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
856 | SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, | |
857 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
858 | SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, | |
859 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
860 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, | |
861 | SYSC_QUIRK_RESOURCE_PROVIDER), | |
862 | ||
a885f0fe TL |
863 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ |
864 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffffffff, | |
09dfe581 | 865 | SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), |
a885f0fe TL |
866 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
867 | SYSC_QUIRK_LEGACY_IDLE), | |
868 | SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, | |
869 | SYSC_QUIRK_LEGACY_IDLE), | |
870 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, | |
871 | SYSC_QUIRK_LEGACY_IDLE), | |
872 | SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, | |
873 | SYSC_QUIRK_LEGACY_IDLE), | |
874 | SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, | |
875 | SYSC_QUIRK_LEGACY_IDLE), | |
876 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, | |
877 | SYSC_QUIRK_LEGACY_IDLE), | |
8cde5d5f TL |
878 | /* Some timers on omap4 and later */ |
879 | SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffffffff, | |
880 | SYSC_QUIRK_LEGACY_IDLE), | |
a885f0fe TL |
881 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
882 | SYSC_QUIRK_LEGACY_IDLE), | |
d708bb14 TL |
883 | /* Uarts on omap4 and later */ |
884 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffffffff, | |
885 | SYSC_QUIRK_LEGACY_IDLE), | |
7e27e5d0 TL |
886 | |
887 | /* These devices don't yet suspend properly without legacy setting */ | |
888 | SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffffffff, | |
889 | SYSC_QUIRK_LEGACY_IDLE), | |
890 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xffffffff, | |
891 | SYSC_QUIRK_LEGACY_IDLE), | |
892 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0d00, 0xffffffff, | |
893 | SYSC_QUIRK_LEGACY_IDLE), | |
dc4c85ea TL |
894 | |
895 | #ifdef DEBUG | |
896 | SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), | |
897 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), | |
898 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0), | |
899 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), | |
900 | SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), | |
901 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), | |
902 | SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), | |
903 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), | |
904 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), | |
905 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), | |
906 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), | |
907 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), | |
908 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), | |
909 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, | |
910 | 0xffffffff, 0), | |
911 | #endif | |
a885f0fe TL |
912 | }; |
913 | ||
914 | static void sysc_init_revision_quirks(struct sysc *ddata) | |
915 | { | |
916 | const struct sysc_revision_quirk *q; | |
917 | int i; | |
918 | ||
919 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
920 | q = &sysc_revision_quirks[i]; | |
921 | ||
922 | if (q->base && q->base != ddata->module_pa) | |
923 | continue; | |
924 | ||
925 | if (q->rev_offset >= 0 && | |
926 | q->rev_offset != ddata->offsets[SYSC_REVISION]) | |
927 | continue; | |
928 | ||
929 | if (q->sysc_offset >= 0 && | |
930 | q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) | |
931 | continue; | |
932 | ||
933 | if (q->syss_offset >= 0 && | |
934 | q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) | |
935 | continue; | |
936 | ||
937 | if (q->revision == ddata->revision || | |
938 | (q->revision & q->revision_mask) == | |
939 | (ddata->revision & q->revision_mask)) { | |
940 | ddata->name = q->name; | |
941 | ddata->cfg.quirks |= q->quirks; | |
942 | } | |
943 | } | |
944 | } | |
945 | ||
566a9b05 TL |
946 | /* At this point the module is configured enough to read the revision */ |
947 | static int sysc_init_module(struct sysc *ddata) | |
948 | { | |
949 | int error; | |
950 | ||
a885f0fe TL |
951 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) { |
952 | ddata->revision = sysc_read_revision(ddata); | |
953 | goto rev_quirks; | |
954 | } | |
955 | ||
566a9b05 TL |
956 | error = pm_runtime_get_sync(ddata->dev); |
957 | if (error < 0) { | |
958 | pm_runtime_put_noidle(ddata->dev); | |
959 | ||
960 | return 0; | |
961 | } | |
5062236e | 962 | |
566a9b05 TL |
963 | ddata->revision = sysc_read_revision(ddata); |
964 | pm_runtime_put_sync(ddata->dev); | |
965 | ||
a885f0fe TL |
966 | rev_quirks: |
967 | sysc_init_revision_quirks(ddata); | |
968 | ||
566a9b05 TL |
969 | return 0; |
970 | } | |
971 | ||
c5a2de97 TL |
972 | static int sysc_init_sysc_mask(struct sysc *ddata) |
973 | { | |
974 | struct device_node *np = ddata->dev->of_node; | |
975 | int error; | |
976 | u32 val; | |
977 | ||
978 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
979 | if (error) | |
980 | return 0; | |
981 | ||
982 | if (val) | |
983 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; | |
984 | else | |
985 | ddata->cfg.sysc_val = ddata->cap->sysc_mask; | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
990 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
991 | const char *name) | |
992 | { | |
993 | struct device_node *np = ddata->dev->of_node; | |
994 | struct property *prop; | |
995 | const __be32 *p; | |
996 | u32 val; | |
997 | ||
998 | of_property_for_each_u32(np, name, prop, p, val) { | |
999 | if (val >= SYSC_NR_IDLEMODES) { | |
1000 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
1001 | return -EINVAL; | |
1002 | } | |
1003 | *idlemodes |= (1 << val); | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static int sysc_init_idlemodes(struct sysc *ddata) | |
1010 | { | |
1011 | int error; | |
1012 | ||
1013 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
1014 | "ti,sysc-midle"); | |
1015 | if (error) | |
1016 | return error; | |
1017 | ||
1018 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
1019 | "ti,sysc-sidle"); | |
1020 | if (error) | |
1021 | return error; | |
1022 | ||
1023 | return 0; | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
1028 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
1029 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
1030 | * have multiple bits for the child devices like OHCI and EHCI. | |
1031 | * Depends on SYSC being parsed first. | |
1032 | */ | |
1033 | static int sysc_init_syss_mask(struct sysc *ddata) | |
1034 | { | |
1035 | struct device_node *np = ddata->dev->of_node; | |
1036 | int error; | |
1037 | u32 val; | |
1038 | ||
1039 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
1040 | if (error) { | |
1041 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
1042 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
1043 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1044 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
1050 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
1051 | ||
1052 | ddata->cfg.syss_mask = val; | |
1053 | ||
1054 | return 0; | |
1055 | } | |
1056 | ||
2c355ff6 | 1057 | /* |
8b2830ba TL |
1058 | * Many child device drivers need to have fck and opt clocks available |
1059 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 1060 | */ |
8b2830ba TL |
1061 | static int sysc_child_add_named_clock(struct sysc *ddata, |
1062 | struct device *child, | |
1063 | const char *name) | |
2c355ff6 | 1064 | { |
8b2830ba | 1065 | struct clk *clk; |
2c355ff6 | 1066 | struct clk_lookup *l; |
8b2830ba | 1067 | int error = 0; |
2c355ff6 | 1068 | |
8b2830ba | 1069 | if (!name) |
2c355ff6 TL |
1070 | return 0; |
1071 | ||
8b2830ba TL |
1072 | clk = clk_get(child, name); |
1073 | if (!IS_ERR(clk)) { | |
1074 | clk_put(clk); | |
2c355ff6 TL |
1075 | |
1076 | return -EEXIST; | |
1077 | } | |
1078 | ||
8b2830ba TL |
1079 | clk = clk_get(ddata->dev, name); |
1080 | if (IS_ERR(clk)) | |
1081 | return -ENODEV; | |
2c355ff6 | 1082 | |
8b2830ba TL |
1083 | l = clkdev_create(clk, name, dev_name(child)); |
1084 | if (!l) | |
1085 | error = -ENOMEM; | |
1086 | ||
1087 | clk_put(clk); | |
1088 | ||
1089 | return error; | |
2c355ff6 TL |
1090 | } |
1091 | ||
09dfe581 TL |
1092 | static int sysc_child_add_clocks(struct sysc *ddata, |
1093 | struct device *child) | |
1094 | { | |
1095 | int i, error; | |
1096 | ||
1097 | for (i = 0; i < ddata->nr_clocks; i++) { | |
1098 | error = sysc_child_add_named_clock(ddata, | |
1099 | child, | |
1100 | ddata->clock_roles[i]); | |
1101 | if (error && error != -EEXIST) { | |
1102 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
1103 | ddata->clock_roles[i], error); | |
1104 | ||
1105 | return error; | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | return 0; | |
1110 | } | |
1111 | ||
2c355ff6 TL |
1112 | static struct device_type sysc_device_type = { |
1113 | }; | |
1114 | ||
1115 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
1116 | { | |
1117 | struct device *parent = dev->parent; | |
1118 | ||
1119 | if (!parent || parent->type != &sysc_device_type) | |
1120 | return NULL; | |
1121 | ||
1122 | return dev_get_drvdata(parent); | |
1123 | } | |
1124 | ||
a885f0fe TL |
1125 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
1126 | { | |
1127 | struct sysc *ddata; | |
1128 | int error; | |
1129 | ||
1130 | ddata = sysc_child_to_parent(dev); | |
1131 | ||
1132 | error = pm_generic_runtime_suspend(dev); | |
1133 | if (error) | |
1134 | return error; | |
1135 | ||
1136 | if (!ddata->enabled) | |
1137 | return 0; | |
1138 | ||
1139 | return sysc_runtime_suspend(ddata->dev); | |
1140 | } | |
1141 | ||
1142 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
1143 | { | |
1144 | struct sysc *ddata; | |
1145 | int error; | |
1146 | ||
1147 | ddata = sysc_child_to_parent(dev); | |
1148 | ||
1149 | if (!ddata->enabled) { | |
1150 | error = sysc_runtime_resume(ddata->dev); | |
1151 | if (error < 0) | |
1152 | dev_err(ddata->dev, | |
1153 | "%s error: %i\n", __func__, error); | |
1154 | } | |
1155 | ||
1156 | return pm_generic_runtime_resume(dev); | |
1157 | } | |
1158 | ||
1159 | #ifdef CONFIG_PM_SLEEP | |
1160 | static int sysc_child_suspend_noirq(struct device *dev) | |
1161 | { | |
1162 | struct sysc *ddata; | |
1163 | int error; | |
1164 | ||
1165 | ddata = sysc_child_to_parent(dev); | |
1166 | ||
ef55f821 TL |
1167 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1168 | ddata->name ? ddata->name : ""); | |
1169 | ||
a885f0fe | 1170 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
1171 | if (error) { |
1172 | dev_err(dev, "%s error at %i: %i\n", | |
1173 | __func__, __LINE__, error); | |
1174 | ||
a885f0fe | 1175 | return error; |
ef55f821 | 1176 | } |
a885f0fe TL |
1177 | |
1178 | if (!pm_runtime_status_suspended(dev)) { | |
1179 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 TL |
1180 | if (error) { |
1181 | dev_err(dev, "%s error at %i: %i\n", | |
1182 | __func__, __LINE__, error); | |
1183 | ||
a885f0fe | 1184 | return error; |
ef55f821 | 1185 | } |
a885f0fe TL |
1186 | |
1187 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
1188 | if (error) { |
1189 | dev_err(dev, "%s error at %i: %i\n", | |
1190 | __func__, __LINE__, error); | |
1191 | ||
a885f0fe | 1192 | return error; |
ef55f821 | 1193 | } |
a885f0fe TL |
1194 | |
1195 | ddata->child_needs_resume = true; | |
1196 | } | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
1201 | static int sysc_child_resume_noirq(struct device *dev) | |
1202 | { | |
1203 | struct sysc *ddata; | |
1204 | int error; | |
1205 | ||
1206 | ddata = sysc_child_to_parent(dev); | |
1207 | ||
ef55f821 TL |
1208 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
1209 | ddata->name ? ddata->name : ""); | |
1210 | ||
a885f0fe TL |
1211 | if (ddata->child_needs_resume) { |
1212 | ddata->child_needs_resume = false; | |
1213 | ||
1214 | error = sysc_runtime_resume(ddata->dev); | |
1215 | if (error) | |
1216 | dev_err(ddata->dev, | |
1217 | "%s runtime resume error: %i\n", | |
1218 | __func__, error); | |
1219 | ||
1220 | error = pm_generic_runtime_resume(dev); | |
1221 | if (error) | |
1222 | dev_err(ddata->dev, | |
1223 | "%s generic runtime resume: %i\n", | |
1224 | __func__, error); | |
1225 | } | |
1226 | ||
1227 | return pm_generic_resume_noirq(dev); | |
1228 | } | |
1229 | #endif | |
1230 | ||
1231 | struct dev_pm_domain sysc_child_pm_domain = { | |
1232 | .ops = { | |
1233 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
1234 | sysc_child_runtime_resume, | |
1235 | NULL) | |
1236 | USE_PLATFORM_PM_SLEEP_OPS | |
1237 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
1238 | sysc_child_resume_noirq) | |
1239 | } | |
1240 | }; | |
1241 | ||
1242 | /** | |
1243 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
1244 | * @ddata: device driver data | |
1245 | * @child: child device driver | |
1246 | * | |
1247 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
1248 | * Otherwise many child devices will not idle because of the permanent | |
1249 | * parent usecount set in pm_runtime_irq_safe(). | |
1250 | * | |
1251 | * Note that the long term solution is to just modify the child device | |
1252 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
1253 | * dropped. | |
1254 | */ | |
1255 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
1256 | { | |
1257 | if (!ddata->legacy_mode) | |
1258 | return; | |
1259 | ||
1260 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) | |
1261 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
1262 | } | |
1263 | ||
2c355ff6 TL |
1264 | static int sysc_notifier_call(struct notifier_block *nb, |
1265 | unsigned long event, void *device) | |
1266 | { | |
1267 | struct device *dev = device; | |
1268 | struct sysc *ddata; | |
1269 | int error; | |
1270 | ||
1271 | ddata = sysc_child_to_parent(dev); | |
1272 | if (!ddata) | |
1273 | return NOTIFY_DONE; | |
1274 | ||
1275 | switch (event) { | |
1276 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
1277 | error = sysc_child_add_clocks(ddata, dev); |
1278 | if (error) | |
1279 | return error; | |
a885f0fe | 1280 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
1281 | break; |
1282 | default: | |
1283 | break; | |
1284 | } | |
1285 | ||
1286 | return NOTIFY_DONE; | |
1287 | } | |
1288 | ||
1289 | static struct notifier_block sysc_nb = { | |
1290 | .notifier_call = sysc_notifier_call, | |
1291 | }; | |
1292 | ||
566a9b05 TL |
1293 | /* Device tree configured quirks */ |
1294 | struct sysc_dts_quirk { | |
1295 | const char *name; | |
1296 | u32 mask; | |
1297 | }; | |
1298 | ||
1299 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
1300 | { .name = "ti,no-idle-on-init", | |
1301 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
1302 | { .name = "ti,no-reset-on-init", | |
1303 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
1304 | }; | |
1305 | ||
1306 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
1307 | { | |
1308 | struct device_node *np = ddata->dev->of_node; | |
1309 | const struct property *prop; | |
1310 | int i, len, error; | |
1311 | u32 val; | |
1312 | ||
1313 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
1314 | ||
1315 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
1316 | prop = of_get_property(np, sysc_dts_quirks[i].name, &len); | |
1317 | if (!prop) | |
d39b6ea4 | 1318 | continue; |
566a9b05 TL |
1319 | |
1320 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
1321 | } | |
1322 | ||
1323 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); | |
1324 | if (!error) { | |
1325 | if (val > 255) { | |
1326 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
1327 | val); | |
1328 | } | |
1329 | ||
1330 | ddata->cfg.srst_udelay = (u8)val; | |
1331 | } | |
1332 | ||
1333 | return 0; | |
1334 | } | |
1335 | ||
0eecc636 TL |
1336 | static void sysc_unprepare(struct sysc *ddata) |
1337 | { | |
1338 | int i; | |
1339 | ||
1340 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { | |
1341 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
1342 | clk_unprepare(ddata->clocks[i]); | |
1343 | } | |
1344 | } | |
1345 | ||
70a65240 TL |
1346 | /* |
1347 | * Common sysc register bits found on omap2, also known as type1 | |
1348 | */ | |
1349 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
1350 | .dmadisable_shift = -ENODEV, | |
1351 | .midle_shift = 12, | |
1352 | .sidle_shift = 3, | |
1353 | .clkact_shift = 8, | |
1354 | .emufree_shift = 5, | |
1355 | .enwkup_shift = 2, | |
1356 | .srst_shift = 1, | |
1357 | .autoidle_shift = 0, | |
1358 | }; | |
1359 | ||
1360 | static const struct sysc_capabilities sysc_omap2 = { | |
1361 | .type = TI_SYSC_OMAP2, | |
1362 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1363 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1364 | SYSC_OMAP2_AUTOIDLE, | |
1365 | .regbits = &sysc_regbits_omap2, | |
1366 | }; | |
1367 | ||
1368 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
1369 | static const struct sysc_capabilities sysc_omap2_timer = { | |
1370 | .type = TI_SYSC_OMAP2_TIMER, | |
1371 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
1372 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
1373 | SYSC_OMAP2_AUTOIDLE, | |
1374 | .regbits = &sysc_regbits_omap2, | |
1375 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
1376 | }; | |
1377 | ||
1378 | /* | |
1379 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
1380 | * with different sidle position | |
1381 | */ | |
1382 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
1383 | .dmadisable_shift = -ENODEV, | |
1384 | .midle_shift = -ENODEV, | |
1385 | .sidle_shift = 4, | |
1386 | .clkact_shift = -ENODEV, | |
1387 | .enwkup_shift = -ENODEV, | |
1388 | .srst_shift = 1, | |
1389 | .autoidle_shift = 0, | |
1390 | .emufree_shift = -ENODEV, | |
1391 | }; | |
1392 | ||
1393 | static const struct sysc_capabilities sysc_omap3_sham = { | |
1394 | .type = TI_SYSC_OMAP3_SHAM, | |
1395 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1396 | .regbits = &sysc_regbits_omap3_sham, | |
1397 | }; | |
1398 | ||
1399 | /* | |
1400 | * AES register bits found on omap3 and later, a variant of | |
1401 | * sysc_regbits_omap2 with different sidle position | |
1402 | */ | |
1403 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
1404 | .dmadisable_shift = -ENODEV, | |
1405 | .midle_shift = -ENODEV, | |
1406 | .sidle_shift = 6, | |
1407 | .clkact_shift = -ENODEV, | |
1408 | .enwkup_shift = -ENODEV, | |
1409 | .srst_shift = 1, | |
1410 | .autoidle_shift = 0, | |
1411 | .emufree_shift = -ENODEV, | |
1412 | }; | |
1413 | ||
1414 | static const struct sysc_capabilities sysc_omap3_aes = { | |
1415 | .type = TI_SYSC_OMAP3_AES, | |
1416 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
1417 | .regbits = &sysc_regbits_omap3_aes, | |
1418 | }; | |
1419 | ||
1420 | /* | |
1421 | * Common sysc register bits found on omap4, also known as type2 | |
1422 | */ | |
1423 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
1424 | .dmadisable_shift = 16, | |
1425 | .midle_shift = 4, | |
1426 | .sidle_shift = 2, | |
1427 | .clkact_shift = -ENODEV, | |
1428 | .enwkup_shift = -ENODEV, | |
1429 | .emufree_shift = 1, | |
1430 | .srst_shift = 0, | |
1431 | .autoidle_shift = -ENODEV, | |
1432 | }; | |
1433 | ||
1434 | static const struct sysc_capabilities sysc_omap4 = { | |
1435 | .type = TI_SYSC_OMAP4, | |
1436 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1437 | SYSC_OMAP4_SOFTRESET, | |
1438 | .regbits = &sysc_regbits_omap4, | |
1439 | }; | |
1440 | ||
1441 | static const struct sysc_capabilities sysc_omap4_timer = { | |
1442 | .type = TI_SYSC_OMAP4_TIMER, | |
1443 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
1444 | SYSC_OMAP4_SOFTRESET, | |
1445 | .regbits = &sysc_regbits_omap4, | |
1446 | }; | |
1447 | ||
1448 | /* | |
1449 | * Common sysc register bits found on omap4, also known as type3 | |
1450 | */ | |
1451 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
1452 | .dmadisable_shift = -ENODEV, | |
1453 | .midle_shift = 2, | |
1454 | .sidle_shift = 0, | |
1455 | .clkact_shift = -ENODEV, | |
1456 | .enwkup_shift = -ENODEV, | |
1457 | .srst_shift = -ENODEV, | |
1458 | .emufree_shift = -ENODEV, | |
1459 | .autoidle_shift = -ENODEV, | |
1460 | }; | |
1461 | ||
1462 | static const struct sysc_capabilities sysc_omap4_simple = { | |
1463 | .type = TI_SYSC_OMAP4_SIMPLE, | |
1464 | .regbits = &sysc_regbits_omap4_simple, | |
1465 | }; | |
1466 | ||
1467 | /* | |
1468 | * SmartReflex sysc found on omap34xx | |
1469 | */ | |
1470 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
1471 | .dmadisable_shift = -ENODEV, | |
1472 | .midle_shift = -ENODEV, | |
1473 | .sidle_shift = -ENODEV, | |
1474 | .clkact_shift = 20, | |
1475 | .enwkup_shift = -ENODEV, | |
1476 | .srst_shift = -ENODEV, | |
1477 | .emufree_shift = -ENODEV, | |
1478 | .autoidle_shift = -ENODEV, | |
1479 | }; | |
1480 | ||
1481 | static const struct sysc_capabilities sysc_34xx_sr = { | |
1482 | .type = TI_SYSC_OMAP34XX_SR, | |
1483 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
1484 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
1485 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
1486 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
1487 | }; |
1488 | ||
1489 | /* | |
1490 | * SmartReflex sysc found on omap36xx and later | |
1491 | */ | |
1492 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
1493 | .dmadisable_shift = -ENODEV, | |
1494 | .midle_shift = -ENODEV, | |
1495 | .sidle_shift = 24, | |
1496 | .clkact_shift = -ENODEV, | |
1497 | .enwkup_shift = 26, | |
1498 | .srst_shift = -ENODEV, | |
1499 | .emufree_shift = -ENODEV, | |
1500 | .autoidle_shift = -ENODEV, | |
1501 | }; | |
1502 | ||
1503 | static const struct sysc_capabilities sysc_36xx_sr = { | |
1504 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 1505 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 1506 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 1507 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1508 | }; |
1509 | ||
1510 | static const struct sysc_capabilities sysc_omap4_sr = { | |
1511 | .type = TI_SYSC_OMAP4_SR, | |
1512 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 1513 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
1514 | }; |
1515 | ||
1516 | /* | |
1517 | * McASP register bits found on omap4 and later | |
1518 | */ | |
1519 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
1520 | .dmadisable_shift = -ENODEV, | |
1521 | .midle_shift = -ENODEV, | |
1522 | .sidle_shift = 0, | |
1523 | .clkact_shift = -ENODEV, | |
1524 | .enwkup_shift = -ENODEV, | |
1525 | .srst_shift = -ENODEV, | |
1526 | .emufree_shift = -ENODEV, | |
1527 | .autoidle_shift = -ENODEV, | |
1528 | }; | |
1529 | ||
1530 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
1531 | .type = TI_SYSC_OMAP4_MCASP, | |
1532 | .regbits = &sysc_regbits_omap4_mcasp, | |
1533 | }; | |
1534 | ||
1535 | /* | |
1536 | * FS USB host found on omap4 and later | |
1537 | */ | |
1538 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
1539 | .dmadisable_shift = -ENODEV, | |
1540 | .midle_shift = -ENODEV, | |
1541 | .sidle_shift = 24, | |
1542 | .clkact_shift = -ENODEV, | |
1543 | .enwkup_shift = 26, | |
1544 | .srst_shift = -ENODEV, | |
1545 | .emufree_shift = -ENODEV, | |
1546 | .autoidle_shift = -ENODEV, | |
1547 | }; | |
1548 | ||
1549 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
1550 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
1551 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
1552 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
1553 | }; | |
1554 | ||
ef70b0bd TL |
1555 | static int sysc_init_pdata(struct sysc *ddata) |
1556 | { | |
1557 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
1558 | struct ti_sysc_module_data mdata; | |
1559 | int error = 0; | |
1560 | ||
1561 | if (!pdata || !ddata->legacy_mode) | |
1562 | return 0; | |
1563 | ||
1564 | mdata.name = ddata->legacy_mode; | |
1565 | mdata.module_pa = ddata->module_pa; | |
1566 | mdata.module_size = ddata->module_size; | |
1567 | mdata.offsets = ddata->offsets; | |
1568 | mdata.nr_offsets = SYSC_MAX_REGS; | |
1569 | mdata.cap = ddata->cap; | |
1570 | mdata.cfg = &ddata->cfg; | |
1571 | ||
1572 | if (!pdata->init_module) | |
1573 | return -ENODEV; | |
1574 | ||
1575 | error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie); | |
1576 | if (error == -EEXIST) | |
1577 | error = 0; | |
1578 | ||
1579 | return error; | |
1580 | } | |
1581 | ||
70a65240 TL |
1582 | static int sysc_init_match(struct sysc *ddata) |
1583 | { | |
1584 | const struct sysc_capabilities *cap; | |
1585 | ||
1586 | cap = of_device_get_match_data(ddata->dev); | |
1587 | if (!cap) | |
1588 | return -EINVAL; | |
1589 | ||
1590 | ddata->cap = cap; | |
1591 | if (ddata->cap) | |
1592 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
1593 | ||
1594 | return 0; | |
1595 | } | |
1596 | ||
76f0f772 TL |
1597 | static void ti_sysc_idle(struct work_struct *work) |
1598 | { | |
1599 | struct sysc *ddata; | |
1600 | ||
1601 | ddata = container_of(work, struct sysc, idle_work.work); | |
1602 | ||
1603 | if (pm_runtime_active(ddata->dev)) | |
1604 | pm_runtime_put_sync(ddata->dev); | |
1605 | } | |
1606 | ||
c4bebea8 TL |
1607 | static const struct of_device_id sysc_match_table[] = { |
1608 | { .compatible = "simple-bus", }, | |
1609 | { /* sentinel */ }, | |
1610 | }; | |
1611 | ||
0eecc636 TL |
1612 | static int sysc_probe(struct platform_device *pdev) |
1613 | { | |
ef70b0bd | 1614 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
1615 | struct sysc *ddata; |
1616 | int error; | |
1617 | ||
1618 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
1619 | if (!ddata) | |
1620 | return -ENOMEM; | |
1621 | ||
1622 | ddata->dev = &pdev->dev; | |
566a9b05 | 1623 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 1624 | |
70a65240 TL |
1625 | error = sysc_init_match(ddata); |
1626 | if (error) | |
1627 | return error; | |
1628 | ||
566a9b05 TL |
1629 | error = sysc_init_dts_quirks(ddata); |
1630 | if (error) | |
1631 | goto unprepare; | |
1632 | ||
0eecc636 TL |
1633 | error = sysc_get_clocks(ddata); |
1634 | if (error) | |
1635 | return error; | |
1636 | ||
1637 | error = sysc_map_and_check_registers(ddata); | |
1638 | if (error) | |
1639 | goto unprepare; | |
1640 | ||
c5a2de97 TL |
1641 | error = sysc_init_sysc_mask(ddata); |
1642 | if (error) | |
1643 | goto unprepare; | |
1644 | ||
1645 | error = sysc_init_idlemodes(ddata); | |
1646 | if (error) | |
1647 | goto unprepare; | |
1648 | ||
1649 | error = sysc_init_syss_mask(ddata); | |
1650 | if (error) | |
1651 | goto unprepare; | |
1652 | ||
ef70b0bd TL |
1653 | error = sysc_init_pdata(ddata); |
1654 | if (error) | |
1655 | goto unprepare; | |
1656 | ||
5062236e TL |
1657 | error = sysc_init_resets(ddata); |
1658 | if (error) | |
1659 | return error; | |
566a9b05 | 1660 | |
5062236e | 1661 | pm_runtime_enable(ddata->dev); |
566a9b05 TL |
1662 | error = sysc_init_module(ddata); |
1663 | if (error) | |
1664 | goto unprepare; | |
1665 | ||
0eecc636 TL |
1666 | error = pm_runtime_get_sync(ddata->dev); |
1667 | if (error < 0) { | |
1668 | pm_runtime_put_noidle(ddata->dev); | |
1669 | pm_runtime_disable(ddata->dev); | |
1670 | goto unprepare; | |
1671 | } | |
1672 | ||
0eecc636 TL |
1673 | sysc_show_registers(ddata); |
1674 | ||
2c355ff6 | 1675 | ddata->dev->type = &sysc_device_type; |
c4bebea8 TL |
1676 | error = of_platform_populate(ddata->dev->of_node, sysc_match_table, |
1677 | pdata ? pdata->auxdata : NULL, | |
ef70b0bd | 1678 | ddata->dev); |
0eecc636 TL |
1679 | if (error) |
1680 | goto err; | |
1681 | ||
76f0f772 TL |
1682 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
1683 | ||
1684 | /* At least earlycon won't survive without deferred idle */ | |
1685 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | | |
1686 | SYSC_QUIRK_NO_RESET_ON_INIT)) { | |
1687 | schedule_delayed_work(&ddata->idle_work, 3000); | |
1688 | } else { | |
1689 | pm_runtime_put(&pdev->dev); | |
1690 | } | |
0eecc636 | 1691 | |
5062236e TL |
1692 | if (!of_get_available_child_count(ddata->dev->of_node)) |
1693 | reset_control_assert(ddata->rsts); | |
1694 | ||
0eecc636 TL |
1695 | return 0; |
1696 | ||
1697 | err: | |
0eecc636 TL |
1698 | pm_runtime_put_sync(&pdev->dev); |
1699 | pm_runtime_disable(&pdev->dev); | |
1700 | unprepare: | |
1701 | sysc_unprepare(ddata); | |
1702 | ||
1703 | return error; | |
1704 | } | |
1705 | ||
684be5a4 TL |
1706 | static int sysc_remove(struct platform_device *pdev) |
1707 | { | |
1708 | struct sysc *ddata = platform_get_drvdata(pdev); | |
1709 | int error; | |
1710 | ||
76f0f772 TL |
1711 | cancel_delayed_work_sync(&ddata->idle_work); |
1712 | ||
684be5a4 TL |
1713 | error = pm_runtime_get_sync(ddata->dev); |
1714 | if (error < 0) { | |
1715 | pm_runtime_put_noidle(ddata->dev); | |
1716 | pm_runtime_disable(ddata->dev); | |
1717 | goto unprepare; | |
1718 | } | |
1719 | ||
1720 | of_platform_depopulate(&pdev->dev); | |
1721 | ||
684be5a4 TL |
1722 | pm_runtime_put_sync(&pdev->dev); |
1723 | pm_runtime_disable(&pdev->dev); | |
5062236e | 1724 | reset_control_assert(ddata->rsts); |
684be5a4 TL |
1725 | |
1726 | unprepare: | |
1727 | sysc_unprepare(ddata); | |
1728 | ||
1729 | return 0; | |
1730 | } | |
1731 | ||
0eecc636 | 1732 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
1733 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
1734 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
1735 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
1736 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
1737 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
1738 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
1739 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
1740 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
1741 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
1742 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
1743 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
1744 | { .compatible = "ti,sysc-usb-host-fs", | |
1745 | .data = &sysc_omap4_usb_host_fs, }, | |
0eecc636 TL |
1746 | { }, |
1747 | }; | |
1748 | MODULE_DEVICE_TABLE(of, sysc_match); | |
1749 | ||
1750 | static struct platform_driver sysc_driver = { | |
1751 | .probe = sysc_probe, | |
684be5a4 | 1752 | .remove = sysc_remove, |
0eecc636 TL |
1753 | .driver = { |
1754 | .name = "ti-sysc", | |
1755 | .of_match_table = sysc_match, | |
1756 | .pm = &sysc_pm_ops, | |
1757 | }, | |
1758 | }; | |
2c355ff6 TL |
1759 | |
1760 | static int __init sysc_init(void) | |
1761 | { | |
1762 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
1763 | ||
1764 | return platform_driver_register(&sysc_driver); | |
1765 | } | |
1766 | module_init(sysc_init); | |
1767 | ||
1768 | static void __exit sysc_exit(void) | |
1769 | { | |
1770 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
1771 | platform_driver_unregister(&sysc_driver); | |
1772 | } | |
1773 | module_exit(sysc_exit); | |
0eecc636 TL |
1774 | |
1775 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
1776 | MODULE_LICENSE("GPL v2"); |