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Merge tag 'ceph-for-5.1-rc3' of git://github.com/ceph/ceph-client
[linux-2.6-block.git] / drivers / bus / ti-sysc.c
CommitLineData
0eecc636
TL		 1/*
2 * ti-sysc.c - Texas Instruments sysc interconnect target driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/io.h>
15#include <linux/clk.h>
2c355ff6 16#include <linux/clkdev.h>
a885f0fe 17#include <linux/delay.h>
0eecc636
TL		 18#include <linux/module.h>
19#include <linux/platform_device.h>
a885f0fe 20#include <linux/pm_domain.h>
0eecc636 21#include <linux/pm_runtime.h>
5062236e 22#include <linux/reset.h>
0eecc636
TL		 23#include <linux/of_address.h>
24#include <linux/of_platform.h>
2c355ff6 25#include <linux/slab.h>
596e7955 26#include <linux/iopoll.h>
2c355ff6 27
70a65240
TL		 28#include <linux/platform_data/ti-sysc.h>
29
30#include <dt-bindings/bus/ti-sysc.h>
0eecc636 31
596e7955
FA		 32#define MAX_MODULE_SOFTRESET_WAIT 10000
33
0eecc636
TL		 34static const char * const reg_names[] = { "rev", "sysc", "syss", };
35
36enum sysc_clocks {
37 SYSC_FCK,
38 SYSC_ICK,
09dfe581
TL		 39 SYSC_OPTFCK0,
40 SYSC_OPTFCK1,
41 SYSC_OPTFCK2,
42 SYSC_OPTFCK3,
43 SYSC_OPTFCK4,
44 SYSC_OPTFCK5,
45 SYSC_OPTFCK6,
46 SYSC_OPTFCK7,
0eecc636
TL		 47 SYSC_MAX_CLOCKS,
48};
49
09dfe581 50static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", };
0eecc636 51
c5a2de97
TL		 52#define SYSC_IDLEMODE_MASK 3
53#define SYSC_CLOCKACTIVITY_MASK 3
54
0eecc636
TL		 55/**
56 * struct sysc - TI sysc interconnect target module registers and capabilities
57 * @dev: struct device pointer
58 * @module_pa: physical address of the interconnect target module
59 * @module_size: size of the interconnect target module
60 * @module_va: virtual address of the interconnect target module
61 * @offsets: register offsets from module base
62 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 63 * @clock_roles: clock role names for the found clocks
64 * @nr_clocks: number of clocks used by the interconnect target module
0eecc636 65 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 66 * @cap: interconnect target module capabilities
67 * @cfg: interconnect target module configuration
566a9b05
TL		 68 * @name: name if available
69 * @revision: interconnect target module revision
62020f23 70 * @needs_resume: runtime resume needed on resume from suspend
0eecc636
TL		 71 */
72struct sysc {
73 struct device *dev;
74 u64 module_pa;
75 u32 module_size;
76 void __iomem *module_va;
77 int offsets[SYSC_MAX_REGS];
09dfe581
TL		 78 struct clk **clocks;
79 const char **clock_roles;
80 int nr_clocks;
5062236e 81 struct reset_control *rsts;
0eecc636 82 const char *legacy_mode;
70a65240
TL		 83 const struct sysc_capabilities *cap;
84 struct sysc_config cfg;
ef70b0bd 85 struct ti_sysc_cookie cookie;
566a9b05
TL		 86 const char *name;
87 u32 revision;
62020f23
TL		 88 bool enabled;
89 bool needs_resume;
a885f0fe 90 bool child_needs_resume;
76f0f772 91 struct delayed_work idle_work;
0eecc636
TL		 92};
93
4014c08b
TL		 94static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
95 bool is_child);
96
596e7955
FA		 97void sysc_write(struct sysc *ddata, int offset, u32 value)
98{
99 writel_relaxed(value, ddata->module_va + offset);
100}
101
566a9b05
TL		 102static u32 sysc_read(struct sysc *ddata, int offset)
103{
104 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
105 u32 val;
106
107 val = readw_relaxed(ddata->module_va + offset);
108 val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
109
110 return val;
111 }
112
113 return readl_relaxed(ddata->module_va + offset);
114}
115
09dfe581
TL		 116static bool sysc_opt_clks_needed(struct sysc *ddata)
117{
118 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
119}
120
0eecc636
TL		 121static u32 sysc_read_revision(struct sysc *ddata)
122{
566a9b05
TL		 123 int offset = ddata->offsets[SYSC_REVISION];
124
125 if (offset < 0)
126 return 0;
127
128 return sysc_read(ddata, offset);
0eecc636
TL		 129}
130
09dfe581 131static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 132{
09dfe581
TL		 133 int error, i, index = -ENODEV;
134
135 if (!strncmp(clock_names[SYSC_FCK], name, 3))
136 index = SYSC_FCK;
137 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
138 index = SYSC_ICK;
139
140 if (index < 0) {
141 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 142 if (!ddata->clocks[i]) {
09dfe581
TL		 143 index = i;
144 break;
145 }
146 }
147 }
0eecc636 148
09dfe581
TL		 149 if (index < 0) {
150 dev_err(ddata->dev, "clock %s not added\n", name);
151 return index;
0eecc636 152 }
0eecc636
TL		 153
154 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
155 if (IS_ERR(ddata->clocks[index])) {
156 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
157 return 0;
158
159 dev_err(ddata->dev, "clock get error for %s: %li\n",
160 name, PTR_ERR(ddata->clocks[index]));
161
162 return PTR_ERR(ddata->clocks[index]);
163 }
164
165 error = clk_prepare(ddata->clocks[index]);
166 if (error) {
167 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
168 name, error);
169
170 return error;
171 }
172
173 return 0;
174}
175
176static int sysc_get_clocks(struct sysc *ddata)
177{
09dfe581
TL		 178 struct device_node *np = ddata->dev->of_node;
179 struct property *prop;
180 const char *name;
181 int nr_fck = 0, nr_ick = 0, i, error = 0;
182
20749051 183 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 184 SYSC_MAX_CLOCKS,
20749051 185 sizeof(*ddata->clock_roles),
09dfe581
TL		 186 GFP_KERNEL);
187 if (!ddata->clock_roles)
188 return -ENOMEM;
189
190 of_property_for_each_string(np, "clock-names", prop, name) {
191 if (!strncmp(clock_names[SYSC_FCK], name, 3))
192 nr_fck++;
193 if (!strncmp(clock_names[SYSC_ICK], name, 3))
194 nr_ick++;
195 ddata->clock_roles[ddata->nr_clocks] = name;
196 ddata->nr_clocks++;
197 }
198
199 if (ddata->nr_clocks < 1)
200 return 0;
201
202 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
203 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
204
205 return -EINVAL;
206 }
207
208 if (nr_fck > 1 || nr_ick > 1) {
209 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 210
09dfe581
TL		 211 return -EINVAL;
212 }
213
20749051
KC		 214 ddata->clocks = devm_kcalloc(ddata->dev,
215 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 216 GFP_KERNEL);
217 if (!ddata->clocks)
218 return -ENOMEM;
219
7b4f8ac2
TL		 220 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
221 const char *name = ddata->clock_roles[i];
222
223 if (!name)
224 continue;
225
226 error = sysc_get_one_clock(ddata, name);
0eecc636
TL		 227 if (error && error != -ENOENT)
228 return error;
229 }
230
231 return 0;
232}
233
5062236e
TL		 234/**
235 * sysc_init_resets - reset module on init
236 * @ddata: device driver data
237 *
238 * A module can have both OCP softreset control and external rstctrl.
239 * If more complicated rstctrl resets are needed, please handle these
240 * directly from the child device driver and map only the module reset
241 * for the parent interconnect target module device.
242 *
243 * Automatic reset of the module on init can be skipped with the
244 * "ti,no-reset-on-init" device tree property.
245 */
246static int sysc_init_resets(struct sysc *ddata)
247{
248 int error;
249
250 ddata->rsts =
251 devm_reset_control_array_get_optional_exclusive(ddata->dev);
252 if (IS_ERR(ddata->rsts))
253 return PTR_ERR(ddata->rsts);
254
255 if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
256 goto deassert;
257
258 error = reset_control_assert(ddata->rsts);
259 if (error)
260 return error;
261
262deassert:
263 error = reset_control_deassert(ddata->rsts);
264 if (error)
265 return error;
266
267 return 0;
268}
269
0eecc636
TL		 270/**
271 * sysc_parse_and_check_child_range - parses module IO region from ranges
272 * @ddata: device driver data
273 *
274 * In general we only need rev, syss, and sysc registers and not the whole
275 * module range. But we do want the offsets for these registers from the
276 * module base. This allows us to check them against the legacy hwmod
277 * platform data. Let's also check the ranges are configured properly.
278 */
279static int sysc_parse_and_check_child_range(struct sysc *ddata)
280{
281 struct device_node *np = ddata->dev->of_node;
282 const __be32 *ranges;
283 u32 nr_addr, nr_size;
284 int len, error;
285
286 ranges = of_get_property(np, "ranges", &len);
287 if (!ranges) {
288 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
289
290 return -ENOENT;
291 }
292
293 len /= sizeof(*ranges);
294
295 if (len < 3) {
296 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
297
298 return -EINVAL;
299 }
300
301 error = of_property_read_u32(np, "#address-cells", &nr_addr);
302 if (error)
303 return -ENOENT;
304
305 error = of_property_read_u32(np, "#size-cells", &nr_size);
306 if (error)
307 return -ENOENT;
308
309 if (nr_addr != 1 || nr_size != 1) {
310 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
311
312 return -EINVAL;
313 }
314
315 ranges++;
316 ddata->module_pa = of_translate_address(np, ranges++);
317 ddata->module_size = be32_to_cpup(ranges);
318
0eecc636
TL		 319 return 0;
320}
321
3bb37c8e
TL		 322static struct device_node *stdout_path;
323
324static void sysc_init_stdout_path(struct sysc *ddata)
325{
326 struct device_node *np = NULL;
327 const char *uart;
328
329 if (IS_ERR(stdout_path))
330 return;
331
332 if (stdout_path)
333 return;
334
335 np = of_find_node_by_path("/chosen");
336 if (!np)
337 goto err;
338
339 uart = of_get_property(np, "stdout-path", NULL);
340 if (!uart)
341 goto err;
342
343 np = of_find_node_by_path(uart);
344 if (!np)
345 goto err;
346
347 stdout_path = np;
348
349 return;
350
351err:
352 stdout_path = ERR_PTR(-ENODEV);
353}
354
355static void sysc_check_quirk_stdout(struct sysc *ddata,
356 struct device_node *np)
357{
358 sysc_init_stdout_path(ddata);
359 if (np != stdout_path)
360 return;
361
362 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
363 SYSC_QUIRK_NO_RESET_ON_INIT;
364}
365
0eecc636
TL		 366/**
367 * sysc_check_one_child - check child configuration
368 * @ddata: device driver data
369 * @np: child device node
370 *
371 * Let's avoid messy situations where we have new interconnect target
372 * node but children have "ti,hwmods". These belong to the interconnect
373 * target node and are managed by this driver.
374 */
375static int sysc_check_one_child(struct sysc *ddata,
376 struct device_node *np)
377{
378 const char *name;
379
380 name = of_get_property(np, "ti,hwmods", NULL);
381 if (name)
382 dev_warn(ddata->dev, "really a child ti,hwmods property?");
383
3bb37c8e 384 sysc_check_quirk_stdout(ddata, np);
4014c08b 385 sysc_parse_dts_quirks(ddata, np, true);
3bb37c8e 386
0eecc636
TL		 387 return 0;
388}
389
390static int sysc_check_children(struct sysc *ddata)
391{
392 struct device_node *child;
393 int error;
394
395 for_each_child_of_node(ddata->dev->of_node, child) {
396 error = sysc_check_one_child(ddata, child);
397 if (error)
398 return error;
399 }
400
401 return 0;
402}
403
a7199e2b
TL		 404/*
405 * So far only I2C uses 16-bit read access with clockactivity with revision
406 * in two registers with stride of 4. We can detect this based on the rev
407 * register size to configure things far enough to be able to properly read
408 * the revision register.
409 */
410static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
411{
dd57ac1e 412 if (resource_size(res) == 8)
a7199e2b 413 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 414}
415
0eecc636
TL		 416/**
417 * sysc_parse_one - parses the interconnect target module registers
418 * @ddata: device driver data
419 * @reg: register to parse
420 */
421static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
422{
423 struct resource *res;
424 const char *name;
425
426 switch (reg) {
427 case SYSC_REVISION:
428 case SYSC_SYSCONFIG:
429 case SYSC_SYSSTATUS:
430 name = reg_names[reg];
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 res = platform_get_resource_byname(to_platform_device(ddata->dev),
437 IORESOURCE_MEM, name);
438 if (!res) {
0eecc636
TL		 439 ddata->offsets[reg] = -ENODEV;
440
441 return 0;
442 }
443
444 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 445 if (reg == SYSC_REVISION)
446 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 447
448 return 0;
449}
450
451static int sysc_parse_registers(struct sysc *ddata)
452{
453 int i, error;
454
455 for (i = 0; i < SYSC_MAX_REGS; i++) {
456 error = sysc_parse_one(ddata, i);
457 if (error)
458 return error;
459 }
460
461 return 0;
462}
463
464/**
465 * sysc_check_registers - check for misconfigured register overlaps
466 * @ddata: device driver data
467 */
468static int sysc_check_registers(struct sysc *ddata)
469{
470 int i, j, nr_regs = 0, nr_matches = 0;
471
472 for (i = 0; i < SYSC_MAX_REGS; i++) {
473 if (ddata->offsets[i] < 0)
474 continue;
475
476 if (ddata->offsets[i] > (ddata->module_size - 4)) {
477 dev_err(ddata->dev, "register outside module range");
478
479 return -EINVAL;
480 }
481
482 for (j = 0; j < SYSC_MAX_REGS; j++) {
483 if (ddata->offsets[j] < 0)
484 continue;
485
486 if (ddata->offsets[i] == ddata->offsets[j])
487 nr_matches++;
488 }
489 nr_regs++;
490 }
491
492 if (nr_regs < 1) {
493 dev_err(ddata->dev, "missing registers\n");
494
495 return -EINVAL;
496 }
497
498 if (nr_matches > nr_regs) {
499 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
500 nr_regs, nr_matches);
501
502 return -EINVAL;
503 }
504
505 return 0;
506}
507
508/**
509 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 510 * @ddata: device driver data
0eecc636
TL		 511 *
512 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 513 * within the interconnect target module range. For example, SGX has
514 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
515 * has them at offset 0x1200 in the CPSW_WR child. Usually the
516 * the interconnect target module registers are at the beginning of
517 * the module range though.
0eecc636
TL		 518 */
519static int sysc_ioremap(struct sysc *ddata)
520{
0ef8e3bb 521 int size;
0eecc636 522
0ef8e3bb
TL		 523 size = max3(ddata->offsets[SYSC_REVISION],
524 ddata->offsets[SYSC_SYSCONFIG],
525 ddata->offsets[SYSC_SYSSTATUS]);
526
527 if (size < 0 || (size + sizeof(u32)) > ddata->module_size)
528 return -EINVAL;
0eecc636
TL		 529
530 ddata->module_va = devm_ioremap(ddata->dev,
531 ddata->module_pa,
0ef8e3bb 532 size + sizeof(u32));
0eecc636
TL		 533 if (!ddata->module_va)
534 return -EIO;
535
536 return 0;
537}
538
539/**
540 * sysc_map_and_check_registers - ioremap and check device registers
541 * @ddata: device driver data
542 */
543static int sysc_map_and_check_registers(struct sysc *ddata)
544{
545 int error;
546
547 error = sysc_parse_and_check_child_range(ddata);
548 if (error)
549 return error;
550
551 error = sysc_check_children(ddata);
552 if (error)
553 return error;
554
555 error = sysc_parse_registers(ddata);
556 if (error)
557 return error;
558
559 error = sysc_ioremap(ddata);
560 if (error)
561 return error;
562
563 error = sysc_check_registers(ddata);
564 if (error)
565 return error;
566
567 return 0;
568}
569
570/**
571 * sysc_show_rev - read and show interconnect target module revision
572 * @bufp: buffer to print the information to
573 * @ddata: device driver data
574 */
575static int sysc_show_rev(char *bufp, struct sysc *ddata)
576{
566a9b05 577 int len;
0eecc636
TL		 578
579 if (ddata->offsets[SYSC_REVISION] < 0)
580 return sprintf(bufp, ":NA");
581
566a9b05 582 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 583
584 return len;
585}
586
587static int sysc_show_reg(struct sysc *ddata,
588 char *bufp, enum sysc_registers reg)
589{
590 if (ddata->offsets[reg] < 0)
591 return sprintf(bufp, ":NA");
592
593 return sprintf(bufp, ":%x", ddata->offsets[reg]);
594}
595
a885f0fe
TL		 596static int sysc_show_name(char *bufp, struct sysc *ddata)
597{
598 if (!ddata->name)
599 return 0;
600
601 return sprintf(bufp, ":%s", ddata->name);
602}
603
0eecc636
TL		 604/**
605 * sysc_show_registers - show information about interconnect target module
606 * @ddata: device driver data
607 */
608static void sysc_show_registers(struct sysc *ddata)
609{
610 char buf[128];
611 char *bufp = buf;
612 int i;
613
614 for (i = 0; i < SYSC_MAX_REGS; i++)
615 bufp += sysc_show_reg(ddata, bufp, i);
616
617 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 618 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 619
620 dev_dbg(ddata->dev, "%llx:%x%s\n",
621 ddata->module_pa, ddata->module_size,
622 buf);
623}
624
a4a5d493 625static int __maybe_unused sysc_runtime_suspend(struct device *dev)
0eecc636 626{
ef70b0bd 627 struct ti_sysc_platform_data *pdata;
0eecc636 628 struct sysc *ddata;
ef70b0bd 629 int error = 0, i;
0eecc636
TL		 630
631 ddata = dev_get_drvdata(dev);
632
ef70b0bd 633 if (!ddata->enabled)
0eecc636
TL		 634 return 0;
635
ef70b0bd
TL		 636 if (ddata->legacy_mode) {
637 pdata = dev_get_platdata(ddata->dev);
638 if (!pdata)
639 return 0;
640
641 if (!pdata->idle_module)
642 return -ENODEV;
643
644 error = pdata->idle_module(dev, &ddata->cookie);
645 if (error)
646 dev_err(dev, "%s: could not idle: %i\n",
647 __func__, error);
648
649 goto idled;
650 }
651
09dfe581 652 for (i = 0; i < ddata->nr_clocks; i++) {
0eecc636
TL		 653 if (IS_ERR_OR_NULL(ddata->clocks[i]))
654 continue;
09dfe581
TL		 655
656 if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
657 break;
658
0eecc636
TL		 659 clk_disable(ddata->clocks[i]);
660 }
661
ef70b0bd
TL		 662idled:
663 ddata->enabled = false;
664
665 return error;
0eecc636
TL		 666}
667
a4a5d493 668static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636 669{
ef70b0bd 670 struct ti_sysc_platform_data *pdata;
0eecc636 671 struct sysc *ddata;
ef70b0bd 672 int error = 0, i;
0eecc636
TL		 673
674 ddata = dev_get_drvdata(dev);
675
ef70b0bd 676 if (ddata->enabled)
0eecc636
TL		 677 return 0;
678
ef70b0bd
TL		 679 if (ddata->legacy_mode) {
680 pdata = dev_get_platdata(ddata->dev);
681 if (!pdata)
682 return 0;
683
684 if (!pdata->enable_module)
685 return -ENODEV;
686
687 error = pdata->enable_module(dev, &ddata->cookie);
688 if (error)
689 dev_err(dev, "%s: could not enable: %i\n",
690 __func__, error);
691
692 goto awake;
693 }
694
09dfe581 695 for (i = 0; i < ddata->nr_clocks; i++) {
0eecc636
TL		 696 if (IS_ERR_OR_NULL(ddata->clocks[i]))
697 continue;
09dfe581
TL		 698
699 if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
700 break;
701
0eecc636
TL		 702 error = clk_enable(ddata->clocks[i]);
703 if (error)
704 return error;
705 }
706
ef70b0bd
TL		 707awake:
708 ddata->enabled = true;
709
710 return error;
0eecc636
TL		 711}
712
f5e80203 713static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 714{
715 struct sysc *ddata;
716
717 ddata = dev_get_drvdata(dev);
718
40d9f912 719 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 720 return 0;
721
f5e80203 722 return pm_runtime_force_suspend(dev);
62020f23
TL		 723}
724
f5e80203 725static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 726{
727 struct sysc *ddata;
728
729 ddata = dev_get_drvdata(dev);
e7420c2d 730
40d9f912 731 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 732 return 0;
733
f5e80203 734 return pm_runtime_force_resume(dev);
0eecc636
TL		 735}
736
737static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 738 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 739 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
740 sysc_runtime_resume,
741 NULL)
742};
743
a885f0fe
TL		 744/* Module revision register based quirks */
745struct sysc_revision_quirk {
746 const char *name;
747 u32 base;
748 int rev_offset;
749 int sysc_offset;
750 int syss_offset;
751 u32 revision;
752 u32 revision_mask;
753 u32 quirks;
754};
755
756#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
757 optrev_val, optrevmask, optquirkmask) \
758 { \
759 .name = (optname), \
760 .base = (optbase), \
761 .rev_offset = (optrev), \
762 .sysc_offset = (optsysc), \
763 .syss_offset = (optsyss), \
764 .revision = (optrev_val), \
765 .revision_mask = (optrevmask), \
766 .quirks = (optquirkmask), \
767 }
768
769static const struct sysc_revision_quirk sysc_revision_quirks[] = {
770 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 771 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 772 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 773 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
774 SYSC_QUIRK_LEGACY_IDLE),
775 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
776 SYSC_QUIRK_LEGACY_IDLE),
777 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
778 SYSC_QUIRK_LEGACY_IDLE),
779 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
780 SYSC_QUIRK_LEGACY_IDLE),
781 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
782 SYSC_QUIRK_LEGACY_IDLE),
783 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
9bd34c63 784 0),
8cde5d5f 785 /* Some timers on omap4 and later */
3a3d802b 786 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
072167d1 787 0),
3a3d802b 788 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
9bd34c63 789 0),
a885f0fe
TL		 790 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
791 SYSC_QUIRK_LEGACY_IDLE),
d708bb14 792 /* Uarts on omap4 and later */
b82beef5
TL		 793 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
794 SYSC_QUIRK_LEGACY_IDLE),
795 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
d708bb14 796 SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 797
dc4c85ea 798#ifdef DEBUG
1ba30693 799 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
c6eb4af3 800 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
dc4c85ea 801 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
c6eb4af3 802 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
40d9f912 803 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1ba30693 804 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac
TL		 805 0xffff00f0, 0),
806 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
1ba30693
TL		 807 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0x00001401, 0xffffffff, 0),
808 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
809 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
dc4c85ea
TL		 810 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
811 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
1ba30693 812 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0),
dc4c85ea
TL		 813 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
814 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
c6eb4af3 815 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0),
23731eac 816 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
dc4c85ea 817 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1ba30693 818 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
dc4c85ea 819 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
c6eb4af3 820 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1ba30693 821 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
dc4c85ea 822 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1ba30693 823 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 824 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1ba30693 825 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
40d9f912 826 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
f0106700 827 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
40d9f912 828 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
23731eac 829 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1ba30693 830 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
40d9f912 831 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
23731eac 832 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1ba30693 833 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
c6eb4af3 834 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
40d9f912 835 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
c6eb4af3 836 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1ba30693 837 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 838 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
dc4c85ea
TL		 839 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
840 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
841 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1ba30693 842 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
c6eb4af3 843 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1ba30693 844 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
dc4c85ea 845 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 846 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
dc4c85ea 847 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
f0106700 848 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
dc4c85ea
TL		 849 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
850 0xffffffff, 0),
1ba30693
TL		 851 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0),
852 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
dc4c85ea 853#endif
a885f0fe
TL		 854};
855
856static void sysc_init_revision_quirks(struct sysc *ddata)
857{
858 const struct sysc_revision_quirk *q;
859 int i;
860
861 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
862 q = &sysc_revision_quirks[i];
863
864 if (q->base && q->base != ddata->module_pa)
865 continue;
866
867 if (q->rev_offset >= 0 &&
868 q->rev_offset != ddata->offsets[SYSC_REVISION])
869 continue;
870
871 if (q->sysc_offset >= 0 &&
872 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
873 continue;
874
875 if (q->syss_offset >= 0 &&
876 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
877 continue;
878
879 if (q->revision == ddata->revision ||
880 (q->revision & q->revision_mask) ==
881 (ddata->revision & q->revision_mask)) {
882 ddata->name = q->name;
883 ddata->cfg.quirks |= q->quirks;
884 }
885 }
886}
887
596e7955
FA		 888static int sysc_reset(struct sysc *ddata)
889{
890 int offset = ddata->offsets[SYSC_SYSCONFIG];
891 int val;
892
893 if (ddata->legacy_mode || offset < 0 ||
894 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
895 return 0;
896
897 /*
898 * Currently only support reset status in sysstatus.
899 * Warn and return error in all other cases
900 */
901 if (!ddata->cfg.syss_mask) {
902 dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n");
903 return -EINVAL;
904 }
905
906 val = sysc_read(ddata, offset);
907 val |= (0x1 << ddata->cap->regbits->srst_shift);
908 sysc_write(ddata, offset, val);
909
910 /* Poll on reset status */
911 offset = ddata->offsets[SYSC_SYSSTATUS];
912
913 return readl_poll_timeout(ddata->module_va + offset, val,
914 (val & ddata->cfg.syss_mask) == 0x0,
915 100, MAX_MODULE_SOFTRESET_WAIT);
916}
917
566a9b05
TL		 918/* At this point the module is configured enough to read the revision */
919static int sysc_init_module(struct sysc *ddata)
920{
921 int error;
922
a885f0fe
TL		 923 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) {
924 ddata->revision = sysc_read_revision(ddata);
925 goto rev_quirks;
926 }
927
566a9b05
TL		 928 error = pm_runtime_get_sync(ddata->dev);
929 if (error < 0) {
930 pm_runtime_put_noidle(ddata->dev);
931
932 return 0;
933 }
5062236e 934
596e7955
FA		 935 error = sysc_reset(ddata);
936 if (error) {
937 dev_err(ddata->dev, "Reset failed with %d\n", error);
938 pm_runtime_put_sync(ddata->dev);
939
940 return error;
941 }
942
566a9b05
TL		 943 ddata->revision = sysc_read_revision(ddata);
944 pm_runtime_put_sync(ddata->dev);
945
a885f0fe
TL		 946rev_quirks:
947 sysc_init_revision_quirks(ddata);
948
566a9b05
TL		 949 return 0;
950}
951
c5a2de97
TL		 952static int sysc_init_sysc_mask(struct sysc *ddata)
953{
954 struct device_node *np = ddata->dev->of_node;
955 int error;
956 u32 val;
957
958 error = of_property_read_u32(np, "ti,sysc-mask", &val);
959 if (error)
960 return 0;
961
962 if (val)
963 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
964 else
965 ddata->cfg.sysc_val = ddata->cap->sysc_mask;
966
967 return 0;
968}
969
970static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
971 const char *name)
972{
973 struct device_node *np = ddata->dev->of_node;
974 struct property *prop;
975 const __be32 *p;
976 u32 val;
977
978 of_property_for_each_u32(np, name, prop, p, val) {
979 if (val >= SYSC_NR_IDLEMODES) {
980 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
981 return -EINVAL;
982 }
983 *idlemodes |= (1 << val);
984 }
985
986 return 0;
987}
988
989static int sysc_init_idlemodes(struct sysc *ddata)
990{
991 int error;
992
993 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
994 "ti,sysc-midle");
995 if (error)
996 return error;
997
998 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
999 "ti,sysc-sidle");
1000 if (error)
1001 return error;
1002
1003 return 0;
1004}
1005
1006/*
1007 * Only some devices on omap4 and later have SYSCONFIG reset done
1008 * bit. We can detect this if there is no SYSSTATUS at all, or the
1009 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1010 * have multiple bits for the child devices like OHCI and EHCI.
1011 * Depends on SYSC being parsed first.
1012 */
1013static int sysc_init_syss_mask(struct sysc *ddata)
1014{
1015 struct device_node *np = ddata->dev->of_node;
1016 int error;
1017 u32 val;
1018
1019 error = of_property_read_u32(np, "ti,syss-mask", &val);
1020 if (error) {
1021 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1022 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1023 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1024 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1025
1026 return 0;
1027 }
1028
1029 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1030 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1031
1032 ddata->cfg.syss_mask = val;
1033
1034 return 0;
1035}
1036
2c355ff6 1037/*
8b2830ba
TL		 1038 * Many child device drivers need to have fck and opt clocks available
1039 * to get the clock rate for device internal configuration etc.
2c355ff6 1040 */
8b2830ba
TL		 1041static int sysc_child_add_named_clock(struct sysc *ddata,
1042 struct device *child,
1043 const char *name)
2c355ff6 1044{
8b2830ba 1045 struct clk *clk;
2c355ff6 1046 struct clk_lookup *l;
8b2830ba 1047 int error = 0;
2c355ff6 1048
8b2830ba 1049 if (!name)
2c355ff6
TL		 1050 return 0;
1051
8b2830ba
TL		 1052 clk = clk_get(child, name);
1053 if (!IS_ERR(clk)) {
1054 clk_put(clk);
2c355ff6
TL		 1055
1056 return -EEXIST;
1057 }
1058
8b2830ba
TL		 1059 clk = clk_get(ddata->dev, name);
1060 if (IS_ERR(clk))
1061 return -ENODEV;
2c355ff6 1062
8b2830ba
TL		 1063 l = clkdev_create(clk, name, dev_name(child));
1064 if (!l)
1065 error = -ENOMEM;
1066
1067 clk_put(clk);
1068
1069 return error;
2c355ff6
TL		 1070}
1071
09dfe581
TL		 1072static int sysc_child_add_clocks(struct sysc *ddata,
1073 struct device *child)
1074{
1075 int i, error;
1076
1077 for (i = 0; i < ddata->nr_clocks; i++) {
1078 error = sysc_child_add_named_clock(ddata,
1079 child,
1080 ddata->clock_roles[i]);
1081 if (error && error != -EEXIST) {
1082 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1083 ddata->clock_roles[i], error);
1084
1085 return error;
1086 }
1087 }
1088
1089 return 0;
1090}
1091
2c355ff6
TL		 1092static struct device_type sysc_device_type = {
1093};
1094
1095static struct sysc *sysc_child_to_parent(struct device *dev)
1096{
1097 struct device *parent = dev->parent;
1098
1099 if (!parent || parent->type != &sysc_device_type)
1100 return NULL;
1101
1102 return dev_get_drvdata(parent);
1103}
1104
a885f0fe
TL		 1105static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1106{
1107 struct sysc *ddata;
1108 int error;
1109
1110 ddata = sysc_child_to_parent(dev);
1111
1112 error = pm_generic_runtime_suspend(dev);
1113 if (error)
1114 return error;
1115
1116 if (!ddata->enabled)
1117 return 0;
1118
1119 return sysc_runtime_suspend(ddata->dev);
1120}
1121
1122static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1123{
1124 struct sysc *ddata;
1125 int error;
1126
1127 ddata = sysc_child_to_parent(dev);
1128
1129 if (!ddata->enabled) {
1130 error = sysc_runtime_resume(ddata->dev);
1131 if (error < 0)
1132 dev_err(ddata->dev,
1133 "%s error: %i\n", __func__, error);
1134 }
1135
1136 return pm_generic_runtime_resume(dev);
1137}
1138
1139#ifdef CONFIG_PM_SLEEP
1140static int sysc_child_suspend_noirq(struct device *dev)
1141{
1142 struct sysc *ddata;
1143 int error;
1144
1145 ddata = sysc_child_to_parent(dev);
1146
ef55f821
TL		 1147 dev_dbg(ddata->dev, "%s %s\n", __func__,
1148 ddata->name ? ddata->name : "");
1149
a885f0fe 1150 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 1151 if (error) {
1152 dev_err(dev, "%s error at %i: %i\n",
1153 __func__, __LINE__, error);
1154
a885f0fe 1155 return error;
ef55f821 1156 }
a885f0fe
TL		 1157
1158 if (!pm_runtime_status_suspended(dev)) {
1159 error = pm_generic_runtime_suspend(dev);
ef55f821 1160 if (error) {
f9490783
TL		 1161 dev_dbg(dev, "%s busy at %i: %i\n",
1162 __func__, __LINE__, error);
ef55f821 1163
4f3530f4 1164 return 0;
ef55f821 1165 }
a885f0fe
TL		 1166
1167 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 1168 if (error) {
1169 dev_err(dev, "%s error at %i: %i\n",
1170 __func__, __LINE__, error);
1171
a885f0fe 1172 return error;
ef55f821 1173 }
a885f0fe
TL		 1174
1175 ddata->child_needs_resume = true;
1176 }
1177
1178 return 0;
1179}
1180
1181static int sysc_child_resume_noirq(struct device *dev)
1182{
1183 struct sysc *ddata;
1184 int error;
1185
1186 ddata = sysc_child_to_parent(dev);
1187
ef55f821
TL		 1188 dev_dbg(ddata->dev, "%s %s\n", __func__,
1189 ddata->name ? ddata->name : "");
1190
a885f0fe
TL		 1191 if (ddata->child_needs_resume) {
1192 ddata->child_needs_resume = false;
1193
1194 error = sysc_runtime_resume(ddata->dev);
1195 if (error)
1196 dev_err(ddata->dev,
1197 "%s runtime resume error: %i\n",
1198 __func__, error);
1199
1200 error = pm_generic_runtime_resume(dev);
1201 if (error)
1202 dev_err(ddata->dev,
1203 "%s generic runtime resume: %i\n",
1204 __func__, error);
1205 }
1206
1207 return pm_generic_resume_noirq(dev);
1208}
1209#endif
1210
1211struct dev_pm_domain sysc_child_pm_domain = {
1212 .ops = {
1213 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1214 sysc_child_runtime_resume,
1215 NULL)
1216 USE_PLATFORM_PM_SLEEP_OPS
1217 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1218 sysc_child_resume_noirq)
1219 }
1220};
1221
1222/**
1223 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1224 * @ddata: device driver data
1225 * @child: child device driver
1226 *
1227 * Allow idle for child devices as done with _od_runtime_suspend().
1228 * Otherwise many child devices will not idle because of the permanent
1229 * parent usecount set in pm_runtime_irq_safe().
1230 *
1231 * Note that the long term solution is to just modify the child device
1232 * drivers to not set pm_runtime_irq_safe() and then this can be just
1233 * dropped.
1234 */
1235static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1236{
1237 if (!ddata->legacy_mode)
1238 return;
1239
1240 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1241 dev_pm_domain_set(child, &sysc_child_pm_domain);
1242}
1243
2c355ff6
TL		 1244static int sysc_notifier_call(struct notifier_block *nb,
1245 unsigned long event, void *device)
1246{
1247 struct device *dev = device;
1248 struct sysc *ddata;
1249 int error;
1250
1251 ddata = sysc_child_to_parent(dev);
1252 if (!ddata)
1253 return NOTIFY_DONE;
1254
1255 switch (event) {
1256 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 1257 error = sysc_child_add_clocks(ddata, dev);
1258 if (error)
1259 return error;
a885f0fe 1260 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 1261 break;
1262 default:
1263 break;
1264 }
1265
1266 return NOTIFY_DONE;
1267}
1268
1269static struct notifier_block sysc_nb = {
1270 .notifier_call = sysc_notifier_call,
1271};
1272
566a9b05
TL		 1273/* Device tree configured quirks */
1274struct sysc_dts_quirk {
1275 const char *name;
1276 u32 mask;
1277};
1278
1279static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1280 { .name = "ti,no-idle-on-init",
1281 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1282 { .name = "ti,no-reset-on-init",
1283 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
1284};
1285
4014c08b
TL		 1286static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
1287 bool is_child)
566a9b05 1288{
566a9b05 1289 const struct property *prop;
4014c08b 1290 int i, len;
566a9b05
TL		 1291
1292 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 1293 const char *name = sysc_dts_quirks[i].name;
1294
1295 prop = of_get_property(np, name, &len);
566a9b05 1296 if (!prop)
d39b6ea4 1297 continue;
566a9b05
TL		 1298
1299 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 1300 if (is_child) {
1301 dev_warn(ddata->dev,
1302 "dts flag should be at module level for %s\n",
1303 name);
1304 }
566a9b05 1305 }
4014c08b
TL		 1306}
1307
1308static int sysc_init_dts_quirks(struct sysc *ddata)
1309{
1310 struct device_node *np = ddata->dev->of_node;
1311 int error;
1312 u32 val;
1313
1314 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 1315
4014c08b 1316 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 1317 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
1318 if (!error) {
1319 if (val > 255) {
1320 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
1321 val);
1322 }
1323
1324 ddata->cfg.srst_udelay = (u8)val;
1325 }
1326
1327 return 0;
1328}
1329
0eecc636
TL		 1330static void sysc_unprepare(struct sysc *ddata)
1331{
1332 int i;
1333
1334 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
1335 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
1336 clk_unprepare(ddata->clocks[i]);
1337 }
1338}
1339
70a65240
TL		 1340/*
1341 * Common sysc register bits found on omap2, also known as type1
1342 */
1343static const struct sysc_regbits sysc_regbits_omap2 = {
1344 .dmadisable_shift = -ENODEV,
1345 .midle_shift = 12,
1346 .sidle_shift = 3,
1347 .clkact_shift = 8,
1348 .emufree_shift = 5,
1349 .enwkup_shift = 2,
1350 .srst_shift = 1,
1351 .autoidle_shift = 0,
1352};
1353
1354static const struct sysc_capabilities sysc_omap2 = {
1355 .type = TI_SYSC_OMAP2,
1356 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1357 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1358 SYSC_OMAP2_AUTOIDLE,
1359 .regbits = &sysc_regbits_omap2,
1360};
1361
1362/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
1363static const struct sysc_capabilities sysc_omap2_timer = {
1364 .type = TI_SYSC_OMAP2_TIMER,
1365 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1366 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1367 SYSC_OMAP2_AUTOIDLE,
1368 .regbits = &sysc_regbits_omap2,
1369 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
1370};
1371
1372/*
1373 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
1374 * with different sidle position
1375 */
1376static const struct sysc_regbits sysc_regbits_omap3_sham = {
1377 .dmadisable_shift = -ENODEV,
1378 .midle_shift = -ENODEV,
1379 .sidle_shift = 4,
1380 .clkact_shift = -ENODEV,
1381 .enwkup_shift = -ENODEV,
1382 .srst_shift = 1,
1383 .autoidle_shift = 0,
1384 .emufree_shift = -ENODEV,
1385};
1386
1387static const struct sysc_capabilities sysc_omap3_sham = {
1388 .type = TI_SYSC_OMAP3_SHAM,
1389 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1390 .regbits = &sysc_regbits_omap3_sham,
1391};
1392
1393/*
1394 * AES register bits found on omap3 and later, a variant of
1395 * sysc_regbits_omap2 with different sidle position
1396 */
1397static const struct sysc_regbits sysc_regbits_omap3_aes = {
1398 .dmadisable_shift = -ENODEV,
1399 .midle_shift = -ENODEV,
1400 .sidle_shift = 6,
1401 .clkact_shift = -ENODEV,
1402 .enwkup_shift = -ENODEV,
1403 .srst_shift = 1,
1404 .autoidle_shift = 0,
1405 .emufree_shift = -ENODEV,
1406};
1407
1408static const struct sysc_capabilities sysc_omap3_aes = {
1409 .type = TI_SYSC_OMAP3_AES,
1410 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1411 .regbits = &sysc_regbits_omap3_aes,
1412};
1413
1414/*
1415 * Common sysc register bits found on omap4, also known as type2
1416 */
1417static const struct sysc_regbits sysc_regbits_omap4 = {
1418 .dmadisable_shift = 16,
1419 .midle_shift = 4,
1420 .sidle_shift = 2,
1421 .clkact_shift = -ENODEV,
1422 .enwkup_shift = -ENODEV,
1423 .emufree_shift = 1,
1424 .srst_shift = 0,
1425 .autoidle_shift = -ENODEV,
1426};
1427
1428static const struct sysc_capabilities sysc_omap4 = {
1429 .type = TI_SYSC_OMAP4,
1430 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1431 SYSC_OMAP4_SOFTRESET,
1432 .regbits = &sysc_regbits_omap4,
1433};
1434
1435static const struct sysc_capabilities sysc_omap4_timer = {
1436 .type = TI_SYSC_OMAP4_TIMER,
1437 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1438 SYSC_OMAP4_SOFTRESET,
1439 .regbits = &sysc_regbits_omap4,
1440};
1441
1442/*
1443 * Common sysc register bits found on omap4, also known as type3
1444 */
1445static const struct sysc_regbits sysc_regbits_omap4_simple = {
1446 .dmadisable_shift = -ENODEV,
1447 .midle_shift = 2,
1448 .sidle_shift = 0,
1449 .clkact_shift = -ENODEV,
1450 .enwkup_shift = -ENODEV,
1451 .srst_shift = -ENODEV,
1452 .emufree_shift = -ENODEV,
1453 .autoidle_shift = -ENODEV,
1454};
1455
1456static const struct sysc_capabilities sysc_omap4_simple = {
1457 .type = TI_SYSC_OMAP4_SIMPLE,
1458 .regbits = &sysc_regbits_omap4_simple,
1459};
1460
1461/*
1462 * SmartReflex sysc found on omap34xx
1463 */
1464static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
1465 .dmadisable_shift = -ENODEV,
1466 .midle_shift = -ENODEV,
1467 .sidle_shift = -ENODEV,
1468 .clkact_shift = 20,
1469 .enwkup_shift = -ENODEV,
1470 .srst_shift = -ENODEV,
1471 .emufree_shift = -ENODEV,
1472 .autoidle_shift = -ENODEV,
1473};
1474
1475static const struct sysc_capabilities sysc_34xx_sr = {
1476 .type = TI_SYSC_OMAP34XX_SR,
1477 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
1478 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 1479 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
1480 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 1481};
1482
1483/*
1484 * SmartReflex sysc found on omap36xx and later
1485 */
1486static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
1487 .dmadisable_shift = -ENODEV,
1488 .midle_shift = -ENODEV,
1489 .sidle_shift = 24,
1490 .clkact_shift = -ENODEV,
1491 .enwkup_shift = 26,
1492 .srst_shift = -ENODEV,
1493 .emufree_shift = -ENODEV,
1494 .autoidle_shift = -ENODEV,
1495};
1496
1497static const struct sysc_capabilities sysc_36xx_sr = {
1498 .type = TI_SYSC_OMAP36XX_SR,
3267c081 1499 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 1500 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 1501 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 1502};
1503
1504static const struct sysc_capabilities sysc_omap4_sr = {
1505 .type = TI_SYSC_OMAP4_SR,
1506 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 1507 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 1508};
1509
1510/*
1511 * McASP register bits found on omap4 and later
1512 */
1513static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
1514 .dmadisable_shift = -ENODEV,
1515 .midle_shift = -ENODEV,
1516 .sidle_shift = 0,
1517 .clkact_shift = -ENODEV,
1518 .enwkup_shift = -ENODEV,
1519 .srst_shift = -ENODEV,
1520 .emufree_shift = -ENODEV,
1521 .autoidle_shift = -ENODEV,
1522};
1523
1524static const struct sysc_capabilities sysc_omap4_mcasp = {
1525 .type = TI_SYSC_OMAP4_MCASP,
1526 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 1527 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
1528};
1529
1530/*
1531 * McASP found on dra7 and later
1532 */
1533static const struct sysc_capabilities sysc_dra7_mcasp = {
1534 .type = TI_SYSC_OMAP4_SIMPLE,
1535 .regbits = &sysc_regbits_omap4_simple,
1536 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 1537};
1538
1539/*
1540 * FS USB host found on omap4 and later
1541 */
1542static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
1543 .dmadisable_shift = -ENODEV,
1544 .midle_shift = -ENODEV,
1545 .sidle_shift = 24,
1546 .clkact_shift = -ENODEV,
1547 .enwkup_shift = 26,
1548 .srst_shift = -ENODEV,
1549 .emufree_shift = -ENODEV,
1550 .autoidle_shift = -ENODEV,
1551};
1552
1553static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
1554 .type = TI_SYSC_OMAP4_USB_HOST_FS,
1555 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
1556 .regbits = &sysc_regbits_omap4_usb_host_fs,
1557};
1558
7f35e63d
FA		 1559static const struct sysc_regbits sysc_regbits_dra7_mcan = {
1560 .dmadisable_shift = -ENODEV,
1561 .midle_shift = -ENODEV,
1562 .sidle_shift = -ENODEV,
1563 .clkact_shift = -ENODEV,
1564 .enwkup_shift = 4,
1565 .srst_shift = 0,
1566 .emufree_shift = -ENODEV,
1567 .autoidle_shift = -ENODEV,
1568};
1569
1570static const struct sysc_capabilities sysc_dra7_mcan = {
1571 .type = TI_SYSC_DRA7_MCAN,
1572 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
1573 .regbits = &sysc_regbits_dra7_mcan,
1574};
1575
ef70b0bd
TL		 1576static int sysc_init_pdata(struct sysc *ddata)
1577{
1578 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1579 struct ti_sysc_module_data mdata;
1580 int error = 0;
1581
1582 if (!pdata || !ddata->legacy_mode)
1583 return 0;
1584
1585 mdata.name = ddata->legacy_mode;
1586 mdata.module_pa = ddata->module_pa;
1587 mdata.module_size = ddata->module_size;
1588 mdata.offsets = ddata->offsets;
1589 mdata.nr_offsets = SYSC_MAX_REGS;
1590 mdata.cap = ddata->cap;
1591 mdata.cfg = &ddata->cfg;
1592
1593 if (!pdata->init_module)
1594 return -ENODEV;
1595
1596 error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie);
1597 if (error == -EEXIST)
1598 error = 0;
1599
1600 return error;
1601}
1602
70a65240
TL		 1603static int sysc_init_match(struct sysc *ddata)
1604{
1605 const struct sysc_capabilities *cap;
1606
1607 cap = of_device_get_match_data(ddata->dev);
1608 if (!cap)
1609 return -EINVAL;
1610
1611 ddata->cap = cap;
1612 if (ddata->cap)
1613 ddata->cfg.quirks |= ddata->cap->mod_quirks;
1614
1615 return 0;
1616}
1617
76f0f772
TL		 1618static void ti_sysc_idle(struct work_struct *work)
1619{
1620 struct sysc *ddata;
1621
1622 ddata = container_of(work, struct sysc, idle_work.work);
1623
1624 if (pm_runtime_active(ddata->dev))
1625 pm_runtime_put_sync(ddata->dev);
1626}
1627
c4bebea8
TL		 1628static const struct of_device_id sysc_match_table[] = {
1629 { .compatible = "simple-bus", },
1630 { /* sentinel */ },
1631};
1632
0eecc636
TL		 1633static int sysc_probe(struct platform_device *pdev)
1634{
ef70b0bd 1635 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 1636 struct sysc *ddata;
1637 int error;
1638
1639 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
1640 if (!ddata)
1641 return -ENOMEM;
1642
1643 ddata->dev = &pdev->dev;
566a9b05 1644 platform_set_drvdata(pdev, ddata);
0eecc636 1645
70a65240
TL		 1646 error = sysc_init_match(ddata);
1647 if (error)
1648 return error;
1649
566a9b05
TL		 1650 error = sysc_init_dts_quirks(ddata);
1651 if (error)
1652 goto unprepare;
1653
0eecc636
TL		 1654 error = sysc_get_clocks(ddata);
1655 if (error)
1656 return error;
1657
1658 error = sysc_map_and_check_registers(ddata);
1659 if (error)
1660 goto unprepare;
1661
c5a2de97
TL		 1662 error = sysc_init_sysc_mask(ddata);
1663 if (error)
1664 goto unprepare;
1665
1666 error = sysc_init_idlemodes(ddata);
1667 if (error)
1668 goto unprepare;
1669
1670 error = sysc_init_syss_mask(ddata);
1671 if (error)
1672 goto unprepare;
1673
ef70b0bd
TL		 1674 error = sysc_init_pdata(ddata);
1675 if (error)
1676 goto unprepare;
1677
5062236e
TL		 1678 error = sysc_init_resets(ddata);
1679 if (error)
1680 return error;
566a9b05 1681
5062236e 1682 pm_runtime_enable(ddata->dev);
566a9b05
TL		 1683 error = sysc_init_module(ddata);
1684 if (error)
1685 goto unprepare;
1686
0eecc636
TL		 1687 error = pm_runtime_get_sync(ddata->dev);
1688 if (error < 0) {
1689 pm_runtime_put_noidle(ddata->dev);
1690 pm_runtime_disable(ddata->dev);
1691 goto unprepare;
1692 }
1693
0eecc636
TL		 1694 sysc_show_registers(ddata);
1695
2c355ff6 1696 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 1697 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
1698 pdata ? pdata->auxdata : NULL,
ef70b0bd 1699 ddata->dev);
0eecc636
TL		 1700 if (error)
1701 goto err;
1702
76f0f772
TL		 1703 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
1704
1705 /* At least earlycon won't survive without deferred idle */
1706 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
1707 SYSC_QUIRK_NO_RESET_ON_INIT)) {
1708 schedule_delayed_work(&ddata->idle_work, 3000);
1709 } else {
1710 pm_runtime_put(&pdev->dev);
1711 }
0eecc636 1712
5062236e
TL		 1713 if (!of_get_available_child_count(ddata->dev->of_node))
1714 reset_control_assert(ddata->rsts);
1715
0eecc636
TL		 1716 return 0;
1717
1718err:
0eecc636
TL		 1719 pm_runtime_put_sync(&pdev->dev);
1720 pm_runtime_disable(&pdev->dev);
1721unprepare:
1722 sysc_unprepare(ddata);
1723
1724 return error;
1725}
1726
684be5a4
TL		 1727static int sysc_remove(struct platform_device *pdev)
1728{
1729 struct sysc *ddata = platform_get_drvdata(pdev);
1730 int error;
1731
76f0f772
TL		 1732 cancel_delayed_work_sync(&ddata->idle_work);
1733
684be5a4
TL		 1734 error = pm_runtime_get_sync(ddata->dev);
1735 if (error < 0) {
1736 pm_runtime_put_noidle(ddata->dev);
1737 pm_runtime_disable(ddata->dev);
1738 goto unprepare;
1739 }
1740
1741 of_platform_depopulate(&pdev->dev);
1742
684be5a4
TL		 1743 pm_runtime_put_sync(&pdev->dev);
1744 pm_runtime_disable(&pdev->dev);
5062236e 1745 reset_control_assert(ddata->rsts);
684be5a4
TL		 1746
1747unprepare:
1748 sysc_unprepare(ddata);
1749
1750 return 0;
1751}
1752
0eecc636 1753static const struct of_device_id sysc_match[] = {
70a65240
TL		 1754 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
1755 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
1756 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
1757 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
1758 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
1759 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
1760 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
1761 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
1762 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
1763 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
1764 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 1765 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 1766 { .compatible = "ti,sysc-usb-host-fs",
1767 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 1768 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
0eecc636
TL		 1769 { },
1770};
1771MODULE_DEVICE_TABLE(of, sysc_match);
1772
1773static struct platform_driver sysc_driver = {
1774 .probe = sysc_probe,
684be5a4 1775 .remove = sysc_remove,
0eecc636
TL		 1776 .driver = {
1777 .name = "ti-sysc",
1778 .of_match_table = sysc_match,
1779 .pm = &sysc_pm_ops,
1780 },
1781};
2c355ff6
TL		 1782
1783static int __init sysc_init(void)
1784{
1785 bus_register_notifier(&platform_bus_type, &sysc_nb);
1786
1787 return platform_driver_register(&sysc_driver);
1788}
1789module_init(sysc_init);
1790
1791static void __exit sysc_exit(void)
1792{
1793 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
1794 platform_driver_unregister(&sysc_driver);
1795}
1796module_exit(sysc_exit);
0eecc636
TL		 1797
1798MODULE_DESCRIPTION("TI sysc interconnect target driver");
1799MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)