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Merge tag 'devicetree-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh...
[linux-2.6-block.git] / drivers / bus / ti-sysc.c
CommitLineData
0eecc636
TL		 1/*
2 * ti-sysc.c - Texas Instruments sysc interconnect target driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/io.h>
15#include <linux/clk.h>
2c355ff6 16#include <linux/clkdev.h>
a885f0fe 17#include <linux/delay.h>
0eecc636
TL		 18#include <linux/module.h>
19#include <linux/platform_device.h>
a885f0fe 20#include <linux/pm_domain.h>
0eecc636 21#include <linux/pm_runtime.h>
5062236e 22#include <linux/reset.h>
0eecc636
TL		 23#include <linux/of_address.h>
24#include <linux/of_platform.h>
2c355ff6 25#include <linux/slab.h>
596e7955 26#include <linux/iopoll.h>
2c355ff6 27
70a65240
TL		 28#include <linux/platform_data/ti-sysc.h>
29
30#include <dt-bindings/bus/ti-sysc.h>
0eecc636 31
596e7955
FA		 32#define MAX_MODULE_SOFTRESET_WAIT 10000
33
0eecc636
TL		 34static const char * const reg_names[] = { "rev", "sysc", "syss", };
35
36enum sysc_clocks {
37 SYSC_FCK,
38 SYSC_ICK,
09dfe581
TL		 39 SYSC_OPTFCK0,
40 SYSC_OPTFCK1,
41 SYSC_OPTFCK2,
42 SYSC_OPTFCK3,
43 SYSC_OPTFCK4,
44 SYSC_OPTFCK5,
45 SYSC_OPTFCK6,
46 SYSC_OPTFCK7,
0eecc636
TL		 47 SYSC_MAX_CLOCKS,
48};
49
a54275f4
TL		 50static const char * const clock_names[SYSC_MAX_CLOCKS] = {
51 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
52 "opt5", "opt6", "opt7",
53};
0eecc636 54
c5a2de97
TL		 55#define SYSC_IDLEMODE_MASK 3
56#define SYSC_CLOCKACTIVITY_MASK 3
57
0eecc636
TL		 58/**
59 * struct sysc - TI sysc interconnect target module registers and capabilities
60 * @dev: struct device pointer
61 * @module_pa: physical address of the interconnect target module
62 * @module_size: size of the interconnect target module
63 * @module_va: virtual address of the interconnect target module
64 * @offsets: register offsets from module base
65 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 66 * @clock_roles: clock role names for the found clocks
67 * @nr_clocks: number of clocks used by the interconnect target module
0eecc636 68 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 69 * @cap: interconnect target module capabilities
70 * @cfg: interconnect target module configuration
566a9b05
TL		 71 * @name: name if available
72 * @revision: interconnect target module revision
62020f23 73 * @needs_resume: runtime resume needed on resume from suspend
0eecc636
TL		 74 */
75struct sysc {
76 struct device *dev;
77 u64 module_pa;
78 u32 module_size;
79 void __iomem *module_va;
80 int offsets[SYSC_MAX_REGS];
a3e92e7b 81 struct ti_sysc_module_data *mdata;
09dfe581
TL		 82 struct clk **clocks;
83 const char **clock_roles;
84 int nr_clocks;
5062236e 85 struct reset_control *rsts;
0eecc636 86 const char *legacy_mode;
70a65240
TL		 87 const struct sysc_capabilities *cap;
88 struct sysc_config cfg;
ef70b0bd 89 struct ti_sysc_cookie cookie;
566a9b05
TL		 90 const char *name;
91 u32 revision;
62020f23
TL		 92 bool enabled;
93 bool needs_resume;
a885f0fe 94 bool child_needs_resume;
76f0f772 95 struct delayed_work idle_work;
0eecc636
TL		 96};
97
4014c08b
TL		 98static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
99 bool is_child);
100
b7182b42 101static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955
FA		 102{
103 writel_relaxed(value, ddata->module_va + offset);
104}
105
566a9b05
TL		 106static u32 sysc_read(struct sysc *ddata, int offset)
107{
108 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
109 u32 val;
110
111 val = readw_relaxed(ddata->module_va + offset);
112 val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
113
114 return val;
115 }
116
117 return readl_relaxed(ddata->module_va + offset);
118}
119
09dfe581
TL		 120static bool sysc_opt_clks_needed(struct sysc *ddata)
121{
122 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
123}
124
0eecc636
TL		 125static u32 sysc_read_revision(struct sysc *ddata)
126{
566a9b05
TL		 127 int offset = ddata->offsets[SYSC_REVISION];
128
129 if (offset < 0)
130 return 0;
131
132 return sysc_read(ddata, offset);
0eecc636
TL		 133}
134
a54275f4
TL		 135static int sysc_add_named_clock_from_child(struct sysc *ddata,
136 const char *name,
137 const char *optfck_name)
138{
139 struct device_node *np = ddata->dev->of_node;
140 struct device_node *child;
141 struct clk_lookup *cl;
142 struct clk *clock;
143 const char *n;
144
145 if (name)
146 n = name;
147 else
148 n = optfck_name;
149
150 /* Does the clock alias already exist? */
151 clock = of_clk_get_by_name(np, n);
152 if (!IS_ERR(clock)) {
153 clk_put(clock);
154
155 return 0;
156 }
157
158 child = of_get_next_available_child(np, NULL);
159 if (!child)
160 return -ENODEV;
161
162 clock = devm_get_clk_from_child(ddata->dev, child, name);
163 if (IS_ERR(clock))
164 return PTR_ERR(clock);
165
166 /*
167 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
168 * limit for clk_get(). If cl ever needs to be freed, it should be done
169 * with clkdev_drop().
170 */
171 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
172 if (!cl)
173 return -ENOMEM;
174
175 cl->con_id = n;
176 cl->dev_id = dev_name(ddata->dev);
177 cl->clk = clock;
178 clkdev_add(cl);
179
180 clk_put(clock);
181
182 return 0;
183}
184
185static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
186{
187 const char *optfck_name;
188 int error, index;
189
190 if (ddata->nr_clocks < SYSC_OPTFCK0)
191 index = SYSC_OPTFCK0;
192 else
193 index = ddata->nr_clocks;
194
195 if (name)
196 optfck_name = name;
197 else
198 optfck_name = clock_names[index];
199
200 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
201 if (error)
202 return error;
203
204 ddata->clock_roles[index] = optfck_name;
205 ddata->nr_clocks++;
206
207 return 0;
208}
209
09dfe581 210static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 211{
09dfe581
TL		 212 int error, i, index = -ENODEV;
213
214 if (!strncmp(clock_names[SYSC_FCK], name, 3))
215 index = SYSC_FCK;
216 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
217 index = SYSC_ICK;
218
219 if (index < 0) {
220 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 221 if (!ddata->clocks[i]) {
09dfe581
TL		 222 index = i;
223 break;
224 }
225 }
226 }
0eecc636 227
09dfe581
TL		 228 if (index < 0) {
229 dev_err(ddata->dev, "clock %s not added\n", name);
230 return index;
0eecc636 231 }
0eecc636
TL		 232
233 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
234 if (IS_ERR(ddata->clocks[index])) {
235 if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
236 return 0;
237
238 dev_err(ddata->dev, "clock get error for %s: %li\n",
239 name, PTR_ERR(ddata->clocks[index]));
240
241 return PTR_ERR(ddata->clocks[index]);
242 }
243
244 error = clk_prepare(ddata->clocks[index]);
245 if (error) {
246 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
247 name, error);
248
249 return error;
250 }
251
252 return 0;
253}
254
255static int sysc_get_clocks(struct sysc *ddata)
256{
09dfe581
TL		 257 struct device_node *np = ddata->dev->of_node;
258 struct property *prop;
259 const char *name;
260 int nr_fck = 0, nr_ick = 0, i, error = 0;
261
20749051 262 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 263 SYSC_MAX_CLOCKS,
20749051 264 sizeof(*ddata->clock_roles),
09dfe581
TL		 265 GFP_KERNEL);
266 if (!ddata->clock_roles)
267 return -ENOMEM;
268
269 of_property_for_each_string(np, "clock-names", prop, name) {
270 if (!strncmp(clock_names[SYSC_FCK], name, 3))
271 nr_fck++;
272 if (!strncmp(clock_names[SYSC_ICK], name, 3))
273 nr_ick++;
274 ddata->clock_roles[ddata->nr_clocks] = name;
275 ddata->nr_clocks++;
276 }
277
278 if (ddata->nr_clocks < 1)
279 return 0;
280
a54275f4
TL		 281 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
282 error = sysc_init_ext_opt_clock(ddata, NULL);
283 if (error)
284 return error;
285 }
286
09dfe581
TL		 287 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
288 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
289
290 return -EINVAL;
291 }
292
293 if (nr_fck > 1 || nr_ick > 1) {
294 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 295
09dfe581
TL		 296 return -EINVAL;
297 }
298
20749051
KC		 299 ddata->clocks = devm_kcalloc(ddata->dev,
300 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 301 GFP_KERNEL);
302 if (!ddata->clocks)
303 return -ENOMEM;
304
7b4f8ac2
TL		 305 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
306 const char *name = ddata->clock_roles[i];
307
308 if (!name)
309 continue;
310
311 error = sysc_get_one_clock(ddata, name);
0eecc636
TL		 312 if (error && error != -ENOENT)
313 return error;
314 }
315
316 return 0;
317}
318
d878970f
TL		 319static int sysc_enable_main_clocks(struct sysc *ddata)
320{
321 struct clk *clock;
322 int i, error;
323
324 if (!ddata->clocks)
325 return 0;
326
327 for (i = 0; i < SYSC_OPTFCK0; i++) {
328 clock = ddata->clocks[i];
329
330 /* Main clocks may not have ick */
331 if (IS_ERR_OR_NULL(clock))
332 continue;
333
334 error = clk_enable(clock);
335 if (error)
336 goto err_disable;
337 }
338
339 return 0;
340
341err_disable:
342 for (i--; i >= 0; i--) {
343 clock = ddata->clocks[i];
344
345 /* Main clocks may not have ick */
346 if (IS_ERR_OR_NULL(clock))
347 continue;
348
349 clk_disable(clock);
350 }
351
352 return error;
353}
354
355static void sysc_disable_main_clocks(struct sysc *ddata)
356{
357 struct clk *clock;
358 int i;
359
360 if (!ddata->clocks)
361 return;
362
363 for (i = 0; i < SYSC_OPTFCK0; i++) {
364 clock = ddata->clocks[i];
365 if (IS_ERR_OR_NULL(clock))
366 continue;
367
368 clk_disable(clock);
369 }
370}
371
372static int sysc_enable_opt_clocks(struct sysc *ddata)
373{
374 struct clk *clock;
375 int i, error;
376
377 if (!ddata->clocks)
378 return 0;
379
380 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
381 clock = ddata->clocks[i];
382
383 /* Assume no holes for opt clocks */
384 if (IS_ERR_OR_NULL(clock))
385 return 0;
386
387 error = clk_enable(clock);
388 if (error)
389 goto err_disable;
390 }
391
392 return 0;
393
394err_disable:
395 for (i--; i >= 0; i--) {
396 clock = ddata->clocks[i];
397 if (IS_ERR_OR_NULL(clock))
398 continue;
399
400 clk_disable(clock);
401 }
402
403 return error;
404}
405
406static void sysc_disable_opt_clocks(struct sysc *ddata)
407{
408 struct clk *clock;
409 int i;
410
411 if (!ddata->clocks)
412 return;
413
414 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
415 clock = ddata->clocks[i];
416
417 /* Assume no holes for opt clocks */
418 if (IS_ERR_OR_NULL(clock))
419 return;
420
421 clk_disable(clock);
422 }
423}
424
5062236e 425/**
b11c1ea1 426 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 427 * @ddata: device driver data
428 *
b11c1ea1 429 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 430 */
431static int sysc_init_resets(struct sysc *ddata)
432{
5062236e
TL		 433 ddata->rsts =
434 devm_reset_control_array_get_optional_exclusive(ddata->dev);
435 if (IS_ERR(ddata->rsts))
436 return PTR_ERR(ddata->rsts);
437
5062236e
TL		 438 return 0;
439}
440
0eecc636
TL		 441/**
442 * sysc_parse_and_check_child_range - parses module IO region from ranges
443 * @ddata: device driver data
444 *
445 * In general we only need rev, syss, and sysc registers and not the whole
446 * module range. But we do want the offsets for these registers from the
447 * module base. This allows us to check them against the legacy hwmod
448 * platform data. Let's also check the ranges are configured properly.
449 */
450static int sysc_parse_and_check_child_range(struct sysc *ddata)
451{
452 struct device_node *np = ddata->dev->of_node;
453 const __be32 *ranges;
454 u32 nr_addr, nr_size;
455 int len, error;
456
457 ranges = of_get_property(np, "ranges", &len);
458 if (!ranges) {
459 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
460
461 return -ENOENT;
462 }
463
464 len /= sizeof(*ranges);
465
466 if (len < 3) {
467 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
468
469 return -EINVAL;
470 }
471
472 error = of_property_read_u32(np, "#address-cells", &nr_addr);
473 if (error)
474 return -ENOENT;
475
476 error = of_property_read_u32(np, "#size-cells", &nr_size);
477 if (error)
478 return -ENOENT;
479
480 if (nr_addr != 1 || nr_size != 1) {
481 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
482
483 return -EINVAL;
484 }
485
486 ranges++;
487 ddata->module_pa = of_translate_address(np, ranges++);
488 ddata->module_size = be32_to_cpup(ranges);
489
0eecc636
TL		 490 return 0;
491}
492
3bb37c8e
TL		 493static struct device_node *stdout_path;
494
495static void sysc_init_stdout_path(struct sysc *ddata)
496{
497 struct device_node *np = NULL;
498 const char *uart;
499
500 if (IS_ERR(stdout_path))
501 return;
502
503 if (stdout_path)
504 return;
505
506 np = of_find_node_by_path("/chosen");
507 if (!np)
508 goto err;
509
510 uart = of_get_property(np, "stdout-path", NULL);
511 if (!uart)
512 goto err;
513
514 np = of_find_node_by_path(uart);
515 if (!np)
516 goto err;
517
518 stdout_path = np;
519
520 return;
521
522err:
523 stdout_path = ERR_PTR(-ENODEV);
524}
525
526static void sysc_check_quirk_stdout(struct sysc *ddata,
527 struct device_node *np)
528{
529 sysc_init_stdout_path(ddata);
530 if (np != stdout_path)
531 return;
532
533 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
534 SYSC_QUIRK_NO_RESET_ON_INIT;
535}
536
0eecc636
TL		 537/**
538 * sysc_check_one_child - check child configuration
539 * @ddata: device driver data
540 * @np: child device node
541 *
542 * Let's avoid messy situations where we have new interconnect target
543 * node but children have "ti,hwmods". These belong to the interconnect
544 * target node and are managed by this driver.
545 */
546static int sysc_check_one_child(struct sysc *ddata,
547 struct device_node *np)
548{
549 const char *name;
550
551 name = of_get_property(np, "ti,hwmods", NULL);
552 if (name)
553 dev_warn(ddata->dev, "really a child ti,hwmods property?");
554
3bb37c8e 555 sysc_check_quirk_stdout(ddata, np);
4014c08b 556 sysc_parse_dts_quirks(ddata, np, true);
3bb37c8e 557
0eecc636
TL		 558 return 0;
559}
560
561static int sysc_check_children(struct sysc *ddata)
562{
563 struct device_node *child;
564 int error;
565
566 for_each_child_of_node(ddata->dev->of_node, child) {
567 error = sysc_check_one_child(ddata, child);
568 if (error)
569 return error;
570 }
571
572 return 0;
573}
574
a7199e2b
TL		 575/*
576 * So far only I2C uses 16-bit read access with clockactivity with revision
577 * in two registers with stride of 4. We can detect this based on the rev
578 * register size to configure things far enough to be able to properly read
579 * the revision register.
580 */
581static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
582{
dd57ac1e 583 if (resource_size(res) == 8)
a7199e2b 584 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 585}
586
0eecc636
TL		 587/**
588 * sysc_parse_one - parses the interconnect target module registers
589 * @ddata: device driver data
590 * @reg: register to parse
591 */
592static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
593{
594 struct resource *res;
595 const char *name;
596
597 switch (reg) {
598 case SYSC_REVISION:
599 case SYSC_SYSCONFIG:
600 case SYSC_SYSSTATUS:
601 name = reg_names[reg];
602 break;
603 default:
604 return -EINVAL;
605 }
606
607 res = platform_get_resource_byname(to_platform_device(ddata->dev),
608 IORESOURCE_MEM, name);
609 if (!res) {
0eecc636
TL		 610 ddata->offsets[reg] = -ENODEV;
611
612 return 0;
613 }
614
615 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 616 if (reg == SYSC_REVISION)
617 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 618
619 return 0;
620}
621
622static int sysc_parse_registers(struct sysc *ddata)
623{
624 int i, error;
625
626 for (i = 0; i < SYSC_MAX_REGS; i++) {
627 error = sysc_parse_one(ddata, i);
628 if (error)
629 return error;
630 }
631
632 return 0;
633}
634
635/**
636 * sysc_check_registers - check for misconfigured register overlaps
637 * @ddata: device driver data
638 */
639static int sysc_check_registers(struct sysc *ddata)
640{
641 int i, j, nr_regs = 0, nr_matches = 0;
642
643 for (i = 0; i < SYSC_MAX_REGS; i++) {
644 if (ddata->offsets[i] < 0)
645 continue;
646
647 if (ddata->offsets[i] > (ddata->module_size - 4)) {
648 dev_err(ddata->dev, "register outside module range");
649
650 return -EINVAL;
651 }
652
653 for (j = 0; j < SYSC_MAX_REGS; j++) {
654 if (ddata->offsets[j] < 0)
655 continue;
656
657 if (ddata->offsets[i] == ddata->offsets[j])
658 nr_matches++;
659 }
660 nr_regs++;
661 }
662
0eecc636
TL		 663 if (nr_matches > nr_regs) {
664 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
665 nr_regs, nr_matches);
666
667 return -EINVAL;
668 }
669
670 return 0;
671}
672
673/**
674 * syc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 675 * @ddata: device driver data
0eecc636
TL		 676 *
677 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 678 * within the interconnect target module range. For example, SGX has
679 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
680 * has them at offset 0x1200 in the CPSW_WR child. Usually the
681 * the interconnect target module registers are at the beginning of
682 * the module range though.
0eecc636
TL		 683 */
684static int sysc_ioremap(struct sysc *ddata)
685{
0ef8e3bb 686 int size;
0eecc636 687
e4f50c8d
TL		 688 if (ddata->offsets[SYSC_REVISION] < 0 &&
689 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
690 ddata->offsets[SYSC_SYSSTATUS] < 0) {
691 size = ddata->module_size;
692 } else {
693 size = max3(ddata->offsets[SYSC_REVISION],
694 ddata->offsets[SYSC_SYSCONFIG],
695 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 696
e4f50c8d
TL		 697 if ((size + sizeof(u32)) > ddata->module_size)
698 return -EINVAL;
699 }
0eecc636
TL		 700
701 ddata->module_va = devm_ioremap(ddata->dev,
702 ddata->module_pa,
0ef8e3bb 703 size + sizeof(u32));
0eecc636
TL		 704 if (!ddata->module_va)
705 return -EIO;
706
707 return 0;
708}
709
710/**
711 * sysc_map_and_check_registers - ioremap and check device registers
712 * @ddata: device driver data
713 */
714static int sysc_map_and_check_registers(struct sysc *ddata)
715{
716 int error;
717
718 error = sysc_parse_and_check_child_range(ddata);
719 if (error)
720 return error;
721
722 error = sysc_check_children(ddata);
723 if (error)
724 return error;
725
726 error = sysc_parse_registers(ddata);
727 if (error)
728 return error;
729
730 error = sysc_ioremap(ddata);
731 if (error)
732 return error;
733
734 error = sysc_check_registers(ddata);
735 if (error)
736 return error;
737
738 return 0;
739}
740
741/**
742 * sysc_show_rev - read and show interconnect target module revision
743 * @bufp: buffer to print the information to
744 * @ddata: device driver data
745 */
746static int sysc_show_rev(char *bufp, struct sysc *ddata)
747{
566a9b05 748 int len;
0eecc636
TL		 749
750 if (ddata->offsets[SYSC_REVISION] < 0)
751 return sprintf(bufp, ":NA");
752
566a9b05 753 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 754
755 return len;
756}
757
758static int sysc_show_reg(struct sysc *ddata,
759 char *bufp, enum sysc_registers reg)
760{
761 if (ddata->offsets[reg] < 0)
762 return sprintf(bufp, ":NA");
763
764 return sprintf(bufp, ":%x", ddata->offsets[reg]);
765}
766
a885f0fe
TL		 767static int sysc_show_name(char *bufp, struct sysc *ddata)
768{
769 if (!ddata->name)
770 return 0;
771
772 return sprintf(bufp, ":%s", ddata->name);
773}
774
0eecc636
TL		 775/**
776 * sysc_show_registers - show information about interconnect target module
777 * @ddata: device driver data
778 */
779static void sysc_show_registers(struct sysc *ddata)
780{
781 char buf[128];
782 char *bufp = buf;
783 int i;
784
785 for (i = 0; i < SYSC_MAX_REGS; i++)
786 bufp += sysc_show_reg(ddata, bufp, i);
787
788 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 789 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 790
791 dev_dbg(ddata->dev, "%llx:%x%s\n",
792 ddata->module_pa, ddata->module_size,
793 buf);
794}
795
d59b6056
RQ		 796#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
797
798static int sysc_enable_module(struct device *dev)
799{
800 struct sysc *ddata;
801 const struct sysc_regbits *regbits;
802 u32 reg, idlemodes, best_mode;
803
804 ddata = dev_get_drvdata(dev);
805 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
806 return 0;
807
808 /*
809 * TODO: Need to prevent clockdomain autoidle?
810 * See clkdm_deny_idle() in arch/mach-omap2/omap_hwmod.c
811 */
812
813 regbits = ddata->cap->regbits;
814 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
815
816 /* Set SIDLE mode */
817 idlemodes = ddata->cfg.sidlemodes;
818 if (!idlemodes || regbits->sidle_shift < 0)
819 goto set_midle;
820
821 best_mode = fls(ddata->cfg.sidlemodes) - 1;
822 if (best_mode > SYSC_IDLE_MASK) {
823 dev_err(dev, "%s: invalid sidlemode\n", __func__);
824 return -EINVAL;
825 }
826
827 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
828 reg |= best_mode << regbits->sidle_shift;
829 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
830
831set_midle:
832 /* Set MIDLE mode */
833 idlemodes = ddata->cfg.midlemodes;
834 if (!idlemodes || regbits->midle_shift < 0)
835 return 0;
836
837 best_mode = fls(ddata->cfg.midlemodes) - 1;
838 if (best_mode > SYSC_IDLE_MASK) {
839 dev_err(dev, "%s: invalid midlemode\n", __func__);
840 return -EINVAL;
841 }
842
843 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
844 reg |= best_mode << regbits->midle_shift;
845 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
846
847 return 0;
848}
849
850static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
851{
852 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
853 *best_mode = SYSC_IDLE_SMART_WKUP;
854 else if (idlemodes & BIT(SYSC_IDLE_SMART))
855 *best_mode = SYSC_IDLE_SMART;
856 else if (idlemodes & SYSC_IDLE_FORCE)
857 *best_mode = SYSC_IDLE_FORCE;
858 else
859 return -EINVAL;
860
861 return 0;
862}
863
864static int sysc_disable_module(struct device *dev)
865{
866 struct sysc *ddata;
867 const struct sysc_regbits *regbits;
868 u32 reg, idlemodes, best_mode;
869 int ret;
870
871 ddata = dev_get_drvdata(dev);
872 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
873 return 0;
874
875 /*
876 * TODO: Need to prevent clockdomain autoidle?
877 * See clkdm_deny_idle() in arch/mach-omap2/omap_hwmod.c
878 */
879
880 regbits = ddata->cap->regbits;
881 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
882
883 /* Set MIDLE mode */
884 idlemodes = ddata->cfg.midlemodes;
885 if (!idlemodes || regbits->midle_shift < 0)
886 goto set_sidle;
887
888 ret = sysc_best_idle_mode(idlemodes, &best_mode);
889 if (ret) {
890 dev_err(dev, "%s: invalid midlemode\n", __func__);
891 return ret;
892 }
893
894 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
895 reg |= best_mode << regbits->midle_shift;
896 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
897
898set_sidle:
899 /* Set SIDLE mode */
900 idlemodes = ddata->cfg.sidlemodes;
901 if (!idlemodes || regbits->sidle_shift < 0)
902 return 0;
903
904 ret = sysc_best_idle_mode(idlemodes, &best_mode);
905 if (ret) {
906 dev_err(dev, "%s: invalid sidlemode\n", __func__);
907 return ret;
908 }
909
910 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
911 reg |= best_mode << regbits->sidle_shift;
912 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
913
914 return 0;
915}
916
ff43728c
TL		 917static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
918 struct sysc *ddata)
919{
920 struct ti_sysc_platform_data *pdata;
921 int error;
922
923 pdata = dev_get_platdata(ddata->dev);
924 if (!pdata)
925 return 0;
926
927 if (!pdata->idle_module)
928 return -ENODEV;
929
930 error = pdata->idle_module(dev, &ddata->cookie);
931 if (error)
932 dev_err(dev, "%s: could not idle: %i\n",
933 __func__, error);
934
935 return 0;
936}
937
938static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
939 struct sysc *ddata)
0eecc636 940{
ef70b0bd 941 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 942 int error;
943
944 pdata = dev_get_platdata(ddata->dev);
945 if (!pdata)
946 return 0;
947
948 if (!pdata->enable_module)
949 return -ENODEV;
950
951 error = pdata->enable_module(dev, &ddata->cookie);
952 if (error)
953 dev_err(dev, "%s: could not enable: %i\n",
954 __func__, error);
955
956 return 0;
957}
958
959static int __maybe_unused sysc_runtime_suspend(struct device *dev)
960{
0eecc636 961 struct sysc *ddata;
d878970f 962 int error = 0;
0eecc636
TL		 963
964 ddata = dev_get_drvdata(dev);
965
ef70b0bd 966 if (!ddata->enabled)
0eecc636
TL		 967 return 0;
968
ef70b0bd 969 if (ddata->legacy_mode) {
ff43728c 970 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2
TL		 971 if (error)
972 return error;
d59b6056
RQ		 973 } else {
974 error = sysc_disable_module(dev);
975 if (error)
976 return error;
ef70b0bd
TL		 977 }
978
d878970f 979 sysc_disable_main_clocks(ddata);
09dfe581 980
d878970f
TL		 981 if (sysc_opt_clks_needed(ddata))
982 sysc_disable_opt_clocks(ddata);
0eecc636 983
ef70b0bd
TL		 984 ddata->enabled = false;
985
986 return error;
0eecc636
TL		 987}
988
a4a5d493 989static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 990{
991 struct sysc *ddata;
d878970f 992 int error = 0;
0eecc636
TL		 993
994 ddata = dev_get_drvdata(dev);
995
ef70b0bd 996 if (ddata->enabled)
0eecc636
TL		 997 return 0;
998
d878970f
TL		 999 if (sysc_opt_clks_needed(ddata)) {
1000 error = sysc_enable_opt_clocks(ddata);
0eecc636
TL		 1001 if (error)
1002 return error;
1003 }
1004
d878970f
TL		 1005 error = sysc_enable_main_clocks(ddata);
1006 if (error)
93de83a2
TL		 1007 goto err_opt_clocks;
1008
1009 if (ddata->legacy_mode) {
1010 error = sysc_runtime_resume_legacy(dev, ddata);
1011 if (error)
1012 goto err_main_clocks;
d59b6056
RQ		 1013 } else {
1014 error = sysc_enable_module(dev);
1015 if (error)
1016 goto err_main_clocks;
93de83a2 1017 }
d878970f 1018
ef70b0bd
TL		 1019 ddata->enabled = true;
1020
d878970f
TL		 1021 return 0;
1022
1023err_main_clocks:
93de83a2
TL		 1024 sysc_disable_main_clocks(ddata);
1025err_opt_clocks:
d878970f
TL		 1026 if (sysc_opt_clks_needed(ddata))
1027 sysc_disable_opt_clocks(ddata);
1028
ef70b0bd 1029 return error;
0eecc636
TL		 1030}
1031
f5e80203 1032static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1033{
1034 struct sysc *ddata;
1035
1036 ddata = dev_get_drvdata(dev);
1037
40d9f912 1038 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1039 return 0;
1040
f5e80203 1041 return pm_runtime_force_suspend(dev);
62020f23
TL		 1042}
1043
f5e80203 1044static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1045{
1046 struct sysc *ddata;
1047
1048 ddata = dev_get_drvdata(dev);
e7420c2d 1049
40d9f912 1050 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
e7420c2d
TL		 1051 return 0;
1052
f5e80203 1053 return pm_runtime_force_resume(dev);
0eecc636
TL		 1054}
1055
1056static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1057 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1058 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1059 sysc_runtime_resume,
1060 NULL)
1061};
1062
a885f0fe
TL		 1063/* Module revision register based quirks */
1064struct sysc_revision_quirk {
1065 const char *name;
1066 u32 base;
1067 int rev_offset;
1068 int sysc_offset;
1069 int syss_offset;
1070 u32 revision;
1071 u32 revision_mask;
1072 u32 quirks;
1073};
1074
1075#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1076 optrev_val, optrevmask, optquirkmask) \
1077 { \
1078 .name = (optname), \
1079 .base = (optbase), \
1080 .rev_offset = (optrev), \
1081 .sysc_offset = (optsysc), \
1082 .syss_offset = (optsyss), \
1083 .revision = (optrev_val), \
1084 .revision_mask = (optrevmask), \
1085 .quirks = (optquirkmask), \
1086 }
1087
1088static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1089 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
3a3d802b 1090 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
09dfe581 1091 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
a885f0fe
TL		 1092 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1093 SYSC_QUIRK_LEGACY_IDLE),
1094 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1095 SYSC_QUIRK_LEGACY_IDLE),
1096 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1097 SYSC_QUIRK_LEGACY_IDLE),
1098 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1099 SYSC_QUIRK_LEGACY_IDLE),
1100 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1101 SYSC_QUIRK_LEGACY_IDLE),
1102 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
9bd34c63 1103 0),
8cde5d5f 1104 /* Some timers on omap4 and later */
3a3d802b 1105 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
072167d1 1106 0),
3a3d802b 1107 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
9bd34c63 1108 0),
a885f0fe 1109 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b4a9a7a3 1110 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1111 /* Uarts on omap4 and later */
b82beef5 1112 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
b4a9a7a3 1113 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1114 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
b4a9a7a3 1115 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1116
a54275f4
TL		 1117 /* Quirks that need to be set based on the module address */
1118 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1119 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1120 SYSC_QUIRK_SWSUP_SIDLE),
1121
dc4c85ea 1122#ifdef DEBUG
1ba30693 1123 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
c6eb4af3 1124 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
dc4c85ea 1125 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
c6eb4af3 1126 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
40d9f912 1127 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1ba30693 1128 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac
TL		 1129 0xffff00f0, 0),
1130 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
13aad519 1131 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1ba30693
TL		 1132 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1133 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
dc4c85ea
TL		 1134 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1135 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
1ba30693 1136 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 0),
dc4c85ea
TL		 1137 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1138 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
c6eb4af3 1139 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 0),
23731eac 1140 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
dc4c85ea 1141 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1ba30693 1142 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
dc4c85ea 1143 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
c6eb4af3 1144 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1145 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
dc4c85ea 1146 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1ba30693 1147 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1148 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1ba30693 1149 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
40d9f912 1150 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
f0106700 1151 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
40d9f912 1152 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
23731eac 1153 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1ba30693 1154 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
40d9f912 1155 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
23731eac 1156 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1ba30693 1157 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
c6eb4af3 1158 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
40d9f912 1159 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
c6eb4af3 1160 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1ba30693 1161 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1162 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
dc4c85ea
TL		 1163 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1164 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1165 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1ba30693 1166 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
c6eb4af3 1167 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1ba30693 1168 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
dc4c85ea 1169 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1170 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
dc4c85ea 1171 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
f0106700 1172 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
dc4c85ea
TL		 1173 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1174 0xffffffff, 0),
1ba30693
TL		 1175 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 0),
1176 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1177#endif
a885f0fe
TL		 1178};
1179
42b9c5c9
TL		 1180/*
1181 * Early quirks based on module base and register offsets only that are
1182 * needed before the module revision can be read
1183 */
1184static void sysc_init_early_quirks(struct sysc *ddata)
1185{
1186 const struct sysc_revision_quirk *q;
1187 int i;
1188
1189 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1190 q = &sysc_revision_quirks[i];
1191
1192 if (!q->base)
1193 continue;
1194
1195 if (q->base != ddata->module_pa)
1196 continue;
1197
1198 if (q->rev_offset >= 0 &&
1199 q->rev_offset != ddata->offsets[SYSC_REVISION])
1200 continue;
1201
1202 if (q->sysc_offset >= 0 &&
1203 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1204 continue;
1205
1206 if (q->syss_offset >= 0 &&
1207 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1208 continue;
1209
1210 ddata->name = q->name;
1211 ddata->cfg.quirks |= q->quirks;
1212 }
1213}
1214
1215/* Quirks that also consider the revision register value */
a885f0fe
TL		 1216static void sysc_init_revision_quirks(struct sysc *ddata)
1217{
1218 const struct sysc_revision_quirk *q;
1219 int i;
1220
1221 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1222 q = &sysc_revision_quirks[i];
1223
1224 if (q->base && q->base != ddata->module_pa)
1225 continue;
1226
1227 if (q->rev_offset >= 0 &&
1228 q->rev_offset != ddata->offsets[SYSC_REVISION])
1229 continue;
1230
1231 if (q->sysc_offset >= 0 &&
1232 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1233 continue;
1234
1235 if (q->syss_offset >= 0 &&
1236 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1237 continue;
1238
1239 if (q->revision == ddata->revision ||
1240 (q->revision & q->revision_mask) ==
1241 (ddata->revision & q->revision_mask)) {
1242 ddata->name = q->name;
1243 ddata->cfg.quirks |= q->quirks;
1244 }
1245 }
1246}
1247
a3e92e7b
TL		 1248/*
1249 * Note that pdata->init_module() typically does a reset first. After
1250 * pdata->init_module() is done, PM runtime can be used for the interconnect
1251 * target module.
1252 */
1253static int sysc_legacy_init(struct sysc *ddata)
1254{
1255 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1256 int error;
1257
1258 if (!ddata->legacy_mode || !pdata || !pdata->init_module)
1259 return 0;
1260
1261 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1262 if (error == -EEXIST)
1263 error = 0;
1264
1265 return error;
1266}
1267
b11c1ea1
TL		 1268/**
1269 * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1270 * @ddata: device driver data
1271 * @reset: reset before deassert
1272 *
1273 * A module can have both OCP softreset control and external rstctrl.
1274 * If more complicated rstctrl resets are needed, please handle these
1275 * directly from the child device driver and map only the module reset
1276 * for the parent interconnect target module device.
1277 *
1278 * Automatic reset of the module on init can be skipped with the
1279 * "ti,no-reset-on-init" device tree property.
1280 */
1281static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1282{
1283 int error;
1284
1285 if (!ddata->rsts)
1286 return 0;
1287
1288 if (reset) {
1289 error = reset_control_assert(ddata->rsts);
1290 if (error)
1291 return error;
1292 }
1293
1294 return reset_control_deassert(ddata->rsts);
1295}
1296
596e7955
FA		 1297static int sysc_reset(struct sysc *ddata)
1298{
1299 int offset = ddata->offsets[SYSC_SYSCONFIG];
1300 int val;
1301
1302 if (ddata->legacy_mode || offset < 0 ||
1303 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1304 return 0;
1305
1306 /*
1307 * Currently only support reset status in sysstatus.
1308 * Warn and return error in all other cases
1309 */
1310 if (!ddata->cfg.syss_mask) {
1311 dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n");
1312 return -EINVAL;
1313 }
1314
1315 val = sysc_read(ddata, offset);
1316 val |= (0x1 << ddata->cap->regbits->srst_shift);
1317 sysc_write(ddata, offset, val);
1318
1319 /* Poll on reset status */
1320 offset = ddata->offsets[SYSC_SYSSTATUS];
1321
1322 return readl_poll_timeout(ddata->module_va + offset, val,
1323 (val & ddata->cfg.syss_mask) == 0x0,
1324 100, MAX_MODULE_SOFTRESET_WAIT);
1325}
1326
1a5cd7c2
TL		 1327/*
1328 * At this point the module is configured enough to read the revision but
1329 * module may not be completely configured yet to use PM runtime. Enable
1330 * all clocks directly during init to configure the quirks needed for PM
1331 * runtime based on the revision register.
1332 */
566a9b05
TL		 1333static int sysc_init_module(struct sysc *ddata)
1334{
1a5cd7c2
TL		 1335 int error = 0;
1336 bool manage_clocks = true;
b11c1ea1
TL		 1337 bool reset = true;
1338
1339 if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1340 reset = false;
1341
1342 error = sysc_rstctrl_reset_deassert(ddata, reset);
1343 if (error)
1344 return error;
566a9b05 1345
386cb766 1346 if (ddata->cfg.quirks &
1a5cd7c2
TL		 1347 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1348 manage_clocks = false;
a885f0fe 1349
1a5cd7c2
TL		 1350 if (manage_clocks) {
1351 error = sysc_enable_opt_clocks(ddata);
1352 if (error)
1353 return error;
566a9b05 1354
1a5cd7c2
TL		 1355 error = sysc_enable_main_clocks(ddata);
1356 if (error)
1357 goto err_opt_clocks;
566a9b05 1358 }
5062236e 1359
1a5cd7c2
TL		 1360 ddata->revision = sysc_read_revision(ddata);
1361 sysc_init_revision_quirks(ddata);
1362
a3e92e7b
TL		 1363 error = sysc_legacy_init(ddata);
1364 if (error)
1365 goto err_main_clocks;
1366
596e7955 1367 error = sysc_reset(ddata);
1a5cd7c2 1368 if (error)
596e7955 1369 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 1370
a3e92e7b 1371err_main_clocks:
1a5cd7c2
TL		 1372 if (manage_clocks)
1373 sysc_disable_main_clocks(ddata);
1374err_opt_clocks:
1375 if (manage_clocks)
1376 sysc_disable_opt_clocks(ddata);
a885f0fe 1377
1a5cd7c2 1378 return error;
566a9b05
TL		 1379}
1380
c5a2de97
TL		 1381static int sysc_init_sysc_mask(struct sysc *ddata)
1382{
1383 struct device_node *np = ddata->dev->of_node;
1384 int error;
1385 u32 val;
1386
1387 error = of_property_read_u32(np, "ti,sysc-mask", &val);
1388 if (error)
1389 return 0;
1390
1391 if (val)
1392 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1393 else
1394 ddata->cfg.sysc_val = ddata->cap->sysc_mask;
1395
1396 return 0;
1397}
1398
1399static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1400 const char *name)
1401{
1402 struct device_node *np = ddata->dev->of_node;
1403 struct property *prop;
1404 const __be32 *p;
1405 u32 val;
1406
1407 of_property_for_each_u32(np, name, prop, p, val) {
1408 if (val >= SYSC_NR_IDLEMODES) {
1409 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1410 return -EINVAL;
1411 }
1412 *idlemodes |= (1 << val);
1413 }
1414
1415 return 0;
1416}
1417
1418static int sysc_init_idlemodes(struct sysc *ddata)
1419{
1420 int error;
1421
1422 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1423 "ti,sysc-midle");
1424 if (error)
1425 return error;
1426
1427 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1428 "ti,sysc-sidle");
1429 if (error)
1430 return error;
1431
1432 return 0;
1433}
1434
1435/*
1436 * Only some devices on omap4 and later have SYSCONFIG reset done
1437 * bit. We can detect this if there is no SYSSTATUS at all, or the
1438 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1439 * have multiple bits for the child devices like OHCI and EHCI.
1440 * Depends on SYSC being parsed first.
1441 */
1442static int sysc_init_syss_mask(struct sysc *ddata)
1443{
1444 struct device_node *np = ddata->dev->of_node;
1445 int error;
1446 u32 val;
1447
1448 error = of_property_read_u32(np, "ti,syss-mask", &val);
1449 if (error) {
1450 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1451 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1452 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1453 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1454
1455 return 0;
1456 }
1457
1458 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1459 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1460
1461 ddata->cfg.syss_mask = val;
1462
1463 return 0;
1464}
1465
2c355ff6 1466/*
8b2830ba
TL		 1467 * Many child device drivers need to have fck and opt clocks available
1468 * to get the clock rate for device internal configuration etc.
2c355ff6 1469 */
8b2830ba
TL		 1470static int sysc_child_add_named_clock(struct sysc *ddata,
1471 struct device *child,
1472 const char *name)
2c355ff6 1473{
8b2830ba 1474 struct clk *clk;
2c355ff6 1475 struct clk_lookup *l;
8b2830ba 1476 int error = 0;
2c355ff6 1477
8b2830ba 1478 if (!name)
2c355ff6
TL		 1479 return 0;
1480
8b2830ba
TL		 1481 clk = clk_get(child, name);
1482 if (!IS_ERR(clk)) {
1483 clk_put(clk);
2c355ff6
TL		 1484
1485 return -EEXIST;
1486 }
1487
8b2830ba
TL		 1488 clk = clk_get(ddata->dev, name);
1489 if (IS_ERR(clk))
1490 return -ENODEV;
2c355ff6 1491
8b2830ba
TL		 1492 l = clkdev_create(clk, name, dev_name(child));
1493 if (!l)
1494 error = -ENOMEM;
1495
1496 clk_put(clk);
1497
1498 return error;
2c355ff6
TL		 1499}
1500
09dfe581
TL		 1501static int sysc_child_add_clocks(struct sysc *ddata,
1502 struct device *child)
1503{
1504 int i, error;
1505
1506 for (i = 0; i < ddata->nr_clocks; i++) {
1507 error = sysc_child_add_named_clock(ddata,
1508 child,
1509 ddata->clock_roles[i]);
1510 if (error && error != -EEXIST) {
1511 dev_err(ddata->dev, "could not add child clock %s: %i\n",
1512 ddata->clock_roles[i], error);
1513
1514 return error;
1515 }
1516 }
1517
1518 return 0;
1519}
1520
2c355ff6
TL		 1521static struct device_type sysc_device_type = {
1522};
1523
1524static struct sysc *sysc_child_to_parent(struct device *dev)
1525{
1526 struct device *parent = dev->parent;
1527
1528 if (!parent || parent->type != &sysc_device_type)
1529 return NULL;
1530
1531 return dev_get_drvdata(parent);
1532}
1533
a885f0fe
TL		 1534static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1535{
1536 struct sysc *ddata;
1537 int error;
1538
1539 ddata = sysc_child_to_parent(dev);
1540
1541 error = pm_generic_runtime_suspend(dev);
1542 if (error)
1543 return error;
1544
1545 if (!ddata->enabled)
1546 return 0;
1547
1548 return sysc_runtime_suspend(ddata->dev);
1549}
1550
1551static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1552{
1553 struct sysc *ddata;
1554 int error;
1555
1556 ddata = sysc_child_to_parent(dev);
1557
1558 if (!ddata->enabled) {
1559 error = sysc_runtime_resume(ddata->dev);
1560 if (error < 0)
1561 dev_err(ddata->dev,
1562 "%s error: %i\n", __func__, error);
1563 }
1564
1565 return pm_generic_runtime_resume(dev);
1566}
1567
1568#ifdef CONFIG_PM_SLEEP
1569static int sysc_child_suspend_noirq(struct device *dev)
1570{
1571 struct sysc *ddata;
1572 int error;
1573
1574 ddata = sysc_child_to_parent(dev);
1575
ef55f821
TL		 1576 dev_dbg(ddata->dev, "%s %s\n", __func__,
1577 ddata->name ? ddata->name : "");
1578
a885f0fe 1579 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 1580 if (error) {
1581 dev_err(dev, "%s error at %i: %i\n",
1582 __func__, __LINE__, error);
1583
a885f0fe 1584 return error;
ef55f821 1585 }
a885f0fe
TL		 1586
1587 if (!pm_runtime_status_suspended(dev)) {
1588 error = pm_generic_runtime_suspend(dev);
ef55f821 1589 if (error) {
f9490783
TL		 1590 dev_dbg(dev, "%s busy at %i: %i\n",
1591 __func__, __LINE__, error);
ef55f821 1592
4f3530f4 1593 return 0;
ef55f821 1594 }
a885f0fe
TL		 1595
1596 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 1597 if (error) {
1598 dev_err(dev, "%s error at %i: %i\n",
1599 __func__, __LINE__, error);
1600
a885f0fe 1601 return error;
ef55f821 1602 }
a885f0fe
TL		 1603
1604 ddata->child_needs_resume = true;
1605 }
1606
1607 return 0;
1608}
1609
1610static int sysc_child_resume_noirq(struct device *dev)
1611{
1612 struct sysc *ddata;
1613 int error;
1614
1615 ddata = sysc_child_to_parent(dev);
1616
ef55f821
TL		 1617 dev_dbg(ddata->dev, "%s %s\n", __func__,
1618 ddata->name ? ddata->name : "");
1619
a885f0fe
TL		 1620 if (ddata->child_needs_resume) {
1621 ddata->child_needs_resume = false;
1622
1623 error = sysc_runtime_resume(ddata->dev);
1624 if (error)
1625 dev_err(ddata->dev,
1626 "%s runtime resume error: %i\n",
1627 __func__, error);
1628
1629 error = pm_generic_runtime_resume(dev);
1630 if (error)
1631 dev_err(ddata->dev,
1632 "%s generic runtime resume: %i\n",
1633 __func__, error);
1634 }
1635
1636 return pm_generic_resume_noirq(dev);
1637}
1638#endif
1639
b7182b42 1640static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 1641 .ops = {
1642 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1643 sysc_child_runtime_resume,
1644 NULL)
1645 USE_PLATFORM_PM_SLEEP_OPS
1646 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1647 sysc_child_resume_noirq)
1648 }
1649};
1650
1651/**
1652 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1653 * @ddata: device driver data
1654 * @child: child device driver
1655 *
1656 * Allow idle for child devices as done with _od_runtime_suspend().
1657 * Otherwise many child devices will not idle because of the permanent
1658 * parent usecount set in pm_runtime_irq_safe().
1659 *
1660 * Note that the long term solution is to just modify the child device
1661 * drivers to not set pm_runtime_irq_safe() and then this can be just
1662 * dropped.
1663 */
1664static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1665{
1666 if (!ddata->legacy_mode)
1667 return;
1668
1669 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1670 dev_pm_domain_set(child, &sysc_child_pm_domain);
1671}
1672
2c355ff6
TL		 1673static int sysc_notifier_call(struct notifier_block *nb,
1674 unsigned long event, void *device)
1675{
1676 struct device *dev = device;
1677 struct sysc *ddata;
1678 int error;
1679
1680 ddata = sysc_child_to_parent(dev);
1681 if (!ddata)
1682 return NOTIFY_DONE;
1683
1684 switch (event) {
1685 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 1686 error = sysc_child_add_clocks(ddata, dev);
1687 if (error)
1688 return error;
a885f0fe 1689 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 1690 break;
1691 default:
1692 break;
1693 }
1694
1695 return NOTIFY_DONE;
1696}
1697
1698static struct notifier_block sysc_nb = {
1699 .notifier_call = sysc_notifier_call,
1700};
1701
566a9b05
TL		 1702/* Device tree configured quirks */
1703struct sysc_dts_quirk {
1704 const char *name;
1705 u32 mask;
1706};
1707
1708static const struct sysc_dts_quirk sysc_dts_quirks[] = {
1709 { .name = "ti,no-idle-on-init",
1710 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1711 { .name = "ti,no-reset-on-init",
1712 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 1713 { .name = "ti,no-idle",
1714 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 1715};
1716
4014c08b
TL		 1717static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
1718 bool is_child)
566a9b05 1719{
566a9b05 1720 const struct property *prop;
4014c08b 1721 int i, len;
566a9b05
TL		 1722
1723 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 1724 const char *name = sysc_dts_quirks[i].name;
1725
1726 prop = of_get_property(np, name, &len);
566a9b05 1727 if (!prop)
d39b6ea4 1728 continue;
566a9b05
TL		 1729
1730 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 1731 if (is_child) {
1732 dev_warn(ddata->dev,
1733 "dts flag should be at module level for %s\n",
1734 name);
1735 }
566a9b05 1736 }
4014c08b
TL		 1737}
1738
1739static int sysc_init_dts_quirks(struct sysc *ddata)
1740{
1741 struct device_node *np = ddata->dev->of_node;
1742 int error;
1743 u32 val;
1744
1745 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 1746
4014c08b 1747 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 1748 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
1749 if (!error) {
1750 if (val > 255) {
1751 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
1752 val);
1753 }
1754
1755 ddata->cfg.srst_udelay = (u8)val;
1756 }
1757
1758 return 0;
1759}
1760
0eecc636
TL		 1761static void sysc_unprepare(struct sysc *ddata)
1762{
1763 int i;
1764
aaa29bb0
TL		 1765 if (!ddata->clocks)
1766 return;
1767
0eecc636
TL		 1768 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
1769 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
1770 clk_unprepare(ddata->clocks[i]);
1771 }
1772}
1773
70a65240
TL		 1774/*
1775 * Common sysc register bits found on omap2, also known as type1
1776 */
1777static const struct sysc_regbits sysc_regbits_omap2 = {
1778 .dmadisable_shift = -ENODEV,
1779 .midle_shift = 12,
1780 .sidle_shift = 3,
1781 .clkact_shift = 8,
1782 .emufree_shift = 5,
1783 .enwkup_shift = 2,
1784 .srst_shift = 1,
1785 .autoidle_shift = 0,
1786};
1787
1788static const struct sysc_capabilities sysc_omap2 = {
1789 .type = TI_SYSC_OMAP2,
1790 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1791 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1792 SYSC_OMAP2_AUTOIDLE,
1793 .regbits = &sysc_regbits_omap2,
1794};
1795
1796/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
1797static const struct sysc_capabilities sysc_omap2_timer = {
1798 .type = TI_SYSC_OMAP2_TIMER,
1799 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
1800 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
1801 SYSC_OMAP2_AUTOIDLE,
1802 .regbits = &sysc_regbits_omap2,
1803 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
1804};
1805
1806/*
1807 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
1808 * with different sidle position
1809 */
1810static const struct sysc_regbits sysc_regbits_omap3_sham = {
1811 .dmadisable_shift = -ENODEV,
1812 .midle_shift = -ENODEV,
1813 .sidle_shift = 4,
1814 .clkact_shift = -ENODEV,
1815 .enwkup_shift = -ENODEV,
1816 .srst_shift = 1,
1817 .autoidle_shift = 0,
1818 .emufree_shift = -ENODEV,
1819};
1820
1821static const struct sysc_capabilities sysc_omap3_sham = {
1822 .type = TI_SYSC_OMAP3_SHAM,
1823 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1824 .regbits = &sysc_regbits_omap3_sham,
1825};
1826
1827/*
1828 * AES register bits found on omap3 and later, a variant of
1829 * sysc_regbits_omap2 with different sidle position
1830 */
1831static const struct sysc_regbits sysc_regbits_omap3_aes = {
1832 .dmadisable_shift = -ENODEV,
1833 .midle_shift = -ENODEV,
1834 .sidle_shift = 6,
1835 .clkact_shift = -ENODEV,
1836 .enwkup_shift = -ENODEV,
1837 .srst_shift = 1,
1838 .autoidle_shift = 0,
1839 .emufree_shift = -ENODEV,
1840};
1841
1842static const struct sysc_capabilities sysc_omap3_aes = {
1843 .type = TI_SYSC_OMAP3_AES,
1844 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
1845 .regbits = &sysc_regbits_omap3_aes,
1846};
1847
1848/*
1849 * Common sysc register bits found on omap4, also known as type2
1850 */
1851static const struct sysc_regbits sysc_regbits_omap4 = {
1852 .dmadisable_shift = 16,
1853 .midle_shift = 4,
1854 .sidle_shift = 2,
1855 .clkact_shift = -ENODEV,
1856 .enwkup_shift = -ENODEV,
1857 .emufree_shift = 1,
1858 .srst_shift = 0,
1859 .autoidle_shift = -ENODEV,
1860};
1861
1862static const struct sysc_capabilities sysc_omap4 = {
1863 .type = TI_SYSC_OMAP4,
1864 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1865 SYSC_OMAP4_SOFTRESET,
1866 .regbits = &sysc_regbits_omap4,
1867};
1868
1869static const struct sysc_capabilities sysc_omap4_timer = {
1870 .type = TI_SYSC_OMAP4_TIMER,
1871 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
1872 SYSC_OMAP4_SOFTRESET,
1873 .regbits = &sysc_regbits_omap4,
1874};
1875
1876/*
1877 * Common sysc register bits found on omap4, also known as type3
1878 */
1879static const struct sysc_regbits sysc_regbits_omap4_simple = {
1880 .dmadisable_shift = -ENODEV,
1881 .midle_shift = 2,
1882 .sidle_shift = 0,
1883 .clkact_shift = -ENODEV,
1884 .enwkup_shift = -ENODEV,
1885 .srst_shift = -ENODEV,
1886 .emufree_shift = -ENODEV,
1887 .autoidle_shift = -ENODEV,
1888};
1889
1890static const struct sysc_capabilities sysc_omap4_simple = {
1891 .type = TI_SYSC_OMAP4_SIMPLE,
1892 .regbits = &sysc_regbits_omap4_simple,
1893};
1894
1895/*
1896 * SmartReflex sysc found on omap34xx
1897 */
1898static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
1899 .dmadisable_shift = -ENODEV,
1900 .midle_shift = -ENODEV,
1901 .sidle_shift = -ENODEV,
1902 .clkact_shift = 20,
1903 .enwkup_shift = -ENODEV,
1904 .srst_shift = -ENODEV,
1905 .emufree_shift = -ENODEV,
1906 .autoidle_shift = -ENODEV,
1907};
1908
1909static const struct sysc_capabilities sysc_34xx_sr = {
1910 .type = TI_SYSC_OMAP34XX_SR,
1911 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
1912 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 1913 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
1914 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 1915};
1916
1917/*
1918 * SmartReflex sysc found on omap36xx and later
1919 */
1920static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
1921 .dmadisable_shift = -ENODEV,
1922 .midle_shift = -ENODEV,
1923 .sidle_shift = 24,
1924 .clkact_shift = -ENODEV,
1925 .enwkup_shift = 26,
1926 .srst_shift = -ENODEV,
1927 .emufree_shift = -ENODEV,
1928 .autoidle_shift = -ENODEV,
1929};
1930
1931static const struct sysc_capabilities sysc_36xx_sr = {
1932 .type = TI_SYSC_OMAP36XX_SR,
3267c081 1933 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 1934 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 1935 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 1936};
1937
1938static const struct sysc_capabilities sysc_omap4_sr = {
1939 .type = TI_SYSC_OMAP4_SR,
1940 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 1941 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 1942};
1943
1944/*
1945 * McASP register bits found on omap4 and later
1946 */
1947static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
1948 .dmadisable_shift = -ENODEV,
1949 .midle_shift = -ENODEV,
1950 .sidle_shift = 0,
1951 .clkact_shift = -ENODEV,
1952 .enwkup_shift = -ENODEV,
1953 .srst_shift = -ENODEV,
1954 .emufree_shift = -ENODEV,
1955 .autoidle_shift = -ENODEV,
1956};
1957
1958static const struct sysc_capabilities sysc_omap4_mcasp = {
1959 .type = TI_SYSC_OMAP4_MCASP,
1960 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 1961 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
1962};
1963
1964/*
1965 * McASP found on dra7 and later
1966 */
1967static const struct sysc_capabilities sysc_dra7_mcasp = {
1968 .type = TI_SYSC_OMAP4_SIMPLE,
1969 .regbits = &sysc_regbits_omap4_simple,
1970 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 1971};
1972
1973/*
1974 * FS USB host found on omap4 and later
1975 */
1976static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
1977 .dmadisable_shift = -ENODEV,
1978 .midle_shift = -ENODEV,
1979 .sidle_shift = 24,
1980 .clkact_shift = -ENODEV,
1981 .enwkup_shift = 26,
1982 .srst_shift = -ENODEV,
1983 .emufree_shift = -ENODEV,
1984 .autoidle_shift = -ENODEV,
1985};
1986
1987static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
1988 .type = TI_SYSC_OMAP4_USB_HOST_FS,
1989 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
1990 .regbits = &sysc_regbits_omap4_usb_host_fs,
1991};
1992
7f35e63d
FA		 1993static const struct sysc_regbits sysc_regbits_dra7_mcan = {
1994 .dmadisable_shift = -ENODEV,
1995 .midle_shift = -ENODEV,
1996 .sidle_shift = -ENODEV,
1997 .clkact_shift = -ENODEV,
1998 .enwkup_shift = 4,
1999 .srst_shift = 0,
2000 .emufree_shift = -ENODEV,
2001 .autoidle_shift = -ENODEV,
2002};
2003
2004static const struct sysc_capabilities sysc_dra7_mcan = {
2005 .type = TI_SYSC_DRA7_MCAN,
2006 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2007 .regbits = &sysc_regbits_dra7_mcan,
2008};
2009
ef70b0bd
TL		 2010static int sysc_init_pdata(struct sysc *ddata)
2011{
2012 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2013 struct ti_sysc_module_data *mdata;
ef70b0bd
TL		 2014
2015 if (!pdata || !ddata->legacy_mode)
2016 return 0;
2017
a3e92e7b
TL		 2018 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2019 if (!mdata)
2020 return -ENOMEM;
ef70b0bd 2021
a3e92e7b
TL		 2022 mdata->name = ddata->legacy_mode;
2023 mdata->module_pa = ddata->module_pa;
2024 mdata->module_size = ddata->module_size;
2025 mdata->offsets = ddata->offsets;
2026 mdata->nr_offsets = SYSC_MAX_REGS;
2027 mdata->cap = ddata->cap;
2028 mdata->cfg = &ddata->cfg;
ef70b0bd 2029
a3e92e7b 2030 ddata->mdata = mdata;
ef70b0bd 2031
a3e92e7b 2032 return 0;
ef70b0bd
TL		 2033}
2034
70a65240
TL		 2035static int sysc_init_match(struct sysc *ddata)
2036{
2037 const struct sysc_capabilities *cap;
2038
2039 cap = of_device_get_match_data(ddata->dev);
2040 if (!cap)
2041 return -EINVAL;
2042
2043 ddata->cap = cap;
2044 if (ddata->cap)
2045 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2046
2047 return 0;
2048}
2049
76f0f772
TL		 2050static void ti_sysc_idle(struct work_struct *work)
2051{
2052 struct sysc *ddata;
2053
2054 ddata = container_of(work, struct sysc, idle_work.work);
2055
2056 if (pm_runtime_active(ddata->dev))
2057 pm_runtime_put_sync(ddata->dev);
2058}
2059
c4bebea8
TL		 2060static const struct of_device_id sysc_match_table[] = {
2061 { .compatible = "simple-bus", },
2062 { /* sentinel */ },
2063};
2064
0eecc636
TL		 2065static int sysc_probe(struct platform_device *pdev)
2066{
ef70b0bd 2067 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 2068 struct sysc *ddata;
2069 int error;
2070
2071 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2072 if (!ddata)
2073 return -ENOMEM;
2074
2075 ddata->dev = &pdev->dev;
566a9b05 2076 platform_set_drvdata(pdev, ddata);
0eecc636 2077
70a65240
TL		 2078 error = sysc_init_match(ddata);
2079 if (error)
2080 return error;
2081
566a9b05
TL		 2082 error = sysc_init_dts_quirks(ddata);
2083 if (error)
2084 goto unprepare;
2085
0eecc636
TL		 2086 error = sysc_map_and_check_registers(ddata);
2087 if (error)
2088 goto unprepare;
2089
c5a2de97
TL		 2090 error = sysc_init_sysc_mask(ddata);
2091 if (error)
2092 goto unprepare;
2093
2094 error = sysc_init_idlemodes(ddata);
2095 if (error)
2096 goto unprepare;
2097
2098 error = sysc_init_syss_mask(ddata);
2099 if (error)
2100 goto unprepare;
2101
ef70b0bd
TL		 2102 error = sysc_init_pdata(ddata);
2103 if (error)
2104 goto unprepare;
2105
42b9c5c9
TL		 2106 sysc_init_early_quirks(ddata);
2107
2108 error = sysc_get_clocks(ddata);
2109 if (error)
2110 return error;
2111
5062236e
TL		 2112 error = sysc_init_resets(ddata);
2113 if (error)
2114 return error;
566a9b05
TL		 2115
2116 error = sysc_init_module(ddata);
2117 if (error)
2118 goto unprepare;
2119
1a5cd7c2 2120 pm_runtime_enable(ddata->dev);
0eecc636
TL		 2121 error = pm_runtime_get_sync(ddata->dev);
2122 if (error < 0) {
2123 pm_runtime_put_noidle(ddata->dev);
2124 pm_runtime_disable(ddata->dev);
2125 goto unprepare;
2126 }
2127
0eecc636
TL		 2128 sysc_show_registers(ddata);
2129
2c355ff6 2130 ddata->dev->type = &sysc_device_type;
c4bebea8
TL		 2131 error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2132 pdata ? pdata->auxdata : NULL,
ef70b0bd 2133 ddata->dev);
0eecc636
TL		 2134 if (error)
2135 goto err;
2136
76f0f772
TL		 2137 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2138
2139 /* At least earlycon won't survive without deferred idle */
2140 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT |
2141 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2142 schedule_delayed_work(&ddata->idle_work, 3000);
2143 } else {
2144 pm_runtime_put(&pdev->dev);
2145 }
0eecc636 2146
5062236e
TL		 2147 if (!of_get_available_child_count(ddata->dev->of_node))
2148 reset_control_assert(ddata->rsts);
2149
0eecc636
TL		 2150 return 0;
2151
2152err:
0eecc636
TL		 2153 pm_runtime_put_sync(&pdev->dev);
2154 pm_runtime_disable(&pdev->dev);
2155unprepare:
2156 sysc_unprepare(ddata);
2157
2158 return error;
2159}
2160
684be5a4
TL		 2161static int sysc_remove(struct platform_device *pdev)
2162{
2163 struct sysc *ddata = platform_get_drvdata(pdev);
2164 int error;
2165
76f0f772
TL		 2166 cancel_delayed_work_sync(&ddata->idle_work);
2167
684be5a4
TL		 2168 error = pm_runtime_get_sync(ddata->dev);
2169 if (error < 0) {
2170 pm_runtime_put_noidle(ddata->dev);
2171 pm_runtime_disable(ddata->dev);
2172 goto unprepare;
2173 }
2174
2175 of_platform_depopulate(&pdev->dev);
2176
684be5a4
TL		 2177 pm_runtime_put_sync(&pdev->dev);
2178 pm_runtime_disable(&pdev->dev);
5062236e 2179 reset_control_assert(ddata->rsts);
684be5a4
TL		 2180
2181unprepare:
2182 sysc_unprepare(ddata);
2183
2184 return 0;
2185}
2186
0eecc636 2187static const struct of_device_id sysc_match[] = {
70a65240
TL		 2188 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2189 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2190 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2191 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2192 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2193 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2194 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2195 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2196 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2197 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2198 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 2199 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 2200 { .compatible = "ti,sysc-usb-host-fs",
2201 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 2202 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
0eecc636
TL		 2203 { },
2204};
2205MODULE_DEVICE_TABLE(of, sysc_match);
2206
2207static struct platform_driver sysc_driver = {
2208 .probe = sysc_probe,
684be5a4 2209 .remove = sysc_remove,
0eecc636
TL		 2210 .driver = {
2211 .name = "ti-sysc",
2212 .of_match_table = sysc_match,
2213 .pm = &sysc_pm_ops,
2214 },
2215};
2c355ff6
TL		 2216
2217static int __init sysc_init(void)
2218{
2219 bus_register_notifier(&platform_bus_type, &sysc_nb);
2220
2221 return platform_driver_register(&sysc_driver);
2222}
2223module_init(sysc_init);
2224
2225static void __exit sysc_exit(void)
2226{
2227 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2228 platform_driver_unregister(&sysc_driver);
2229}
2230module_exit(sysc_exit);
0eecc636
TL		 2231
2232MODULE_DESCRIPTION("TI sysc interconnect target driver");
2233MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)