Commit | Line | Data |
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54d66222 | 1 | // SPDX-License-Identifier: GPL-2.0 |
0eecc636 TL |
2 | /* |
3 | * ti-sysc.c - Texas Instruments sysc interconnect target driver | |
0eecc636 TL |
4 | */ |
5 | ||
6 | #include <linux/io.h> | |
7 | #include <linux/clk.h> | |
2c355ff6 | 8 | #include <linux/clkdev.h> |
9d881361 | 9 | #include <linux/cpu_pm.h> |
a885f0fe | 10 | #include <linux/delay.h> |
feaa8bae | 11 | #include <linux/list.h> |
0eecc636 TL |
12 | #include <linux/module.h> |
13 | #include <linux/platform_device.h> | |
a885f0fe | 14 | #include <linux/pm_domain.h> |
0eecc636 | 15 | #include <linux/pm_runtime.h> |
5062236e | 16 | #include <linux/reset.h> |
0eecc636 TL |
17 | #include <linux/of_address.h> |
18 | #include <linux/of_platform.h> | |
2c355ff6 | 19 | #include <linux/slab.h> |
feaa8bae | 20 | #include <linux/sys_soc.h> |
b3e94318 | 21 | #include <linux/timekeeping.h> |
596e7955 | 22 | #include <linux/iopoll.h> |
2c355ff6 | 23 | |
70a65240 TL |
24 | #include <linux/platform_data/ti-sysc.h> |
25 | ||
26 | #include <dt-bindings/bus/ti-sysc.h> | |
0eecc636 | 27 | |
feaa8bae TL |
28 | #define DIS_ISP BIT(2) |
29 | #define DIS_IVA BIT(1) | |
30 | #define DIS_SGX BIT(0) | |
31 | ||
32 | #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } | |
33 | ||
e4a8fc05 | 34 | #define MAX_MODULE_SOFTRESET_WAIT 10000 |
596e7955 | 35 | |
feaa8bae TL |
36 | enum sysc_soc { |
37 | SOC_UNKNOWN, | |
38 | SOC_2420, | |
39 | SOC_2430, | |
40 | SOC_3430, | |
11729caa | 41 | SOC_AM35, |
feaa8bae TL |
42 | SOC_3630, |
43 | SOC_4430, | |
44 | SOC_4460, | |
45 | SOC_4470, | |
46 | SOC_5430, | |
47 | SOC_AM3, | |
48 | SOC_AM4, | |
49 | SOC_DRA7, | |
50 | }; | |
51 | ||
52 | struct sysc_address { | |
53 | unsigned long base; | |
54 | struct list_head node; | |
55 | }; | |
56 | ||
9d881361 TL |
57 | struct sysc_module { |
58 | struct sysc *ddata; | |
59 | struct list_head node; | |
60 | }; | |
61 | ||
feaa8bae TL |
62 | struct sysc_soc_info { |
63 | unsigned long general_purpose:1; | |
64 | enum sysc_soc soc; | |
9d881361 | 65 | struct mutex list_lock; /* disabled and restored modules list lock */ |
feaa8bae | 66 | struct list_head disabled_modules; |
9d881361 TL |
67 | struct list_head restored_modules; |
68 | struct notifier_block nb; | |
feaa8bae | 69 | }; |
0eecc636 TL |
70 | |
71 | enum sysc_clocks { | |
72 | SYSC_FCK, | |
73 | SYSC_ICK, | |
09dfe581 TL |
74 | SYSC_OPTFCK0, |
75 | SYSC_OPTFCK1, | |
76 | SYSC_OPTFCK2, | |
77 | SYSC_OPTFCK3, | |
78 | SYSC_OPTFCK4, | |
79 | SYSC_OPTFCK5, | |
80 | SYSC_OPTFCK6, | |
81 | SYSC_OPTFCK7, | |
0eecc636 TL |
82 | SYSC_MAX_CLOCKS, |
83 | }; | |
84 | ||
feaa8bae TL |
85 | static struct sysc_soc_info *sysc_soc; |
86 | static const char * const reg_names[] = { "rev", "sysc", "syss", }; | |
a54275f4 TL |
87 | static const char * const clock_names[SYSC_MAX_CLOCKS] = { |
88 | "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", | |
89 | "opt5", "opt6", "opt7", | |
90 | }; | |
0eecc636 | 91 | |
c5a2de97 TL |
92 | #define SYSC_IDLEMODE_MASK 3 |
93 | #define SYSC_CLOCKACTIVITY_MASK 3 | |
94 | ||
0eecc636 TL |
95 | /** |
96 | * struct sysc - TI sysc interconnect target module registers and capabilities | |
97 | * @dev: struct device pointer | |
98 | * @module_pa: physical address of the interconnect target module | |
99 | * @module_size: size of the interconnect target module | |
100 | * @module_va: virtual address of the interconnect target module | |
101 | * @offsets: register offsets from module base | |
b58056da | 102 | * @mdata: ti-sysc to hwmod translation data for a module |
0eecc636 | 103 | * @clocks: clocks used by the interconnect target module |
09dfe581 TL |
104 | * @clock_roles: clock role names for the found clocks |
105 | * @nr_clocks: number of clocks used by the interconnect target module | |
b58056da | 106 | * @rsts: resets used by the interconnect target module |
0eecc636 | 107 | * @legacy_mode: configured for legacy mode if set |
70a65240 TL |
108 | * @cap: interconnect target module capabilities |
109 | * @cfg: interconnect target module configuration | |
b58056da | 110 | * @cookie: data used by legacy platform callbacks |
566a9b05 TL |
111 | * @name: name if available |
112 | * @revision: interconnect target module revision | |
40a4f49c | 113 | * @sysconfig: saved sysconfig register value |
3ff340e2 | 114 | * @reserved: target module is reserved and already in use |
b58056da | 115 | * @enabled: sysc runtime enabled status |
62020f23 | 116 | * @needs_resume: runtime resume needed on resume from suspend |
b58056da SA |
117 | * @child_needs_resume: runtime resume needed for child on resume from suspend |
118 | * @disable_on_idle: status flag used for disabling modules with resets | |
119 | * @idle_work: work structure used to perform delayed idle on a module | |
e64c021f TL |
120 | * @pre_reset_quirk: module specific pre-reset quirk |
121 | * @post_reset_quirk: module specific post-reset quirk | |
4e23be47 | 122 | * @reset_done_quirk: module specific reset done quirk |
d7f563db | 123 | * @module_enable_quirk: module specific enable quirk |
c7d8669f | 124 | * @module_disable_quirk: module specific disable quirk |
e8639e1c TL |
125 | * @module_unlock_quirk: module specific sysconfig unlock quirk |
126 | * @module_lock_quirk: module specific sysconfig lock quirk | |
0eecc636 TL |
127 | */ |
128 | struct sysc { | |
129 | struct device *dev; | |
130 | u64 module_pa; | |
131 | u32 module_size; | |
132 | void __iomem *module_va; | |
133 | int offsets[SYSC_MAX_REGS]; | |
a3e92e7b | 134 | struct ti_sysc_module_data *mdata; |
09dfe581 TL |
135 | struct clk **clocks; |
136 | const char **clock_roles; | |
137 | int nr_clocks; | |
5062236e | 138 | struct reset_control *rsts; |
0eecc636 | 139 | const char *legacy_mode; |
70a65240 TL |
140 | const struct sysc_capabilities *cap; |
141 | struct sysc_config cfg; | |
ef70b0bd | 142 | struct ti_sysc_cookie cookie; |
566a9b05 TL |
143 | const char *name; |
144 | u32 revision; | |
95ec14fa | 145 | u32 sysconfig; |
3ff340e2 | 146 | unsigned int reserved:1; |
8383e259 TL |
147 | unsigned int enabled:1; |
148 | unsigned int needs_resume:1; | |
149 | unsigned int child_needs_resume:1; | |
76f0f772 | 150 | struct delayed_work idle_work; |
e64c021f TL |
151 | void (*pre_reset_quirk)(struct sysc *sysc); |
152 | void (*post_reset_quirk)(struct sysc *sysc); | |
4e23be47 | 153 | void (*reset_done_quirk)(struct sysc *sysc); |
d7f563db | 154 | void (*module_enable_quirk)(struct sysc *sysc); |
c7d8669f | 155 | void (*module_disable_quirk)(struct sysc *sysc); |
e8639e1c TL |
156 | void (*module_unlock_quirk)(struct sysc *sysc); |
157 | void (*module_lock_quirk)(struct sysc *sysc); | |
0eecc636 TL |
158 | }; |
159 | ||
4014c08b TL |
160 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
161 | bool is_child); | |
6a52bc2b | 162 | static int sysc_reset(struct sysc *ddata); |
4014c08b | 163 | |
b7182b42 | 164 | static void sysc_write(struct sysc *ddata, int offset, u32 value) |
596e7955 | 165 | { |
5aa91295 TL |
166 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { |
167 | writew_relaxed(value & 0xffff, ddata->module_va + offset); | |
168 | ||
169 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
170 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
171 | offset == ddata->offsets[SYSC_REVISION]) { | |
172 | u16 hi = value >> 16; | |
173 | ||
174 | writew_relaxed(hi, ddata->module_va + offset + 4); | |
175 | } | |
176 | ||
177 | return; | |
178 | } | |
179 | ||
596e7955 FA |
180 | writel_relaxed(value, ddata->module_va + offset); |
181 | } | |
182 | ||
566a9b05 TL |
183 | static u32 sysc_read(struct sysc *ddata, int offset) |
184 | { | |
185 | if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { | |
186 | u32 val; | |
187 | ||
188 | val = readw_relaxed(ddata->module_va + offset); | |
5aa91295 TL |
189 | |
190 | /* Only i2c revision has LO and HI register with stride of 4 */ | |
191 | if (ddata->offsets[SYSC_REVISION] >= 0 && | |
192 | offset == ddata->offsets[SYSC_REVISION]) { | |
193 | u16 tmp = readw_relaxed(ddata->module_va + offset + 4); | |
194 | ||
195 | val |= tmp << 16; | |
196 | } | |
566a9b05 TL |
197 | |
198 | return val; | |
199 | } | |
200 | ||
201 | return readl_relaxed(ddata->module_va + offset); | |
202 | } | |
203 | ||
09dfe581 TL |
204 | static bool sysc_opt_clks_needed(struct sysc *ddata) |
205 | { | |
206 | return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); | |
207 | } | |
208 | ||
0eecc636 TL |
209 | static u32 sysc_read_revision(struct sysc *ddata) |
210 | { | |
566a9b05 TL |
211 | int offset = ddata->offsets[SYSC_REVISION]; |
212 | ||
213 | if (offset < 0) | |
214 | return 0; | |
215 | ||
216 | return sysc_read(ddata, offset); | |
0eecc636 TL |
217 | } |
218 | ||
e0db94fe TL |
219 | static u32 sysc_read_sysconfig(struct sysc *ddata) |
220 | { | |
221 | int offset = ddata->offsets[SYSC_SYSCONFIG]; | |
222 | ||
223 | if (offset < 0) | |
224 | return 0; | |
225 | ||
226 | return sysc_read(ddata, offset); | |
227 | } | |
228 | ||
229 | static u32 sysc_read_sysstatus(struct sysc *ddata) | |
230 | { | |
231 | int offset = ddata->offsets[SYSC_SYSSTATUS]; | |
232 | ||
233 | if (offset < 0) | |
234 | return 0; | |
235 | ||
236 | return sysc_read(ddata, offset); | |
237 | } | |
238 | ||
b3e94318 | 239 | static int sysc_poll_reset_sysstatus(struct sysc *ddata) |
d46f9fbe | 240 | { |
b3e94318 TL |
241 | int error, retries; |
242 | u32 syss_done, rstval; | |
d46f9fbe TL |
243 | |
244 | if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) | |
245 | syss_done = 0; | |
246 | else | |
247 | syss_done = ddata->cfg.syss_mask; | |
248 | ||
b3e94318 | 249 | if (likely(!timekeeping_suspended)) { |
9f911392 TL |
250 | error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, |
251 | rstval, (rstval & ddata->cfg.syss_mask) == | |
252 | syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); | |
b3e94318 TL |
253 | } else { |
254 | retries = MAX_MODULE_SOFTRESET_WAIT; | |
255 | while (retries--) { | |
256 | rstval = sysc_read_sysstatus(ddata); | |
257 | if ((rstval & ddata->cfg.syss_mask) == syss_done) | |
258 | return 0; | |
259 | udelay(2); /* Account for udelay flakeyness */ | |
260 | } | |
261 | error = -ETIMEDOUT; | |
262 | } | |
263 | ||
264 | return error; | |
265 | } | |
266 | ||
267 | static int sysc_poll_reset_sysconfig(struct sysc *ddata) | |
268 | { | |
269 | int error, retries; | |
270 | u32 sysc_mask, rstval; | |
d46f9fbe | 271 | |
b3e94318 | 272 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); |
d46f9fbe | 273 | |
b3e94318 | 274 | if (likely(!timekeeping_suspended)) { |
9f911392 TL |
275 | error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, |
276 | rstval, !(rstval & sysc_mask), | |
277 | 100, MAX_MODULE_SOFTRESET_WAIT); | |
b3e94318 TL |
278 | } else { |
279 | retries = MAX_MODULE_SOFTRESET_WAIT; | |
280 | while (retries--) { | |
281 | rstval = sysc_read_sysconfig(ddata); | |
282 | if (!(rstval & sysc_mask)) | |
283 | return 0; | |
284 | udelay(2); /* Account for udelay flakeyness */ | |
285 | } | |
286 | error = -ETIMEDOUT; | |
d46f9fbe TL |
287 | } |
288 | ||
289 | return error; | |
290 | } | |
291 | ||
b3e94318 TL |
292 | /* Poll on reset status */ |
293 | static int sysc_wait_softreset(struct sysc *ddata) | |
294 | { | |
295 | int syss_offset, error = 0; | |
296 | ||
297 | if (ddata->cap->regbits->srst_shift < 0) | |
298 | return 0; | |
299 | ||
300 | syss_offset = ddata->offsets[SYSC_SYSSTATUS]; | |
301 | ||
302 | if (syss_offset >= 0) | |
303 | error = sysc_poll_reset_sysstatus(ddata); | |
304 | else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) | |
305 | error = sysc_poll_reset_sysconfig(ddata); | |
306 | ||
307 | return error; | |
308 | } | |
309 | ||
a54275f4 TL |
310 | static int sysc_add_named_clock_from_child(struct sysc *ddata, |
311 | const char *name, | |
312 | const char *optfck_name) | |
313 | { | |
314 | struct device_node *np = ddata->dev->of_node; | |
315 | struct device_node *child; | |
316 | struct clk_lookup *cl; | |
317 | struct clk *clock; | |
318 | const char *n; | |
319 | ||
320 | if (name) | |
321 | n = name; | |
322 | else | |
323 | n = optfck_name; | |
324 | ||
325 | /* Does the clock alias already exist? */ | |
326 | clock = of_clk_get_by_name(np, n); | |
327 | if (!IS_ERR(clock)) { | |
328 | clk_put(clock); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | child = of_get_next_available_child(np, NULL); | |
334 | if (!child) | |
335 | return -ENODEV; | |
336 | ||
337 | clock = devm_get_clk_from_child(ddata->dev, child, name); | |
338 | if (IS_ERR(clock)) | |
339 | return PTR_ERR(clock); | |
340 | ||
341 | /* | |
342 | * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID | |
343 | * limit for clk_get(). If cl ever needs to be freed, it should be done | |
344 | * with clkdev_drop(). | |
345 | */ | |
d995d3d0 | 346 | cl = kzalloc(sizeof(*cl), GFP_KERNEL); |
a54275f4 TL |
347 | if (!cl) |
348 | return -ENOMEM; | |
349 | ||
350 | cl->con_id = n; | |
351 | cl->dev_id = dev_name(ddata->dev); | |
352 | cl->clk = clock; | |
353 | clkdev_add(cl); | |
354 | ||
355 | clk_put(clock); | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) | |
361 | { | |
362 | const char *optfck_name; | |
363 | int error, index; | |
364 | ||
365 | if (ddata->nr_clocks < SYSC_OPTFCK0) | |
366 | index = SYSC_OPTFCK0; | |
367 | else | |
368 | index = ddata->nr_clocks; | |
369 | ||
370 | if (name) | |
371 | optfck_name = name; | |
372 | else | |
373 | optfck_name = clock_names[index]; | |
374 | ||
375 | error = sysc_add_named_clock_from_child(ddata, name, optfck_name); | |
376 | if (error) | |
377 | return error; | |
378 | ||
379 | ddata->clock_roles[index] = optfck_name; | |
380 | ddata->nr_clocks++; | |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
09dfe581 | 385 | static int sysc_get_one_clock(struct sysc *ddata, const char *name) |
0eecc636 | 386 | { |
09dfe581 TL |
387 | int error, i, index = -ENODEV; |
388 | ||
389 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
390 | index = SYSC_FCK; | |
391 | else if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
392 | index = SYSC_ICK; | |
393 | ||
394 | if (index < 0) { | |
395 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
c97c8620 | 396 | if (!ddata->clocks[i]) { |
09dfe581 TL |
397 | index = i; |
398 | break; | |
399 | } | |
400 | } | |
401 | } | |
0eecc636 | 402 | |
09dfe581 TL |
403 | if (index < 0) { |
404 | dev_err(ddata->dev, "clock %s not added\n", name); | |
405 | return index; | |
0eecc636 | 406 | } |
0eecc636 TL |
407 | |
408 | ddata->clocks[index] = devm_clk_get(ddata->dev, name); | |
409 | if (IS_ERR(ddata->clocks[index])) { | |
0eecc636 TL |
410 | dev_err(ddata->dev, "clock get error for %s: %li\n", |
411 | name, PTR_ERR(ddata->clocks[index])); | |
412 | ||
413 | return PTR_ERR(ddata->clocks[index]); | |
414 | } | |
415 | ||
416 | error = clk_prepare(ddata->clocks[index]); | |
417 | if (error) { | |
418 | dev_err(ddata->dev, "clock prepare error for %s: %i\n", | |
419 | name, error); | |
420 | ||
421 | return error; | |
422 | } | |
423 | ||
424 | return 0; | |
425 | } | |
426 | ||
427 | static int sysc_get_clocks(struct sysc *ddata) | |
428 | { | |
09dfe581 TL |
429 | struct device_node *np = ddata->dev->of_node; |
430 | struct property *prop; | |
431 | const char *name; | |
432 | int nr_fck = 0, nr_ick = 0, i, error = 0; | |
433 | ||
20749051 | 434 | ddata->clock_roles = devm_kcalloc(ddata->dev, |
09dfe581 | 435 | SYSC_MAX_CLOCKS, |
20749051 | 436 | sizeof(*ddata->clock_roles), |
09dfe581 TL |
437 | GFP_KERNEL); |
438 | if (!ddata->clock_roles) | |
439 | return -ENOMEM; | |
440 | ||
441 | of_property_for_each_string(np, "clock-names", prop, name) { | |
442 | if (!strncmp(clock_names[SYSC_FCK], name, 3)) | |
443 | nr_fck++; | |
444 | if (!strncmp(clock_names[SYSC_ICK], name, 3)) | |
445 | nr_ick++; | |
446 | ddata->clock_roles[ddata->nr_clocks] = name; | |
447 | ddata->nr_clocks++; | |
448 | } | |
449 | ||
450 | if (ddata->nr_clocks < 1) | |
451 | return 0; | |
452 | ||
a54275f4 TL |
453 | if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { |
454 | error = sysc_init_ext_opt_clock(ddata, NULL); | |
455 | if (error) | |
456 | return error; | |
457 | } | |
458 | ||
09dfe581 TL |
459 | if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { |
460 | dev_err(ddata->dev, "too many clocks for %pOF\n", np); | |
461 | ||
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | if (nr_fck > 1 || nr_ick > 1) { | |
466 | dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); | |
0eecc636 | 467 | |
09dfe581 TL |
468 | return -EINVAL; |
469 | } | |
470 | ||
2c81f0f6 TL |
471 | /* Always add a slot for main clocks fck and ick even if unused */ |
472 | if (!nr_fck) | |
473 | ddata->nr_clocks++; | |
474 | if (!nr_ick) | |
475 | ddata->nr_clocks++; | |
476 | ||
20749051 KC |
477 | ddata->clocks = devm_kcalloc(ddata->dev, |
478 | ddata->nr_clocks, sizeof(*ddata->clocks), | |
09dfe581 TL |
479 | GFP_KERNEL); |
480 | if (!ddata->clocks) | |
481 | return -ENOMEM; | |
482 | ||
7b4f8ac2 TL |
483 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
484 | const char *name = ddata->clock_roles[i]; | |
485 | ||
486 | if (!name) | |
487 | continue; | |
488 | ||
489 | error = sysc_get_one_clock(ddata, name); | |
2783d063 | 490 | if (error) |
0eecc636 TL |
491 | return error; |
492 | } | |
493 | ||
494 | return 0; | |
495 | } | |
496 | ||
d878970f TL |
497 | static int sysc_enable_main_clocks(struct sysc *ddata) |
498 | { | |
499 | struct clk *clock; | |
500 | int i, error; | |
501 | ||
502 | if (!ddata->clocks) | |
503 | return 0; | |
504 | ||
505 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
506 | clock = ddata->clocks[i]; | |
507 | ||
508 | /* Main clocks may not have ick */ | |
509 | if (IS_ERR_OR_NULL(clock)) | |
510 | continue; | |
511 | ||
512 | error = clk_enable(clock); | |
513 | if (error) | |
514 | goto err_disable; | |
515 | } | |
516 | ||
517 | return 0; | |
518 | ||
519 | err_disable: | |
520 | for (i--; i >= 0; i--) { | |
521 | clock = ddata->clocks[i]; | |
522 | ||
523 | /* Main clocks may not have ick */ | |
524 | if (IS_ERR_OR_NULL(clock)) | |
525 | continue; | |
526 | ||
527 | clk_disable(clock); | |
528 | } | |
529 | ||
530 | return error; | |
531 | } | |
532 | ||
533 | static void sysc_disable_main_clocks(struct sysc *ddata) | |
534 | { | |
535 | struct clk *clock; | |
536 | int i; | |
537 | ||
538 | if (!ddata->clocks) | |
539 | return; | |
540 | ||
541 | for (i = 0; i < SYSC_OPTFCK0; i++) { | |
542 | clock = ddata->clocks[i]; | |
543 | if (IS_ERR_OR_NULL(clock)) | |
544 | continue; | |
545 | ||
546 | clk_disable(clock); | |
547 | } | |
548 | } | |
549 | ||
550 | static int sysc_enable_opt_clocks(struct sysc *ddata) | |
551 | { | |
552 | struct clk *clock; | |
553 | int i, error; | |
554 | ||
2c81f0f6 | 555 | if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) |
d878970f TL |
556 | return 0; |
557 | ||
558 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
559 | clock = ddata->clocks[i]; | |
560 | ||
561 | /* Assume no holes for opt clocks */ | |
562 | if (IS_ERR_OR_NULL(clock)) | |
563 | return 0; | |
564 | ||
565 | error = clk_enable(clock); | |
566 | if (error) | |
567 | goto err_disable; | |
568 | } | |
569 | ||
570 | return 0; | |
571 | ||
572 | err_disable: | |
573 | for (i--; i >= 0; i--) { | |
574 | clock = ddata->clocks[i]; | |
575 | if (IS_ERR_OR_NULL(clock)) | |
576 | continue; | |
577 | ||
578 | clk_disable(clock); | |
579 | } | |
580 | ||
581 | return error; | |
582 | } | |
583 | ||
584 | static void sysc_disable_opt_clocks(struct sysc *ddata) | |
585 | { | |
586 | struct clk *clock; | |
587 | int i; | |
588 | ||
2c81f0f6 | 589 | if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) |
d878970f TL |
590 | return; |
591 | ||
592 | for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { | |
593 | clock = ddata->clocks[i]; | |
594 | ||
595 | /* Assume no holes for opt clocks */ | |
596 | if (IS_ERR_OR_NULL(clock)) | |
597 | return; | |
598 | ||
599 | clk_disable(clock); | |
600 | } | |
601 | } | |
602 | ||
2b2f7def TL |
603 | static void sysc_clkdm_deny_idle(struct sysc *ddata) |
604 | { | |
605 | struct ti_sysc_platform_data *pdata; | |
606 | ||
94f63457 | 607 | if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) |
2b2f7def TL |
608 | return; |
609 | ||
610 | pdata = dev_get_platdata(ddata->dev); | |
611 | if (pdata && pdata->clkdm_deny_idle) | |
612 | pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); | |
613 | } | |
614 | ||
615 | static void sysc_clkdm_allow_idle(struct sysc *ddata) | |
616 | { | |
617 | struct ti_sysc_platform_data *pdata; | |
618 | ||
94f63457 | 619 | if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) |
2b2f7def TL |
620 | return; |
621 | ||
622 | pdata = dev_get_platdata(ddata->dev); | |
623 | if (pdata && pdata->clkdm_allow_idle) | |
624 | pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); | |
625 | } | |
626 | ||
5062236e | 627 | /** |
b11c1ea1 | 628 | * sysc_init_resets - init rstctrl reset line if configured |
5062236e TL |
629 | * @ddata: device driver data |
630 | * | |
b11c1ea1 | 631 | * See sysc_rstctrl_reset_deassert(). |
5062236e TL |
632 | */ |
633 | static int sysc_init_resets(struct sysc *ddata) | |
634 | { | |
5062236e | 635 | ddata->rsts = |
bb88b86c | 636 | devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); |
5062236e | 637 | |
3f2c4205 | 638 | return PTR_ERR_OR_ZERO(ddata->rsts); |
5062236e TL |
639 | } |
640 | ||
0eecc636 TL |
641 | /** |
642 | * sysc_parse_and_check_child_range - parses module IO region from ranges | |
643 | * @ddata: device driver data | |
644 | * | |
645 | * In general we only need rev, syss, and sysc registers and not the whole | |
646 | * module range. But we do want the offsets for these registers from the | |
647 | * module base. This allows us to check them against the legacy hwmod | |
648 | * platform data. Let's also check the ranges are configured properly. | |
649 | */ | |
650 | static int sysc_parse_and_check_child_range(struct sysc *ddata) | |
651 | { | |
652 | struct device_node *np = ddata->dev->of_node; | |
41e4f807 RH |
653 | struct of_range_parser parser; |
654 | struct of_range range; | |
655 | int error; | |
0eecc636 | 656 | |
41e4f807 | 657 | error = of_range_parser_init(&parser, np); |
0eecc636 | 658 | if (error) |
41e4f807 | 659 | return error; |
0eecc636 | 660 | |
41e4f807 RH |
661 | for_each_of_range(&parser, &range) { |
662 | ddata->module_pa = range.cpu_addr; | |
663 | ddata->module_size = range.size; | |
664 | break; | |
0eecc636 TL |
665 | } |
666 | ||
0eecc636 TL |
667 | return 0; |
668 | } | |
669 | ||
4700a007 TL |
670 | /* Interconnect instances to probe before l4_per instances */ |
671 | static struct resource early_bus_ranges[] = { | |
672 | /* am3/4 l4_wkup */ | |
673 | { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, }, | |
674 | /* omap4/5 and dra7 l4_cfg */ | |
675 | { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, }, | |
676 | /* omap4 l4_wkup */ | |
677 | { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, }, | |
678 | /* omap5 and dra7 l4_wkup without dra7 dcan segment */ | |
679 | { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, }, | |
680 | }; | |
681 | ||
682 | static atomic_t sysc_defer = ATOMIC_INIT(10); | |
683 | ||
684 | /** | |
685 | * sysc_defer_non_critical - defer non_critical interconnect probing | |
686 | * @ddata: device driver data | |
687 | * | |
688 | * We want to probe l4_cfg and l4_wkup interconnect instances before any | |
689 | * l4_per instances as l4_per instances depend on resources on l4_cfg and | |
690 | * l4_wkup interconnects. | |
691 | */ | |
692 | static int sysc_defer_non_critical(struct sysc *ddata) | |
693 | { | |
694 | struct resource *res; | |
695 | int i; | |
696 | ||
697 | if (!atomic_read(&sysc_defer)) | |
698 | return 0; | |
699 | ||
700 | for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) { | |
701 | res = &early_bus_ranges[i]; | |
702 | if (ddata->module_pa >= res->start && | |
703 | ddata->module_pa <= res->end) { | |
704 | atomic_set(&sysc_defer, 0); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | } | |
709 | ||
710 | atomic_dec_if_positive(&sysc_defer); | |
711 | ||
712 | return -EPROBE_DEFER; | |
713 | } | |
714 | ||
3bb37c8e TL |
715 | static struct device_node *stdout_path; |
716 | ||
717 | static void sysc_init_stdout_path(struct sysc *ddata) | |
718 | { | |
719 | struct device_node *np = NULL; | |
720 | const char *uart; | |
721 | ||
722 | if (IS_ERR(stdout_path)) | |
723 | return; | |
724 | ||
725 | if (stdout_path) | |
726 | return; | |
727 | ||
728 | np = of_find_node_by_path("/chosen"); | |
729 | if (!np) | |
730 | goto err; | |
731 | ||
732 | uart = of_get_property(np, "stdout-path", NULL); | |
733 | if (!uart) | |
734 | goto err; | |
735 | ||
736 | np = of_find_node_by_path(uart); | |
737 | if (!np) | |
738 | goto err; | |
739 | ||
740 | stdout_path = np; | |
741 | ||
742 | return; | |
743 | ||
744 | err: | |
745 | stdout_path = ERR_PTR(-ENODEV); | |
746 | } | |
747 | ||
748 | static void sysc_check_quirk_stdout(struct sysc *ddata, | |
749 | struct device_node *np) | |
750 | { | |
751 | sysc_init_stdout_path(ddata); | |
752 | if (np != stdout_path) | |
753 | return; | |
754 | ||
755 | ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | | |
756 | SYSC_QUIRK_NO_RESET_ON_INIT; | |
757 | } | |
758 | ||
0eecc636 TL |
759 | /** |
760 | * sysc_check_one_child - check child configuration | |
761 | * @ddata: device driver data | |
762 | * @np: child device node | |
763 | * | |
764 | * Let's avoid messy situations where we have new interconnect target | |
765 | * node but children have "ti,hwmods". These belong to the interconnect | |
766 | * target node and are managed by this driver. | |
767 | */ | |
c6e78d70 ND |
768 | static void sysc_check_one_child(struct sysc *ddata, |
769 | struct device_node *np) | |
0eecc636 TL |
770 | { |
771 | const char *name; | |
772 | ||
773 | name = of_get_property(np, "ti,hwmods", NULL); | |
7320fd32 | 774 | if (name && !of_device_is_compatible(np, "ti,sysc")) |
0eecc636 TL |
775 | dev_warn(ddata->dev, "really a child ti,hwmods property?"); |
776 | ||
3bb37c8e | 777 | sysc_check_quirk_stdout(ddata, np); |
4014c08b | 778 | sysc_parse_dts_quirks(ddata, np, true); |
0eecc636 TL |
779 | } |
780 | ||
c6e78d70 | 781 | static void sysc_check_children(struct sysc *ddata) |
0eecc636 TL |
782 | { |
783 | struct device_node *child; | |
0eecc636 | 784 | |
c6e78d70 ND |
785 | for_each_child_of_node(ddata->dev->of_node, child) |
786 | sysc_check_one_child(ddata, child); | |
0eecc636 TL |
787 | } |
788 | ||
a7199e2b TL |
789 | /* |
790 | * So far only I2C uses 16-bit read access with clockactivity with revision | |
791 | * in two registers with stride of 4. We can detect this based on the rev | |
792 | * register size to configure things far enough to be able to properly read | |
793 | * the revision register. | |
794 | */ | |
795 | static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) | |
796 | { | |
dd57ac1e | 797 | if (resource_size(res) == 8) |
a7199e2b | 798 | ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; |
a7199e2b TL |
799 | } |
800 | ||
0eecc636 TL |
801 | /** |
802 | * sysc_parse_one - parses the interconnect target module registers | |
803 | * @ddata: device driver data | |
804 | * @reg: register to parse | |
805 | */ | |
806 | static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) | |
807 | { | |
808 | struct resource *res; | |
809 | const char *name; | |
810 | ||
811 | switch (reg) { | |
812 | case SYSC_REVISION: | |
813 | case SYSC_SYSCONFIG: | |
814 | case SYSC_SYSSTATUS: | |
815 | name = reg_names[reg]; | |
816 | break; | |
817 | default: | |
818 | return -EINVAL; | |
819 | } | |
820 | ||
821 | res = platform_get_resource_byname(to_platform_device(ddata->dev), | |
822 | IORESOURCE_MEM, name); | |
823 | if (!res) { | |
0eecc636 TL |
824 | ddata->offsets[reg] = -ENODEV; |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
829 | ddata->offsets[reg] = res->start - ddata->module_pa; | |
a7199e2b TL |
830 | if (reg == SYSC_REVISION) |
831 | sysc_check_quirk_16bit(ddata, res); | |
0eecc636 TL |
832 | |
833 | return 0; | |
834 | } | |
835 | ||
836 | static int sysc_parse_registers(struct sysc *ddata) | |
837 | { | |
838 | int i, error; | |
839 | ||
840 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
841 | error = sysc_parse_one(ddata, i); | |
842 | if (error) | |
843 | return error; | |
844 | } | |
845 | ||
846 | return 0; | |
847 | } | |
848 | ||
849 | /** | |
850 | * sysc_check_registers - check for misconfigured register overlaps | |
851 | * @ddata: device driver data | |
852 | */ | |
853 | static int sysc_check_registers(struct sysc *ddata) | |
854 | { | |
855 | int i, j, nr_regs = 0, nr_matches = 0; | |
856 | ||
857 | for (i = 0; i < SYSC_MAX_REGS; i++) { | |
858 | if (ddata->offsets[i] < 0) | |
859 | continue; | |
860 | ||
861 | if (ddata->offsets[i] > (ddata->module_size - 4)) { | |
862 | dev_err(ddata->dev, "register outside module range"); | |
863 | ||
864 | return -EINVAL; | |
865 | } | |
866 | ||
867 | for (j = 0; j < SYSC_MAX_REGS; j++) { | |
868 | if (ddata->offsets[j] < 0) | |
869 | continue; | |
870 | ||
871 | if (ddata->offsets[i] == ddata->offsets[j]) | |
872 | nr_matches++; | |
873 | } | |
874 | nr_regs++; | |
875 | } | |
876 | ||
0eecc636 TL |
877 | if (nr_matches > nr_regs) { |
878 | dev_err(ddata->dev, "overlapping registers: (%i/%i)", | |
879 | nr_regs, nr_matches); | |
880 | ||
881 | return -EINVAL; | |
882 | } | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | /** | |
4e001853 | 888 | * sysc_ioremap - ioremap register space for the interconnect target module |
0ef8e3bb | 889 | * @ddata: device driver data |
0eecc636 TL |
890 | * |
891 | * Note that the interconnect target module registers can be anywhere | |
0ef8e3bb TL |
892 | * within the interconnect target module range. For example, SGX has |
893 | * them at offset 0x1fc00 in the 32MB module address space. And cpsw | |
894 | * has them at offset 0x1200 in the CPSW_WR child. Usually the | |
b79ad230 | 895 | * interconnect target module registers are at the beginning of |
0ef8e3bb | 896 | * the module range though. |
0eecc636 TL |
897 | */ |
898 | static int sysc_ioremap(struct sysc *ddata) | |
899 | { | |
0ef8e3bb | 900 | int size; |
0eecc636 | 901 | |
e4f50c8d TL |
902 | if (ddata->offsets[SYSC_REVISION] < 0 && |
903 | ddata->offsets[SYSC_SYSCONFIG] < 0 && | |
904 | ddata->offsets[SYSC_SYSSTATUS] < 0) { | |
905 | size = ddata->module_size; | |
906 | } else { | |
907 | size = max3(ddata->offsets[SYSC_REVISION], | |
908 | ddata->offsets[SYSC_SYSCONFIG], | |
909 | ddata->offsets[SYSC_SYSSTATUS]); | |
0ef8e3bb | 910 | |
4e23be47 TL |
911 | if (size < SZ_1K) |
912 | size = SZ_1K; | |
913 | ||
e4f50c8d | 914 | if ((size + sizeof(u32)) > ddata->module_size) |
4e23be47 | 915 | size = ddata->module_size; |
e4f50c8d | 916 | } |
0eecc636 TL |
917 | |
918 | ddata->module_va = devm_ioremap(ddata->dev, | |
919 | ddata->module_pa, | |
0ef8e3bb | 920 | size + sizeof(u32)); |
0eecc636 TL |
921 | if (!ddata->module_va) |
922 | return -EIO; | |
923 | ||
924 | return 0; | |
925 | } | |
926 | ||
927 | /** | |
928 | * sysc_map_and_check_registers - ioremap and check device registers | |
929 | * @ddata: device driver data | |
930 | */ | |
931 | static int sysc_map_and_check_registers(struct sysc *ddata) | |
932 | { | |
2928135c | 933 | struct device_node *np = ddata->dev->of_node; |
0eecc636 TL |
934 | int error; |
935 | ||
936 | error = sysc_parse_and_check_child_range(ddata); | |
937 | if (error) | |
938 | return error; | |
939 | ||
4700a007 TL |
940 | error = sysc_defer_non_critical(ddata); |
941 | if (error) | |
942 | return error; | |
943 | ||
c6e78d70 | 944 | sysc_check_children(ddata); |
0eecc636 | 945 | |
2ee1bdd3 | 946 | if (!of_property_present(np, "reg")) |
7bad5af8 TL |
947 | return 0; |
948 | ||
0eecc636 TL |
949 | error = sysc_parse_registers(ddata); |
950 | if (error) | |
951 | return error; | |
952 | ||
953 | error = sysc_ioremap(ddata); | |
954 | if (error) | |
955 | return error; | |
956 | ||
957 | error = sysc_check_registers(ddata); | |
958 | if (error) | |
959 | return error; | |
960 | ||
961 | return 0; | |
962 | } | |
963 | ||
964 | /** | |
965 | * sysc_show_rev - read and show interconnect target module revision | |
966 | * @bufp: buffer to print the information to | |
967 | * @ddata: device driver data | |
968 | */ | |
969 | static int sysc_show_rev(char *bufp, struct sysc *ddata) | |
970 | { | |
566a9b05 | 971 | int len; |
0eecc636 TL |
972 | |
973 | if (ddata->offsets[SYSC_REVISION] < 0) | |
974 | return sprintf(bufp, ":NA"); | |
975 | ||
566a9b05 | 976 | len = sprintf(bufp, ":%08x", ddata->revision); |
0eecc636 TL |
977 | |
978 | return len; | |
979 | } | |
980 | ||
981 | static int sysc_show_reg(struct sysc *ddata, | |
982 | char *bufp, enum sysc_registers reg) | |
983 | { | |
984 | if (ddata->offsets[reg] < 0) | |
985 | return sprintf(bufp, ":NA"); | |
986 | ||
987 | return sprintf(bufp, ":%x", ddata->offsets[reg]); | |
988 | } | |
989 | ||
a885f0fe TL |
990 | static int sysc_show_name(char *bufp, struct sysc *ddata) |
991 | { | |
992 | if (!ddata->name) | |
993 | return 0; | |
994 | ||
995 | return sprintf(bufp, ":%s", ddata->name); | |
996 | } | |
997 | ||
0eecc636 TL |
998 | /** |
999 | * sysc_show_registers - show information about interconnect target module | |
1000 | * @ddata: device driver data | |
1001 | */ | |
1002 | static void sysc_show_registers(struct sysc *ddata) | |
1003 | { | |
1004 | char buf[128]; | |
1005 | char *bufp = buf; | |
1006 | int i; | |
1007 | ||
1008 | for (i = 0; i < SYSC_MAX_REGS; i++) | |
1009 | bufp += sysc_show_reg(ddata, bufp, i); | |
1010 | ||
1011 | bufp += sysc_show_rev(bufp, ddata); | |
a885f0fe | 1012 | bufp += sysc_show_name(bufp, ddata); |
0eecc636 TL |
1013 | |
1014 | dev_dbg(ddata->dev, "%llx:%x%s\n", | |
1015 | ddata->module_pa, ddata->module_size, | |
1016 | buf); | |
1017 | } | |
1018 | ||
e8639e1c TL |
1019 | /** |
1020 | * sysc_write_sysconfig - handle sysconfig quirks for register write | |
1021 | * @ddata: device driver data | |
1022 | * @value: register value | |
1023 | */ | |
1024 | static void sysc_write_sysconfig(struct sysc *ddata, u32 value) | |
1025 | { | |
1026 | if (ddata->module_unlock_quirk) | |
1027 | ddata->module_unlock_quirk(ddata); | |
1028 | ||
1029 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); | |
1030 | ||
1031 | if (ddata->module_lock_quirk) | |
1032 | ddata->module_lock_quirk(ddata); | |
1033 | } | |
1034 | ||
d59b6056 | 1035 | #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) |
ae9ae12e | 1036 | #define SYSC_CLOCACT_ICK 2 |
d59b6056 | 1037 | |
2b2f7def | 1038 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ |
d59b6056 RQ |
1039 | static int sysc_enable_module(struct device *dev) |
1040 | { | |
1041 | struct sysc *ddata; | |
1042 | const struct sysc_regbits *regbits; | |
1043 | u32 reg, idlemodes, best_mode; | |
d46f9fbe | 1044 | int error; |
d59b6056 RQ |
1045 | |
1046 | ddata = dev_get_drvdata(dev); | |
d46f9fbe TL |
1047 | |
1048 | /* | |
1049 | * Some modules like DSS reset automatically on idle. Enable optional | |
1050 | * reset clocks and wait for OCP softreset to complete. | |
1051 | */ | |
1052 | if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { | |
1053 | error = sysc_enable_opt_clocks(ddata); | |
1054 | if (error) { | |
1055 | dev_err(ddata->dev, | |
1056 | "Optional clocks failed for enable: %i\n", | |
1057 | error); | |
1058 | return error; | |
1059 | } | |
1060 | } | |
e275d210 TL |
1061 | /* |
1062 | * Some modules like i2c and hdq1w have unusable reset status unless | |
1063 | * the module reset quirk is enabled. Skip status check on enable. | |
1064 | */ | |
1065 | if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { | |
1066 | error = sysc_wait_softreset(ddata); | |
1067 | if (error) | |
1068 | dev_warn(ddata->dev, "OCP softreset timed out\n"); | |
1069 | } | |
d46f9fbe TL |
1070 | if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) |
1071 | sysc_disable_opt_clocks(ddata); | |
1072 | ||
1073 | /* | |
1074 | * Some subsystem private interconnects, like DSS top level module, | |
1075 | * need only the automatic OCP softreset handling with no sysconfig | |
1076 | * register bits to configure. | |
1077 | */ | |
d59b6056 RQ |
1078 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) |
1079 | return 0; | |
1080 | ||
d59b6056 RQ |
1081 | regbits = ddata->cap->regbits; |
1082 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1083 | ||
08b91dd6 TL |
1084 | /* |
1085 | * Set CLOCKACTIVITY, we only use it for ick. And we only configure it | |
1086 | * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware | |
1087 | * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. | |
1088 | */ | |
ae9ae12e | 1089 | if (regbits->clkact_shift >= 0 && |
08b91dd6 | 1090 | (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) |
ae9ae12e TL |
1091 | reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; |
1092 | ||
d59b6056 RQ |
1093 | /* Set SIDLE mode */ |
1094 | idlemodes = ddata->cfg.sidlemodes; | |
1095 | if (!idlemodes || regbits->sidle_shift < 0) | |
1096 | goto set_midle; | |
1097 | ||
fb685f1c TL |
1098 | if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | |
1099 | SYSC_QUIRK_SWSUP_SIDLE_ACT)) { | |
1100 | best_mode = SYSC_IDLE_NO; | |
e5deb8f7 TL |
1101 | |
1102 | /* Clear WAKEUP */ | |
1103 | if (regbits->enwkup_shift >= 0 && | |
1104 | ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) | |
1105 | reg &= ~BIT(regbits->enwkup_shift); | |
fb685f1c TL |
1106 | } else { |
1107 | best_mode = fls(ddata->cfg.sidlemodes) - 1; | |
1108 | if (best_mode > SYSC_IDLE_MASK) { | |
1109 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
1110 | return -EINVAL; | |
1111 | } | |
6e09f497 TL |
1112 | |
1113 | /* Set WAKEUP */ | |
1114 | if (regbits->enwkup_shift >= 0 && | |
1115 | ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) | |
1116 | reg |= BIT(regbits->enwkup_shift); | |
d59b6056 RQ |
1117 | } |
1118 | ||
1119 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); | |
1120 | reg |= best_mode << regbits->sidle_shift; | |
e8639e1c | 1121 | sysc_write_sysconfig(ddata, reg); |
d59b6056 RQ |
1122 | |
1123 | set_midle: | |
1124 | /* Set MIDLE mode */ | |
1125 | idlemodes = ddata->cfg.midlemodes; | |
1126 | if (!idlemodes || regbits->midle_shift < 0) | |
eec26555 | 1127 | goto set_autoidle; |
d59b6056 RQ |
1128 | |
1129 | best_mode = fls(ddata->cfg.midlemodes) - 1; | |
1130 | if (best_mode > SYSC_IDLE_MASK) { | |
1131 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
95ec14fa TL |
1132 | error = -EINVAL; |
1133 | goto save_context; | |
d59b6056 RQ |
1134 | } |
1135 | ||
03856e92 TL |
1136 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) |
1137 | best_mode = SYSC_IDLE_NO; | |
1138 | ||
d59b6056 RQ |
1139 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); |
1140 | reg |= best_mode << regbits->midle_shift; | |
e8639e1c | 1141 | sysc_write_sysconfig(ddata, reg); |
d59b6056 | 1142 | |
eec26555 TL |
1143 | set_autoidle: |
1144 | /* Autoidle bit must enabled separately if available */ | |
1145 | if (regbits->autoidle_shift >= 0 && | |
1146 | ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { | |
1147 | reg |= 1 << regbits->autoidle_shift; | |
e8639e1c | 1148 | sysc_write_sysconfig(ddata, reg); |
eec26555 TL |
1149 | } |
1150 | ||
95ec14fa TL |
1151 | error = 0; |
1152 | ||
1153 | save_context: | |
1154 | /* Save context and flush posted write */ | |
1155 | ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
5ce8aee8 | 1156 | |
d7f563db TL |
1157 | if (ddata->module_enable_quirk) |
1158 | ddata->module_enable_quirk(ddata); | |
1159 | ||
95ec14fa | 1160 | return error; |
d59b6056 RQ |
1161 | } |
1162 | ||
1163 | static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) | |
1164 | { | |
1165 | if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) | |
1166 | *best_mode = SYSC_IDLE_SMART_WKUP; | |
1167 | else if (idlemodes & BIT(SYSC_IDLE_SMART)) | |
1168 | *best_mode = SYSC_IDLE_SMART; | |
6ee8241d | 1169 | else if (idlemodes & BIT(SYSC_IDLE_FORCE)) |
d59b6056 RQ |
1170 | *best_mode = SYSC_IDLE_FORCE; |
1171 | else | |
1172 | return -EINVAL; | |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
2b2f7def | 1177 | /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ |
d59b6056 RQ |
1178 | static int sysc_disable_module(struct device *dev) |
1179 | { | |
1180 | struct sysc *ddata; | |
1181 | const struct sysc_regbits *regbits; | |
1182 | u32 reg, idlemodes, best_mode; | |
1183 | int ret; | |
1184 | ||
1185 | ddata = dev_get_drvdata(dev); | |
1186 | if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) | |
1187 | return 0; | |
1188 | ||
c7d8669f TL |
1189 | if (ddata->module_disable_quirk) |
1190 | ddata->module_disable_quirk(ddata); | |
1191 | ||
d59b6056 RQ |
1192 | regbits = ddata->cap->regbits; |
1193 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1194 | ||
1195 | /* Set MIDLE mode */ | |
1196 | idlemodes = ddata->cfg.midlemodes; | |
1197 | if (!idlemodes || regbits->midle_shift < 0) | |
1198 | goto set_sidle; | |
1199 | ||
1200 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
1201 | if (ret) { | |
1202 | dev_err(dev, "%s: invalid midlemode\n", __func__); | |
1203 | return ret; | |
1204 | } | |
1205 | ||
93c60483 TL |
1206 | if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || |
1207 | ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) | |
03856e92 TL |
1208 | best_mode = SYSC_IDLE_FORCE; |
1209 | ||
d59b6056 RQ |
1210 | reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); |
1211 | reg |= best_mode << regbits->midle_shift; | |
e8639e1c | 1212 | sysc_write_sysconfig(ddata, reg); |
d59b6056 RQ |
1213 | |
1214 | set_sidle: | |
1215 | /* Set SIDLE mode */ | |
1216 | idlemodes = ddata->cfg.sidlemodes; | |
95ec14fa TL |
1217 | if (!idlemodes || regbits->sidle_shift < 0) { |
1218 | ret = 0; | |
1219 | goto save_context; | |
1220 | } | |
d59b6056 | 1221 | |
fb685f1c TL |
1222 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { |
1223 | best_mode = SYSC_IDLE_FORCE; | |
1224 | } else { | |
1225 | ret = sysc_best_idle_mode(idlemodes, &best_mode); | |
1226 | if (ret) { | |
1227 | dev_err(dev, "%s: invalid sidlemode\n", __func__); | |
95ec14fa TL |
1228 | ret = -EINVAL; |
1229 | goto save_context; | |
fb685f1c | 1230 | } |
d59b6056 RQ |
1231 | } |
1232 | ||
e5deb8f7 TL |
1233 | if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) { |
1234 | /* Set WAKEUP */ | |
1235 | if (regbits->enwkup_shift >= 0 && | |
1236 | ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) | |
1237 | reg |= BIT(regbits->enwkup_shift); | |
1238 | } | |
1239 | ||
d59b6056 RQ |
1240 | reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); |
1241 | reg |= best_mode << regbits->sidle_shift; | |
eec26555 TL |
1242 | if (regbits->autoidle_shift >= 0 && |
1243 | ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) | |
1244 | reg |= 1 << regbits->autoidle_shift; | |
e8639e1c | 1245 | sysc_write_sysconfig(ddata, reg); |
d59b6056 | 1246 | |
95ec14fa | 1247 | ret = 0; |
5ce8aee8 | 1248 | |
95ec14fa TL |
1249 | save_context: |
1250 | /* Save context and flush posted write */ | |
1251 | ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1252 | ||
1253 | return ret; | |
d59b6056 RQ |
1254 | } |
1255 | ||
ff43728c TL |
1256 | static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, |
1257 | struct sysc *ddata) | |
1258 | { | |
1259 | struct ti_sysc_platform_data *pdata; | |
1260 | int error; | |
1261 | ||
1262 | pdata = dev_get_platdata(ddata->dev); | |
1263 | if (!pdata) | |
1264 | return 0; | |
1265 | ||
1266 | if (!pdata->idle_module) | |
1267 | return -ENODEV; | |
1268 | ||
1269 | error = pdata->idle_module(dev, &ddata->cookie); | |
1270 | if (error) | |
1271 | dev_err(dev, "%s: could not idle: %i\n", | |
1272 | __func__, error); | |
1273 | ||
4345f0dc | 1274 | reset_control_assert(ddata->rsts); |
8383e259 | 1275 | |
ff43728c TL |
1276 | return 0; |
1277 | } | |
1278 | ||
1279 | static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, | |
1280 | struct sysc *ddata) | |
0eecc636 | 1281 | { |
ef70b0bd | 1282 | struct ti_sysc_platform_data *pdata; |
ff43728c TL |
1283 | int error; |
1284 | ||
1285 | pdata = dev_get_platdata(ddata->dev); | |
1286 | if (!pdata) | |
1287 | return 0; | |
1288 | ||
1289 | if (!pdata->enable_module) | |
1290 | return -ENODEV; | |
1291 | ||
1292 | error = pdata->enable_module(dev, &ddata->cookie); | |
1293 | if (error) | |
1294 | dev_err(dev, "%s: could not enable: %i\n", | |
1295 | __func__, error); | |
1296 | ||
bf59ebbe TK |
1297 | reset_control_deassert(ddata->rsts); |
1298 | ||
ff43728c TL |
1299 | return 0; |
1300 | } | |
1301 | ||
1302 | static int __maybe_unused sysc_runtime_suspend(struct device *dev) | |
1303 | { | |
0eecc636 | 1304 | struct sysc *ddata; |
d878970f | 1305 | int error = 0; |
0eecc636 TL |
1306 | |
1307 | ddata = dev_get_drvdata(dev); | |
1308 | ||
ef70b0bd | 1309 | if (!ddata->enabled) |
0eecc636 TL |
1310 | return 0; |
1311 | ||
2b2f7def TL |
1312 | sysc_clkdm_deny_idle(ddata); |
1313 | ||
ef70b0bd | 1314 | if (ddata->legacy_mode) { |
ff43728c | 1315 | error = sysc_runtime_suspend_legacy(dev, ddata); |
93de83a2 | 1316 | if (error) |
2b2f7def | 1317 | goto err_allow_idle; |
d59b6056 RQ |
1318 | } else { |
1319 | error = sysc_disable_module(dev); | |
1320 | if (error) | |
2b2f7def | 1321 | goto err_allow_idle; |
ef70b0bd TL |
1322 | } |
1323 | ||
d878970f | 1324 | sysc_disable_main_clocks(ddata); |
09dfe581 | 1325 | |
d878970f TL |
1326 | if (sysc_opt_clks_needed(ddata)) |
1327 | sysc_disable_opt_clocks(ddata); | |
0eecc636 | 1328 | |
ef70b0bd TL |
1329 | ddata->enabled = false; |
1330 | ||
2b2f7def | 1331 | err_allow_idle: |
b6036314 TK |
1332 | sysc_clkdm_allow_idle(ddata); |
1333 | ||
4097c9a6 TL |
1334 | reset_control_assert(ddata->rsts); |
1335 | ||
ef70b0bd | 1336 | return error; |
0eecc636 TL |
1337 | } |
1338 | ||
a4a5d493 | 1339 | static int __maybe_unused sysc_runtime_resume(struct device *dev) |
0eecc636 TL |
1340 | { |
1341 | struct sysc *ddata; | |
d878970f | 1342 | int error = 0; |
0eecc636 TL |
1343 | |
1344 | ddata = dev_get_drvdata(dev); | |
1345 | ||
ef70b0bd | 1346 | if (ddata->enabled) |
0eecc636 TL |
1347 | return 0; |
1348 | ||
8383e259 | 1349 | |
2b2f7def TL |
1350 | sysc_clkdm_deny_idle(ddata); |
1351 | ||
d878970f TL |
1352 | if (sysc_opt_clks_needed(ddata)) { |
1353 | error = sysc_enable_opt_clocks(ddata); | |
0eecc636 | 1354 | if (error) |
2b2f7def | 1355 | goto err_allow_idle; |
0eecc636 TL |
1356 | } |
1357 | ||
d878970f TL |
1358 | error = sysc_enable_main_clocks(ddata); |
1359 | if (error) | |
93de83a2 TL |
1360 | goto err_opt_clocks; |
1361 | ||
bf59ebbe TK |
1362 | reset_control_deassert(ddata->rsts); |
1363 | ||
93de83a2 TL |
1364 | if (ddata->legacy_mode) { |
1365 | error = sysc_runtime_resume_legacy(dev, ddata); | |
1366 | if (error) | |
1367 | goto err_main_clocks; | |
d59b6056 RQ |
1368 | } else { |
1369 | error = sysc_enable_module(dev); | |
1370 | if (error) | |
1371 | goto err_main_clocks; | |
93de83a2 | 1372 | } |
d878970f | 1373 | |
ef70b0bd TL |
1374 | ddata->enabled = true; |
1375 | ||
2b2f7def TL |
1376 | sysc_clkdm_allow_idle(ddata); |
1377 | ||
d878970f TL |
1378 | return 0; |
1379 | ||
1380 | err_main_clocks: | |
93de83a2 TL |
1381 | sysc_disable_main_clocks(ddata); |
1382 | err_opt_clocks: | |
d878970f TL |
1383 | if (sysc_opt_clks_needed(ddata)) |
1384 | sysc_disable_opt_clocks(ddata); | |
2b2f7def TL |
1385 | err_allow_idle: |
1386 | sysc_clkdm_allow_idle(ddata); | |
d878970f | 1387 | |
ef70b0bd | 1388 | return error; |
0eecc636 TL |
1389 | } |
1390 | ||
95ec14fa TL |
1391 | /* |
1392 | * Checks if device context was lost. Assumes the sysconfig register value | |
1393 | * after lost context is different from the configured value. Only works for | |
1394 | * enabled devices. | |
1395 | * | |
1396 | * Eventually we may want to also add support to using the context lost | |
1397 | * registers that some SoCs have. | |
1398 | */ | |
1399 | static int sysc_check_context(struct sysc *ddata) | |
1400 | { | |
1401 | u32 reg; | |
1402 | ||
1403 | if (!ddata->enabled) | |
1404 | return -ENODATA; | |
1405 | ||
1406 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
1407 | if (reg == ddata->sysconfig) | |
1408 | return 0; | |
1409 | ||
1410 | return -EACCES; | |
1411 | } | |
1412 | ||
4d7b324e TL |
1413 | static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) |
1414 | { | |
1415 | struct device *dev = ddata->dev; | |
1416 | int error; | |
1417 | ||
4d7b324e | 1418 | if (ddata->enabled) { |
95ec14fa TL |
1419 | /* Nothing to do if enabled and context not lost */ |
1420 | error = sysc_check_context(ddata); | |
1421 | if (!error) | |
1422 | return 0; | |
1423 | ||
1424 | /* Disable target module if it is enabled */ | |
4d7b324e TL |
1425 | error = sysc_runtime_suspend(dev); |
1426 | if (error) | |
1427 | dev_warn(dev, "reinit suspend failed: %i\n", error); | |
1428 | } | |
1429 | ||
1430 | /* Enable target module */ | |
1431 | error = sysc_runtime_resume(dev); | |
1432 | if (error) | |
1433 | dev_warn(dev, "reinit resume failed: %i\n", error); | |
1434 | ||
6a52bc2b TL |
1435 | /* Some modules like am335x gpmc need reset and restore of sysconfig */ |
1436 | if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) { | |
1437 | error = sysc_reset(ddata); | |
1438 | if (error) | |
1439 | dev_warn(dev, "reinit reset failed: %i\n", error); | |
1440 | ||
1441 | sysc_write_sysconfig(ddata, ddata->sysconfig); | |
1442 | } | |
1443 | ||
4d7b324e TL |
1444 | if (leave_enabled) |
1445 | return error; | |
1446 | ||
1447 | /* Disable target module if no leave_enabled was set */ | |
1448 | error = sysc_runtime_suspend(dev); | |
1449 | if (error) | |
1450 | dev_warn(dev, "reinit suspend failed: %i\n", error); | |
1451 | ||
1452 | return error; | |
1453 | } | |
1454 | ||
f5e80203 | 1455 | static int __maybe_unused sysc_noirq_suspend(struct device *dev) |
62020f23 TL |
1456 | { |
1457 | struct sysc *ddata; | |
1458 | ||
1459 | ddata = dev_get_drvdata(dev); | |
1460 | ||
a55de412 TL |
1461 | if (ddata->cfg.quirks & |
1462 | (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) | |
e7420c2d TL |
1463 | return 0; |
1464 | ||
4d7b324e TL |
1465 | if (!ddata->enabled) |
1466 | return 0; | |
1467 | ||
1468 | ddata->needs_resume = 1; | |
1469 | ||
1470 | return sysc_runtime_suspend(dev); | |
62020f23 TL |
1471 | } |
1472 | ||
f5e80203 | 1473 | static int __maybe_unused sysc_noirq_resume(struct device *dev) |
62020f23 TL |
1474 | { |
1475 | struct sysc *ddata; | |
4d7b324e | 1476 | int error = 0; |
62020f23 TL |
1477 | |
1478 | ddata = dev_get_drvdata(dev); | |
e7420c2d | 1479 | |
a55de412 TL |
1480 | if (ddata->cfg.quirks & |
1481 | (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) | |
e7420c2d TL |
1482 | return 0; |
1483 | ||
4d7b324e TL |
1484 | if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { |
1485 | error = sysc_reinit_module(ddata, ddata->needs_resume); | |
1486 | if (error) | |
1487 | dev_warn(dev, "noirq_resume failed: %i\n", error); | |
1488 | } else if (ddata->needs_resume) { | |
1489 | error = sysc_runtime_resume(dev); | |
1490 | if (error) | |
1491 | dev_warn(dev, "noirq_resume failed: %i\n", error); | |
1492 | } | |
1493 | ||
1494 | ddata->needs_resume = 0; | |
1495 | ||
1496 | return error; | |
0eecc636 TL |
1497 | } |
1498 | ||
1499 | static const struct dev_pm_ops sysc_pm_ops = { | |
e7420c2d | 1500 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) |
0eecc636 TL |
1501 | SET_RUNTIME_PM_OPS(sysc_runtime_suspend, |
1502 | sysc_runtime_resume, | |
1503 | NULL) | |
1504 | }; | |
1505 | ||
a885f0fe TL |
1506 | /* Module revision register based quirks */ |
1507 | struct sysc_revision_quirk { | |
1508 | const char *name; | |
1509 | u32 base; | |
1510 | int rev_offset; | |
1511 | int sysc_offset; | |
1512 | int syss_offset; | |
1513 | u32 revision; | |
1514 | u32 revision_mask; | |
1515 | u32 quirks; | |
1516 | }; | |
1517 | ||
1518 | #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ | |
1519 | optrev_val, optrevmask, optquirkmask) \ | |
1520 | { \ | |
1521 | .name = (optname), \ | |
1522 | .base = (optbase), \ | |
1523 | .rev_offset = (optrev), \ | |
1524 | .sysc_offset = (optsysc), \ | |
1525 | .syss_offset = (optsyss), \ | |
1526 | .revision = (optrev_val), \ | |
1527 | .revision_mask = (optrevmask), \ | |
1528 | .quirks = (optquirkmask), \ | |
1529 | } | |
1530 | ||
1531 | static const struct sysc_revision_quirk sysc_revision_quirks[] = { | |
1532 | /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ | |
b6a53c4c | 1533 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, |
e5deb8f7 | 1534 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
a885f0fe | 1535 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, |
e5deb8f7 | 1536 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
d708bb14 | 1537 | /* Uarts on omap4 and later */ |
b82beef5 | 1538 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, |
e5deb8f7 | 1539 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
b82beef5 | 1540 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, |
e5deb8f7 | 1541 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
03a711d3 | 1542 | SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, |
e5deb8f7 | 1543 | SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), |
7e27e5d0 | 1544 | |
a54275f4 | 1545 | /* Quirks that need to be set based on the module address */ |
590e15c7 | 1546 | SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, |
a54275f4 TL |
1547 | SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | |
1548 | SYSC_QUIRK_SWSUP_SIDLE), | |
1549 | ||
4e23be47 | 1550 | /* Quirks that need to be set based on detected module */ |
590e15c7 | 1551 | SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, |
020003f7 | 1552 | SYSC_MODULE_QUIRK_AESS), |
b13a270a TL |
1553 | /* Errata i893 handling for dra7 dcan1 and 2 */ |
1554 | SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, | |
1555 | SYSC_QUIRK_CLKDM_NOAUTO), | |
590e15c7 | 1556 | SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, |
94f63457 | 1557 | SYSC_QUIRK_CLKDM_NOAUTO), |
77dfece2 | 1558 | SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, |
7324a7a0 | 1559 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), |
77dfece2 | 1560 | SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, |
7324a7a0 | 1561 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), |
77dfece2 | 1562 | SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, |
7324a7a0 | 1563 | SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), |
590e15c7 | 1564 | SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, |
94f63457 | 1565 | SYSC_QUIRK_CLKDM_NOAUTO), |
590e15c7 | 1566 | SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, |
94f63457 | 1567 | SYSC_QUIRK_CLKDM_NOAUTO), |
1b99c1ee TL |
1568 | SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, |
1569 | SYSC_QUIRK_OPT_CLKS_IN_RESET), | |
cfeeea60 | 1570 | SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, |
d48dca51 | 1571 | SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST | |
cfeeea60 | 1572 | SYSC_QUIRK_GPMC_DEBUG), |
77dfece2 TL |
1573 | SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, |
1574 | SYSC_QUIRK_OPT_CLKS_NEEDED), | |
4e23be47 | 1575 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, |
e275d210 | 1576 | SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1577 | SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, |
e275d210 | 1578 | SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1579 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, |
e275d210 | 1580 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1581 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, |
e275d210 | 1582 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1583 | SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, |
e275d210 | 1584 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
4e23be47 | 1585 | SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, |
e275d210 | 1586 | SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), |
590e15c7 TL |
1587 | SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), |
1588 | SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, | |
d7f563db | 1589 | SYSC_MODULE_QUIRK_SGX), |
aef067e8 TL |
1590 | SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, |
1591 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
8122dc58 PU |
1592 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, |
1593 | SYSC_QUIRK_SWSUP_SIDLE), | |
e8639e1c TL |
1594 | SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, |
1595 | SYSC_MODULE_QUIRK_RTC_UNLOCK), | |
25bfaaa7 TL |
1596 | SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, |
1597 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1598 | SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, | |
1599 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
db8e712e TL |
1600 | SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, |
1601 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
4254632d TL |
1602 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, |
1603 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
1604 | SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, | |
1605 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), | |
41c3b936 TL |
1606 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033, |
1607 | 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | | |
1608 | SYSC_MODULE_QUIRK_OTG), | |
1609 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040, | |
1610 | 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | | |
1611 | SYSC_MODULE_QUIRK_OTG), | |
03856e92 | 1612 | SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, |
5c99fa73 TL |
1613 | 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | |
1614 | SYSC_MODULE_QUIRK_OTG), | |
590e15c7 | 1615 | SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, |
4d7b324e | 1616 | SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | |
9067839f | 1617 | SYSC_QUIRK_REINIT_ON_CTX_LOST), |
4e23be47 TL |
1618 | SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, |
1619 | SYSC_MODULE_QUIRK_WDT), | |
b2745d92 SA |
1620 | /* PRUSS on am3, am4 and am5 */ |
1621 | SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, | |
1622 | SYSC_MODULE_QUIRK_PRUSS), | |
c7d8669f TL |
1623 | /* Watchdog on am3 and am4 */ |
1624 | SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, | |
1625 | SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), | |
4e23be47 | 1626 | |
dc4c85ea | 1627 | #ifdef DEBUG |
590e15c7 TL |
1628 | SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), |
1629 | SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), | |
1630 | SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), | |
1631 | SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1ba30693 | 1632 | SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, |
23731eac | 1633 | 0xffff00f0, 0), |
590e15c7 TL |
1634 | SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), |
1635 | SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), | |
77dfece2 TL |
1636 | SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), |
1637 | SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1638 | SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), | |
590e15c7 | 1639 | SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), |
77dfece2 TL |
1640 | SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), |
1641 | SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), | |
1642 | SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
1643 | SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), | |
590e15c7 | 1644 | SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), |
7edd00f7 TL |
1645 | SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), |
1646 | SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
f2dc0755 TL |
1647 | SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), |
1648 | SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), | |
1649 | SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), | |
590e15c7 TL |
1650 | SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), |
1651 | SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), | |
1652 | SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), | |
77dfece2 | 1653 | SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), |
dc4c85ea | 1654 | SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), |
590e15c7 | 1655 | SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), |
f2dc0755 | 1656 | SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), |
590e15c7 TL |
1657 | SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), |
1658 | SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), | |
1659 | SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), | |
1ba30693 | 1660 | SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), |
590e15c7 TL |
1661 | SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), |
1662 | SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), | |
c6eb4af3 | 1663 | SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), |
590e15c7 TL |
1664 | SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), |
1665 | SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), | |
1666 | SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), | |
f2dc0755 TL |
1667 | SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), |
1668 | SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), | |
590e15c7 TL |
1669 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), |
1670 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), | |
1671 | SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), | |
77dfece2 TL |
1672 | SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), |
1673 | SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), | |
590e15c7 TL |
1674 | SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), |
1675 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), | |
1676 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), | |
1677 | SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), | |
1678 | SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), | |
1679 | SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), | |
1ba30693 | 1680 | SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), |
40d9f912 | 1681 | SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), |
ce7b4323 | 1682 | SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0), |
590e15c7 TL |
1683 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), |
1684 | SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), | |
ed4520d6 TL |
1685 | SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), |
1686 | SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), | |
590e15c7 TL |
1687 | SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), |
1688 | SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), | |
1a542811 TL |
1689 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), |
1690 | SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), | |
1691 | /* Some timers on omap4 and later */ | |
1692 | SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), | |
1693 | SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), | |
1694 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), | |
1695 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), | |
590e15c7 | 1696 | SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), |
25bfaaa7 | 1697 | SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), |
dc4c85ea | 1698 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), |
f0106700 | 1699 | SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), |
77dfece2 | 1700 | SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), |
590e15c7 | 1701 | SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), |
dc4c85ea | 1702 | #endif |
a885f0fe TL |
1703 | }; |
1704 | ||
42b9c5c9 TL |
1705 | /* |
1706 | * Early quirks based on module base and register offsets only that are | |
1707 | * needed before the module revision can be read | |
1708 | */ | |
1709 | static void sysc_init_early_quirks(struct sysc *ddata) | |
1710 | { | |
1711 | const struct sysc_revision_quirk *q; | |
1712 | int i; | |
1713 | ||
1714 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1715 | q = &sysc_revision_quirks[i]; | |
1716 | ||
1717 | if (!q->base) | |
1718 | continue; | |
1719 | ||
1720 | if (q->base != ddata->module_pa) | |
1721 | continue; | |
1722 | ||
590e15c7 | 1723 | if (q->rev_offset != ddata->offsets[SYSC_REVISION]) |
42b9c5c9 TL |
1724 | continue; |
1725 | ||
590e15c7 | 1726 | if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) |
42b9c5c9 TL |
1727 | continue; |
1728 | ||
590e15c7 | 1729 | if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) |
42b9c5c9 TL |
1730 | continue; |
1731 | ||
1732 | ddata->name = q->name; | |
1733 | ddata->cfg.quirks |= q->quirks; | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | /* Quirks that also consider the revision register value */ | |
a885f0fe TL |
1738 | static void sysc_init_revision_quirks(struct sysc *ddata) |
1739 | { | |
1740 | const struct sysc_revision_quirk *q; | |
1741 | int i; | |
1742 | ||
1743 | for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { | |
1744 | q = &sysc_revision_quirks[i]; | |
1745 | ||
1746 | if (q->base && q->base != ddata->module_pa) | |
1747 | continue; | |
1748 | ||
590e15c7 | 1749 | if (q->rev_offset != ddata->offsets[SYSC_REVISION]) |
a885f0fe TL |
1750 | continue; |
1751 | ||
590e15c7 | 1752 | if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) |
a885f0fe TL |
1753 | continue; |
1754 | ||
590e15c7 | 1755 | if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) |
a885f0fe TL |
1756 | continue; |
1757 | ||
1758 | if (q->revision == ddata->revision || | |
1759 | (q->revision & q->revision_mask) == | |
1760 | (ddata->revision & q->revision_mask)) { | |
1761 | ddata->name = q->name; | |
1762 | ddata->cfg.quirks |= q->quirks; | |
1763 | } | |
1764 | } | |
1765 | } | |
1766 | ||
7324a7a0 TL |
1767 | /* |
1768 | * DSS needs dispc outputs disabled to reset modules. Returns mask of | |
1769 | * enabled DSS interrupts. Eventually we may be able to do this on | |
1770 | * dispc init rather than top-level DSS init. | |
1771 | */ | |
1772 | static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, | |
1773 | bool disable) | |
1774 | { | |
1775 | bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; | |
1776 | const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); | |
1777 | int manager_count; | |
085bc0e5 | 1778 | bool framedonetv_irq = true; |
7324a7a0 TL |
1779 | u32 val, irq_mask = 0; |
1780 | ||
1781 | switch (sysc_soc->soc) { | |
1782 | case SOC_2420 ... SOC_3630: | |
1783 | manager_count = 2; | |
1784 | framedonetv_irq = false; | |
1785 | break; | |
1786 | case SOC_4430 ... SOC_4470: | |
1787 | manager_count = 3; | |
1788 | break; | |
1789 | case SOC_5430: | |
1790 | case SOC_DRA7: | |
1791 | manager_count = 4; | |
1792 | break; | |
1793 | case SOC_AM4: | |
1794 | manager_count = 1; | |
085bc0e5 | 1795 | framedonetv_irq = false; |
7324a7a0 TL |
1796 | break; |
1797 | case SOC_UNKNOWN: | |
1798 | default: | |
1799 | return 0; | |
52fbb5aa | 1800 | } |
7324a7a0 TL |
1801 | |
1802 | /* Remap the whole module range to be able to reset dispc outputs */ | |
1803 | devm_iounmap(ddata->dev, ddata->module_va); | |
1804 | ddata->module_va = devm_ioremap(ddata->dev, | |
1805 | ddata->module_pa, | |
1806 | ddata->module_size); | |
1807 | if (!ddata->module_va) | |
1808 | return -EIO; | |
1809 | ||
f620596f | 1810 | /* DISP_CONTROL, shut down lcd and digit on disable if enabled */ |
7324a7a0 TL |
1811 | val = sysc_read(ddata, dispc_offset + 0x40); |
1812 | lcd_en = val & lcd_en_mask; | |
1813 | digit_en = val & digit_en_mask; | |
1814 | if (lcd_en) | |
1815 | irq_mask |= BIT(0); /* FRAMEDONE */ | |
1816 | if (digit_en) { | |
1817 | if (framedonetv_irq) | |
1818 | irq_mask |= BIT(24); /* FRAMEDONETV */ | |
1819 | else | |
1820 | irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ | |
1821 | } | |
f620596f | 1822 | if (disable && (lcd_en || digit_en)) |
7324a7a0 TL |
1823 | sysc_write(ddata, dispc_offset + 0x40, |
1824 | val & ~(lcd_en_mask | digit_en_mask)); | |
1825 | ||
1826 | if (manager_count <= 2) | |
1827 | return irq_mask; | |
1828 | ||
1829 | /* DISPC_CONTROL2 */ | |
1830 | val = sysc_read(ddata, dispc_offset + 0x238); | |
1831 | lcd2_en = val & lcd_en_mask; | |
1832 | if (lcd2_en) | |
1833 | irq_mask |= BIT(22); /* FRAMEDONE2 */ | |
1834 | if (disable && lcd2_en) | |
1835 | sysc_write(ddata, dispc_offset + 0x238, | |
1836 | val & ~lcd_en_mask); | |
1837 | ||
1838 | if (manager_count <= 3) | |
1839 | return irq_mask; | |
1840 | ||
1841 | /* DISPC_CONTROL3 */ | |
1842 | val = sysc_read(ddata, dispc_offset + 0x848); | |
1843 | lcd3_en = val & lcd_en_mask; | |
1844 | if (lcd3_en) | |
1845 | irq_mask |= BIT(30); /* FRAMEDONE3 */ | |
1846 | if (disable && lcd3_en) | |
1847 | sysc_write(ddata, dispc_offset + 0x848, | |
1848 | val & ~lcd_en_mask); | |
1849 | ||
1850 | return irq_mask; | |
1851 | } | |
1852 | ||
1853 | /* DSS needs child outputs disabled and SDI registers cleared for reset */ | |
1854 | static void sysc_pre_reset_quirk_dss(struct sysc *ddata) | |
1855 | { | |
1856 | const int dispc_offset = 0x1000; | |
1857 | int error; | |
1858 | u32 irq_mask, val; | |
1859 | ||
1860 | /* Get enabled outputs */ | |
1861 | irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); | |
1862 | if (!irq_mask) | |
1863 | return; | |
1864 | ||
1865 | /* Clear IRQSTATUS */ | |
69e60903 | 1866 | sysc_write(ddata, dispc_offset + 0x18, irq_mask); |
7324a7a0 TL |
1867 | |
1868 | /* Disable outputs */ | |
1869 | val = sysc_quirk_dispc(ddata, dispc_offset, true); | |
1870 | ||
1871 | /* Poll IRQSTATUS */ | |
1872 | error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, | |
1873 | val, val != irq_mask, 100, 50); | |
1874 | if (error) | |
1875 | dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", | |
1876 | __func__, val, irq_mask); | |
1877 | ||
11729caa | 1878 | if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) { |
7324a7a0 | 1879 | /* Clear DSS_SDI_CONTROL */ |
69e60903 | 1880 | sysc_write(ddata, 0x44, 0); |
7324a7a0 TL |
1881 | |
1882 | /* Clear DSS_PLL_CONTROL */ | |
69e60903 | 1883 | sysc_write(ddata, 0x48, 0); |
7324a7a0 TL |
1884 | } |
1885 | ||
1886 | /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ | |
69e60903 | 1887 | sysc_write(ddata, 0x40, 0); |
7324a7a0 TL |
1888 | } |
1889 | ||
4e23be47 | 1890 | /* 1-wire needs module's internal clocks enabled for reset */ |
aec551c7 | 1891 | static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) |
4e23be47 TL |
1892 | { |
1893 | int offset = 0x0c; /* HDQ_CTRL_STATUS */ | |
1894 | u16 val; | |
1895 | ||
1896 | val = sysc_read(ddata, offset); | |
1897 | val |= BIT(5); | |
1898 | sysc_write(ddata, offset, val); | |
1899 | } | |
1900 | ||
020003f7 TL |
1901 | /* AESS (Audio Engine SubSystem) needs autogating set after enable */ |
1902 | static void sysc_module_enable_quirk_aess(struct sysc *ddata) | |
1903 | { | |
1904 | int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ | |
1905 | ||
1906 | sysc_write(ddata, offset, 1); | |
1907 | } | |
1908 | ||
e64c021f | 1909 | /* I2C needs to be disabled for reset */ |
4e23be47 TL |
1910 | static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) |
1911 | { | |
1912 | int offset; | |
1913 | u16 val; | |
1914 | ||
1915 | /* I2C_CON, omap2/3 is different from omap4 and later */ | |
1916 | if ((ddata->revision & 0xffffff00) == 0x001f0000) | |
1917 | offset = 0x24; | |
1918 | else | |
1919 | offset = 0xa4; | |
1920 | ||
1921 | /* I2C_EN */ | |
1922 | val = sysc_read(ddata, offset); | |
1923 | if (enable) | |
1924 | val |= BIT(15); | |
1925 | else | |
1926 | val &= ~BIT(15); | |
1927 | sysc_write(ddata, offset, val); | |
1928 | } | |
1929 | ||
e64c021f | 1930 | static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) |
4e23be47 | 1931 | { |
e64c021f | 1932 | sysc_clk_quirk_i2c(ddata, false); |
4e23be47 TL |
1933 | } |
1934 | ||
e64c021f | 1935 | static void sysc_post_reset_quirk_i2c(struct sysc *ddata) |
4e23be47 | 1936 | { |
e64c021f | 1937 | sysc_clk_quirk_i2c(ddata, true); |
4e23be47 TL |
1938 | } |
1939 | ||
e8639e1c TL |
1940 | /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ |
1941 | static void sysc_quirk_rtc(struct sysc *ddata, bool lock) | |
1942 | { | |
1943 | u32 val, kick0_val = 0, kick1_val = 0; | |
1944 | unsigned long flags; | |
1945 | int error; | |
1946 | ||
1947 | if (!lock) { | |
1948 | kick0_val = 0x83e70b13; | |
1949 | kick1_val = 0x95a4f1e0; | |
1950 | } | |
1951 | ||
1952 | local_irq_save(flags); | |
1953 | /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ | |
afe6f1ee TL |
1954 | error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, |
1955 | !(val & BIT(0)), 100, 50); | |
e8639e1c TL |
1956 | if (error) |
1957 | dev_warn(ddata->dev, "rtc busy timeout\n"); | |
1958 | /* Now we have ~15 microseconds to read/write various registers */ | |
1959 | sysc_write(ddata, 0x6c, kick0_val); | |
1960 | sysc_write(ddata, 0x70, kick1_val); | |
1961 | local_irq_restore(flags); | |
1962 | } | |
1963 | ||
1964 | static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) | |
1965 | { | |
1966 | sysc_quirk_rtc(ddata, false); | |
1967 | } | |
1968 | ||
1969 | static void sysc_module_lock_quirk_rtc(struct sysc *ddata) | |
1970 | { | |
1971 | sysc_quirk_rtc(ddata, true); | |
1972 | } | |
1973 | ||
5c99fa73 TL |
1974 | /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */ |
1975 | static void sysc_module_enable_quirk_otg(struct sysc *ddata) | |
1976 | { | |
1977 | int offset = 0x414; /* OTG_FORCESTDBY */ | |
1978 | ||
1979 | sysc_write(ddata, offset, 0); | |
1980 | } | |
1981 | ||
1982 | static void sysc_module_disable_quirk_otg(struct sysc *ddata) | |
1983 | { | |
1984 | int offset = 0x414; /* OTG_FORCESTDBY */ | |
1985 | u32 val = BIT(0); /* ENABLEFORCE */ | |
1986 | ||
1987 | sysc_write(ddata, offset, val); | |
1988 | } | |
1989 | ||
d7f563db TL |
1990 | /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ |
1991 | static void sysc_module_enable_quirk_sgx(struct sysc *ddata) | |
1992 | { | |
1993 | int offset = 0xff08; /* OCP_DEBUG_CONFIG */ | |
1994 | u32 val = BIT(31); /* THALIA_INT_BYPASS */ | |
1995 | ||
1996 | sysc_write(ddata, offset, val); | |
1997 | } | |
1998 | ||
4e23be47 TL |
1999 | /* Watchdog timer needs a disable sequence after reset */ |
2000 | static void sysc_reset_done_quirk_wdt(struct sysc *ddata) | |
2001 | { | |
2002 | int wps, spr, error; | |
2003 | u32 val; | |
2004 | ||
2005 | wps = 0x34; | |
2006 | spr = 0x48; | |
2007 | ||
2008 | sysc_write(ddata, spr, 0xaaaa); | |
2009 | error = readl_poll_timeout(ddata->module_va + wps, val, | |
2010 | !(val & 0x10), 100, | |
2011 | MAX_MODULE_SOFTRESET_WAIT); | |
2012 | if (error) | |
c7d8669f | 2013 | dev_warn(ddata->dev, "wdt disable step1 failed\n"); |
4e23be47 | 2014 | |
c7d8669f | 2015 | sysc_write(ddata, spr, 0x5555); |
4e23be47 TL |
2016 | error = readl_poll_timeout(ddata->module_va + wps, val, |
2017 | !(val & 0x10), 100, | |
2018 | MAX_MODULE_SOFTRESET_WAIT); | |
2019 | if (error) | |
c7d8669f | 2020 | dev_warn(ddata->dev, "wdt disable step2 failed\n"); |
4e23be47 TL |
2021 | } |
2022 | ||
b2745d92 SA |
2023 | /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ |
2024 | static void sysc_module_disable_quirk_pruss(struct sysc *ddata) | |
2025 | { | |
2026 | u32 reg; | |
2027 | ||
2028 | reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); | |
2029 | reg |= SYSC_PRUSS_STANDBY_INIT; | |
2030 | sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); | |
2031 | } | |
2032 | ||
4e23be47 TL |
2033 | static void sysc_init_module_quirks(struct sysc *ddata) |
2034 | { | |
2035 | if (ddata->legacy_mode || !ddata->name) | |
2036 | return; | |
2037 | ||
2038 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { | |
e64c021f | 2039 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; |
4e23be47 TL |
2040 | |
2041 | return; | |
2042 | } | |
2043 | ||
cfeeea60 TL |
2044 | #ifdef CONFIG_OMAP_GPMC_DEBUG |
2045 | if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { | |
2046 | ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; | |
2047 | ||
2048 | return; | |
2049 | } | |
2050 | #endif | |
2051 | ||
4e23be47 | 2052 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { |
e64c021f TL |
2053 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; |
2054 | ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; | |
4e23be47 TL |
2055 | |
2056 | return; | |
2057 | } | |
2058 | ||
020003f7 TL |
2059 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) |
2060 | ddata->module_enable_quirk = sysc_module_enable_quirk_aess; | |
2061 | ||
7324a7a0 TL |
2062 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) |
2063 | ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; | |
2064 | ||
e8639e1c TL |
2065 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { |
2066 | ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; | |
2067 | ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; | |
2068 | ||
2069 | return; | |
2070 | } | |
2071 | ||
5c99fa73 TL |
2072 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) { |
2073 | ddata->module_enable_quirk = sysc_module_enable_quirk_otg; | |
2074 | ddata->module_disable_quirk = sysc_module_disable_quirk_otg; | |
2075 | } | |
2076 | ||
d7f563db TL |
2077 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) |
2078 | ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; | |
2079 | ||
c7d8669f | 2080 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { |
4e23be47 | 2081 | ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; |
c7d8669f TL |
2082 | ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; |
2083 | } | |
b2745d92 SA |
2084 | |
2085 | if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) | |
2086 | ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; | |
4e23be47 TL |
2087 | } |
2088 | ||
2b2f7def TL |
2089 | static int sysc_clockdomain_init(struct sysc *ddata) |
2090 | { | |
2091 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
2092 | struct clk *fck = NULL, *ick = NULL; | |
2093 | int error; | |
2094 | ||
2095 | if (!pdata || !pdata->init_clockdomain) | |
2096 | return 0; | |
2097 | ||
2098 | switch (ddata->nr_clocks) { | |
2099 | case 2: | |
2100 | ick = ddata->clocks[SYSC_ICK]; | |
df561f66 | 2101 | fallthrough; |
2b2f7def TL |
2102 | case 1: |
2103 | fck = ddata->clocks[SYSC_FCK]; | |
2104 | break; | |
2105 | case 0: | |
2106 | return 0; | |
2107 | } | |
2108 | ||
2109 | error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); | |
2110 | if (!error || error == -ENODEV) | |
2111 | return 0; | |
2112 | ||
2113 | return error; | |
2114 | } | |
2115 | ||
a3e92e7b TL |
2116 | /* |
2117 | * Note that pdata->init_module() typically does a reset first. After | |
2118 | * pdata->init_module() is done, PM runtime can be used for the interconnect | |
2119 | * target module. | |
2120 | */ | |
2121 | static int sysc_legacy_init(struct sysc *ddata) | |
2122 | { | |
2123 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
2124 | int error; | |
2125 | ||
2b2f7def | 2126 | if (!pdata || !pdata->init_module) |
a3e92e7b TL |
2127 | return 0; |
2128 | ||
2129 | error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); | |
2130 | if (error == -EEXIST) | |
2131 | error = 0; | |
2132 | ||
2133 | return error; | |
2134 | } | |
2135 | ||
e0db94fe TL |
2136 | /* |
2137 | * Note that the caller must ensure the interconnect target module is enabled | |
2138 | * before calling reset. Otherwise reset will not complete. | |
2139 | */ | |
596e7955 FA |
2140 | static int sysc_reset(struct sysc *ddata) |
2141 | { | |
d46f9fbe TL |
2142 | int sysc_offset, sysc_val, error; |
2143 | u32 sysc_mask; | |
e0db94fe TL |
2144 | |
2145 | sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; | |
596e7955 | 2146 | |
ab4d309d | 2147 | if (ddata->legacy_mode || |
e0db94fe | 2148 | ddata->cap->regbits->srst_shift < 0 || |
596e7955 FA |
2149 | ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) |
2150 | return 0; | |
2151 | ||
e0db94fe | 2152 | sysc_mask = BIT(ddata->cap->regbits->srst_shift); |
596e7955 | 2153 | |
e64c021f TL |
2154 | if (ddata->pre_reset_quirk) |
2155 | ddata->pre_reset_quirk(ddata); | |
4e23be47 | 2156 | |
ab4d309d TL |
2157 | if (sysc_offset >= 0) { |
2158 | sysc_val = sysc_read_sysconfig(ddata); | |
2159 | sysc_val |= sysc_mask; | |
2160 | sysc_write(ddata, sysc_offset, sysc_val); | |
f71f6ff8 TL |
2161 | |
2162 | /* | |
2163 | * Some devices need a delay before reading registers | |
2164 | * after reset. Presumably a srst_udelay is not needed | |
2165 | * for devices that use a rstctrl register reset. | |
2166 | */ | |
2167 | if (ddata->cfg.srst_udelay) | |
2168 | fsleep(ddata->cfg.srst_udelay); | |
2169 | ||
2170 | /* | |
2171 | * Flush posted write. For devices needing srst_udelay | |
2172 | * this should trigger an interconnect error if the | |
2173 | * srst_udelay value is needed but not configured. | |
2174 | */ | |
34539b44 | 2175 | sysc_val = sysc_read_sysconfig(ddata); |
ab4d309d | 2176 | } |
596e7955 | 2177 | |
e64c021f TL |
2178 | if (ddata->post_reset_quirk) |
2179 | ddata->post_reset_quirk(ddata); | |
4e23be47 | 2180 | |
d46f9fbe TL |
2181 | error = sysc_wait_softreset(ddata); |
2182 | if (error) | |
2183 | dev_warn(ddata->dev, "OCP softreset timed out\n"); | |
596e7955 | 2184 | |
4e23be47 TL |
2185 | if (ddata->reset_done_quirk) |
2186 | ddata->reset_done_quirk(ddata); | |
2187 | ||
e0db94fe | 2188 | return error; |
596e7955 FA |
2189 | } |
2190 | ||
1a5cd7c2 TL |
2191 | /* |
2192 | * At this point the module is configured enough to read the revision but | |
2193 | * module may not be completely configured yet to use PM runtime. Enable | |
2194 | * all clocks directly during init to configure the quirks needed for PM | |
2195 | * runtime based on the revision register. | |
2196 | */ | |
566a9b05 TL |
2197 | static int sysc_init_module(struct sysc *ddata) |
2198 | { | |
4097c9a6 | 2199 | bool rstctrl_deasserted = false; |
1a5cd7c2 | 2200 | int error = 0; |
a885f0fe | 2201 | |
2b2f7def TL |
2202 | error = sysc_clockdomain_init(ddata); |
2203 | if (error) | |
2204 | return error; | |
2205 | ||
d098913a | 2206 | sysc_clkdm_deny_idle(ddata); |
2b2f7def | 2207 | |
d098913a TL |
2208 | /* |
2209 | * Always enable clocks. The bootloader may or may not have enabled | |
2210 | * the related clocks. | |
2211 | */ | |
2212 | error = sysc_enable_opt_clocks(ddata); | |
2213 | if (error) | |
2214 | return error; | |
566a9b05 | 2215 | |
d098913a TL |
2216 | error = sysc_enable_main_clocks(ddata); |
2217 | if (error) | |
2218 | goto err_opt_clocks; | |
5062236e | 2219 | |
ea5a2e4d | 2220 | if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { |
df4f3459 | 2221 | error = reset_control_deassert(ddata->rsts); |
ea5a2e4d TL |
2222 | if (error) |
2223 | goto err_main_clocks; | |
4097c9a6 | 2224 | rstctrl_deasserted = true; |
ea5a2e4d TL |
2225 | } |
2226 | ||
1a5cd7c2 TL |
2227 | ddata->revision = sysc_read_revision(ddata); |
2228 | sysc_init_revision_quirks(ddata); | |
4e23be47 | 2229 | sysc_init_module_quirks(ddata); |
1a5cd7c2 | 2230 | |
2b2f7def TL |
2231 | if (ddata->legacy_mode) { |
2232 | error = sysc_legacy_init(ddata); | |
2233 | if (error) | |
4097c9a6 | 2234 | goto err_main_clocks; |
2b2f7def TL |
2235 | } |
2236 | ||
d098913a | 2237 | if (!ddata->legacy_mode) { |
2b2f7def TL |
2238 | error = sysc_enable_module(ddata->dev); |
2239 | if (error) | |
4097c9a6 | 2240 | goto err_main_clocks; |
2b2f7def | 2241 | } |
a3e92e7b | 2242 | |
596e7955 | 2243 | error = sysc_reset(ddata); |
1a5cd7c2 | 2244 | if (error) |
596e7955 | 2245 | dev_err(ddata->dev, "Reset failed with %d\n", error); |
596e7955 | 2246 | |
cdc56c11 | 2247 | if (error && !ddata->legacy_mode) |
2b2f7def TL |
2248 | sysc_disable_module(ddata->dev); |
2249 | ||
a3e92e7b | 2250 | err_main_clocks: |
cdc56c11 | 2251 | if (error) |
1a5cd7c2 TL |
2252 | sysc_disable_main_clocks(ddata); |
2253 | err_opt_clocks: | |
d098913a | 2254 | /* No re-enable of clockdomain autoidle to prevent module autoidle */ |
cdc56c11 | 2255 | if (error) { |
1a5cd7c2 | 2256 | sysc_disable_opt_clocks(ddata); |
2b2f7def TL |
2257 | sysc_clkdm_allow_idle(ddata); |
2258 | } | |
a885f0fe | 2259 | |
4097c9a6 TL |
2260 | if (error && rstctrl_deasserted && |
2261 | !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) | |
2262 | reset_control_assert(ddata->rsts); | |
2263 | ||
1a5cd7c2 | 2264 | return error; |
566a9b05 TL |
2265 | } |
2266 | ||
c5a2de97 TL |
2267 | static int sysc_init_sysc_mask(struct sysc *ddata) |
2268 | { | |
2269 | struct device_node *np = ddata->dev->of_node; | |
2270 | int error; | |
2271 | u32 val; | |
2272 | ||
2273 | error = of_property_read_u32(np, "ti,sysc-mask", &val); | |
2274 | if (error) | |
2275 | return 0; | |
2276 | ||
e212abd4 | 2277 | ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; |
c5a2de97 TL |
2278 | |
2279 | return 0; | |
2280 | } | |
2281 | ||
2282 | static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, | |
2283 | const char *name) | |
2284 | { | |
2285 | struct device_node *np = ddata->dev->of_node; | |
2286 | struct property *prop; | |
2287 | const __be32 *p; | |
2288 | u32 val; | |
2289 | ||
2290 | of_property_for_each_u32(np, name, prop, p, val) { | |
2291 | if (val >= SYSC_NR_IDLEMODES) { | |
2292 | dev_err(ddata->dev, "invalid idlemode: %i\n", val); | |
2293 | return -EINVAL; | |
2294 | } | |
2295 | *idlemodes |= (1 << val); | |
2296 | } | |
2297 | ||
2298 | return 0; | |
2299 | } | |
2300 | ||
2301 | static int sysc_init_idlemodes(struct sysc *ddata) | |
2302 | { | |
2303 | int error; | |
2304 | ||
2305 | error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, | |
2306 | "ti,sysc-midle"); | |
2307 | if (error) | |
2308 | return error; | |
2309 | ||
2310 | error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, | |
2311 | "ti,sysc-sidle"); | |
2312 | if (error) | |
2313 | return error; | |
2314 | ||
2315 | return 0; | |
2316 | } | |
2317 | ||
2318 | /* | |
2319 | * Only some devices on omap4 and later have SYSCONFIG reset done | |
2320 | * bit. We can detect this if there is no SYSSTATUS at all, or the | |
2321 | * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers | |
2322 | * have multiple bits for the child devices like OHCI and EHCI. | |
2323 | * Depends on SYSC being parsed first. | |
2324 | */ | |
2325 | static int sysc_init_syss_mask(struct sysc *ddata) | |
2326 | { | |
2327 | struct device_node *np = ddata->dev->of_node; | |
2328 | int error; | |
2329 | u32 val; | |
2330 | ||
2331 | error = of_property_read_u32(np, "ti,syss-mask", &val); | |
2332 | if (error) { | |
2333 | if ((ddata->cap->type == TI_SYSC_OMAP4 || | |
2334 | ddata->cap->type == TI_SYSC_OMAP4_TIMER) && | |
2335 | (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
2336 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
2337 | ||
2338 | return 0; | |
2339 | } | |
2340 | ||
2341 | if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) | |
2342 | ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; | |
2343 | ||
2344 | ddata->cfg.syss_mask = val; | |
2345 | ||
2346 | return 0; | |
2347 | } | |
2348 | ||
2c355ff6 | 2349 | /* |
8b2830ba TL |
2350 | * Many child device drivers need to have fck and opt clocks available |
2351 | * to get the clock rate for device internal configuration etc. | |
2c355ff6 | 2352 | */ |
8b2830ba TL |
2353 | static int sysc_child_add_named_clock(struct sysc *ddata, |
2354 | struct device *child, | |
2355 | const char *name) | |
2c355ff6 | 2356 | { |
8b2830ba | 2357 | struct clk *clk; |
2c355ff6 | 2358 | struct clk_lookup *l; |
8b2830ba | 2359 | int error = 0; |
2c355ff6 | 2360 | |
8b2830ba | 2361 | if (!name) |
2c355ff6 TL |
2362 | return 0; |
2363 | ||
8b2830ba TL |
2364 | clk = clk_get(child, name); |
2365 | if (!IS_ERR(clk)) { | |
cb6cfe2e ME |
2366 | error = -EEXIST; |
2367 | goto put_clk; | |
2c355ff6 TL |
2368 | } |
2369 | ||
8b2830ba TL |
2370 | clk = clk_get(ddata->dev, name); |
2371 | if (IS_ERR(clk)) | |
2372 | return -ENODEV; | |
2c355ff6 | 2373 | |
8b2830ba TL |
2374 | l = clkdev_create(clk, name, dev_name(child)); |
2375 | if (!l) | |
2376 | error = -ENOMEM; | |
cb6cfe2e | 2377 | put_clk: |
8b2830ba TL |
2378 | clk_put(clk); |
2379 | ||
2380 | return error; | |
2c355ff6 TL |
2381 | } |
2382 | ||
09dfe581 TL |
2383 | static int sysc_child_add_clocks(struct sysc *ddata, |
2384 | struct device *child) | |
2385 | { | |
2386 | int i, error; | |
2387 | ||
2388 | for (i = 0; i < ddata->nr_clocks; i++) { | |
2389 | error = sysc_child_add_named_clock(ddata, | |
2390 | child, | |
2391 | ddata->clock_roles[i]); | |
2392 | if (error && error != -EEXIST) { | |
2393 | dev_err(ddata->dev, "could not add child clock %s: %i\n", | |
2394 | ddata->clock_roles[i], error); | |
2395 | ||
2396 | return error; | |
2397 | } | |
2398 | } | |
2399 | ||
2400 | return 0; | |
2401 | } | |
2402 | ||
2c355ff6 TL |
2403 | static struct device_type sysc_device_type = { |
2404 | }; | |
2405 | ||
2406 | static struct sysc *sysc_child_to_parent(struct device *dev) | |
2407 | { | |
2408 | struct device *parent = dev->parent; | |
2409 | ||
2410 | if (!parent || parent->type != &sysc_device_type) | |
2411 | return NULL; | |
2412 | ||
2413 | return dev_get_drvdata(parent); | |
2414 | } | |
2415 | ||
a885f0fe TL |
2416 | static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) |
2417 | { | |
2418 | struct sysc *ddata; | |
2419 | int error; | |
2420 | ||
2421 | ddata = sysc_child_to_parent(dev); | |
2422 | ||
2423 | error = pm_generic_runtime_suspend(dev); | |
2424 | if (error) | |
2425 | return error; | |
2426 | ||
2427 | if (!ddata->enabled) | |
2428 | return 0; | |
2429 | ||
2430 | return sysc_runtime_suspend(ddata->dev); | |
2431 | } | |
2432 | ||
2433 | static int __maybe_unused sysc_child_runtime_resume(struct device *dev) | |
2434 | { | |
2435 | struct sysc *ddata; | |
2436 | int error; | |
2437 | ||
2438 | ddata = sysc_child_to_parent(dev); | |
2439 | ||
2440 | if (!ddata->enabled) { | |
2441 | error = sysc_runtime_resume(ddata->dev); | |
2442 | if (error < 0) | |
2443 | dev_err(ddata->dev, | |
2444 | "%s error: %i\n", __func__, error); | |
2445 | } | |
2446 | ||
2447 | return pm_generic_runtime_resume(dev); | |
2448 | } | |
2449 | ||
2450 | #ifdef CONFIG_PM_SLEEP | |
2451 | static int sysc_child_suspend_noirq(struct device *dev) | |
2452 | { | |
2453 | struct sysc *ddata; | |
2454 | int error; | |
2455 | ||
2456 | ddata = sysc_child_to_parent(dev); | |
2457 | ||
ef55f821 TL |
2458 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
2459 | ddata->name ? ddata->name : ""); | |
2460 | ||
a885f0fe | 2461 | error = pm_generic_suspend_noirq(dev); |
ef55f821 TL |
2462 | if (error) { |
2463 | dev_err(dev, "%s error at %i: %i\n", | |
2464 | __func__, __LINE__, error); | |
2465 | ||
a885f0fe | 2466 | return error; |
ef55f821 | 2467 | } |
a885f0fe TL |
2468 | |
2469 | if (!pm_runtime_status_suspended(dev)) { | |
2470 | error = pm_generic_runtime_suspend(dev); | |
ef55f821 | 2471 | if (error) { |
f9490783 TL |
2472 | dev_dbg(dev, "%s busy at %i: %i\n", |
2473 | __func__, __LINE__, error); | |
ef55f821 | 2474 | |
4f3530f4 | 2475 | return 0; |
ef55f821 | 2476 | } |
a885f0fe TL |
2477 | |
2478 | error = sysc_runtime_suspend(ddata->dev); | |
ef55f821 TL |
2479 | if (error) { |
2480 | dev_err(dev, "%s error at %i: %i\n", | |
2481 | __func__, __LINE__, error); | |
2482 | ||
a885f0fe | 2483 | return error; |
ef55f821 | 2484 | } |
a885f0fe TL |
2485 | |
2486 | ddata->child_needs_resume = true; | |
2487 | } | |
2488 | ||
2489 | return 0; | |
2490 | } | |
2491 | ||
2492 | static int sysc_child_resume_noirq(struct device *dev) | |
2493 | { | |
2494 | struct sysc *ddata; | |
2495 | int error; | |
2496 | ||
2497 | ddata = sysc_child_to_parent(dev); | |
2498 | ||
ef55f821 TL |
2499 | dev_dbg(ddata->dev, "%s %s\n", __func__, |
2500 | ddata->name ? ddata->name : ""); | |
2501 | ||
a885f0fe TL |
2502 | if (ddata->child_needs_resume) { |
2503 | ddata->child_needs_resume = false; | |
2504 | ||
2505 | error = sysc_runtime_resume(ddata->dev); | |
2506 | if (error) | |
2507 | dev_err(ddata->dev, | |
2508 | "%s runtime resume error: %i\n", | |
2509 | __func__, error); | |
2510 | ||
2511 | error = pm_generic_runtime_resume(dev); | |
2512 | if (error) | |
2513 | dev_err(ddata->dev, | |
2514 | "%s generic runtime resume: %i\n", | |
2515 | __func__, error); | |
2516 | } | |
2517 | ||
2518 | return pm_generic_resume_noirq(dev); | |
2519 | } | |
2520 | #endif | |
2521 | ||
b7182b42 | 2522 | static struct dev_pm_domain sysc_child_pm_domain = { |
a885f0fe TL |
2523 | .ops = { |
2524 | SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, | |
2525 | sysc_child_runtime_resume, | |
2526 | NULL) | |
2527 | USE_PLATFORM_PM_SLEEP_OPS | |
2528 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, | |
2529 | sysc_child_resume_noirq) | |
2530 | } | |
2531 | }; | |
2532 | ||
9d881361 TL |
2533 | /* Caller needs to take list_lock if ever used outside of cpu_pm */ |
2534 | static void sysc_reinit_modules(struct sysc_soc_info *soc) | |
2535 | { | |
2536 | struct sysc_module *module; | |
9d881361 | 2537 | struct sysc *ddata; |
9d881361 | 2538 | |
d4f1d01d | 2539 | list_for_each_entry(module, &sysc_soc->restored_modules, node) { |
9d881361 | 2540 | ddata = module->ddata; |
1b1da99b | 2541 | sysc_reinit_module(ddata, ddata->enabled); |
9d881361 TL |
2542 | } |
2543 | } | |
2544 | ||
2545 | /** | |
2546 | * sysc_context_notifier - optionally reset and restore module after idle | |
2547 | * @nb: notifier block | |
2548 | * @cmd: unused | |
2549 | * @v: unused | |
2550 | * | |
2551 | * Some interconnect target modules need to be restored, or reset and restored | |
2552 | * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x | |
2553 | * OTG and GPMC target modules even if the modules are unused. | |
2554 | */ | |
2555 | static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd, | |
2556 | void *v) | |
2557 | { | |
2558 | struct sysc_soc_info *soc; | |
2559 | ||
2560 | soc = container_of(nb, struct sysc_soc_info, nb); | |
2561 | ||
2562 | switch (cmd) { | |
2563 | case CPU_CLUSTER_PM_ENTER: | |
2564 | break; | |
2565 | case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ | |
2566 | break; | |
2567 | case CPU_CLUSTER_PM_EXIT: | |
2568 | sysc_reinit_modules(soc); | |
2569 | break; | |
2570 | } | |
2571 | ||
2572 | return NOTIFY_OK; | |
2573 | } | |
2574 | ||
2575 | /** | |
2576 | * sysc_add_restored - optionally add reset and restore quirk hanlling | |
2577 | * @ddata: device data | |
2578 | */ | |
2579 | static void sysc_add_restored(struct sysc *ddata) | |
2580 | { | |
2581 | struct sysc_module *restored_module; | |
2582 | ||
2583 | restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL); | |
2584 | if (!restored_module) | |
2585 | return; | |
2586 | ||
2587 | restored_module->ddata = ddata; | |
2588 | ||
2589 | mutex_lock(&sysc_soc->list_lock); | |
2590 | ||
2591 | list_add(&restored_module->node, &sysc_soc->restored_modules); | |
2592 | ||
2593 | if (sysc_soc->nb.notifier_call) | |
2594 | goto out_unlock; | |
2595 | ||
2596 | sysc_soc->nb.notifier_call = sysc_context_notifier; | |
2597 | cpu_pm_register_notifier(&sysc_soc->nb); | |
2598 | ||
2599 | out_unlock: | |
2600 | mutex_unlock(&sysc_soc->list_lock); | |
2601 | } | |
2602 | ||
a885f0fe TL |
2603 | /** |
2604 | * sysc_legacy_idle_quirk - handle children in omap_device compatible way | |
2605 | * @ddata: device driver data | |
2606 | * @child: child device driver | |
2607 | * | |
2608 | * Allow idle for child devices as done with _od_runtime_suspend(). | |
2609 | * Otherwise many child devices will not idle because of the permanent | |
2610 | * parent usecount set in pm_runtime_irq_safe(). | |
2611 | * | |
2612 | * Note that the long term solution is to just modify the child device | |
2613 | * drivers to not set pm_runtime_irq_safe() and then this can be just | |
2614 | * dropped. | |
2615 | */ | |
2616 | static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) | |
2617 | { | |
a885f0fe TL |
2618 | if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) |
2619 | dev_pm_domain_set(child, &sysc_child_pm_domain); | |
2620 | } | |
2621 | ||
2c355ff6 TL |
2622 | static int sysc_notifier_call(struct notifier_block *nb, |
2623 | unsigned long event, void *device) | |
2624 | { | |
2625 | struct device *dev = device; | |
2626 | struct sysc *ddata; | |
2627 | int error; | |
2628 | ||
2629 | ddata = sysc_child_to_parent(dev); | |
2630 | if (!ddata) | |
2631 | return NOTIFY_DONE; | |
2632 | ||
2633 | switch (event) { | |
2634 | case BUS_NOTIFY_ADD_DEVICE: | |
09dfe581 TL |
2635 | error = sysc_child_add_clocks(ddata, dev); |
2636 | if (error) | |
2637 | return error; | |
a885f0fe | 2638 | sysc_legacy_idle_quirk(ddata, dev); |
2c355ff6 TL |
2639 | break; |
2640 | default: | |
2641 | break; | |
2642 | } | |
2643 | ||
2644 | return NOTIFY_DONE; | |
2645 | } | |
2646 | ||
2647 | static struct notifier_block sysc_nb = { | |
2648 | .notifier_call = sysc_notifier_call, | |
2649 | }; | |
2650 | ||
566a9b05 TL |
2651 | /* Device tree configured quirks */ |
2652 | struct sysc_dts_quirk { | |
2653 | const char *name; | |
2654 | u32 mask; | |
2655 | }; | |
2656 | ||
2657 | static const struct sysc_dts_quirk sysc_dts_quirks[] = { | |
2658 | { .name = "ti,no-idle-on-init", | |
2659 | .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, | |
2660 | { .name = "ti,no-reset-on-init", | |
2661 | .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, | |
386cb766 TL |
2662 | { .name = "ti,no-idle", |
2663 | .mask = SYSC_QUIRK_NO_IDLE, }, | |
566a9b05 TL |
2664 | }; |
2665 | ||
4014c08b TL |
2666 | static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, |
2667 | bool is_child) | |
566a9b05 | 2668 | { |
566a9b05 | 2669 | const struct property *prop; |
4014c08b | 2670 | int i, len; |
566a9b05 TL |
2671 | |
2672 | for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { | |
4014c08b TL |
2673 | const char *name = sysc_dts_quirks[i].name; |
2674 | ||
2675 | prop = of_get_property(np, name, &len); | |
566a9b05 | 2676 | if (!prop) |
d39b6ea4 | 2677 | continue; |
566a9b05 TL |
2678 | |
2679 | ddata->cfg.quirks |= sysc_dts_quirks[i].mask; | |
4014c08b TL |
2680 | if (is_child) { |
2681 | dev_warn(ddata->dev, | |
2682 | "dts flag should be at module level for %s\n", | |
2683 | name); | |
2684 | } | |
566a9b05 | 2685 | } |
4014c08b TL |
2686 | } |
2687 | ||
2688 | static int sysc_init_dts_quirks(struct sysc *ddata) | |
2689 | { | |
2690 | struct device_node *np = ddata->dev->of_node; | |
2691 | int error; | |
2692 | u32 val; | |
2693 | ||
2694 | ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); | |
566a9b05 | 2695 | |
4014c08b | 2696 | sysc_parse_dts_quirks(ddata, np, false); |
566a9b05 TL |
2697 | error = of_property_read_u32(np, "ti,sysc-delay-us", &val); |
2698 | if (!error) { | |
2699 | if (val > 255) { | |
2700 | dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", | |
2701 | val); | |
2702 | } | |
2703 | ||
2704 | ddata->cfg.srst_udelay = (u8)val; | |
2705 | } | |
2706 | ||
2707 | return 0; | |
2708 | } | |
2709 | ||
0eecc636 TL |
2710 | static void sysc_unprepare(struct sysc *ddata) |
2711 | { | |
2712 | int i; | |
2713 | ||
aaa29bb0 TL |
2714 | if (!ddata->clocks) |
2715 | return; | |
2716 | ||
0eecc636 TL |
2717 | for (i = 0; i < SYSC_MAX_CLOCKS; i++) { |
2718 | if (!IS_ERR_OR_NULL(ddata->clocks[i])) | |
2719 | clk_unprepare(ddata->clocks[i]); | |
2720 | } | |
2721 | } | |
2722 | ||
70a65240 TL |
2723 | /* |
2724 | * Common sysc register bits found on omap2, also known as type1 | |
2725 | */ | |
2726 | static const struct sysc_regbits sysc_regbits_omap2 = { | |
2727 | .dmadisable_shift = -ENODEV, | |
2728 | .midle_shift = 12, | |
2729 | .sidle_shift = 3, | |
2730 | .clkact_shift = 8, | |
2731 | .emufree_shift = 5, | |
2732 | .enwkup_shift = 2, | |
2733 | .srst_shift = 1, | |
2734 | .autoidle_shift = 0, | |
2735 | }; | |
2736 | ||
2737 | static const struct sysc_capabilities sysc_omap2 = { | |
2738 | .type = TI_SYSC_OMAP2, | |
2739 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
2740 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
2741 | SYSC_OMAP2_AUTOIDLE, | |
2742 | .regbits = &sysc_regbits_omap2, | |
2743 | }; | |
2744 | ||
2745 | /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ | |
2746 | static const struct sysc_capabilities sysc_omap2_timer = { | |
2747 | .type = TI_SYSC_OMAP2_TIMER, | |
2748 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | | |
2749 | SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | | |
2750 | SYSC_OMAP2_AUTOIDLE, | |
2751 | .regbits = &sysc_regbits_omap2, | |
2752 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, | |
2753 | }; | |
2754 | ||
2755 | /* | |
2756 | * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 | |
2757 | * with different sidle position | |
2758 | */ | |
2759 | static const struct sysc_regbits sysc_regbits_omap3_sham = { | |
2760 | .dmadisable_shift = -ENODEV, | |
2761 | .midle_shift = -ENODEV, | |
2762 | .sidle_shift = 4, | |
2763 | .clkact_shift = -ENODEV, | |
2764 | .enwkup_shift = -ENODEV, | |
2765 | .srst_shift = 1, | |
2766 | .autoidle_shift = 0, | |
2767 | .emufree_shift = -ENODEV, | |
2768 | }; | |
2769 | ||
2770 | static const struct sysc_capabilities sysc_omap3_sham = { | |
2771 | .type = TI_SYSC_OMAP3_SHAM, | |
2772 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
2773 | .regbits = &sysc_regbits_omap3_sham, | |
2774 | }; | |
2775 | ||
2776 | /* | |
2777 | * AES register bits found on omap3 and later, a variant of | |
2778 | * sysc_regbits_omap2 with different sidle position | |
2779 | */ | |
2780 | static const struct sysc_regbits sysc_regbits_omap3_aes = { | |
2781 | .dmadisable_shift = -ENODEV, | |
2782 | .midle_shift = -ENODEV, | |
2783 | .sidle_shift = 6, | |
2784 | .clkact_shift = -ENODEV, | |
2785 | .enwkup_shift = -ENODEV, | |
2786 | .srst_shift = 1, | |
2787 | .autoidle_shift = 0, | |
2788 | .emufree_shift = -ENODEV, | |
2789 | }; | |
2790 | ||
2791 | static const struct sysc_capabilities sysc_omap3_aes = { | |
2792 | .type = TI_SYSC_OMAP3_AES, | |
2793 | .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, | |
2794 | .regbits = &sysc_regbits_omap3_aes, | |
2795 | }; | |
2796 | ||
2797 | /* | |
2798 | * Common sysc register bits found on omap4, also known as type2 | |
2799 | */ | |
2800 | static const struct sysc_regbits sysc_regbits_omap4 = { | |
2801 | .dmadisable_shift = 16, | |
2802 | .midle_shift = 4, | |
2803 | .sidle_shift = 2, | |
2804 | .clkact_shift = -ENODEV, | |
2805 | .enwkup_shift = -ENODEV, | |
2806 | .emufree_shift = 1, | |
2807 | .srst_shift = 0, | |
2808 | .autoidle_shift = -ENODEV, | |
2809 | }; | |
2810 | ||
2811 | static const struct sysc_capabilities sysc_omap4 = { | |
2812 | .type = TI_SYSC_OMAP4, | |
2813 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
2814 | SYSC_OMAP4_SOFTRESET, | |
2815 | .regbits = &sysc_regbits_omap4, | |
2816 | }; | |
2817 | ||
2818 | static const struct sysc_capabilities sysc_omap4_timer = { | |
2819 | .type = TI_SYSC_OMAP4_TIMER, | |
2820 | .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | | |
2821 | SYSC_OMAP4_SOFTRESET, | |
2822 | .regbits = &sysc_regbits_omap4, | |
2823 | }; | |
2824 | ||
2825 | /* | |
2826 | * Common sysc register bits found on omap4, also known as type3 | |
2827 | */ | |
2828 | static const struct sysc_regbits sysc_regbits_omap4_simple = { | |
2829 | .dmadisable_shift = -ENODEV, | |
2830 | .midle_shift = 2, | |
2831 | .sidle_shift = 0, | |
2832 | .clkact_shift = -ENODEV, | |
2833 | .enwkup_shift = -ENODEV, | |
2834 | .srst_shift = -ENODEV, | |
2835 | .emufree_shift = -ENODEV, | |
2836 | .autoidle_shift = -ENODEV, | |
2837 | }; | |
2838 | ||
2839 | static const struct sysc_capabilities sysc_omap4_simple = { | |
2840 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2841 | .regbits = &sysc_regbits_omap4_simple, | |
2842 | }; | |
2843 | ||
2844 | /* | |
2845 | * SmartReflex sysc found on omap34xx | |
2846 | */ | |
2847 | static const struct sysc_regbits sysc_regbits_omap34xx_sr = { | |
2848 | .dmadisable_shift = -ENODEV, | |
2849 | .midle_shift = -ENODEV, | |
2850 | .sidle_shift = -ENODEV, | |
2851 | .clkact_shift = 20, | |
2852 | .enwkup_shift = -ENODEV, | |
2853 | .srst_shift = -ENODEV, | |
2854 | .emufree_shift = -ENODEV, | |
2855 | .autoidle_shift = -ENODEV, | |
2856 | }; | |
2857 | ||
2858 | static const struct sysc_capabilities sysc_34xx_sr = { | |
2859 | .type = TI_SYSC_OMAP34XX_SR, | |
2860 | .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, | |
2861 | .regbits = &sysc_regbits_omap34xx_sr, | |
a885f0fe TL |
2862 | .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | |
2863 | SYSC_QUIRK_LEGACY_IDLE, | |
70a65240 TL |
2864 | }; |
2865 | ||
2866 | /* | |
2867 | * SmartReflex sysc found on omap36xx and later | |
2868 | */ | |
2869 | static const struct sysc_regbits sysc_regbits_omap36xx_sr = { | |
2870 | .dmadisable_shift = -ENODEV, | |
2871 | .midle_shift = -ENODEV, | |
2872 | .sidle_shift = 24, | |
2873 | .clkact_shift = -ENODEV, | |
2874 | .enwkup_shift = 26, | |
2875 | .srst_shift = -ENODEV, | |
2876 | .emufree_shift = -ENODEV, | |
2877 | .autoidle_shift = -ENODEV, | |
2878 | }; | |
2879 | ||
2880 | static const struct sysc_capabilities sysc_36xx_sr = { | |
2881 | .type = TI_SYSC_OMAP36XX_SR, | |
3267c081 | 2882 | .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, |
70a65240 | 2883 | .regbits = &sysc_regbits_omap36xx_sr, |
a885f0fe | 2884 | .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
2885 | }; |
2886 | ||
2887 | static const struct sysc_capabilities sysc_omap4_sr = { | |
2888 | .type = TI_SYSC_OMAP4_SR, | |
2889 | .regbits = &sysc_regbits_omap36xx_sr, | |
a885f0fe | 2890 | .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, |
70a65240 TL |
2891 | }; |
2892 | ||
2893 | /* | |
2894 | * McASP register bits found on omap4 and later | |
2895 | */ | |
2896 | static const struct sysc_regbits sysc_regbits_omap4_mcasp = { | |
2897 | .dmadisable_shift = -ENODEV, | |
2898 | .midle_shift = -ENODEV, | |
2899 | .sidle_shift = 0, | |
2900 | .clkact_shift = -ENODEV, | |
2901 | .enwkup_shift = -ENODEV, | |
2902 | .srst_shift = -ENODEV, | |
2903 | .emufree_shift = -ENODEV, | |
2904 | .autoidle_shift = -ENODEV, | |
2905 | }; | |
2906 | ||
2907 | static const struct sysc_capabilities sysc_omap4_mcasp = { | |
2908 | .type = TI_SYSC_OMAP4_MCASP, | |
2909 | .regbits = &sysc_regbits_omap4_mcasp, | |
2c63a833 TL |
2910 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, |
2911 | }; | |
2912 | ||
2913 | /* | |
2914 | * McASP found on dra7 and later | |
2915 | */ | |
2916 | static const struct sysc_capabilities sysc_dra7_mcasp = { | |
2917 | .type = TI_SYSC_OMAP4_SIMPLE, | |
2918 | .regbits = &sysc_regbits_omap4_simple, | |
2919 | .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, | |
70a65240 TL |
2920 | }; |
2921 | ||
2922 | /* | |
2923 | * FS USB host found on omap4 and later | |
2924 | */ | |
2925 | static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { | |
2926 | .dmadisable_shift = -ENODEV, | |
2927 | .midle_shift = -ENODEV, | |
2928 | .sidle_shift = 24, | |
2929 | .clkact_shift = -ENODEV, | |
2930 | .enwkup_shift = 26, | |
2931 | .srst_shift = -ENODEV, | |
2932 | .emufree_shift = -ENODEV, | |
2933 | .autoidle_shift = -ENODEV, | |
2934 | }; | |
2935 | ||
2936 | static const struct sysc_capabilities sysc_omap4_usb_host_fs = { | |
2937 | .type = TI_SYSC_OMAP4_USB_HOST_FS, | |
2938 | .sysc_mask = SYSC_OMAP2_ENAWAKEUP, | |
2939 | .regbits = &sysc_regbits_omap4_usb_host_fs, | |
2940 | }; | |
2941 | ||
7f35e63d FA |
2942 | static const struct sysc_regbits sysc_regbits_dra7_mcan = { |
2943 | .dmadisable_shift = -ENODEV, | |
2944 | .midle_shift = -ENODEV, | |
2945 | .sidle_shift = -ENODEV, | |
2946 | .clkact_shift = -ENODEV, | |
2947 | .enwkup_shift = 4, | |
2948 | .srst_shift = 0, | |
2949 | .emufree_shift = -ENODEV, | |
2950 | .autoidle_shift = -ENODEV, | |
2951 | }; | |
2952 | ||
2953 | static const struct sysc_capabilities sysc_dra7_mcan = { | |
2954 | .type = TI_SYSC_DRA7_MCAN, | |
2955 | .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, | |
2956 | .regbits = &sysc_regbits_dra7_mcan, | |
e0db94fe | 2957 | .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, |
7f35e63d FA |
2958 | }; |
2959 | ||
b2745d92 SA |
2960 | /* |
2961 | * PRUSS found on some AM33xx, AM437x and AM57xx SoCs | |
2962 | */ | |
2963 | static const struct sysc_capabilities sysc_pruss = { | |
2964 | .type = TI_SYSC_PRUSS, | |
2965 | .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, | |
2966 | .regbits = &sysc_regbits_omap4_simple, | |
2967 | .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, | |
2968 | }; | |
2969 | ||
ef70b0bd TL |
2970 | static int sysc_init_pdata(struct sysc *ddata) |
2971 | { | |
2972 | struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); | |
a3e92e7b | 2973 | struct ti_sysc_module_data *mdata; |
ef70b0bd | 2974 | |
2b2f7def | 2975 | if (!pdata) |
ef70b0bd TL |
2976 | return 0; |
2977 | ||
a3e92e7b TL |
2978 | mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); |
2979 | if (!mdata) | |
2980 | return -ENOMEM; | |
ef70b0bd | 2981 | |
2b2f7def TL |
2982 | if (ddata->legacy_mode) { |
2983 | mdata->name = ddata->legacy_mode; | |
2984 | mdata->module_pa = ddata->module_pa; | |
2985 | mdata->module_size = ddata->module_size; | |
2986 | mdata->offsets = ddata->offsets; | |
2987 | mdata->nr_offsets = SYSC_MAX_REGS; | |
2988 | mdata->cap = ddata->cap; | |
2989 | mdata->cfg = &ddata->cfg; | |
2990 | } | |
ef70b0bd | 2991 | |
a3e92e7b | 2992 | ddata->mdata = mdata; |
ef70b0bd | 2993 | |
a3e92e7b | 2994 | return 0; |
ef70b0bd TL |
2995 | } |
2996 | ||
70a65240 TL |
2997 | static int sysc_init_match(struct sysc *ddata) |
2998 | { | |
2999 | const struct sysc_capabilities *cap; | |
3000 | ||
3001 | cap = of_device_get_match_data(ddata->dev); | |
3002 | if (!cap) | |
3003 | return -EINVAL; | |
3004 | ||
3005 | ddata->cap = cap; | |
3006 | if (ddata->cap) | |
3007 | ddata->cfg.quirks |= ddata->cap->mod_quirks; | |
3008 | ||
3009 | return 0; | |
3010 | } | |
3011 | ||
76f0f772 TL |
3012 | static void ti_sysc_idle(struct work_struct *work) |
3013 | { | |
3014 | struct sysc *ddata; | |
3015 | ||
3016 | ddata = container_of(work, struct sysc, idle_work.work); | |
3017 | ||
d098913a TL |
3018 | /* |
3019 | * One time decrement of clock usage counts if left on from init. | |
3020 | * Note that we disable opt clocks unconditionally in this case | |
3021 | * as they are enabled unconditionally during init without | |
3022 | * considering sysc_opt_clks_needed() at that point. | |
3023 | */ | |
3024 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | | |
3025 | SYSC_QUIRK_NO_IDLE_ON_INIT)) { | |
d098913a TL |
3026 | sysc_disable_main_clocks(ddata); |
3027 | sysc_disable_opt_clocks(ddata); | |
3028 | sysc_clkdm_allow_idle(ddata); | |
3029 | } | |
3030 | ||
3031 | /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ | |
3032 | if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) | |
3033 | return; | |
3034 | ||
3035 | /* | |
3036 | * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT | |
3037 | * and SYSC_QUIRK_NO_RESET_ON_INIT | |
3038 | */ | |
76f0f772 TL |
3039 | if (pm_runtime_active(ddata->dev)) |
3040 | pm_runtime_put_sync(ddata->dev); | |
3041 | } | |
3042 | ||
feaa8bae TL |
3043 | /* |
3044 | * SoC model and features detection. Only needed for SoCs that need | |
3045 | * special handling for quirks, no need to list others. | |
3046 | */ | |
3047 | static const struct soc_device_attribute sysc_soc_match[] = { | |
3048 | SOC_FLAG("OMAP242*", SOC_2420), | |
3049 | SOC_FLAG("OMAP243*", SOC_2430), | |
11729caa | 3050 | SOC_FLAG("AM35*", SOC_AM35), |
feaa8bae TL |
3051 | SOC_FLAG("OMAP3[45]*", SOC_3430), |
3052 | SOC_FLAG("OMAP3[67]*", SOC_3630), | |
3053 | SOC_FLAG("OMAP443*", SOC_4430), | |
3054 | SOC_FLAG("OMAP446*", SOC_4460), | |
3055 | SOC_FLAG("OMAP447*", SOC_4470), | |
3056 | SOC_FLAG("OMAP54*", SOC_5430), | |
3057 | SOC_FLAG("AM433", SOC_AM3), | |
3058 | SOC_FLAG("AM43*", SOC_AM4), | |
3059 | SOC_FLAG("DRA7*", SOC_DRA7), | |
3060 | ||
b6cd9be3 | 3061 | { /* sentinel */ } |
feaa8bae TL |
3062 | }; |
3063 | ||
3064 | /* | |
3065 | * List of SoCs variants with disabled features. By default we assume all | |
3066 | * devices in the device tree are available so no need to list those SoCs. | |
3067 | */ | |
3068 | static const struct soc_device_attribute sysc_soc_feat_match[] = { | |
3069 | /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ | |
3070 | SOC_FLAG("AM3505", DIS_SGX), | |
3071 | SOC_FLAG("OMAP3525", DIS_SGX), | |
3072 | SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), | |
3073 | SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), | |
3074 | ||
3075 | /* OMAP3630/DM3730 variants with some accelerators disabled */ | |
3076 | SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), | |
3077 | SOC_FLAG("DM3725", DIS_SGX), | |
3078 | SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), | |
3079 | SOC_FLAG("OMAP3615/AM3715", DIS_IVA), | |
3080 | SOC_FLAG("OMAP3621", DIS_ISP), | |
3081 | ||
b6cd9be3 | 3082 | { /* sentinel */ } |
feaa8bae TL |
3083 | }; |
3084 | ||
3085 | static int sysc_add_disabled(unsigned long base) | |
3086 | { | |
3087 | struct sysc_address *disabled_module; | |
3088 | ||
3089 | disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); | |
3090 | if (!disabled_module) | |
3091 | return -ENOMEM; | |
3092 | ||
3093 | disabled_module->base = base; | |
3094 | ||
3095 | mutex_lock(&sysc_soc->list_lock); | |
3096 | list_add(&disabled_module->node, &sysc_soc->disabled_modules); | |
3097 | mutex_unlock(&sysc_soc->list_lock); | |
3098 | ||
3099 | return 0; | |
3100 | } | |
3101 | ||
3102 | /* | |
9d881361 TL |
3103 | * One time init to detect the booted SoC, disable unavailable features |
3104 | * and initialize list for optional cpu_pm notifier. | |
3105 | * | |
feaa8bae TL |
3106 | * Note that we initialize static data shared across all ti-sysc instances |
3107 | * so ddata is only used for SoC type. This can be called from module_init | |
3108 | * once we no longer need to rely on platform data. | |
3109 | */ | |
9d881361 | 3110 | static int sysc_init_static_data(struct sysc *ddata) |
feaa8bae TL |
3111 | { |
3112 | const struct soc_device_attribute *match; | |
3113 | struct ti_sysc_platform_data *pdata; | |
3114 | unsigned long features = 0; | |
5f7259a5 | 3115 | struct device_node *np; |
feaa8bae TL |
3116 | |
3117 | if (sysc_soc) | |
3118 | return 0; | |
3119 | ||
3120 | sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); | |
3121 | if (!sysc_soc) | |
3122 | return -ENOMEM; | |
3123 | ||
3124 | mutex_init(&sysc_soc->list_lock); | |
3125 | INIT_LIST_HEAD(&sysc_soc->disabled_modules); | |
9d881361 | 3126 | INIT_LIST_HEAD(&sysc_soc->restored_modules); |
feaa8bae TL |
3127 | sysc_soc->general_purpose = true; |
3128 | ||
3129 | pdata = dev_get_platdata(ddata->dev); | |
3130 | if (pdata && pdata->soc_type_gp) | |
3131 | sysc_soc->general_purpose = pdata->soc_type_gp(); | |
3132 | ||
3133 | match = soc_device_match(sysc_soc_match); | |
3134 | if (match && match->data) | |
de44bf2f | 3135 | sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data; |
feaa8bae | 3136 | |
5f7259a5 TL |
3137 | /* |
3138 | * Check and warn about possible old incomplete dtb. We now want to see | |
3139 | * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. | |
3140 | */ | |
3141 | switch (sysc_soc->soc) { | |
3142 | case SOC_AM3: | |
3143 | case SOC_AM4: | |
4adcf4c2 TL |
3144 | case SOC_4430 ... SOC_4470: |
3145 | case SOC_5430: | |
3146 | case SOC_DRA7: | |
5f7259a5 TL |
3147 | np = of_find_node_by_path("/ocp"); |
3148 | WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), | |
3149 | "ti-sysc: Incomplete old dtb, please update\n"); | |
3150 | break; | |
3151 | default: | |
3152 | break; | |
3153 | } | |
3154 | ||
4bba9bf0 TL |
3155 | /* Ignore devices that are not available on HS and EMU SoCs */ |
3156 | if (!sysc_soc->general_purpose) { | |
3157 | switch (sysc_soc->soc) { | |
3158 | case SOC_3430 ... SOC_3630: | |
3159 | sysc_add_disabled(0x48304000); /* timer12 */ | |
3160 | break; | |
a6d90e9f KH |
3161 | case SOC_AM3: |
3162 | sysc_add_disabled(0x48310000); /* rng */ | |
e879f855 | 3163 | break; |
4bba9bf0 TL |
3164 | default: |
3165 | break; | |
52fbb5aa | 3166 | } |
4bba9bf0 TL |
3167 | } |
3168 | ||
feaa8bae TL |
3169 | match = soc_device_match(sysc_soc_feat_match); |
3170 | if (!match) | |
3171 | return 0; | |
3172 | ||
3173 | if (match->data) | |
3174 | features = (unsigned long)match->data; | |
3175 | ||
3176 | /* | |
3177 | * Add disabled devices to the list based on the module base. | |
3178 | * Note that this must be done before we attempt to access the | |
3179 | * device and have module revision checks working. | |
3180 | */ | |
3181 | if (features & DIS_ISP) | |
3182 | sysc_add_disabled(0x480bd400); | |
3183 | if (features & DIS_IVA) | |
3184 | sysc_add_disabled(0x5d000000); | |
3185 | if (features & DIS_SGX) | |
3186 | sysc_add_disabled(0x50000000); | |
3187 | ||
3188 | return 0; | |
3189 | } | |
3190 | ||
9d881361 | 3191 | static void sysc_cleanup_static_data(void) |
feaa8bae | 3192 | { |
9d881361 | 3193 | struct sysc_module *restored_module; |
feaa8bae TL |
3194 | struct sysc_address *disabled_module; |
3195 | struct list_head *pos, *tmp; | |
3196 | ||
3197 | if (!sysc_soc) | |
3198 | return; | |
3199 | ||
9d881361 TL |
3200 | if (sysc_soc->nb.notifier_call) |
3201 | cpu_pm_unregister_notifier(&sysc_soc->nb); | |
3202 | ||
feaa8bae | 3203 | mutex_lock(&sysc_soc->list_lock); |
9d881361 TL |
3204 | list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) { |
3205 | restored_module = list_entry(pos, struct sysc_module, node); | |
3206 | list_del(pos); | |
3207 | kfree(restored_module); | |
3208 | } | |
feaa8bae TL |
3209 | list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { |
3210 | disabled_module = list_entry(pos, struct sysc_address, node); | |
3211 | list_del(pos); | |
3212 | kfree(disabled_module); | |
3213 | } | |
3214 | mutex_unlock(&sysc_soc->list_lock); | |
3215 | } | |
3216 | ||
3217 | static int sysc_check_disabled_devices(struct sysc *ddata) | |
3218 | { | |
3219 | struct sysc_address *disabled_module; | |
feaa8bae TL |
3220 | int error = 0; |
3221 | ||
3222 | mutex_lock(&sysc_soc->list_lock); | |
d4f1d01d | 3223 | list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) { |
feaa8bae TL |
3224 | if (ddata->module_pa == disabled_module->base) { |
3225 | dev_dbg(ddata->dev, "module disabled for this SoC\n"); | |
3226 | error = -ENODEV; | |
3227 | break; | |
3228 | } | |
3229 | } | |
3230 | mutex_unlock(&sysc_soc->list_lock); | |
3231 | ||
3232 | return error; | |
3233 | } | |
3234 | ||
6cfcd556 TL |
3235 | /* |
3236 | * Ignore timers tagged with no-reset and no-idle. These are likely in use, | |
3237 | * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks | |
3238 | * are needed, we could also look at the timer register configuration. | |
3239 | */ | |
3240 | static int sysc_check_active_timer(struct sysc *ddata) | |
3241 | { | |
a12315d6 TL |
3242 | int error; |
3243 | ||
6cfcd556 TL |
3244 | if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && |
3245 | ddata->cap->type != TI_SYSC_OMAP4_TIMER) | |
3246 | return 0; | |
3247 | ||
a12315d6 TL |
3248 | /* |
3249 | * Quirk for omap3 beagleboard revision A to B4 to use gpt12. | |
3250 | * Revision C and later are fixed with commit 23885389dbbb ("ARM: | |
3251 | * dts: Fix timer regression for beagleboard revision c"). This all | |
3252 | * can be dropped if we stop supporting old beagleboard revisions | |
3253 | * A to B4 at some point. | |
3254 | */ | |
11729caa | 3255 | if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) |
a12315d6 TL |
3256 | error = -ENXIO; |
3257 | else | |
3258 | error = -EBUSY; | |
3259 | ||
6cfcd556 TL |
3260 | if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && |
3261 | (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) | |
a12315d6 | 3262 | return error; |
6cfcd556 TL |
3263 | |
3264 | return 0; | |
3265 | } | |
3266 | ||
c4bebea8 TL |
3267 | static const struct of_device_id sysc_match_table[] = { |
3268 | { .compatible = "simple-bus", }, | |
3269 | { /* sentinel */ }, | |
3270 | }; | |
3271 | ||
0eecc636 TL |
3272 | static int sysc_probe(struct platform_device *pdev) |
3273 | { | |
ef70b0bd | 3274 | struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); |
0eecc636 TL |
3275 | struct sysc *ddata; |
3276 | int error; | |
3277 | ||
3278 | ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); | |
3279 | if (!ddata) | |
3280 | return -ENOMEM; | |
3281 | ||
2928135c TL |
3282 | ddata->offsets[SYSC_REVISION] = -ENODEV; |
3283 | ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; | |
3284 | ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; | |
0eecc636 | 3285 | ddata->dev = &pdev->dev; |
566a9b05 | 3286 | platform_set_drvdata(pdev, ddata); |
0eecc636 | 3287 | |
9d881361 | 3288 | error = sysc_init_static_data(ddata); |
feaa8bae TL |
3289 | if (error) |
3290 | return error; | |
3291 | ||
70a65240 TL |
3292 | error = sysc_init_match(ddata); |
3293 | if (error) | |
3294 | return error; | |
3295 | ||
566a9b05 TL |
3296 | error = sysc_init_dts_quirks(ddata); |
3297 | if (error) | |
a304f483 | 3298 | return error; |
566a9b05 | 3299 | |
0eecc636 TL |
3300 | error = sysc_map_and_check_registers(ddata); |
3301 | if (error) | |
a304f483 | 3302 | return error; |
0eecc636 | 3303 | |
c5a2de97 TL |
3304 | error = sysc_init_sysc_mask(ddata); |
3305 | if (error) | |
a304f483 | 3306 | return error; |
c5a2de97 TL |
3307 | |
3308 | error = sysc_init_idlemodes(ddata); | |
3309 | if (error) | |
a304f483 | 3310 | return error; |
c5a2de97 TL |
3311 | |
3312 | error = sysc_init_syss_mask(ddata); | |
3313 | if (error) | |
a304f483 | 3314 | return error; |
c5a2de97 | 3315 | |
ef70b0bd TL |
3316 | error = sysc_init_pdata(ddata); |
3317 | if (error) | |
a304f483 | 3318 | return error; |
ef70b0bd | 3319 | |
42b9c5c9 TL |
3320 | sysc_init_early_quirks(ddata); |
3321 | ||
feaa8bae TL |
3322 | error = sysc_check_disabled_devices(ddata); |
3323 | if (error) | |
3324 | return error; | |
3325 | ||
6cfcd556 | 3326 | error = sysc_check_active_timer(ddata); |
06a089ef | 3327 | if (error == -ENXIO) |
3ff340e2 | 3328 | ddata->reserved = true; |
06a089ef TL |
3329 | else if (error) |
3330 | return error; | |
6cfcd556 | 3331 | |
42b9c5c9 TL |
3332 | error = sysc_get_clocks(ddata); |
3333 | if (error) | |
3334 | return error; | |
3335 | ||
5062236e TL |
3336 | error = sysc_init_resets(ddata); |
3337 | if (error) | |
a304f483 | 3338 | goto unprepare; |
566a9b05 TL |
3339 | |
3340 | error = sysc_init_module(ddata); | |
3341 | if (error) | |
3342 | goto unprepare; | |
3343 | ||
1a5cd7c2 | 3344 | pm_runtime_enable(ddata->dev); |
cea08169 | 3345 | error = pm_runtime_resume_and_get(ddata->dev); |
0eecc636 | 3346 | if (error < 0) { |
0eecc636 TL |
3347 | pm_runtime_disable(ddata->dev); |
3348 | goto unprepare; | |
3349 | } | |
3350 | ||
cdc56c11 | 3351 | /* Balance use counts as PM runtime should have enabled these all */ |
cdc56c11 TK |
3352 | if (!(ddata->cfg.quirks & |
3353 | (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { | |
3354 | sysc_disable_main_clocks(ddata); | |
3355 | sysc_disable_opt_clocks(ddata); | |
3356 | sysc_clkdm_allow_idle(ddata); | |
3357 | } | |
3358 | ||
4097c9a6 TL |
3359 | if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) |
3360 | reset_control_assert(ddata->rsts); | |
3361 | ||
0eecc636 TL |
3362 | sysc_show_registers(ddata); |
3363 | ||
2c355ff6 | 3364 | ddata->dev->type = &sysc_device_type; |
3ff340e2 TL |
3365 | |
3366 | if (!ddata->reserved) { | |
3367 | error = of_platform_populate(ddata->dev->of_node, | |
3368 | sysc_match_table, | |
3369 | pdata ? pdata->auxdata : NULL, | |
3370 | ddata->dev); | |
3371 | if (error) | |
3372 | goto err; | |
3373 | } | |
0eecc636 | 3374 | |
76f0f772 TL |
3375 | INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); |
3376 | ||
3377 | /* At least earlycon won't survive without deferred idle */ | |
d098913a TL |
3378 | if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | |
3379 | SYSC_QUIRK_NO_IDLE_ON_INIT | | |
76f0f772 TL |
3380 | SYSC_QUIRK_NO_RESET_ON_INIT)) { |
3381 | schedule_delayed_work(&ddata->idle_work, 3000); | |
3382 | } else { | |
3383 | pm_runtime_put(&pdev->dev); | |
3384 | } | |
0eecc636 | 3385 | |
9d881361 TL |
3386 | if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST) |
3387 | sysc_add_restored(ddata); | |
3388 | ||
0eecc636 TL |
3389 | return 0; |
3390 | ||
3391 | err: | |
0eecc636 TL |
3392 | pm_runtime_put_sync(&pdev->dev); |
3393 | pm_runtime_disable(&pdev->dev); | |
3394 | unprepare: | |
3395 | sysc_unprepare(ddata); | |
3396 | ||
3397 | return error; | |
3398 | } | |
3399 | ||
684be5a4 TL |
3400 | static int sysc_remove(struct platform_device *pdev) |
3401 | { | |
3402 | struct sysc *ddata = platform_get_drvdata(pdev); | |
3403 | int error; | |
3404 | ||
c337125b TL |
3405 | /* Device can still be enabled, see deferred idle quirk in probe */ |
3406 | if (cancel_delayed_work_sync(&ddata->idle_work)) | |
3407 | ti_sysc_idle(&ddata->idle_work.work); | |
76f0f772 | 3408 | |
cea08169 | 3409 | error = pm_runtime_resume_and_get(ddata->dev); |
684be5a4 | 3410 | if (error < 0) { |
684be5a4 TL |
3411 | pm_runtime_disable(ddata->dev); |
3412 | goto unprepare; | |
3413 | } | |
3414 | ||
3415 | of_platform_depopulate(&pdev->dev); | |
3416 | ||
684be5a4 TL |
3417 | pm_runtime_put_sync(&pdev->dev); |
3418 | pm_runtime_disable(&pdev->dev); | |
a7b5d7c4 TL |
3419 | |
3420 | if (!reset_control_status(ddata->rsts)) | |
3421 | reset_control_assert(ddata->rsts); | |
684be5a4 TL |
3422 | |
3423 | unprepare: | |
3424 | sysc_unprepare(ddata); | |
3425 | ||
3426 | return 0; | |
3427 | } | |
3428 | ||
0eecc636 | 3429 | static const struct of_device_id sysc_match[] = { |
70a65240 TL |
3430 | { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, |
3431 | { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, | |
3432 | { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, | |
3433 | { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, | |
3434 | { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, | |
3435 | { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, | |
3436 | { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, | |
3437 | { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, | |
3438 | { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, | |
3439 | { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, | |
3440 | { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, | |
2c63a833 | 3441 | { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, |
70a65240 TL |
3442 | { .compatible = "ti,sysc-usb-host-fs", |
3443 | .data = &sysc_omap4_usb_host_fs, }, | |
7f35e63d | 3444 | { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, |
b2745d92 | 3445 | { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, |
0eecc636 TL |
3446 | { }, |
3447 | }; | |
3448 | MODULE_DEVICE_TABLE(of, sysc_match); | |
3449 | ||
3450 | static struct platform_driver sysc_driver = { | |
3451 | .probe = sysc_probe, | |
684be5a4 | 3452 | .remove = sysc_remove, |
0eecc636 TL |
3453 | .driver = { |
3454 | .name = "ti-sysc", | |
3455 | .of_match_table = sysc_match, | |
3456 | .pm = &sysc_pm_ops, | |
3457 | }, | |
3458 | }; | |
2c355ff6 TL |
3459 | |
3460 | static int __init sysc_init(void) | |
3461 | { | |
3462 | bus_register_notifier(&platform_bus_type, &sysc_nb); | |
3463 | ||
3464 | return platform_driver_register(&sysc_driver); | |
3465 | } | |
3466 | module_init(sysc_init); | |
3467 | ||
3468 | static void __exit sysc_exit(void) | |
3469 | { | |
3470 | bus_unregister_notifier(&platform_bus_type, &sysc_nb); | |
3471 | platform_driver_unregister(&sysc_driver); | |
9d881361 | 3472 | sysc_cleanup_static_data(); |
2c355ff6 TL |
3473 | } |
3474 | module_exit(sysc_exit); | |
0eecc636 TL |
3475 | |
3476 | MODULE_DESCRIPTION("TI sysc interconnect target driver"); | |
3477 | MODULE_LICENSE("GPL v2"); |