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Merge tag 'pci-v5.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[linux-2.6-block.git] / drivers / bus / ti-sysc.c
CommitLineData
54d66222 1// SPDX-License-Identifier: GPL-2.0
0eecc636
TL		 2/*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
0eecc636
TL		 4 */
5
6#include <linux/io.h>
7#include <linux/clk.h>
2c355ff6 8#include <linux/clkdev.h>
9d881361 9#include <linux/cpu_pm.h>
a885f0fe 10#include <linux/delay.h>
feaa8bae 11#include <linux/list.h>
0eecc636
TL		 12#include <linux/module.h>
13#include <linux/platform_device.h>
a885f0fe 14#include <linux/pm_domain.h>
0eecc636 15#include <linux/pm_runtime.h>
5062236e 16#include <linux/reset.h>
0eecc636
TL		 17#include <linux/of_address.h>
18#include <linux/of_platform.h>
2c355ff6 19#include <linux/slab.h>
feaa8bae 20#include <linux/sys_soc.h>
b3e94318 21#include <linux/timekeeping.h>
596e7955 22#include <linux/iopoll.h>
2c355ff6 23
70a65240
TL		 24#include <linux/platform_data/ti-sysc.h>
25
26#include <dt-bindings/bus/ti-sysc.h>
0eecc636 27
feaa8bae
TL		 28#define DIS_ISP BIT(2)
29#define DIS_IVA BIT(1)
30#define DIS_SGX BIT(0)
31
32#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
33
e4a8fc05 34#define MAX_MODULE_SOFTRESET_WAIT 10000
596e7955 35
feaa8bae
TL		 36enum sysc_soc {
37 SOC_UNKNOWN,
38 SOC_2420,
39 SOC_2430,
40 SOC_3430,
41 SOC_3630,
42 SOC_4430,
43 SOC_4460,
44 SOC_4470,
45 SOC_5430,
46 SOC_AM3,
47 SOC_AM4,
48 SOC_DRA7,
49};
50
51struct sysc_address {
52 unsigned long base;
53 struct list_head node;
54};
55
9d881361
TL		 56struct sysc_module {
57 struct sysc *ddata;
58 struct list_head node;
59};
60
feaa8bae
TL		 61struct sysc_soc_info {
62 unsigned long general_purpose:1;
63 enum sysc_soc soc;
9d881361 64 struct mutex list_lock; /* disabled and restored modules list lock */
feaa8bae 65 struct list_head disabled_modules;
9d881361
TL		 66 struct list_head restored_modules;
67 struct notifier_block nb;
feaa8bae 68};
0eecc636
TL		 69
70enum sysc_clocks {
71 SYSC_FCK,
72 SYSC_ICK,
09dfe581
TL		 73 SYSC_OPTFCK0,
74 SYSC_OPTFCK1,
75 SYSC_OPTFCK2,
76 SYSC_OPTFCK3,
77 SYSC_OPTFCK4,
78 SYSC_OPTFCK5,
79 SYSC_OPTFCK6,
80 SYSC_OPTFCK7,
0eecc636
TL		 81 SYSC_MAX_CLOCKS,
82};
83
feaa8bae
TL		 84static struct sysc_soc_info *sysc_soc;
85static const char * const reg_names[] = { "rev", "sysc", "syss", };
a54275f4
TL		 86static const char * const clock_names[SYSC_MAX_CLOCKS] = {
87 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
88 "opt5", "opt6", "opt7",
89};
0eecc636 90
c5a2de97
TL		 91#define SYSC_IDLEMODE_MASK 3
92#define SYSC_CLOCKACTIVITY_MASK 3
93
0eecc636
TL		 94/**
95 * struct sysc - TI sysc interconnect target module registers and capabilities
96 * @dev: struct device pointer
97 * @module_pa: physical address of the interconnect target module
98 * @module_size: size of the interconnect target module
99 * @module_va: virtual address of the interconnect target module
100 * @offsets: register offsets from module base
b58056da 101 * @mdata: ti-sysc to hwmod translation data for a module
0eecc636 102 * @clocks: clocks used by the interconnect target module
09dfe581
TL		 103 * @clock_roles: clock role names for the found clocks
104 * @nr_clocks: number of clocks used by the interconnect target module
b58056da 105 * @rsts: resets used by the interconnect target module
0eecc636 106 * @legacy_mode: configured for legacy mode if set
70a65240
TL		 107 * @cap: interconnect target module capabilities
108 * @cfg: interconnect target module configuration
b58056da 109 * @cookie: data used by legacy platform callbacks
566a9b05
TL		 110 * @name: name if available
111 * @revision: interconnect target module revision
3ff340e2 112 * @reserved: target module is reserved and already in use
b58056da 113 * @enabled: sysc runtime enabled status
62020f23 114 * @needs_resume: runtime resume needed on resume from suspend
b58056da
SA		 115 * @child_needs_resume: runtime resume needed for child on resume from suspend
116 * @disable_on_idle: status flag used for disabling modules with resets
117 * @idle_work: work structure used to perform delayed idle on a module
e64c021f
TL		 118 * @pre_reset_quirk: module specific pre-reset quirk
119 * @post_reset_quirk: module specific post-reset quirk
4e23be47 120 * @reset_done_quirk: module specific reset done quirk
d7f563db 121 * @module_enable_quirk: module specific enable quirk
c7d8669f 122 * @module_disable_quirk: module specific disable quirk
e8639e1c
TL		 123 * @module_unlock_quirk: module specific sysconfig unlock quirk
124 * @module_lock_quirk: module specific sysconfig lock quirk
0eecc636
TL		 125 */
126struct sysc {
127 struct device *dev;
128 u64 module_pa;
129 u32 module_size;
130 void __iomem *module_va;
131 int offsets[SYSC_MAX_REGS];
a3e92e7b 132 struct ti_sysc_module_data *mdata;
09dfe581
TL		 133 struct clk **clocks;
134 const char **clock_roles;
135 int nr_clocks;
5062236e 136 struct reset_control *rsts;
0eecc636 137 const char *legacy_mode;
70a65240
TL		 138 const struct sysc_capabilities *cap;
139 struct sysc_config cfg;
ef70b0bd 140 struct ti_sysc_cookie cookie;
566a9b05
TL		 141 const char *name;
142 u32 revision;
95ec14fa 143 u32 sysconfig;
3ff340e2 144 unsigned int reserved:1;
8383e259
TL		 145 unsigned int enabled:1;
146 unsigned int needs_resume:1;
147 unsigned int child_needs_resume:1;
76f0f772 148 struct delayed_work idle_work;
e64c021f
TL		 149 void (*pre_reset_quirk)(struct sysc *sysc);
150 void (*post_reset_quirk)(struct sysc *sysc);
4e23be47 151 void (*reset_done_quirk)(struct sysc *sysc);
d7f563db 152 void (*module_enable_quirk)(struct sysc *sysc);
c7d8669f 153 void (*module_disable_quirk)(struct sysc *sysc);
e8639e1c
TL		 154 void (*module_unlock_quirk)(struct sysc *sysc);
155 void (*module_lock_quirk)(struct sysc *sysc);
0eecc636
TL		 156};
157
4014c08b
TL		 158static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
159 bool is_child);
6a52bc2b 160static int sysc_reset(struct sysc *ddata);
4014c08b 161
b7182b42 162static void sysc_write(struct sysc *ddata, int offset, u32 value)
596e7955 163{
5aa91295
TL		 164 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
165 writew_relaxed(value & 0xffff, ddata->module_va + offset);
166
167 /* Only i2c revision has LO and HI register with stride of 4 */
168 if (ddata->offsets[SYSC_REVISION] >= 0 &&
169 offset == ddata->offsets[SYSC_REVISION]) {
170 u16 hi = value >> 16;
171
172 writew_relaxed(hi, ddata->module_va + offset + 4);
173 }
174
175 return;
176 }
177
596e7955
FA		 178 writel_relaxed(value, ddata->module_va + offset);
179}
180
566a9b05
TL		 181static u32 sysc_read(struct sysc *ddata, int offset)
182{
183 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
184 u32 val;
185
186 val = readw_relaxed(ddata->module_va + offset);
5aa91295
TL		 187
188 /* Only i2c revision has LO and HI register with stride of 4 */
189 if (ddata->offsets[SYSC_REVISION] >= 0 &&
190 offset == ddata->offsets[SYSC_REVISION]) {
191 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
192
193 val |= tmp << 16;
194 }
566a9b05
TL		 195
196 return val;
197 }
198
199 return readl_relaxed(ddata->module_va + offset);
200}
201
09dfe581
TL		 202static bool sysc_opt_clks_needed(struct sysc *ddata)
203{
204 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
205}
206
0eecc636
TL		 207static u32 sysc_read_revision(struct sysc *ddata)
208{
566a9b05
TL		 209 int offset = ddata->offsets[SYSC_REVISION];
210
211 if (offset < 0)
212 return 0;
213
214 return sysc_read(ddata, offset);
0eecc636
TL		 215}
216
e0db94fe
TL		 217static u32 sysc_read_sysconfig(struct sysc *ddata)
218{
219 int offset = ddata->offsets[SYSC_SYSCONFIG];
220
221 if (offset < 0)
222 return 0;
223
224 return sysc_read(ddata, offset);
225}
226
227static u32 sysc_read_sysstatus(struct sysc *ddata)
228{
229 int offset = ddata->offsets[SYSC_SYSSTATUS];
230
231 if (offset < 0)
232 return 0;
233
234 return sysc_read(ddata, offset);
235}
236
b3e94318 237static int sysc_poll_reset_sysstatus(struct sysc *ddata)
d46f9fbe 238{
b3e94318
TL		 239 int error, retries;
240 u32 syss_done, rstval;
d46f9fbe
TL		 241
242 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
243 syss_done = 0;
244 else
245 syss_done = ddata->cfg.syss_mask;
246
b3e94318 247 if (likely(!timekeeping_suspended)) {
9f911392
TL		 248 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
249 rstval, (rstval & ddata->cfg.syss_mask) ==
250 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
b3e94318
TL		 251 } else {
252 retries = MAX_MODULE_SOFTRESET_WAIT;
253 while (retries--) {
254 rstval = sysc_read_sysstatus(ddata);
255 if ((rstval & ddata->cfg.syss_mask) == syss_done)
256 return 0;
257 udelay(2); /* Account for udelay flakeyness */
258 }
259 error = -ETIMEDOUT;
260 }
261
262 return error;
263}
264
265static int sysc_poll_reset_sysconfig(struct sysc *ddata)
266{
267 int error, retries;
268 u32 sysc_mask, rstval;
d46f9fbe 269
b3e94318 270 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
d46f9fbe 271
b3e94318 272 if (likely(!timekeeping_suspended)) {
9f911392
TL		 273 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
274 rstval, !(rstval & sysc_mask),
275 100, MAX_MODULE_SOFTRESET_WAIT);
b3e94318
TL		 276 } else {
277 retries = MAX_MODULE_SOFTRESET_WAIT;
278 while (retries--) {
279 rstval = sysc_read_sysconfig(ddata);
280 if (!(rstval & sysc_mask))
281 return 0;
282 udelay(2); /* Account for udelay flakeyness */
283 }
284 error = -ETIMEDOUT;
d46f9fbe
TL		 285 }
286
287 return error;
288}
289
b3e94318
TL		 290/* Poll on reset status */
291static int sysc_wait_softreset(struct sysc *ddata)
292{
293 int syss_offset, error = 0;
294
295 if (ddata->cap->regbits->srst_shift < 0)
296 return 0;
297
298 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
299
300 if (syss_offset >= 0)
301 error = sysc_poll_reset_sysstatus(ddata);
302 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
303 error = sysc_poll_reset_sysconfig(ddata);
304
305 return error;
306}
307
a54275f4
TL		 308static int sysc_add_named_clock_from_child(struct sysc *ddata,
309 const char *name,
310 const char *optfck_name)
311{
312 struct device_node *np = ddata->dev->of_node;
313 struct device_node *child;
314 struct clk_lookup *cl;
315 struct clk *clock;
316 const char *n;
317
318 if (name)
319 n = name;
320 else
321 n = optfck_name;
322
323 /* Does the clock alias already exist? */
324 clock = of_clk_get_by_name(np, n);
325 if (!IS_ERR(clock)) {
326 clk_put(clock);
327
328 return 0;
329 }
330
331 child = of_get_next_available_child(np, NULL);
332 if (!child)
333 return -ENODEV;
334
335 clock = devm_get_clk_from_child(ddata->dev, child, name);
336 if (IS_ERR(clock))
337 return PTR_ERR(clock);
338
339 /*
340 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
341 * limit for clk_get(). If cl ever needs to be freed, it should be done
342 * with clkdev_drop().
343 */
d995d3d0 344 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
a54275f4
TL		 345 if (!cl)
346 return -ENOMEM;
347
348 cl->con_id = n;
349 cl->dev_id = dev_name(ddata->dev);
350 cl->clk = clock;
351 clkdev_add(cl);
352
353 clk_put(clock);
354
355 return 0;
356}
357
358static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
359{
360 const char *optfck_name;
361 int error, index;
362
363 if (ddata->nr_clocks < SYSC_OPTFCK0)
364 index = SYSC_OPTFCK0;
365 else
366 index = ddata->nr_clocks;
367
368 if (name)
369 optfck_name = name;
370 else
371 optfck_name = clock_names[index];
372
373 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
374 if (error)
375 return error;
376
377 ddata->clock_roles[index] = optfck_name;
378 ddata->nr_clocks++;
379
380 return 0;
381}
382
09dfe581 383static int sysc_get_one_clock(struct sysc *ddata, const char *name)
0eecc636 384{
09dfe581
TL		 385 int error, i, index = -ENODEV;
386
387 if (!strncmp(clock_names[SYSC_FCK], name, 3))
388 index = SYSC_FCK;
389 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
390 index = SYSC_ICK;
391
392 if (index < 0) {
393 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
c97c8620 394 if (!ddata->clocks[i]) {
09dfe581
TL		 395 index = i;
396 break;
397 }
398 }
399 }
0eecc636 400
09dfe581
TL		 401 if (index < 0) {
402 dev_err(ddata->dev, "clock %s not added\n", name);
403 return index;
0eecc636 404 }
0eecc636
TL		 405
406 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
407 if (IS_ERR(ddata->clocks[index])) {
0eecc636
TL		 408 dev_err(ddata->dev, "clock get error for %s: %li\n",
409 name, PTR_ERR(ddata->clocks[index]));
410
411 return PTR_ERR(ddata->clocks[index]);
412 }
413
414 error = clk_prepare(ddata->clocks[index]);
415 if (error) {
416 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
417 name, error);
418
419 return error;
420 }
421
422 return 0;
423}
424
425static int sysc_get_clocks(struct sysc *ddata)
426{
09dfe581
TL		 427 struct device_node *np = ddata->dev->of_node;
428 struct property *prop;
429 const char *name;
430 int nr_fck = 0, nr_ick = 0, i, error = 0;
431
20749051 432 ddata->clock_roles = devm_kcalloc(ddata->dev,
09dfe581 433 SYSC_MAX_CLOCKS,
20749051 434 sizeof(*ddata->clock_roles),
09dfe581
TL		 435 GFP_KERNEL);
436 if (!ddata->clock_roles)
437 return -ENOMEM;
438
439 of_property_for_each_string(np, "clock-names", prop, name) {
440 if (!strncmp(clock_names[SYSC_FCK], name, 3))
441 nr_fck++;
442 if (!strncmp(clock_names[SYSC_ICK], name, 3))
443 nr_ick++;
444 ddata->clock_roles[ddata->nr_clocks] = name;
445 ddata->nr_clocks++;
446 }
447
448 if (ddata->nr_clocks < 1)
449 return 0;
450
a54275f4
TL		 451 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
452 error = sysc_init_ext_opt_clock(ddata, NULL);
453 if (error)
454 return error;
455 }
456
09dfe581
TL		 457 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
458 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
459
460 return -EINVAL;
461 }
462
463 if (nr_fck > 1 || nr_ick > 1) {
464 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
0eecc636 465
09dfe581
TL		 466 return -EINVAL;
467 }
468
2c81f0f6
TL		 469 /* Always add a slot for main clocks fck and ick even if unused */
470 if (!nr_fck)
471 ddata->nr_clocks++;
472 if (!nr_ick)
473 ddata->nr_clocks++;
474
20749051
KC		 475 ddata->clocks = devm_kcalloc(ddata->dev,
476 ddata->nr_clocks, sizeof(*ddata->clocks),
09dfe581
TL		 477 GFP_KERNEL);
478 if (!ddata->clocks)
479 return -ENOMEM;
480
7b4f8ac2
TL		 481 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
482 const char *name = ddata->clock_roles[i];
483
484 if (!name)
485 continue;
486
487 error = sysc_get_one_clock(ddata, name);
2783d063 488 if (error)
0eecc636
TL		 489 return error;
490 }
491
492 return 0;
493}
494
d878970f
TL		 495static int sysc_enable_main_clocks(struct sysc *ddata)
496{
497 struct clk *clock;
498 int i, error;
499
500 if (!ddata->clocks)
501 return 0;
502
503 for (i = 0; i < SYSC_OPTFCK0; i++) {
504 clock = ddata->clocks[i];
505
506 /* Main clocks may not have ick */
507 if (IS_ERR_OR_NULL(clock))
508 continue;
509
510 error = clk_enable(clock);
511 if (error)
512 goto err_disable;
513 }
514
515 return 0;
516
517err_disable:
518 for (i--; i >= 0; i--) {
519 clock = ddata->clocks[i];
520
521 /* Main clocks may not have ick */
522 if (IS_ERR_OR_NULL(clock))
523 continue;
524
525 clk_disable(clock);
526 }
527
528 return error;
529}
530
531static void sysc_disable_main_clocks(struct sysc *ddata)
532{
533 struct clk *clock;
534 int i;
535
536 if (!ddata->clocks)
537 return;
538
539 for (i = 0; i < SYSC_OPTFCK0; i++) {
540 clock = ddata->clocks[i];
541 if (IS_ERR_OR_NULL(clock))
542 continue;
543
544 clk_disable(clock);
545 }
546}
547
548static int sysc_enable_opt_clocks(struct sysc *ddata)
549{
550 struct clk *clock;
551 int i, error;
552
2c81f0f6 553 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
d878970f
TL		 554 return 0;
555
556 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
557 clock = ddata->clocks[i];
558
559 /* Assume no holes for opt clocks */
560 if (IS_ERR_OR_NULL(clock))
561 return 0;
562
563 error = clk_enable(clock);
564 if (error)
565 goto err_disable;
566 }
567
568 return 0;
569
570err_disable:
571 for (i--; i >= 0; i--) {
572 clock = ddata->clocks[i];
573 if (IS_ERR_OR_NULL(clock))
574 continue;
575
576 clk_disable(clock);
577 }
578
579 return error;
580}
581
582static void sysc_disable_opt_clocks(struct sysc *ddata)
583{
584 struct clk *clock;
585 int i;
586
2c81f0f6 587 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
d878970f
TL		 588 return;
589
590 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
591 clock = ddata->clocks[i];
592
593 /* Assume no holes for opt clocks */
594 if (IS_ERR_OR_NULL(clock))
595 return;
596
597 clk_disable(clock);
598 }
599}
600
2b2f7def
TL		 601static void sysc_clkdm_deny_idle(struct sysc *ddata)
602{
603 struct ti_sysc_platform_data *pdata;
604
94f63457 605 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
2b2f7def
TL		 606 return;
607
608 pdata = dev_get_platdata(ddata->dev);
609 if (pdata && pdata->clkdm_deny_idle)
610 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
611}
612
613static void sysc_clkdm_allow_idle(struct sysc *ddata)
614{
615 struct ti_sysc_platform_data *pdata;
616
94f63457 617 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
2b2f7def
TL		 618 return;
619
620 pdata = dev_get_platdata(ddata->dev);
621 if (pdata && pdata->clkdm_allow_idle)
622 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
623}
624
5062236e 625/**
b11c1ea1 626 * sysc_init_resets - init rstctrl reset line if configured
5062236e
TL		 627 * @ddata: device driver data
628 *
b11c1ea1 629 * See sysc_rstctrl_reset_deassert().
5062236e
TL		 630 */
631static int sysc_init_resets(struct sysc *ddata)
632{
5062236e 633 ddata->rsts =
bb88b86c 634 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
5062236e 635
3f2c4205 636 return PTR_ERR_OR_ZERO(ddata->rsts);
5062236e
TL		 637}
638
0eecc636
TL		 639/**
640 * sysc_parse_and_check_child_range - parses module IO region from ranges
641 * @ddata: device driver data
642 *
643 * In general we only need rev, syss, and sysc registers and not the whole
644 * module range. But we do want the offsets for these registers from the
645 * module base. This allows us to check them against the legacy hwmod
646 * platform data. Let's also check the ranges are configured properly.
647 */
648static int sysc_parse_and_check_child_range(struct sysc *ddata)
649{
650 struct device_node *np = ddata->dev->of_node;
651 const __be32 *ranges;
652 u32 nr_addr, nr_size;
653 int len, error;
654
655 ranges = of_get_property(np, "ranges", &len);
656 if (!ranges) {
657 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
658
659 return -ENOENT;
660 }
661
662 len /= sizeof(*ranges);
663
664 if (len < 3) {
665 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
666
667 return -EINVAL;
668 }
669
670 error = of_property_read_u32(np, "#address-cells", &nr_addr);
671 if (error)
672 return -ENOENT;
673
674 error = of_property_read_u32(np, "#size-cells", &nr_size);
675 if (error)
676 return -ENOENT;
677
678 if (nr_addr != 1 || nr_size != 1) {
679 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
680
681 return -EINVAL;
682 }
683
684 ranges++;
685 ddata->module_pa = of_translate_address(np, ranges++);
686 ddata->module_size = be32_to_cpup(ranges);
687
0eecc636
TL		 688 return 0;
689}
690
4700a007
TL		 691/* Interconnect instances to probe before l4_per instances */
692static struct resource early_bus_ranges[] = {
693 /* am3/4 l4_wkup */
694 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
695 /* omap4/5 and dra7 l4_cfg */
696 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
697 /* omap4 l4_wkup */
698 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
699 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
700 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
701};
702
703static atomic_t sysc_defer = ATOMIC_INIT(10);
704
705/**
706 * sysc_defer_non_critical - defer non_critical interconnect probing
707 * @ddata: device driver data
708 *
709 * We want to probe l4_cfg and l4_wkup interconnect instances before any
710 * l4_per instances as l4_per instances depend on resources on l4_cfg and
711 * l4_wkup interconnects.
712 */
713static int sysc_defer_non_critical(struct sysc *ddata)
714{
715 struct resource *res;
716 int i;
717
718 if (!atomic_read(&sysc_defer))
719 return 0;
720
721 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
722 res = &early_bus_ranges[i];
723 if (ddata->module_pa >= res->start &&
724 ddata->module_pa <= res->end) {
725 atomic_set(&sysc_defer, 0);
726
727 return 0;
728 }
729 }
730
731 atomic_dec_if_positive(&sysc_defer);
732
733 return -EPROBE_DEFER;
734}
735
3bb37c8e
TL		 736static struct device_node *stdout_path;
737
738static void sysc_init_stdout_path(struct sysc *ddata)
739{
740 struct device_node *np = NULL;
741 const char *uart;
742
743 if (IS_ERR(stdout_path))
744 return;
745
746 if (stdout_path)
747 return;
748
749 np = of_find_node_by_path("/chosen");
750 if (!np)
751 goto err;
752
753 uart = of_get_property(np, "stdout-path", NULL);
754 if (!uart)
755 goto err;
756
757 np = of_find_node_by_path(uart);
758 if (!np)
759 goto err;
760
761 stdout_path = np;
762
763 return;
764
765err:
766 stdout_path = ERR_PTR(-ENODEV);
767}
768
769static void sysc_check_quirk_stdout(struct sysc *ddata,
770 struct device_node *np)
771{
772 sysc_init_stdout_path(ddata);
773 if (np != stdout_path)
774 return;
775
776 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
777 SYSC_QUIRK_NO_RESET_ON_INIT;
778}
779
0eecc636
TL		 780/**
781 * sysc_check_one_child - check child configuration
782 * @ddata: device driver data
783 * @np: child device node
784 *
785 * Let's avoid messy situations where we have new interconnect target
786 * node but children have "ti,hwmods". These belong to the interconnect
787 * target node and are managed by this driver.
788 */
c6e78d70
ND		 789static void sysc_check_one_child(struct sysc *ddata,
790 struct device_node *np)
0eecc636
TL		 791{
792 const char *name;
793
794 name = of_get_property(np, "ti,hwmods", NULL);
7320fd32 795 if (name && !of_device_is_compatible(np, "ti,sysc"))
0eecc636
TL		 796 dev_warn(ddata->dev, "really a child ti,hwmods property?");
797
3bb37c8e 798 sysc_check_quirk_stdout(ddata, np);
4014c08b 799 sysc_parse_dts_quirks(ddata, np, true);
0eecc636
TL		 800}
801
c6e78d70 802static void sysc_check_children(struct sysc *ddata)
0eecc636
TL		 803{
804 struct device_node *child;
0eecc636 805
c6e78d70
ND		 806 for_each_child_of_node(ddata->dev->of_node, child)
807 sysc_check_one_child(ddata, child);
0eecc636
TL		 808}
809
a7199e2b
TL		 810/*
811 * So far only I2C uses 16-bit read access with clockactivity with revision
812 * in two registers with stride of 4. We can detect this based on the rev
813 * register size to configure things far enough to be able to properly read
814 * the revision register.
815 */
816static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
817{
dd57ac1e 818 if (resource_size(res) == 8)
a7199e2b 819 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
a7199e2b
TL		 820}
821
0eecc636
TL		 822/**
823 * sysc_parse_one - parses the interconnect target module registers
824 * @ddata: device driver data
825 * @reg: register to parse
826 */
827static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
828{
829 struct resource *res;
830 const char *name;
831
832 switch (reg) {
833 case SYSC_REVISION:
834 case SYSC_SYSCONFIG:
835 case SYSC_SYSSTATUS:
836 name = reg_names[reg];
837 break;
838 default:
839 return -EINVAL;
840 }
841
842 res = platform_get_resource_byname(to_platform_device(ddata->dev),
843 IORESOURCE_MEM, name);
844 if (!res) {
0eecc636
TL		 845 ddata->offsets[reg] = -ENODEV;
846
847 return 0;
848 }
849
850 ddata->offsets[reg] = res->start - ddata->module_pa;
a7199e2b
TL		 851 if (reg == SYSC_REVISION)
852 sysc_check_quirk_16bit(ddata, res);
0eecc636
TL		 853
854 return 0;
855}
856
857static int sysc_parse_registers(struct sysc *ddata)
858{
859 int i, error;
860
861 for (i = 0; i < SYSC_MAX_REGS; i++) {
862 error = sysc_parse_one(ddata, i);
863 if (error)
864 return error;
865 }
866
867 return 0;
868}
869
870/**
871 * sysc_check_registers - check for misconfigured register overlaps
872 * @ddata: device driver data
873 */
874static int sysc_check_registers(struct sysc *ddata)
875{
876 int i, j, nr_regs = 0, nr_matches = 0;
877
878 for (i = 0; i < SYSC_MAX_REGS; i++) {
879 if (ddata->offsets[i] < 0)
880 continue;
881
882 if (ddata->offsets[i] > (ddata->module_size - 4)) {
883 dev_err(ddata->dev, "register outside module range");
884
885 return -EINVAL;
886 }
887
888 for (j = 0; j < SYSC_MAX_REGS; j++) {
889 if (ddata->offsets[j] < 0)
890 continue;
891
892 if (ddata->offsets[i] == ddata->offsets[j])
893 nr_matches++;
894 }
895 nr_regs++;
896 }
897
0eecc636
TL		 898 if (nr_matches > nr_regs) {
899 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
900 nr_regs, nr_matches);
901
902 return -EINVAL;
903 }
904
905 return 0;
906}
907
908/**
4e001853 909 * sysc_ioremap - ioremap register space for the interconnect target module
0ef8e3bb 910 * @ddata: device driver data
0eecc636
TL		 911 *
912 * Note that the interconnect target module registers can be anywhere
0ef8e3bb
TL		 913 * within the interconnect target module range. For example, SGX has
914 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
915 * has them at offset 0x1200 in the CPSW_WR child. Usually the
916 * the interconnect target module registers are at the beginning of
917 * the module range though.
0eecc636
TL		 918 */
919static int sysc_ioremap(struct sysc *ddata)
920{
0ef8e3bb 921 int size;
0eecc636 922
e4f50c8d
TL		 923 if (ddata->offsets[SYSC_REVISION] < 0 &&
924 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
925 ddata->offsets[SYSC_SYSSTATUS] < 0) {
926 size = ddata->module_size;
927 } else {
928 size = max3(ddata->offsets[SYSC_REVISION],
929 ddata->offsets[SYSC_SYSCONFIG],
930 ddata->offsets[SYSC_SYSSTATUS]);
0ef8e3bb 931
4e23be47
TL		 932 if (size < SZ_1K)
933 size = SZ_1K;
934
e4f50c8d 935 if ((size + sizeof(u32)) > ddata->module_size)
4e23be47 936 size = ddata->module_size;
e4f50c8d 937 }
0eecc636
TL		 938
939 ddata->module_va = devm_ioremap(ddata->dev,
940 ddata->module_pa,
0ef8e3bb 941 size + sizeof(u32));
0eecc636
TL		 942 if (!ddata->module_va)
943 return -EIO;
944
945 return 0;
946}
947
948/**
949 * sysc_map_and_check_registers - ioremap and check device registers
950 * @ddata: device driver data
951 */
952static int sysc_map_and_check_registers(struct sysc *ddata)
953{
2928135c 954 struct device_node *np = ddata->dev->of_node;
0eecc636
TL		 955 int error;
956
957 error = sysc_parse_and_check_child_range(ddata);
958 if (error)
959 return error;
960
4700a007
TL		 961 error = sysc_defer_non_critical(ddata);
962 if (error)
963 return error;
964
c6e78d70 965 sysc_check_children(ddata);
0eecc636 966
7bad5af8
TL		 967 if (!of_get_property(np, "reg", NULL))
968 return 0;
969
0eecc636
TL		 970 error = sysc_parse_registers(ddata);
971 if (error)
972 return error;
973
974 error = sysc_ioremap(ddata);
975 if (error)
976 return error;
977
978 error = sysc_check_registers(ddata);
979 if (error)
980 return error;
981
982 return 0;
983}
984
985/**
986 * sysc_show_rev - read and show interconnect target module revision
987 * @bufp: buffer to print the information to
988 * @ddata: device driver data
989 */
990static int sysc_show_rev(char *bufp, struct sysc *ddata)
991{
566a9b05 992 int len;
0eecc636
TL		 993
994 if (ddata->offsets[SYSC_REVISION] < 0)
995 return sprintf(bufp, ":NA");
996
566a9b05 997 len = sprintf(bufp, ":%08x", ddata->revision);
0eecc636
TL		 998
999 return len;
1000}
1001
1002static int sysc_show_reg(struct sysc *ddata,
1003 char *bufp, enum sysc_registers reg)
1004{
1005 if (ddata->offsets[reg] < 0)
1006 return sprintf(bufp, ":NA");
1007
1008 return sprintf(bufp, ":%x", ddata->offsets[reg]);
1009}
1010
a885f0fe
TL		 1011static int sysc_show_name(char *bufp, struct sysc *ddata)
1012{
1013 if (!ddata->name)
1014 return 0;
1015
1016 return sprintf(bufp, ":%s", ddata->name);
1017}
1018
0eecc636
TL		 1019/**
1020 * sysc_show_registers - show information about interconnect target module
1021 * @ddata: device driver data
1022 */
1023static void sysc_show_registers(struct sysc *ddata)
1024{
1025 char buf[128];
1026 char *bufp = buf;
1027 int i;
1028
1029 for (i = 0; i < SYSC_MAX_REGS; i++)
1030 bufp += sysc_show_reg(ddata, bufp, i);
1031
1032 bufp += sysc_show_rev(bufp, ddata);
a885f0fe 1033 bufp += sysc_show_name(bufp, ddata);
0eecc636
TL		 1034
1035 dev_dbg(ddata->dev, "%llx:%x%s\n",
1036 ddata->module_pa, ddata->module_size,
1037 buf);
1038}
1039
e8639e1c
TL		 1040/**
1041 * sysc_write_sysconfig - handle sysconfig quirks for register write
1042 * @ddata: device driver data
1043 * @value: register value
1044 */
1045static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1046{
1047 if (ddata->module_unlock_quirk)
1048 ddata->module_unlock_quirk(ddata);
1049
1050 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1051
1052 if (ddata->module_lock_quirk)
1053 ddata->module_lock_quirk(ddata);
1054}
1055
d59b6056 1056#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
ae9ae12e 1057#define SYSC_CLOCACT_ICK 2
d59b6056 1058
2b2f7def 1059/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 1060static int sysc_enable_module(struct device *dev)
1061{
1062 struct sysc *ddata;
1063 const struct sysc_regbits *regbits;
1064 u32 reg, idlemodes, best_mode;
d46f9fbe 1065 int error;
d59b6056
RQ		 1066
1067 ddata = dev_get_drvdata(dev);
d46f9fbe
TL		 1068
1069 /*
1070 * Some modules like DSS reset automatically on idle. Enable optional
1071 * reset clocks and wait for OCP softreset to complete.
1072 */
1073 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1074 error = sysc_enable_opt_clocks(ddata);
1075 if (error) {
1076 dev_err(ddata->dev,
1077 "Optional clocks failed for enable: %i\n",
1078 error);
1079 return error;
1080 }
1081 }
e275d210
TL		 1082 /*
1083 * Some modules like i2c and hdq1w have unusable reset status unless
1084 * the module reset quirk is enabled. Skip status check on enable.
1085 */
1086 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1087 error = sysc_wait_softreset(ddata);
1088 if (error)
1089 dev_warn(ddata->dev, "OCP softreset timed out\n");
1090 }
d46f9fbe
TL		 1091 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1092 sysc_disable_opt_clocks(ddata);
1093
1094 /*
1095 * Some subsystem private interconnects, like DSS top level module,
1096 * need only the automatic OCP softreset handling with no sysconfig
1097 * register bits to configure.
1098 */
d59b6056
RQ		 1099 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1100 return 0;
1101
d59b6056
RQ		 1102 regbits = ddata->cap->regbits;
1103 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1104
08b91dd6
TL		 1105 /*
1106 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1107 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1108 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1109 */
ae9ae12e 1110 if (regbits->clkact_shift >= 0 &&
08b91dd6 1111 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
ae9ae12e
TL		 1112 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1113
d59b6056
RQ		 1114 /* Set SIDLE mode */
1115 idlemodes = ddata->cfg.sidlemodes;
1116 if (!idlemodes || regbits->sidle_shift < 0)
1117 goto set_midle;
1118
fb685f1c
TL		 1119 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1120 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1121 best_mode = SYSC_IDLE_NO;
1122 } else {
1123 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1124 if (best_mode > SYSC_IDLE_MASK) {
1125 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1126 return -EINVAL;
1127 }
6e09f497
TL		 1128
1129 /* Set WAKEUP */
1130 if (regbits->enwkup_shift >= 0 &&
1131 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1132 reg |= BIT(regbits->enwkup_shift);
d59b6056
RQ		 1133 }
1134
1135 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1136 reg |= best_mode << regbits->sidle_shift;
e8639e1c 1137 sysc_write_sysconfig(ddata, reg);
d59b6056
RQ		 1138
1139set_midle:
1140 /* Set MIDLE mode */
1141 idlemodes = ddata->cfg.midlemodes;
1142 if (!idlemodes || regbits->midle_shift < 0)
eec26555 1143 goto set_autoidle;
d59b6056
RQ		 1144
1145 best_mode = fls(ddata->cfg.midlemodes) - 1;
1146 if (best_mode > SYSC_IDLE_MASK) {
1147 dev_err(dev, "%s: invalid midlemode\n", __func__);
95ec14fa
TL		 1148 error = -EINVAL;
1149 goto save_context;
d59b6056
RQ		 1150 }
1151
03856e92
TL		 1152 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1153 best_mode = SYSC_IDLE_NO;
1154
d59b6056
RQ		 1155 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1156 reg |= best_mode << regbits->midle_shift;
e8639e1c 1157 sysc_write_sysconfig(ddata, reg);
d59b6056 1158
eec26555
TL		 1159set_autoidle:
1160 /* Autoidle bit must enabled separately if available */
1161 if (regbits->autoidle_shift >= 0 &&
1162 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1163 reg |= 1 << regbits->autoidle_shift;
e8639e1c 1164 sysc_write_sysconfig(ddata, reg);
eec26555
TL		 1165 }
1166
95ec14fa
TL		 1167 error = 0;
1168
1169save_context:
1170 /* Save context and flush posted write */
1171 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
5ce8aee8 1172
d7f563db
TL		 1173 if (ddata->module_enable_quirk)
1174 ddata->module_enable_quirk(ddata);
1175
95ec14fa 1176 return error;
d59b6056
RQ		 1177}
1178
1179static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1180{
1181 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1182 *best_mode = SYSC_IDLE_SMART_WKUP;
1183 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1184 *best_mode = SYSC_IDLE_SMART;
6ee8241d 1185 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
d59b6056
RQ		 1186 *best_mode = SYSC_IDLE_FORCE;
1187 else
1188 return -EINVAL;
1189
1190 return 0;
1191}
1192
2b2f7def 1193/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
d59b6056
RQ		 1194static int sysc_disable_module(struct device *dev)
1195{
1196 struct sysc *ddata;
1197 const struct sysc_regbits *regbits;
1198 u32 reg, idlemodes, best_mode;
1199 int ret;
1200
1201 ddata = dev_get_drvdata(dev);
1202 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1203 return 0;
1204
c7d8669f
TL		 1205 if (ddata->module_disable_quirk)
1206 ddata->module_disable_quirk(ddata);
1207
d59b6056
RQ		 1208 regbits = ddata->cap->regbits;
1209 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1210
1211 /* Set MIDLE mode */
1212 idlemodes = ddata->cfg.midlemodes;
1213 if (!idlemodes || regbits->midle_shift < 0)
1214 goto set_sidle;
1215
1216 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1217 if (ret) {
1218 dev_err(dev, "%s: invalid midlemode\n", __func__);
1219 return ret;
1220 }
1221
93c60483
TL		 1222 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1223 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
03856e92
TL		 1224 best_mode = SYSC_IDLE_FORCE;
1225
d59b6056
RQ		 1226 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1227 reg |= best_mode << regbits->midle_shift;
e8639e1c 1228 sysc_write_sysconfig(ddata, reg);
d59b6056
RQ		 1229
1230set_sidle:
1231 /* Set SIDLE mode */
1232 idlemodes = ddata->cfg.sidlemodes;
95ec14fa
TL		 1233 if (!idlemodes || regbits->sidle_shift < 0) {
1234 ret = 0;
1235 goto save_context;
1236 }
d59b6056 1237
fb685f1c
TL		 1238 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1239 best_mode = SYSC_IDLE_FORCE;
1240 } else {
1241 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1242 if (ret) {
1243 dev_err(dev, "%s: invalid sidlemode\n", __func__);
95ec14fa
TL		 1244 ret = -EINVAL;
1245 goto save_context;
fb685f1c 1246 }
d59b6056
RQ		 1247 }
1248
1249 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1250 reg |= best_mode << regbits->sidle_shift;
eec26555
TL		 1251 if (regbits->autoidle_shift >= 0 &&
1252 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1253 reg |= 1 << regbits->autoidle_shift;
e8639e1c 1254 sysc_write_sysconfig(ddata, reg);
d59b6056 1255
95ec14fa 1256 ret = 0;
5ce8aee8 1257
95ec14fa
TL		 1258save_context:
1259 /* Save context and flush posted write */
1260 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1261
1262 return ret;
d59b6056
RQ		 1263}
1264
ff43728c
TL		 1265static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1266 struct sysc *ddata)
1267{
1268 struct ti_sysc_platform_data *pdata;
1269 int error;
1270
1271 pdata = dev_get_platdata(ddata->dev);
1272 if (!pdata)
1273 return 0;
1274
1275 if (!pdata->idle_module)
1276 return -ENODEV;
1277
1278 error = pdata->idle_module(dev, &ddata->cookie);
1279 if (error)
1280 dev_err(dev, "%s: could not idle: %i\n",
1281 __func__, error);
1282
4345f0dc 1283 reset_control_assert(ddata->rsts);
8383e259 1284
ff43728c
TL		 1285 return 0;
1286}
1287
1288static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1289 struct sysc *ddata)
0eecc636 1290{
ef70b0bd 1291 struct ti_sysc_platform_data *pdata;
ff43728c
TL		 1292 int error;
1293
1294 pdata = dev_get_platdata(ddata->dev);
1295 if (!pdata)
1296 return 0;
1297
1298 if (!pdata->enable_module)
1299 return -ENODEV;
1300
1301 error = pdata->enable_module(dev, &ddata->cookie);
1302 if (error)
1303 dev_err(dev, "%s: could not enable: %i\n",
1304 __func__, error);
1305
bf59ebbe
TK		 1306 reset_control_deassert(ddata->rsts);
1307
ff43728c
TL		 1308 return 0;
1309}
1310
1311static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1312{
0eecc636 1313 struct sysc *ddata;
d878970f 1314 int error = 0;
0eecc636
TL		 1315
1316 ddata = dev_get_drvdata(dev);
1317
ef70b0bd 1318 if (!ddata->enabled)
0eecc636
TL		 1319 return 0;
1320
2b2f7def
TL		 1321 sysc_clkdm_deny_idle(ddata);
1322
ef70b0bd 1323 if (ddata->legacy_mode) {
ff43728c 1324 error = sysc_runtime_suspend_legacy(dev, ddata);
93de83a2 1325 if (error)
2b2f7def 1326 goto err_allow_idle;
d59b6056
RQ		 1327 } else {
1328 error = sysc_disable_module(dev);
1329 if (error)
2b2f7def 1330 goto err_allow_idle;
ef70b0bd
TL		 1331 }
1332
d878970f 1333 sysc_disable_main_clocks(ddata);
09dfe581 1334
d878970f
TL		 1335 if (sysc_opt_clks_needed(ddata))
1336 sysc_disable_opt_clocks(ddata);
0eecc636 1337
ef70b0bd
TL		 1338 ddata->enabled = false;
1339
2b2f7def 1340err_allow_idle:
b6036314
TK		 1341 sysc_clkdm_allow_idle(ddata);
1342
4097c9a6
TL		 1343 reset_control_assert(ddata->rsts);
1344
ef70b0bd 1345 return error;
0eecc636
TL		 1346}
1347
a4a5d493 1348static int __maybe_unused sysc_runtime_resume(struct device *dev)
0eecc636
TL		 1349{
1350 struct sysc *ddata;
d878970f 1351 int error = 0;
0eecc636
TL		 1352
1353 ddata = dev_get_drvdata(dev);
1354
ef70b0bd 1355 if (ddata->enabled)
0eecc636
TL		 1356 return 0;
1357
8383e259 1358
2b2f7def
TL		 1359 sysc_clkdm_deny_idle(ddata);
1360
d878970f
TL		 1361 if (sysc_opt_clks_needed(ddata)) {
1362 error = sysc_enable_opt_clocks(ddata);
0eecc636 1363 if (error)
2b2f7def 1364 goto err_allow_idle;
0eecc636
TL		 1365 }
1366
d878970f
TL		 1367 error = sysc_enable_main_clocks(ddata);
1368 if (error)
93de83a2
TL		 1369 goto err_opt_clocks;
1370
bf59ebbe
TK		 1371 reset_control_deassert(ddata->rsts);
1372
93de83a2
TL		 1373 if (ddata->legacy_mode) {
1374 error = sysc_runtime_resume_legacy(dev, ddata);
1375 if (error)
1376 goto err_main_clocks;
d59b6056
RQ		 1377 } else {
1378 error = sysc_enable_module(dev);
1379 if (error)
1380 goto err_main_clocks;
93de83a2 1381 }
d878970f 1382
ef70b0bd
TL		 1383 ddata->enabled = true;
1384
2b2f7def
TL		 1385 sysc_clkdm_allow_idle(ddata);
1386
d878970f
TL		 1387 return 0;
1388
1389err_main_clocks:
93de83a2
TL		 1390 sysc_disable_main_clocks(ddata);
1391err_opt_clocks:
d878970f
TL		 1392 if (sysc_opt_clks_needed(ddata))
1393 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 1394err_allow_idle:
1395 sysc_clkdm_allow_idle(ddata);
d878970f 1396
ef70b0bd 1397 return error;
0eecc636
TL		 1398}
1399
95ec14fa
TL		 1400/*
1401 * Checks if device context was lost. Assumes the sysconfig register value
1402 * after lost context is different from the configured value. Only works for
1403 * enabled devices.
1404 *
1405 * Eventually we may want to also add support to using the context lost
1406 * registers that some SoCs have.
1407 */
1408static int sysc_check_context(struct sysc *ddata)
1409{
1410 u32 reg;
1411
1412 if (!ddata->enabled)
1413 return -ENODATA;
1414
1415 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1416 if (reg == ddata->sysconfig)
1417 return 0;
1418
1419 return -EACCES;
1420}
1421
4d7b324e
TL		 1422static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1423{
1424 struct device *dev = ddata->dev;
1425 int error;
1426
4d7b324e 1427 if (ddata->enabled) {
95ec14fa
TL		 1428 /* Nothing to do if enabled and context not lost */
1429 error = sysc_check_context(ddata);
1430 if (!error)
1431 return 0;
1432
1433 /* Disable target module if it is enabled */
4d7b324e
TL		 1434 error = sysc_runtime_suspend(dev);
1435 if (error)
1436 dev_warn(dev, "reinit suspend failed: %i\n", error);
1437 }
1438
1439 /* Enable target module */
1440 error = sysc_runtime_resume(dev);
1441 if (error)
1442 dev_warn(dev, "reinit resume failed: %i\n", error);
1443
6a52bc2b
TL		 1444 /* Some modules like am335x gpmc need reset and restore of sysconfig */
1445 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) {
1446 error = sysc_reset(ddata);
1447 if (error)
1448 dev_warn(dev, "reinit reset failed: %i\n", error);
1449
1450 sysc_write_sysconfig(ddata, ddata->sysconfig);
1451 }
1452
4d7b324e
TL		 1453 if (leave_enabled)
1454 return error;
1455
1456 /* Disable target module if no leave_enabled was set */
1457 error = sysc_runtime_suspend(dev);
1458 if (error)
1459 dev_warn(dev, "reinit suspend failed: %i\n", error);
1460
1461 return error;
1462}
1463
f5e80203 1464static int __maybe_unused sysc_noirq_suspend(struct device *dev)
62020f23
TL		 1465{
1466 struct sysc *ddata;
1467
1468 ddata = dev_get_drvdata(dev);
1469
a55de412
TL		 1470 if (ddata->cfg.quirks &
1471 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
e7420c2d
TL		 1472 return 0;
1473
4d7b324e
TL		 1474 if (!ddata->enabled)
1475 return 0;
1476
1477 ddata->needs_resume = 1;
1478
1479 return sysc_runtime_suspend(dev);
62020f23
TL		 1480}
1481
f5e80203 1482static int __maybe_unused sysc_noirq_resume(struct device *dev)
62020f23
TL		 1483{
1484 struct sysc *ddata;
4d7b324e 1485 int error = 0;
62020f23
TL		 1486
1487 ddata = dev_get_drvdata(dev);
e7420c2d 1488
a55de412
TL		 1489 if (ddata->cfg.quirks &
1490 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
e7420c2d
TL		 1491 return 0;
1492
4d7b324e
TL		 1493 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1494 error = sysc_reinit_module(ddata, ddata->needs_resume);
1495 if (error)
1496 dev_warn(dev, "noirq_resume failed: %i\n", error);
1497 } else if (ddata->needs_resume) {
1498 error = sysc_runtime_resume(dev);
1499 if (error)
1500 dev_warn(dev, "noirq_resume failed: %i\n", error);
1501 }
1502
1503 ddata->needs_resume = 0;
1504
1505 return error;
0eecc636
TL		 1506}
1507
1508static const struct dev_pm_ops sysc_pm_ops = {
e7420c2d 1509 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
0eecc636
TL		 1510 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1511 sysc_runtime_resume,
1512 NULL)
1513};
1514
a885f0fe
TL		 1515/* Module revision register based quirks */
1516struct sysc_revision_quirk {
1517 const char *name;
1518 u32 base;
1519 int rev_offset;
1520 int sysc_offset;
1521 int syss_offset;
1522 u32 revision;
1523 u32 revision_mask;
1524 u32 quirks;
1525};
1526
1527#define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1528 optrev_val, optrevmask, optquirkmask) \
1529 { \
1530 .name = (optname), \
1531 .base = (optbase), \
1532 .rev_offset = (optrev), \
1533 .sysc_offset = (optsysc), \
1534 .syss_offset = (optsyss), \
1535 .revision = (optrev_val), \
1536 .revision_mask = (optrevmask), \
1537 .quirks = (optquirkmask), \
1538 }
1539
1540static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1541 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
b6a53c4c
TL		 1542 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1543 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
a885f0fe 1544 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
b6a53c4c 1545 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
d708bb14 1546 /* Uarts on omap4 and later */
b82beef5 1547 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
c8692ad4 1548 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
b82beef5 1549 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
c8692ad4 1550 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
7e27e5d0 1551
a54275f4 1552 /* Quirks that need to be set based on the module address */
590e15c7 1553 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
a54275f4
TL		 1554 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1555 SYSC_QUIRK_SWSUP_SIDLE),
1556
4e23be47 1557 /* Quirks that need to be set based on detected module */
590e15c7 1558 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
020003f7 1559 SYSC_MODULE_QUIRK_AESS),
b13a270a
TL		 1560 /* Errata i893 handling for dra7 dcan1 and 2 */
1561 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1562 SYSC_QUIRK_CLKDM_NOAUTO),
590e15c7 1563 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
94f63457 1564 SYSC_QUIRK_CLKDM_NOAUTO),
77dfece2 1565 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
7324a7a0 1566 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
77dfece2 1567 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
7324a7a0 1568 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
77dfece2 1569 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
7324a7a0 1570 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
590e15c7 1571 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
94f63457 1572 SYSC_QUIRK_CLKDM_NOAUTO),
590e15c7 1573 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
94f63457 1574 SYSC_QUIRK_CLKDM_NOAUTO),
1b99c1ee
TL		 1575 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1576 SYSC_QUIRK_OPT_CLKS_IN_RESET),
cfeeea60 1577 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
d48dca51 1578 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST |
cfeeea60 1579 SYSC_QUIRK_GPMC_DEBUG),
77dfece2
TL		 1580 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1581 SYSC_QUIRK_OPT_CLKS_NEEDED),
4e23be47 1582 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
e275d210 1583 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1584 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
e275d210 1585 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1586 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
e275d210 1587 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1588 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
e275d210 1589 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1590 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
e275d210 1591 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
4e23be47 1592 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
e275d210 1593 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
590e15c7
TL		 1594 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1595 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
d7f563db 1596 SYSC_MODULE_QUIRK_SGX),
aef067e8
TL		 1597 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1598 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
8122dc58
PU		 1599 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1600 SYSC_QUIRK_SWSUP_SIDLE),
e8639e1c
TL		 1601 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1602 SYSC_MODULE_QUIRK_RTC_UNLOCK),
25bfaaa7
TL		 1603 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1604 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1605 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1606 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
db8e712e
TL		 1607 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1608 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
4254632d
TL		 1609 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1610 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1611 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1612 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
03856e92 1613 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
5c99fa73
TL		 1614 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1615 SYSC_MODULE_QUIRK_OTG),
590e15c7 1616 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
4d7b324e 1617 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
9067839f 1618 SYSC_QUIRK_REINIT_ON_CTX_LOST),
4e23be47
TL		 1619 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1620 SYSC_MODULE_QUIRK_WDT),
b2745d92
SA		 1621 /* PRUSS on am3, am4 and am5 */
1622 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1623 SYSC_MODULE_QUIRK_PRUSS),
c7d8669f
TL		 1624 /* Watchdog on am3 and am4 */
1625 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1626 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
4e23be47 1627
dc4c85ea 1628#ifdef DEBUG
590e15c7
TL		 1629 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1630 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1631 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1632 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1ba30693 1633 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
23731eac 1634 0xffff00f0, 0),
590e15c7
TL		 1635 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1636 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
77dfece2
TL		 1637 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1638 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1639 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
590e15c7 1640 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
77dfece2
TL		 1641 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1642 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1643 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1644 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
590e15c7 1645 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
7edd00f7
TL		 1646 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1647 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
f2dc0755
TL		 1648 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1649 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1650 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
590e15c7
TL		 1651 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1652 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1653 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
77dfece2 1654 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
dc4c85ea 1655 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
590e15c7 1656 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
f2dc0755 1657 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
590e15c7
TL		 1658 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1659 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1660 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1ba30693 1661 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
590e15c7
TL		 1662 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1663 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
c6eb4af3 1664 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
590e15c7
TL		 1665 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1666 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1667 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
f2dc0755
TL		 1668 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1669 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
590e15c7
TL		 1670 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1671 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1672 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
77dfece2
TL		 1673 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1674 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
590e15c7
TL		 1675 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1676 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1677 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1678 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1679 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1680 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1ba30693 1681 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
40d9f912 1682 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
ce7b4323 1683 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0),
590e15c7
TL		 1684 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1685 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
ed4520d6
TL		 1686 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1687 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
590e15c7
TL		 1688 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1689 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1a542811
TL		 1690 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1691 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1692 /* Some timers on omap4 and later */
1693 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1694 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1695 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1696 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
590e15c7 1697 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
25bfaaa7 1698 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
dc4c85ea 1699 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
f0106700 1700 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
77dfece2 1701 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
590e15c7 1702 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
dc4c85ea 1703#endif
a885f0fe
TL		 1704};
1705
42b9c5c9
TL		 1706/*
1707 * Early quirks based on module base and register offsets only that are
1708 * needed before the module revision can be read
1709 */
1710static void sysc_init_early_quirks(struct sysc *ddata)
1711{
1712 const struct sysc_revision_quirk *q;
1713 int i;
1714
1715 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1716 q = &sysc_revision_quirks[i];
1717
1718 if (!q->base)
1719 continue;
1720
1721 if (q->base != ddata->module_pa)
1722 continue;
1723
590e15c7 1724 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
42b9c5c9
TL		 1725 continue;
1726
590e15c7 1727 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
42b9c5c9
TL		 1728 continue;
1729
590e15c7 1730 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
42b9c5c9
TL		 1731 continue;
1732
1733 ddata->name = q->name;
1734 ddata->cfg.quirks |= q->quirks;
1735 }
1736}
1737
1738/* Quirks that also consider the revision register value */
a885f0fe
TL		 1739static void sysc_init_revision_quirks(struct sysc *ddata)
1740{
1741 const struct sysc_revision_quirk *q;
1742 int i;
1743
1744 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1745 q = &sysc_revision_quirks[i];
1746
1747 if (q->base && q->base != ddata->module_pa)
1748 continue;
1749
590e15c7 1750 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
a885f0fe
TL		 1751 continue;
1752
590e15c7 1753 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
a885f0fe
TL		 1754 continue;
1755
590e15c7 1756 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
a885f0fe
TL		 1757 continue;
1758
1759 if (q->revision == ddata->revision ||
1760 (q->revision & q->revision_mask) ==
1761 (ddata->revision & q->revision_mask)) {
1762 ddata->name = q->name;
1763 ddata->cfg.quirks |= q->quirks;
1764 }
1765 }
1766}
1767
7324a7a0
TL		 1768/*
1769 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1770 * enabled DSS interrupts. Eventually we may be able to do this on
1771 * dispc init rather than top-level DSS init.
1772 */
1773static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1774 bool disable)
1775{
1776 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1777 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1778 int manager_count;
085bc0e5 1779 bool framedonetv_irq = true;
7324a7a0
TL		 1780 u32 val, irq_mask = 0;
1781
1782 switch (sysc_soc->soc) {
1783 case SOC_2420 ... SOC_3630:
1784 manager_count = 2;
1785 framedonetv_irq = false;
1786 break;
1787 case SOC_4430 ... SOC_4470:
1788 manager_count = 3;
1789 break;
1790 case SOC_5430:
1791 case SOC_DRA7:
1792 manager_count = 4;
1793 break;
1794 case SOC_AM4:
1795 manager_count = 1;
085bc0e5 1796 framedonetv_irq = false;
7324a7a0
TL		 1797 break;
1798 case SOC_UNKNOWN:
1799 default:
1800 return 0;
52fbb5aa 1801 }
7324a7a0
TL		 1802
1803 /* Remap the whole module range to be able to reset dispc outputs */
1804 devm_iounmap(ddata->dev, ddata->module_va);
1805 ddata->module_va = devm_ioremap(ddata->dev,
1806 ddata->module_pa,
1807 ddata->module_size);
1808 if (!ddata->module_va)
1809 return -EIO;
1810
1811 /* DISP_CONTROL */
1812 val = sysc_read(ddata, dispc_offset + 0x40);
1813 lcd_en = val & lcd_en_mask;
1814 digit_en = val & digit_en_mask;
1815 if (lcd_en)
1816 irq_mask |= BIT(0); /* FRAMEDONE */
1817 if (digit_en) {
1818 if (framedonetv_irq)
1819 irq_mask |= BIT(24); /* FRAMEDONETV */
1820 else
1821 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1822 }
1823 if (disable & (lcd_en | digit_en))
1824 sysc_write(ddata, dispc_offset + 0x40,
1825 val & ~(lcd_en_mask | digit_en_mask));
1826
1827 if (manager_count <= 2)
1828 return irq_mask;
1829
1830 /* DISPC_CONTROL2 */
1831 val = sysc_read(ddata, dispc_offset + 0x238);
1832 lcd2_en = val & lcd_en_mask;
1833 if (lcd2_en)
1834 irq_mask |= BIT(22); /* FRAMEDONE2 */
1835 if (disable && lcd2_en)
1836 sysc_write(ddata, dispc_offset + 0x238,
1837 val & ~lcd_en_mask);
1838
1839 if (manager_count <= 3)
1840 return irq_mask;
1841
1842 /* DISPC_CONTROL3 */
1843 val = sysc_read(ddata, dispc_offset + 0x848);
1844 lcd3_en = val & lcd_en_mask;
1845 if (lcd3_en)
1846 irq_mask |= BIT(30); /* FRAMEDONE3 */
1847 if (disable && lcd3_en)
1848 sysc_write(ddata, dispc_offset + 0x848,
1849 val & ~lcd_en_mask);
1850
1851 return irq_mask;
1852}
1853
1854/* DSS needs child outputs disabled and SDI registers cleared for reset */
1855static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1856{
1857 const int dispc_offset = 0x1000;
1858 int error;
1859 u32 irq_mask, val;
1860
1861 /* Get enabled outputs */
1862 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1863 if (!irq_mask)
1864 return;
1865
1866 /* Clear IRQSTATUS */
69e60903 1867 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
7324a7a0
TL		 1868
1869 /* Disable outputs */
1870 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1871
1872 /* Poll IRQSTATUS */
1873 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1874 val, val != irq_mask, 100, 50);
1875 if (error)
1876 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1877 __func__, val, irq_mask);
1878
1879 if (sysc_soc->soc == SOC_3430) {
1880 /* Clear DSS_SDI_CONTROL */
69e60903 1881 sysc_write(ddata, 0x44, 0);
7324a7a0
TL		 1882
1883 /* Clear DSS_PLL_CONTROL */
69e60903 1884 sysc_write(ddata, 0x48, 0);
7324a7a0
TL		 1885 }
1886
1887 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
69e60903 1888 sysc_write(ddata, 0x40, 0);
7324a7a0
TL		 1889}
1890
4e23be47 1891/* 1-wire needs module's internal clocks enabled for reset */
aec551c7 1892static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
4e23be47
TL		 1893{
1894 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1895 u16 val;
1896
1897 val = sysc_read(ddata, offset);
1898 val |= BIT(5);
1899 sysc_write(ddata, offset, val);
1900}
1901
020003f7
TL		 1902/* AESS (Audio Engine SubSystem) needs autogating set after enable */
1903static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1904{
1905 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1906
1907 sysc_write(ddata, offset, 1);
1908}
1909
e64c021f 1910/* I2C needs to be disabled for reset */
4e23be47
TL		 1911static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1912{
1913 int offset;
1914 u16 val;
1915
1916 /* I2C_CON, omap2/3 is different from omap4 and later */
1917 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1918 offset = 0x24;
1919 else
1920 offset = 0xa4;
1921
1922 /* I2C_EN */
1923 val = sysc_read(ddata, offset);
1924 if (enable)
1925 val |= BIT(15);
1926 else
1927 val &= ~BIT(15);
1928 sysc_write(ddata, offset, val);
1929}
1930
e64c021f 1931static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
4e23be47 1932{
e64c021f 1933 sysc_clk_quirk_i2c(ddata, false);
4e23be47
TL		 1934}
1935
e64c021f 1936static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
4e23be47 1937{
e64c021f 1938 sysc_clk_quirk_i2c(ddata, true);
4e23be47
TL		 1939}
1940
e8639e1c
TL		 1941/* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1942static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1943{
1944 u32 val, kick0_val = 0, kick1_val = 0;
1945 unsigned long flags;
1946 int error;
1947
1948 if (!lock) {
1949 kick0_val = 0x83e70b13;
1950 kick1_val = 0x95a4f1e0;
1951 }
1952
1953 local_irq_save(flags);
1954 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
afe6f1ee
TL		 1955 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1956 !(val & BIT(0)), 100, 50);
e8639e1c
TL		 1957 if (error)
1958 dev_warn(ddata->dev, "rtc busy timeout\n");
1959 /* Now we have ~15 microseconds to read/write various registers */
1960 sysc_write(ddata, 0x6c, kick0_val);
1961 sysc_write(ddata, 0x70, kick1_val);
1962 local_irq_restore(flags);
1963}
1964
1965static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1966{
1967 sysc_quirk_rtc(ddata, false);
1968}
1969
1970static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1971{
1972 sysc_quirk_rtc(ddata, true);
1973}
1974
5c99fa73
TL		 1975/* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */
1976static void sysc_module_enable_quirk_otg(struct sysc *ddata)
1977{
1978 int offset = 0x414; /* OTG_FORCESTDBY */
1979
1980 sysc_write(ddata, offset, 0);
1981}
1982
1983static void sysc_module_disable_quirk_otg(struct sysc *ddata)
1984{
1985 int offset = 0x414; /* OTG_FORCESTDBY */
1986 u32 val = BIT(0); /* ENABLEFORCE */
1987
1988 sysc_write(ddata, offset, val);
1989}
1990
d7f563db
TL		 1991/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1992static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1993{
1994 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1995 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1996
1997 sysc_write(ddata, offset, val);
1998}
1999
4e23be47
TL		 2000/* Watchdog timer needs a disable sequence after reset */
2001static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
2002{
2003 int wps, spr, error;
2004 u32 val;
2005
2006 wps = 0x34;
2007 spr = 0x48;
2008
2009 sysc_write(ddata, spr, 0xaaaa);
2010 error = readl_poll_timeout(ddata->module_va + wps, val,
2011 !(val & 0x10), 100,
2012 MAX_MODULE_SOFTRESET_WAIT);
2013 if (error)
c7d8669f 2014 dev_warn(ddata->dev, "wdt disable step1 failed\n");
4e23be47 2015
c7d8669f 2016 sysc_write(ddata, spr, 0x5555);
4e23be47
TL		 2017 error = readl_poll_timeout(ddata->module_va + wps, val,
2018 !(val & 0x10), 100,
2019 MAX_MODULE_SOFTRESET_WAIT);
2020 if (error)
c7d8669f 2021 dev_warn(ddata->dev, "wdt disable step2 failed\n");
4e23be47
TL		 2022}
2023
b2745d92
SA		 2024/* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
2025static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
2026{
2027 u32 reg;
2028
2029 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
2030 reg |= SYSC_PRUSS_STANDBY_INIT;
2031 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
2032}
2033
4e23be47
TL		 2034static void sysc_init_module_quirks(struct sysc *ddata)
2035{
2036 if (ddata->legacy_mode || !ddata->name)
2037 return;
2038
2039 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
e64c021f 2040 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
4e23be47
TL		 2041
2042 return;
2043 }
2044
cfeeea60
TL		 2045#ifdef CONFIG_OMAP_GPMC_DEBUG
2046 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
2047 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
2048
2049 return;
2050 }
2051#endif
2052
4e23be47 2053 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
e64c021f
TL		 2054 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2055 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
4e23be47
TL		 2056
2057 return;
2058 }
2059
020003f7
TL		 2060 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2061 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2062
7324a7a0
TL		 2063 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2064 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2065
e8639e1c
TL		 2066 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2067 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2068 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2069
2070 return;
2071 }
2072
5c99fa73
TL		 2073 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) {
2074 ddata->module_enable_quirk = sysc_module_enable_quirk_otg;
2075 ddata->module_disable_quirk = sysc_module_disable_quirk_otg;
2076 }
2077
d7f563db
TL		 2078 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2079 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2080
c7d8669f 2081 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
4e23be47 2082 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
c7d8669f
TL		 2083 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2084 }
b2745d92
SA		 2085
2086 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2087 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
4e23be47
TL		 2088}
2089
2b2f7def
TL		 2090static int sysc_clockdomain_init(struct sysc *ddata)
2091{
2092 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2093 struct clk *fck = NULL, *ick = NULL;
2094 int error;
2095
2096 if (!pdata || !pdata->init_clockdomain)
2097 return 0;
2098
2099 switch (ddata->nr_clocks) {
2100 case 2:
2101 ick = ddata->clocks[SYSC_ICK];
df561f66 2102 fallthrough;
2b2f7def
TL		 2103 case 1:
2104 fck = ddata->clocks[SYSC_FCK];
2105 break;
2106 case 0:
2107 return 0;
2108 }
2109
2110 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2111 if (!error || error == -ENODEV)
2112 return 0;
2113
2114 return error;
2115}
2116
a3e92e7b
TL		 2117/*
2118 * Note that pdata->init_module() typically does a reset first. After
2119 * pdata->init_module() is done, PM runtime can be used for the interconnect
2120 * target module.
2121 */
2122static int sysc_legacy_init(struct sysc *ddata)
2123{
2124 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2125 int error;
2126
2b2f7def 2127 if (!pdata || !pdata->init_module)
a3e92e7b
TL		 2128 return 0;
2129
2130 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2131 if (error == -EEXIST)
2132 error = 0;
2133
2134 return error;
2135}
2136
e0db94fe
TL		 2137/*
2138 * Note that the caller must ensure the interconnect target module is enabled
2139 * before calling reset. Otherwise reset will not complete.
2140 */
596e7955
FA		 2141static int sysc_reset(struct sysc *ddata)
2142{
d46f9fbe
TL		 2143 int sysc_offset, sysc_val, error;
2144 u32 sysc_mask;
e0db94fe
TL		 2145
2146 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
596e7955 2147
ab4d309d 2148 if (ddata->legacy_mode ||
e0db94fe 2149 ddata->cap->regbits->srst_shift < 0 ||
596e7955
FA		 2150 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2151 return 0;
2152
e0db94fe 2153 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
596e7955 2154
e64c021f
TL		 2155 if (ddata->pre_reset_quirk)
2156 ddata->pre_reset_quirk(ddata);
4e23be47 2157
ab4d309d
TL		 2158 if (sysc_offset >= 0) {
2159 sysc_val = sysc_read_sysconfig(ddata);
2160 sysc_val |= sysc_mask;
2161 sysc_write(ddata, sysc_offset, sysc_val);
2162 }
596e7955 2163
e709ed70
TL		 2164 if (ddata->cfg.srst_udelay)
2165 usleep_range(ddata->cfg.srst_udelay,
2166 ddata->cfg.srst_udelay * 2);
2167
e64c021f
TL		 2168 if (ddata->post_reset_quirk)
2169 ddata->post_reset_quirk(ddata);
4e23be47 2170
d46f9fbe
TL		 2171 error = sysc_wait_softreset(ddata);
2172 if (error)
2173 dev_warn(ddata->dev, "OCP softreset timed out\n");
596e7955 2174
4e23be47
TL		 2175 if (ddata->reset_done_quirk)
2176 ddata->reset_done_quirk(ddata);
2177
e0db94fe 2178 return error;
596e7955
FA		 2179}
2180
1a5cd7c2
TL		 2181/*
2182 * At this point the module is configured enough to read the revision but
2183 * module may not be completely configured yet to use PM runtime. Enable
2184 * all clocks directly during init to configure the quirks needed for PM
2185 * runtime based on the revision register.
2186 */
566a9b05
TL		 2187static int sysc_init_module(struct sysc *ddata)
2188{
4097c9a6 2189 bool rstctrl_deasserted = false;
1a5cd7c2 2190 int error = 0;
a885f0fe 2191
2b2f7def
TL		 2192 error = sysc_clockdomain_init(ddata);
2193 if (error)
2194 return error;
2195
d098913a 2196 sysc_clkdm_deny_idle(ddata);
2b2f7def 2197
d098913a
TL		 2198 /*
2199 * Always enable clocks. The bootloader may or may not have enabled
2200 * the related clocks.
2201 */
2202 error = sysc_enable_opt_clocks(ddata);
2203 if (error)
2204 return error;
566a9b05 2205
d098913a
TL		 2206 error = sysc_enable_main_clocks(ddata);
2207 if (error)
2208 goto err_opt_clocks;
5062236e 2209
ea5a2e4d 2210 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
df4f3459 2211 error = reset_control_deassert(ddata->rsts);
ea5a2e4d
TL		 2212 if (error)
2213 goto err_main_clocks;
4097c9a6 2214 rstctrl_deasserted = true;
ea5a2e4d
TL		 2215 }
2216
1a5cd7c2
TL		 2217 ddata->revision = sysc_read_revision(ddata);
2218 sysc_init_revision_quirks(ddata);
4e23be47 2219 sysc_init_module_quirks(ddata);
1a5cd7c2 2220
2b2f7def
TL		 2221 if (ddata->legacy_mode) {
2222 error = sysc_legacy_init(ddata);
2223 if (error)
4097c9a6 2224 goto err_main_clocks;
2b2f7def
TL		 2225 }
2226
d098913a 2227 if (!ddata->legacy_mode) {
2b2f7def
TL		 2228 error = sysc_enable_module(ddata->dev);
2229 if (error)
4097c9a6 2230 goto err_main_clocks;
2b2f7def 2231 }
a3e92e7b 2232
596e7955 2233 error = sysc_reset(ddata);
1a5cd7c2 2234 if (error)
596e7955 2235 dev_err(ddata->dev, "Reset failed with %d\n", error);
596e7955 2236
cdc56c11 2237 if (error && !ddata->legacy_mode)
2b2f7def
TL		 2238 sysc_disable_module(ddata->dev);
2239
a3e92e7b 2240err_main_clocks:
cdc56c11 2241 if (error)
1a5cd7c2
TL		 2242 sysc_disable_main_clocks(ddata);
2243err_opt_clocks:
d098913a 2244 /* No re-enable of clockdomain autoidle to prevent module autoidle */
cdc56c11 2245 if (error) {
1a5cd7c2 2246 sysc_disable_opt_clocks(ddata);
2b2f7def
TL		 2247 sysc_clkdm_allow_idle(ddata);
2248 }
a885f0fe 2249
4097c9a6
TL		 2250 if (error && rstctrl_deasserted &&
2251 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2252 reset_control_assert(ddata->rsts);
2253
1a5cd7c2 2254 return error;
566a9b05
TL		 2255}
2256
c5a2de97
TL		 2257static int sysc_init_sysc_mask(struct sysc *ddata)
2258{
2259 struct device_node *np = ddata->dev->of_node;
2260 int error;
2261 u32 val;
2262
2263 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2264 if (error)
2265 return 0;
2266
e212abd4 2267 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
c5a2de97
TL		 2268
2269 return 0;
2270}
2271
2272static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2273 const char *name)
2274{
2275 struct device_node *np = ddata->dev->of_node;
2276 struct property *prop;
2277 const __be32 *p;
2278 u32 val;
2279
2280 of_property_for_each_u32(np, name, prop, p, val) {
2281 if (val >= SYSC_NR_IDLEMODES) {
2282 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2283 return -EINVAL;
2284 }
2285 *idlemodes |= (1 << val);
2286 }
2287
2288 return 0;
2289}
2290
2291static int sysc_init_idlemodes(struct sysc *ddata)
2292{
2293 int error;
2294
2295 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2296 "ti,sysc-midle");
2297 if (error)
2298 return error;
2299
2300 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2301 "ti,sysc-sidle");
2302 if (error)
2303 return error;
2304
2305 return 0;
2306}
2307
2308/*
2309 * Only some devices on omap4 and later have SYSCONFIG reset done
2310 * bit. We can detect this if there is no SYSSTATUS at all, or the
2311 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2312 * have multiple bits for the child devices like OHCI and EHCI.
2313 * Depends on SYSC being parsed first.
2314 */
2315static int sysc_init_syss_mask(struct sysc *ddata)
2316{
2317 struct device_node *np = ddata->dev->of_node;
2318 int error;
2319 u32 val;
2320
2321 error = of_property_read_u32(np, "ti,syss-mask", &val);
2322 if (error) {
2323 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2324 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2325 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2326 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2327
2328 return 0;
2329 }
2330
2331 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2332 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2333
2334 ddata->cfg.syss_mask = val;
2335
2336 return 0;
2337}
2338
2c355ff6 2339/*
8b2830ba
TL		 2340 * Many child device drivers need to have fck and opt clocks available
2341 * to get the clock rate for device internal configuration etc.
2c355ff6 2342 */
8b2830ba
TL		 2343static int sysc_child_add_named_clock(struct sysc *ddata,
2344 struct device *child,
2345 const char *name)
2c355ff6 2346{
8b2830ba 2347 struct clk *clk;
2c355ff6 2348 struct clk_lookup *l;
8b2830ba 2349 int error = 0;
2c355ff6 2350
8b2830ba 2351 if (!name)
2c355ff6
TL		 2352 return 0;
2353
8b2830ba
TL		 2354 clk = clk_get(child, name);
2355 if (!IS_ERR(clk)) {
cb6cfe2e
ME		 2356 error = -EEXIST;
2357 goto put_clk;
2c355ff6
TL		 2358 }
2359
8b2830ba
TL		 2360 clk = clk_get(ddata->dev, name);
2361 if (IS_ERR(clk))
2362 return -ENODEV;
2c355ff6 2363
8b2830ba
TL		 2364 l = clkdev_create(clk, name, dev_name(child));
2365 if (!l)
2366 error = -ENOMEM;
cb6cfe2e 2367put_clk:
8b2830ba
TL		 2368 clk_put(clk);
2369
2370 return error;
2c355ff6
TL		 2371}
2372
09dfe581
TL		 2373static int sysc_child_add_clocks(struct sysc *ddata,
2374 struct device *child)
2375{
2376 int i, error;
2377
2378 for (i = 0; i < ddata->nr_clocks; i++) {
2379 error = sysc_child_add_named_clock(ddata,
2380 child,
2381 ddata->clock_roles[i]);
2382 if (error && error != -EEXIST) {
2383 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2384 ddata->clock_roles[i], error);
2385
2386 return error;
2387 }
2388 }
2389
2390 return 0;
2391}
2392
2c355ff6
TL		 2393static struct device_type sysc_device_type = {
2394};
2395
2396static struct sysc *sysc_child_to_parent(struct device *dev)
2397{
2398 struct device *parent = dev->parent;
2399
2400 if (!parent || parent->type != &sysc_device_type)
2401 return NULL;
2402
2403 return dev_get_drvdata(parent);
2404}
2405
a885f0fe
TL		 2406static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2407{
2408 struct sysc *ddata;
2409 int error;
2410
2411 ddata = sysc_child_to_parent(dev);
2412
2413 error = pm_generic_runtime_suspend(dev);
2414 if (error)
2415 return error;
2416
2417 if (!ddata->enabled)
2418 return 0;
2419
2420 return sysc_runtime_suspend(ddata->dev);
2421}
2422
2423static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2424{
2425 struct sysc *ddata;
2426 int error;
2427
2428 ddata = sysc_child_to_parent(dev);
2429
2430 if (!ddata->enabled) {
2431 error = sysc_runtime_resume(ddata->dev);
2432 if (error < 0)
2433 dev_err(ddata->dev,
2434 "%s error: %i\n", __func__, error);
2435 }
2436
2437 return pm_generic_runtime_resume(dev);
2438}
2439
2440#ifdef CONFIG_PM_SLEEP
2441static int sysc_child_suspend_noirq(struct device *dev)
2442{
2443 struct sysc *ddata;
2444 int error;
2445
2446 ddata = sysc_child_to_parent(dev);
2447
ef55f821
TL		 2448 dev_dbg(ddata->dev, "%s %s\n", __func__,
2449 ddata->name ? ddata->name : "");
2450
a885f0fe 2451 error = pm_generic_suspend_noirq(dev);
ef55f821
TL		 2452 if (error) {
2453 dev_err(dev, "%s error at %i: %i\n",
2454 __func__, __LINE__, error);
2455
a885f0fe 2456 return error;
ef55f821 2457 }
a885f0fe
TL		 2458
2459 if (!pm_runtime_status_suspended(dev)) {
2460 error = pm_generic_runtime_suspend(dev);
ef55f821 2461 if (error) {
f9490783
TL		 2462 dev_dbg(dev, "%s busy at %i: %i\n",
2463 __func__, __LINE__, error);
ef55f821 2464
4f3530f4 2465 return 0;
ef55f821 2466 }
a885f0fe
TL		 2467
2468 error = sysc_runtime_suspend(ddata->dev);
ef55f821
TL		 2469 if (error) {
2470 dev_err(dev, "%s error at %i: %i\n",
2471 __func__, __LINE__, error);
2472
a885f0fe 2473 return error;
ef55f821 2474 }
a885f0fe
TL		 2475
2476 ddata->child_needs_resume = true;
2477 }
2478
2479 return 0;
2480}
2481
2482static int sysc_child_resume_noirq(struct device *dev)
2483{
2484 struct sysc *ddata;
2485 int error;
2486
2487 ddata = sysc_child_to_parent(dev);
2488
ef55f821
TL		 2489 dev_dbg(ddata->dev, "%s %s\n", __func__,
2490 ddata->name ? ddata->name : "");
2491
a885f0fe
TL		 2492 if (ddata->child_needs_resume) {
2493 ddata->child_needs_resume = false;
2494
2495 error = sysc_runtime_resume(ddata->dev);
2496 if (error)
2497 dev_err(ddata->dev,
2498 "%s runtime resume error: %i\n",
2499 __func__, error);
2500
2501 error = pm_generic_runtime_resume(dev);
2502 if (error)
2503 dev_err(ddata->dev,
2504 "%s generic runtime resume: %i\n",
2505 __func__, error);
2506 }
2507
2508 return pm_generic_resume_noirq(dev);
2509}
2510#endif
2511
b7182b42 2512static struct dev_pm_domain sysc_child_pm_domain = {
a885f0fe
TL		 2513 .ops = {
2514 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2515 sysc_child_runtime_resume,
2516 NULL)
2517 USE_PLATFORM_PM_SLEEP_OPS
2518 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2519 sysc_child_resume_noirq)
2520 }
2521};
2522
9d881361
TL		 2523/* Caller needs to take list_lock if ever used outside of cpu_pm */
2524static void sysc_reinit_modules(struct sysc_soc_info *soc)
2525{
2526 struct sysc_module *module;
2527 struct list_head *pos;
2528 struct sysc *ddata;
9d881361
TL		 2529
2530 list_for_each(pos, &sysc_soc->restored_modules) {
2531 module = list_entry(pos, struct sysc_module, node);
2532 ddata = module->ddata;
1b1da99b 2533 sysc_reinit_module(ddata, ddata->enabled);
9d881361
TL		 2534 }
2535}
2536
2537/**
2538 * sysc_context_notifier - optionally reset and restore module after idle
2539 * @nb: notifier block
2540 * @cmd: unused
2541 * @v: unused
2542 *
2543 * Some interconnect target modules need to be restored, or reset and restored
2544 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2545 * OTG and GPMC target modules even if the modules are unused.
2546 */
2547static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2548 void *v)
2549{
2550 struct sysc_soc_info *soc;
2551
2552 soc = container_of(nb, struct sysc_soc_info, nb);
2553
2554 switch (cmd) {
2555 case CPU_CLUSTER_PM_ENTER:
2556 break;
2557 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
2558 break;
2559 case CPU_CLUSTER_PM_EXIT:
2560 sysc_reinit_modules(soc);
2561 break;
2562 }
2563
2564 return NOTIFY_OK;
2565}
2566
2567/**
2568 * sysc_add_restored - optionally add reset and restore quirk hanlling
2569 * @ddata: device data
2570 */
2571static void sysc_add_restored(struct sysc *ddata)
2572{
2573 struct sysc_module *restored_module;
2574
2575 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2576 if (!restored_module)
2577 return;
2578
2579 restored_module->ddata = ddata;
2580
2581 mutex_lock(&sysc_soc->list_lock);
2582
2583 list_add(&restored_module->node, &sysc_soc->restored_modules);
2584
2585 if (sysc_soc->nb.notifier_call)
2586 goto out_unlock;
2587
2588 sysc_soc->nb.notifier_call = sysc_context_notifier;
2589 cpu_pm_register_notifier(&sysc_soc->nb);
2590
2591out_unlock:
2592 mutex_unlock(&sysc_soc->list_lock);
2593}
2594
a885f0fe
TL		 2595/**
2596 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2597 * @ddata: device driver data
2598 * @child: child device driver
2599 *
2600 * Allow idle for child devices as done with _od_runtime_suspend().
2601 * Otherwise many child devices will not idle because of the permanent
2602 * parent usecount set in pm_runtime_irq_safe().
2603 *
2604 * Note that the long term solution is to just modify the child device
2605 * drivers to not set pm_runtime_irq_safe() and then this can be just
2606 * dropped.
2607 */
2608static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2609{
a885f0fe
TL		 2610 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2611 dev_pm_domain_set(child, &sysc_child_pm_domain);
2612}
2613
2c355ff6
TL		 2614static int sysc_notifier_call(struct notifier_block *nb,
2615 unsigned long event, void *device)
2616{
2617 struct device *dev = device;
2618 struct sysc *ddata;
2619 int error;
2620
2621 ddata = sysc_child_to_parent(dev);
2622 if (!ddata)
2623 return NOTIFY_DONE;
2624
2625 switch (event) {
2626 case BUS_NOTIFY_ADD_DEVICE:
09dfe581
TL		 2627 error = sysc_child_add_clocks(ddata, dev);
2628 if (error)
2629 return error;
a885f0fe 2630 sysc_legacy_idle_quirk(ddata, dev);
2c355ff6
TL		 2631 break;
2632 default:
2633 break;
2634 }
2635
2636 return NOTIFY_DONE;
2637}
2638
2639static struct notifier_block sysc_nb = {
2640 .notifier_call = sysc_notifier_call,
2641};
2642
566a9b05
TL		 2643/* Device tree configured quirks */
2644struct sysc_dts_quirk {
2645 const char *name;
2646 u32 mask;
2647};
2648
2649static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2650 { .name = "ti,no-idle-on-init",
2651 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2652 { .name = "ti,no-reset-on-init",
2653 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
386cb766
TL		 2654 { .name = "ti,no-idle",
2655 .mask = SYSC_QUIRK_NO_IDLE, },
566a9b05
TL		 2656};
2657
4014c08b
TL		 2658static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2659 bool is_child)
566a9b05 2660{
566a9b05 2661 const struct property *prop;
4014c08b 2662 int i, len;
566a9b05
TL		 2663
2664 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
4014c08b
TL		 2665 const char *name = sysc_dts_quirks[i].name;
2666
2667 prop = of_get_property(np, name, &len);
566a9b05 2668 if (!prop)
d39b6ea4 2669 continue;
566a9b05
TL		 2670
2671 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
4014c08b
TL		 2672 if (is_child) {
2673 dev_warn(ddata->dev,
2674 "dts flag should be at module level for %s\n",
2675 name);
2676 }
566a9b05 2677 }
4014c08b
TL		 2678}
2679
2680static int sysc_init_dts_quirks(struct sysc *ddata)
2681{
2682 struct device_node *np = ddata->dev->of_node;
2683 int error;
2684 u32 val;
2685
2686 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
566a9b05 2687
4014c08b 2688 sysc_parse_dts_quirks(ddata, np, false);
566a9b05
TL		 2689 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2690 if (!error) {
2691 if (val > 255) {
2692 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2693 val);
2694 }
2695
2696 ddata->cfg.srst_udelay = (u8)val;
2697 }
2698
2699 return 0;
2700}
2701
0eecc636
TL		 2702static void sysc_unprepare(struct sysc *ddata)
2703{
2704 int i;
2705
aaa29bb0
TL		 2706 if (!ddata->clocks)
2707 return;
2708
0eecc636
TL		 2709 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2710 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2711 clk_unprepare(ddata->clocks[i]);
2712 }
2713}
2714
70a65240
TL		 2715/*
2716 * Common sysc register bits found on omap2, also known as type1
2717 */
2718static const struct sysc_regbits sysc_regbits_omap2 = {
2719 .dmadisable_shift = -ENODEV,
2720 .midle_shift = 12,
2721 .sidle_shift = 3,
2722 .clkact_shift = 8,
2723 .emufree_shift = 5,
2724 .enwkup_shift = 2,
2725 .srst_shift = 1,
2726 .autoidle_shift = 0,
2727};
2728
2729static const struct sysc_capabilities sysc_omap2 = {
2730 .type = TI_SYSC_OMAP2,
2731 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2732 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2733 SYSC_OMAP2_AUTOIDLE,
2734 .regbits = &sysc_regbits_omap2,
2735};
2736
2737/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2738static const struct sysc_capabilities sysc_omap2_timer = {
2739 .type = TI_SYSC_OMAP2_TIMER,
2740 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2741 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2742 SYSC_OMAP2_AUTOIDLE,
2743 .regbits = &sysc_regbits_omap2,
2744 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2745};
2746
2747/*
2748 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2749 * with different sidle position
2750 */
2751static const struct sysc_regbits sysc_regbits_omap3_sham = {
2752 .dmadisable_shift = -ENODEV,
2753 .midle_shift = -ENODEV,
2754 .sidle_shift = 4,
2755 .clkact_shift = -ENODEV,
2756 .enwkup_shift = -ENODEV,
2757 .srst_shift = 1,
2758 .autoidle_shift = 0,
2759 .emufree_shift = -ENODEV,
2760};
2761
2762static const struct sysc_capabilities sysc_omap3_sham = {
2763 .type = TI_SYSC_OMAP3_SHAM,
2764 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2765 .regbits = &sysc_regbits_omap3_sham,
2766};
2767
2768/*
2769 * AES register bits found on omap3 and later, a variant of
2770 * sysc_regbits_omap2 with different sidle position
2771 */
2772static const struct sysc_regbits sysc_regbits_omap3_aes = {
2773 .dmadisable_shift = -ENODEV,
2774 .midle_shift = -ENODEV,
2775 .sidle_shift = 6,
2776 .clkact_shift = -ENODEV,
2777 .enwkup_shift = -ENODEV,
2778 .srst_shift = 1,
2779 .autoidle_shift = 0,
2780 .emufree_shift = -ENODEV,
2781};
2782
2783static const struct sysc_capabilities sysc_omap3_aes = {
2784 .type = TI_SYSC_OMAP3_AES,
2785 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2786 .regbits = &sysc_regbits_omap3_aes,
2787};
2788
2789/*
2790 * Common sysc register bits found on omap4, also known as type2
2791 */
2792static const struct sysc_regbits sysc_regbits_omap4 = {
2793 .dmadisable_shift = 16,
2794 .midle_shift = 4,
2795 .sidle_shift = 2,
2796 .clkact_shift = -ENODEV,
2797 .enwkup_shift = -ENODEV,
2798 .emufree_shift = 1,
2799 .srst_shift = 0,
2800 .autoidle_shift = -ENODEV,
2801};
2802
2803static const struct sysc_capabilities sysc_omap4 = {
2804 .type = TI_SYSC_OMAP4,
2805 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2806 SYSC_OMAP4_SOFTRESET,
2807 .regbits = &sysc_regbits_omap4,
2808};
2809
2810static const struct sysc_capabilities sysc_omap4_timer = {
2811 .type = TI_SYSC_OMAP4_TIMER,
2812 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2813 SYSC_OMAP4_SOFTRESET,
2814 .regbits = &sysc_regbits_omap4,
2815};
2816
2817/*
2818 * Common sysc register bits found on omap4, also known as type3
2819 */
2820static const struct sysc_regbits sysc_regbits_omap4_simple = {
2821 .dmadisable_shift = -ENODEV,
2822 .midle_shift = 2,
2823 .sidle_shift = 0,
2824 .clkact_shift = -ENODEV,
2825 .enwkup_shift = -ENODEV,
2826 .srst_shift = -ENODEV,
2827 .emufree_shift = -ENODEV,
2828 .autoidle_shift = -ENODEV,
2829};
2830
2831static const struct sysc_capabilities sysc_omap4_simple = {
2832 .type = TI_SYSC_OMAP4_SIMPLE,
2833 .regbits = &sysc_regbits_omap4_simple,
2834};
2835
2836/*
2837 * SmartReflex sysc found on omap34xx
2838 */
2839static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2840 .dmadisable_shift = -ENODEV,
2841 .midle_shift = -ENODEV,
2842 .sidle_shift = -ENODEV,
2843 .clkact_shift = 20,
2844 .enwkup_shift = -ENODEV,
2845 .srst_shift = -ENODEV,
2846 .emufree_shift = -ENODEV,
2847 .autoidle_shift = -ENODEV,
2848};
2849
2850static const struct sysc_capabilities sysc_34xx_sr = {
2851 .type = TI_SYSC_OMAP34XX_SR,
2852 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2853 .regbits = &sysc_regbits_omap34xx_sr,
a885f0fe
TL		 2854 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2855 SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2856};
2857
2858/*
2859 * SmartReflex sysc found on omap36xx and later
2860 */
2861static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2862 .dmadisable_shift = -ENODEV,
2863 .midle_shift = -ENODEV,
2864 .sidle_shift = 24,
2865 .clkact_shift = -ENODEV,
2866 .enwkup_shift = 26,
2867 .srst_shift = -ENODEV,
2868 .emufree_shift = -ENODEV,
2869 .autoidle_shift = -ENODEV,
2870};
2871
2872static const struct sysc_capabilities sysc_36xx_sr = {
2873 .type = TI_SYSC_OMAP36XX_SR,
3267c081 2874 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
70a65240 2875 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2876 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2877};
2878
2879static const struct sysc_capabilities sysc_omap4_sr = {
2880 .type = TI_SYSC_OMAP4_SR,
2881 .regbits = &sysc_regbits_omap36xx_sr,
a885f0fe 2882 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
70a65240
TL		 2883};
2884
2885/*
2886 * McASP register bits found on omap4 and later
2887 */
2888static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2889 .dmadisable_shift = -ENODEV,
2890 .midle_shift = -ENODEV,
2891 .sidle_shift = 0,
2892 .clkact_shift = -ENODEV,
2893 .enwkup_shift = -ENODEV,
2894 .srst_shift = -ENODEV,
2895 .emufree_shift = -ENODEV,
2896 .autoidle_shift = -ENODEV,
2897};
2898
2899static const struct sysc_capabilities sysc_omap4_mcasp = {
2900 .type = TI_SYSC_OMAP4_MCASP,
2901 .regbits = &sysc_regbits_omap4_mcasp,
2c63a833
TL		 2902 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2903};
2904
2905/*
2906 * McASP found on dra7 and later
2907 */
2908static const struct sysc_capabilities sysc_dra7_mcasp = {
2909 .type = TI_SYSC_OMAP4_SIMPLE,
2910 .regbits = &sysc_regbits_omap4_simple,
2911 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
70a65240
TL		 2912};
2913
2914/*
2915 * FS USB host found on omap4 and later
2916 */
2917static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2918 .dmadisable_shift = -ENODEV,
2919 .midle_shift = -ENODEV,
2920 .sidle_shift = 24,
2921 .clkact_shift = -ENODEV,
2922 .enwkup_shift = 26,
2923 .srst_shift = -ENODEV,
2924 .emufree_shift = -ENODEV,
2925 .autoidle_shift = -ENODEV,
2926};
2927
2928static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2929 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2930 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2931 .regbits = &sysc_regbits_omap4_usb_host_fs,
2932};
2933
7f35e63d
FA		 2934static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2935 .dmadisable_shift = -ENODEV,
2936 .midle_shift = -ENODEV,
2937 .sidle_shift = -ENODEV,
2938 .clkact_shift = -ENODEV,
2939 .enwkup_shift = 4,
2940 .srst_shift = 0,
2941 .emufree_shift = -ENODEV,
2942 .autoidle_shift = -ENODEV,
2943};
2944
2945static const struct sysc_capabilities sysc_dra7_mcan = {
2946 .type = TI_SYSC_DRA7_MCAN,
2947 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2948 .regbits = &sysc_regbits_dra7_mcan,
e0db94fe 2949 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
7f35e63d
FA		 2950};
2951
b2745d92
SA		 2952/*
2953 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2954 */
2955static const struct sysc_capabilities sysc_pruss = {
2956 .type = TI_SYSC_PRUSS,
2957 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2958 .regbits = &sysc_regbits_omap4_simple,
2959 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2960};
2961
ef70b0bd
TL		 2962static int sysc_init_pdata(struct sysc *ddata)
2963{
2964 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
a3e92e7b 2965 struct ti_sysc_module_data *mdata;
ef70b0bd 2966
2b2f7def 2967 if (!pdata)
ef70b0bd
TL		 2968 return 0;
2969
a3e92e7b
TL		 2970 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2971 if (!mdata)
2972 return -ENOMEM;
ef70b0bd 2973
2b2f7def
TL		 2974 if (ddata->legacy_mode) {
2975 mdata->name = ddata->legacy_mode;
2976 mdata->module_pa = ddata->module_pa;
2977 mdata->module_size = ddata->module_size;
2978 mdata->offsets = ddata->offsets;
2979 mdata->nr_offsets = SYSC_MAX_REGS;
2980 mdata->cap = ddata->cap;
2981 mdata->cfg = &ddata->cfg;
2982 }
ef70b0bd 2983
a3e92e7b 2984 ddata->mdata = mdata;
ef70b0bd 2985
a3e92e7b 2986 return 0;
ef70b0bd
TL		 2987}
2988
70a65240
TL		 2989static int sysc_init_match(struct sysc *ddata)
2990{
2991 const struct sysc_capabilities *cap;
2992
2993 cap = of_device_get_match_data(ddata->dev);
2994 if (!cap)
2995 return -EINVAL;
2996
2997 ddata->cap = cap;
2998 if (ddata->cap)
2999 ddata->cfg.quirks |= ddata->cap->mod_quirks;
3000
3001 return 0;
3002}
3003
76f0f772
TL		 3004static void ti_sysc_idle(struct work_struct *work)
3005{
3006 struct sysc *ddata;
3007
3008 ddata = container_of(work, struct sysc, idle_work.work);
3009
d098913a
TL		 3010 /*
3011 * One time decrement of clock usage counts if left on from init.
3012 * Note that we disable opt clocks unconditionally in this case
3013 * as they are enabled unconditionally during init without
3014 * considering sysc_opt_clks_needed() at that point.
3015 */
3016 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3017 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
d098913a
TL		 3018 sysc_disable_main_clocks(ddata);
3019 sysc_disable_opt_clocks(ddata);
3020 sysc_clkdm_allow_idle(ddata);
3021 }
3022
3023 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
3024 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
3025 return;
3026
3027 /*
3028 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
3029 * and SYSC_QUIRK_NO_RESET_ON_INIT
3030 */
76f0f772
TL		 3031 if (pm_runtime_active(ddata->dev))
3032 pm_runtime_put_sync(ddata->dev);
3033}
3034
feaa8bae
TL		 3035/*
3036 * SoC model and features detection. Only needed for SoCs that need
3037 * special handling for quirks, no need to list others.
3038 */
3039static const struct soc_device_attribute sysc_soc_match[] = {
3040 SOC_FLAG("OMAP242*", SOC_2420),
3041 SOC_FLAG("OMAP243*", SOC_2430),
3042 SOC_FLAG("OMAP3[45]*", SOC_3430),
3043 SOC_FLAG("OMAP3[67]*", SOC_3630),
3044 SOC_FLAG("OMAP443*", SOC_4430),
3045 SOC_FLAG("OMAP446*", SOC_4460),
3046 SOC_FLAG("OMAP447*", SOC_4470),
3047 SOC_FLAG("OMAP54*", SOC_5430),
3048 SOC_FLAG("AM433", SOC_AM3),
3049 SOC_FLAG("AM43*", SOC_AM4),
3050 SOC_FLAG("DRA7*", SOC_DRA7),
3051
3052 { /* sentinel */ },
3053};
3054
3055/*
3056 * List of SoCs variants with disabled features. By default we assume all
3057 * devices in the device tree are available so no need to list those SoCs.
3058 */
3059static const struct soc_device_attribute sysc_soc_feat_match[] = {
3060 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
3061 SOC_FLAG("AM3505", DIS_SGX),
3062 SOC_FLAG("OMAP3525", DIS_SGX),
3063 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
3064 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
3065
3066 /* OMAP3630/DM3730 variants with some accelerators disabled */
3067 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
3068 SOC_FLAG("DM3725", DIS_SGX),
3069 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
3070 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
3071 SOC_FLAG("OMAP3621", DIS_ISP),
3072
3073 { /* sentinel */ },
3074};
3075
3076static int sysc_add_disabled(unsigned long base)
3077{
3078 struct sysc_address *disabled_module;
3079
3080 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
3081 if (!disabled_module)
3082 return -ENOMEM;
3083
3084 disabled_module->base = base;
3085
3086 mutex_lock(&sysc_soc->list_lock);
3087 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3088 mutex_unlock(&sysc_soc->list_lock);
3089
3090 return 0;
3091}
3092
3093/*
9d881361
TL		 3094 * One time init to detect the booted SoC, disable unavailable features
3095 * and initialize list for optional cpu_pm notifier.
3096 *
feaa8bae
TL		 3097 * Note that we initialize static data shared across all ti-sysc instances
3098 * so ddata is only used for SoC type. This can be called from module_init
3099 * once we no longer need to rely on platform data.
3100 */
9d881361 3101static int sysc_init_static_data(struct sysc *ddata)
feaa8bae
TL		 3102{
3103 const struct soc_device_attribute *match;
3104 struct ti_sysc_platform_data *pdata;
3105 unsigned long features = 0;
5f7259a5 3106 struct device_node *np;
feaa8bae
TL		 3107
3108 if (sysc_soc)
3109 return 0;
3110
3111 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3112 if (!sysc_soc)
3113 return -ENOMEM;
3114
3115 mutex_init(&sysc_soc->list_lock);
3116 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
9d881361 3117 INIT_LIST_HEAD(&sysc_soc->restored_modules);
feaa8bae
TL		 3118 sysc_soc->general_purpose = true;
3119
3120 pdata = dev_get_platdata(ddata->dev);
3121 if (pdata && pdata->soc_type_gp)
3122 sysc_soc->general_purpose = pdata->soc_type_gp();
3123
3124 match = soc_device_match(sysc_soc_match);
3125 if (match && match->data)
3126 sysc_soc->soc = (int)match->data;
3127
5f7259a5
TL		 3128 /*
3129 * Check and warn about possible old incomplete dtb. We now want to see
3130 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3131 */
3132 switch (sysc_soc->soc) {
3133 case SOC_AM3:
3134 case SOC_AM4:
4adcf4c2
TL		 3135 case SOC_4430 ... SOC_4470:
3136 case SOC_5430:
3137 case SOC_DRA7:
5f7259a5
TL		 3138 np = of_find_node_by_path("/ocp");
3139 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3140 "ti-sysc: Incomplete old dtb, please update\n");
3141 break;
3142 default:
3143 break;
3144 }
3145
4bba9bf0
TL		 3146 /* Ignore devices that are not available on HS and EMU SoCs */
3147 if (!sysc_soc->general_purpose) {
3148 switch (sysc_soc->soc) {
3149 case SOC_3430 ... SOC_3630:
3150 sysc_add_disabled(0x48304000); /* timer12 */
3151 break;
a6d90e9f
KH		 3152 case SOC_AM3:
3153 sysc_add_disabled(0x48310000); /* rng */
e879f855 3154 break;
4bba9bf0
TL		 3155 default:
3156 break;
52fbb5aa 3157 }
4bba9bf0
TL		 3158 }
3159
feaa8bae
TL		 3160 match = soc_device_match(sysc_soc_feat_match);
3161 if (!match)
3162 return 0;
3163
3164 if (match->data)
3165 features = (unsigned long)match->data;
3166
3167 /*
3168 * Add disabled devices to the list based on the module base.
3169 * Note that this must be done before we attempt to access the
3170 * device and have module revision checks working.
3171 */
3172 if (features & DIS_ISP)
3173 sysc_add_disabled(0x480bd400);
3174 if (features & DIS_IVA)
3175 sysc_add_disabled(0x5d000000);
3176 if (features & DIS_SGX)
3177 sysc_add_disabled(0x50000000);
3178
3179 return 0;
3180}
3181
9d881361 3182static void sysc_cleanup_static_data(void)
feaa8bae 3183{
9d881361 3184 struct sysc_module *restored_module;
feaa8bae
TL		 3185 struct sysc_address *disabled_module;
3186 struct list_head *pos, *tmp;
3187
3188 if (!sysc_soc)
3189 return;
3190
9d881361
TL		 3191 if (sysc_soc->nb.notifier_call)
3192 cpu_pm_unregister_notifier(&sysc_soc->nb);
3193
feaa8bae 3194 mutex_lock(&sysc_soc->list_lock);
9d881361
TL		 3195 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3196 restored_module = list_entry(pos, struct sysc_module, node);
3197 list_del(pos);
3198 kfree(restored_module);
3199 }
feaa8bae
TL		 3200 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3201 disabled_module = list_entry(pos, struct sysc_address, node);
3202 list_del(pos);
3203 kfree(disabled_module);
3204 }
3205 mutex_unlock(&sysc_soc->list_lock);
3206}
3207
3208static int sysc_check_disabled_devices(struct sysc *ddata)
3209{
3210 struct sysc_address *disabled_module;
3211 struct list_head *pos;
3212 int error = 0;
3213
3214 mutex_lock(&sysc_soc->list_lock);
3215 list_for_each(pos, &sysc_soc->disabled_modules) {
3216 disabled_module = list_entry(pos, struct sysc_address, node);
3217 if (ddata->module_pa == disabled_module->base) {
3218 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3219 error = -ENODEV;
3220 break;
3221 }
3222 }
3223 mutex_unlock(&sysc_soc->list_lock);
3224
3225 return error;
3226}
3227
6cfcd556
TL		 3228/*
3229 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3230 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3231 * are needed, we could also look at the timer register configuration.
3232 */
3233static int sysc_check_active_timer(struct sysc *ddata)
3234{
3235 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3236 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3237 return 0;
3238
3239 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3240 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
65fb7367 3241 return -ENXIO;
6cfcd556
TL		 3242
3243 return 0;
3244}
3245
c4bebea8
TL		 3246static const struct of_device_id sysc_match_table[] = {
3247 { .compatible = "simple-bus", },
3248 { /* sentinel */ },
3249};
3250
0eecc636
TL		 3251static int sysc_probe(struct platform_device *pdev)
3252{
ef70b0bd 3253 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
0eecc636
TL		 3254 struct sysc *ddata;
3255 int error;
3256
3257 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3258 if (!ddata)
3259 return -ENOMEM;
3260
2928135c
TL		 3261 ddata->offsets[SYSC_REVISION] = -ENODEV;
3262 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3263 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
0eecc636 3264 ddata->dev = &pdev->dev;
566a9b05 3265 platform_set_drvdata(pdev, ddata);
0eecc636 3266
9d881361 3267 error = sysc_init_static_data(ddata);
feaa8bae
TL		 3268 if (error)
3269 return error;
3270
70a65240
TL		 3271 error = sysc_init_match(ddata);
3272 if (error)
3273 return error;
3274
566a9b05
TL		 3275 error = sysc_init_dts_quirks(ddata);
3276 if (error)
a304f483 3277 return error;
566a9b05 3278
0eecc636
TL		 3279 error = sysc_map_and_check_registers(ddata);
3280 if (error)
a304f483 3281 return error;
0eecc636 3282
c5a2de97
TL		 3283 error = sysc_init_sysc_mask(ddata);
3284 if (error)
a304f483 3285 return error;
c5a2de97
TL		 3286
3287 error = sysc_init_idlemodes(ddata);
3288 if (error)
a304f483 3289 return error;
c5a2de97
TL		 3290
3291 error = sysc_init_syss_mask(ddata);
3292 if (error)
a304f483 3293 return error;
c5a2de97 3294
ef70b0bd
TL		 3295 error = sysc_init_pdata(ddata);
3296 if (error)
a304f483 3297 return error;
ef70b0bd 3298
42b9c5c9
TL		 3299 sysc_init_early_quirks(ddata);
3300
feaa8bae
TL		 3301 error = sysc_check_disabled_devices(ddata);
3302 if (error)
3303 return error;
3304
6cfcd556 3305 error = sysc_check_active_timer(ddata);
06a089ef 3306 if (error == -ENXIO)
3ff340e2 3307 ddata->reserved = true;
06a089ef
TL		 3308 else if (error)
3309 return error;
6cfcd556 3310
42b9c5c9
TL		 3311 error = sysc_get_clocks(ddata);
3312 if (error)
3313 return error;
3314
5062236e
TL		 3315 error = sysc_init_resets(ddata);
3316 if (error)
a304f483 3317 goto unprepare;
566a9b05
TL		 3318
3319 error = sysc_init_module(ddata);
3320 if (error)
3321 goto unprepare;
3322
1a5cd7c2 3323 pm_runtime_enable(ddata->dev);
cea08169 3324 error = pm_runtime_resume_and_get(ddata->dev);
0eecc636 3325 if (error < 0) {
0eecc636
TL		 3326 pm_runtime_disable(ddata->dev);
3327 goto unprepare;
3328 }
3329
cdc56c11 3330 /* Balance use counts as PM runtime should have enabled these all */
cdc56c11
TK		 3331 if (!(ddata->cfg.quirks &
3332 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3333 sysc_disable_main_clocks(ddata);
3334 sysc_disable_opt_clocks(ddata);
3335 sysc_clkdm_allow_idle(ddata);
3336 }
3337
4097c9a6
TL		 3338 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3339 reset_control_assert(ddata->rsts);
3340
0eecc636
TL		 3341 sysc_show_registers(ddata);
3342
2c355ff6 3343 ddata->dev->type = &sysc_device_type;
3ff340e2
TL		 3344
3345 if (!ddata->reserved) {
3346 error = of_platform_populate(ddata->dev->of_node,
3347 sysc_match_table,
3348 pdata ? pdata->auxdata : NULL,
3349 ddata->dev);
3350 if (error)
3351 goto err;
3352 }
0eecc636 3353
76f0f772
TL		 3354 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3355
3356 /* At least earlycon won't survive without deferred idle */
d098913a
TL		 3357 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3358 SYSC_QUIRK_NO_IDLE_ON_INIT |
76f0f772
TL		 3359 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3360 schedule_delayed_work(&ddata->idle_work, 3000);
3361 } else {
3362 pm_runtime_put(&pdev->dev);
3363 }
0eecc636 3364
9d881361
TL		 3365 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3366 sysc_add_restored(ddata);
3367
0eecc636
TL		 3368 return 0;
3369
3370err:
0eecc636
TL		 3371 pm_runtime_put_sync(&pdev->dev);
3372 pm_runtime_disable(&pdev->dev);
3373unprepare:
3374 sysc_unprepare(ddata);
3375
3376 return error;
3377}
3378
684be5a4
TL		 3379static int sysc_remove(struct platform_device *pdev)
3380{
3381 struct sysc *ddata = platform_get_drvdata(pdev);
3382 int error;
3383
76f0f772
TL		 3384 cancel_delayed_work_sync(&ddata->idle_work);
3385
cea08169 3386 error = pm_runtime_resume_and_get(ddata->dev);
684be5a4 3387 if (error < 0) {
684be5a4
TL		 3388 pm_runtime_disable(ddata->dev);
3389 goto unprepare;
3390 }
3391
3392 of_platform_depopulate(&pdev->dev);
3393
684be5a4
TL		 3394 pm_runtime_put_sync(&pdev->dev);
3395 pm_runtime_disable(&pdev->dev);
a7b5d7c4
TL		 3396
3397 if (!reset_control_status(ddata->rsts))
3398 reset_control_assert(ddata->rsts);
684be5a4
TL		 3399
3400unprepare:
3401 sysc_unprepare(ddata);
3402
3403 return 0;
3404}
3405
0eecc636 3406static const struct of_device_id sysc_match[] = {
70a65240
TL		 3407 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3408 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3409 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3410 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3411 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3412 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3413 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3414 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3415 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3416 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3417 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2c63a833 3418 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
70a65240
TL		 3419 { .compatible = "ti,sysc-usb-host-fs",
3420 .data = &sysc_omap4_usb_host_fs, },
7f35e63d 3421 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
b2745d92 3422 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
0eecc636
TL		 3423 { },
3424};
3425MODULE_DEVICE_TABLE(of, sysc_match);
3426
3427static struct platform_driver sysc_driver = {
3428 .probe = sysc_probe,
684be5a4 3429 .remove = sysc_remove,
0eecc636
TL		 3430 .driver = {
3431 .name = "ti-sysc",
3432 .of_match_table = sysc_match,
3433 .pm = &sysc_pm_ops,
3434 },
3435};
2c355ff6
TL		 3436
3437static int __init sysc_init(void)
3438{
3439 bus_register_notifier(&platform_bus_type, &sysc_nb);
3440
3441 return platform_driver_register(&sysc_driver);
3442}
3443module_init(sysc_init);
3444
3445static void __exit sysc_exit(void)
3446{
3447 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3448 platform_driver_unregister(&sysc_driver);
9d881361 3449 sysc_cleanup_static_data();
2c355ff6
TL		 3450}
3451module_exit(sysc_exit);
0eecc636
TL		 3452
3453MODULE_DESCRIPTION("TI sysc interconnect target driver");
3454MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)