[linux-2.6-block.git] / drivers / bus / omap_l3_noc.h

/*
 * OMAP L3 Interconnect  error handling driver header
 *
 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
 *	sricharan <r.sricharan@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
#ifndef __OMAP_L3_NOC_H
#define __OMAP_L3_NOC_H

#define MAX_L3_MODULES			3
#define MAX_CLKDM_TARGETS		31

#define CLEAR_STDERR_LOG		(1 << 31)
#define CUSTOM_ERROR			0x2
#define STANDARD_ERROR			0x0
#define INBAND_ERROR			0x0
#define L3_APPLICATION_ERROR		0x0
#define L3_DEBUG_ERROR			0x1

/* L3 TARG register offsets */
#define L3_TARG_STDERRLOG_MAIN		0x48
#define L3_TARG_STDERRLOG_HDR		0x4c
#define L3_TARG_STDERRLOG_MSTADDR	0x50
#define L3_TARG_STDERRLOG_INFO		0x58
#define L3_TARG_STDERRLOG_SLVOFSLSB	0x5c
#define L3_TARG_STDERRLOG_CINFO_INFO	0x64
#define L3_TARG_STDERRLOG_CINFO_MSTADDR	0x68
#define L3_TARG_STDERRLOG_CINFO_OPCODE	0x6c
#define L3_FLAGMUX_REGERR0		0xc
#define L3_FLAGMUX_MASK0		0x8

#define L3_TARGET_NOT_SUPPORTED		NULL

#define L3_BASE_IS_SUBMODULE		((void __iomem *)(1 << 0))

static const char * const l3_transaction_type[] = {
	/* 0 0 0 */ "Idle",
	/* 0 0 1 */ "Write",
	/* 0 1 0 */ "Read",
	/* 0 1 1 */ "ReadEx",
	/* 1 0 0 */ "Read Link",
	/* 1 0 1 */ "Write Non-Posted",
	/* 1 1 0 */ "Write Conditional",
	/* 1 1 1 */ "Write Broadcast",
};

/**
 * struct l3_masters_data - L3 Master information
 * @id:		ID of the L3 Master
 * @name:	master name
 */
struct l3_masters_data {
	u32 id;
	char *name;
};

/**
 * struct l3_target_data - L3 Target information
 * @offset:	Offset from base for L3 Target
 * @name:	Target name
 *
 * Target information is organized indexed by bit field definitions.
 */
struct l3_target_data {
	u32 offset;
	char *name;
};

/**
 * struct l3_flagmux_data - Flag Mux information
 * @offset:	offset from base for flagmux register
 * @l3_targ:	array indexed by flagmux index (bit offset) pointing to the
 *		target data. unsupported ones are marked with
 *		L3_TARGET_NOT_SUPPORTED
 * @num_targ_data: number of entries in target data
 * @mask_app_bits: ignore these from raw application irq status
 * @mask_dbg_bits: ignore these from raw debug irq status
 */
struct l3_flagmux_data {
	u32 offset;
	struct l3_target_data *l3_targ;
	u8 num_targ_data;
	u32 mask_app_bits;
	u32 mask_dbg_bits;
};


/**
 * struct omap_l3 - Description of data relevant for L3 bus.
 * @dev:	device representing the bus (populated runtime)
 * @l3_base:	base addresses of modules (populated runtime if 0)
 *		if set to L3_BASE_IS_SUBMODULE, then uses previous
 *		module index as the base address
 * @l3_flag_mux: array containing flag mux data per module
 *		 offset from corresponding module base indexed per
 *		 module.
 * @num_modules: number of clock domains / modules.
 * @l3_masters:	array pointing to master data containing name and register
 *		offset for the master.
 * @num_master: number of masters
 * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
 * @debug_irq:	irq number of the debug interrupt (populated runtime)
 * @app_irq:	irq number of the application interrupt (populated runtime)
 */
struct omap_l3 {
	struct device *dev;

	void __iomem *l3_base[MAX_L3_MODULES];
	struct l3_flagmux_data **l3_flagmux;
	int num_modules;

	struct l3_masters_data *l3_masters;
	int num_masters;
	u32 mst_addr_mask;

	int debug_irq;
	int app_irq;
};

static struct l3_target_data omap_l3_target_data_clk1[] = {
	{0x100,	"DMM1",},
	{0x200,	"DMM2",},
	{0x300,	"ABE",},
	{0x400,	"L4CFG",},
	{0x600,	"CLK2PWRDISC",},
	{0x0,	"HOSTCLK1",},
	{0x900,	"L4WAKEUP",},
};

static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
	.offset = 0x500,
	.l3_targ = omap_l3_target_data_clk1,
	.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
};


static struct l3_target_data omap_l3_target_data_clk2[] = {
	{0x500,	"CORTEXM3",},
	{0x300,	"DSS",},
	{0x100,	"GPMC",},
	{0x400,	"ISS",},
	{0x700,	"IVAHD",},
	{0xD00,	"AES1",},
	{0x900,	"L4PER0",},
	{0x200,	"OCMRAM",},
	{0x100,	"GPMCsERROR",},
	{0x600,	"SGX",},
	{0x800,	"SL2",},
	{0x1600, "C2C",},
	{0x1100, "PWRDISCCLK1",},
	{0xF00,	"SHA1",},
	{0xE00,	"AES2",},
	{0xC00,	"L4PER3",},
	{0xA00,	"L4PER1",},
	{0xB00,	"L4PER2",},
	{0x0,	"HOSTCLK2",},
	{0x1800, "CAL",},
	{0x1700, "LLI",},
};

static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
	.offset = 0x1000,
	.l3_targ = omap_l3_target_data_clk2,
	.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
};


static struct l3_target_data omap_l3_target_data_clk3[] = {
	{0x0100, "EMUSS",},
	{0x0300, "DEBUG SOURCE",},
	{0x0,	"HOST CLK3",},
};

static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
	.offset = 0x0200,
	.l3_targ = omap_l3_target_data_clk3,
	.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
};

static struct l3_masters_data omap_l3_masters[] = {
	{ 0x0 , "MPU"},
	{ 0x10, "CS_ADP"},
	{ 0x14, "xxx"},
	{ 0x20, "DSP"},
	{ 0x30, "IVAHD"},
	{ 0x40, "ISS"},
	{ 0x44, "DucatiM3"},
	{ 0x48, "FaceDetect"},
	{ 0x50, "SDMA_Rd"},
	{ 0x54, "SDMA_Wr"},
	{ 0x58, "xxx"},
	{ 0x5C, "xxx"},
	{ 0x60, "SGX"},
	{ 0x70, "DSS"},
	{ 0x80, "C2C"},
	{ 0x88, "xxx"},
	{ 0x8C, "xxx"},
	{ 0x90, "HSI"},
	{ 0xA0, "MMC1"},
	{ 0xA4, "MMC2"},
	{ 0xA8, "MMC6"},
	{ 0xB0, "UNIPRO1"},
	{ 0xC0, "USBHOSTHS"},
	{ 0xC4, "USBOTGHS"},
	{ 0xC8, "USBHOSTFS"}
};

static struct l3_flagmux_data *omap_l3_flagmux[] = {
	&omap_l3_flagmux_clk1,
	&omap_l3_flagmux_clk2,
	&omap_l3_flagmux_clk3,
};

static const struct omap_l3 omap_l3_data = {
	.l3_flagmux = omap_l3_flagmux,
	.num_modules = ARRAY_SIZE(omap_l3_flagmux),
	.l3_masters = omap_l3_masters,
	.num_masters = ARRAY_SIZE(omap_l3_masters),
	/* The 6 MSBs of register field used to distinguish initiator */
	.mst_addr_mask = 0xFC,
};

#endif	/* __OMAP_L3_NOC_H */
Commit	Line	Data
ed0e3520	1	/*
c10d5c9e	2	* OMAP L3 Interconnect error handling driver header
ed0e3520	3	*
c5f2aea0	4	* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
ed0e3520	5	* Santosh Shilimkar <santosh.shilimkar@ti.com>
	6	* sricharan <r.sricharan@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
c5f2aea0 NM	9	* it under the terms of the GNU General Public License version 2 as
c5f2aea0 NM	10	* published by the Free Software Foundation.
ed0e3520	11	*
c5f2aea0 NM	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
ed0e3520	15	* GNU General Public License for more details.
ed0e3520	16	*/
c10d5c9e S	17	#ifndef __OMAP_L3_NOC_H
c10d5c9e S	18	#define __OMAP_L3_NOC_H
2722e56d	19
0659452d	20	#define MAX_L3_MODULES 3
97708c08	21	#define MAX_CLKDM_TARGETS 31
0659452d	22
2722e56d SS	23	#define CLEAR_STDERR_LOG (1 << 31)
	24	#define CUSTOM_ERROR 0x2
	25	#define STANDARD_ERROR 0x0
	26	#define INBAND_ERROR 0x0
2722e56d SS	27	#define L3_APPLICATION_ERROR 0x0
	28	#define L3_DEBUG_ERROR 0x1
	29
342fd144	30	/* L3 TARG register offsets */
ed0e3520	31	#define L3_TARG_STDERRLOG_MAIN 0x48
7f9de02d	32	#define L3_TARG_STDERRLOG_HDR 0x4c
c98aa7aa	33	#define L3_TARG_STDERRLOG_MSTADDR 0x50
cf52b2ec	34	#define L3_TARG_STDERRLOG_INFO 0x58
ed0e3520	35	#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
cf52b2ec	36	#define L3_TARG_STDERRLOG_CINFO_INFO 0x64
c98aa7aa	37	#define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
7f9de02d	38	#define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c
ed0e3520	39	#define L3_FLAGMUX_REGERR0 0xc
3340d739 RN	40	#define L3_FLAGMUX_MASK0 0x8
	41
	42	#define L3_TARGET_NOT_SUPPORTED NULL
	43
f33ddf74 NM	44	#define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
f33ddf74 NM	45
7f9de02d NM	46	static const char * const l3_transaction_type[] = {
	47	/* 0 0 0 */ "Idle",
	48	/* 0 0 1 */ "Write",
	49	/* 0 1 0 */ "Read",
	50	/* 0 1 1 */ "ReadEx",
	51	/* 1 0 0 */ "Read Link",
	52	/* 1 0 1 */ "Write Non-Posted",
	53	/* 1 1 0 */ "Write Conditional",
	54	/* 1 1 1 */ "Write Broadcast",
	55	};
	56
f0a6e654 NM	57	/**
	58	* struct l3_masters_data - L3 Master information
	59	* @id: ID of the L3 Master
	60	* @name: master name
	61	*/
	62	struct l3_masters_data {
	63	u32 id;
	64	char *name;
	65	};
	66
3ae9af7c NM	67	/**
	68	* struct l3_target_data - L3 Target information
	69	* @offset: Offset from base for L3 Target
	70	* @name: Target name
	71	*
	72	* Target information is organized indexed by bit field definitions.
	73	*/
	74	struct l3_target_data {
	75	u32 offset;
	76	char *name;
	77	};
	78
97708c08 NM	79	/**
	80	* struct l3_flagmux_data - Flag Mux information
	81	* @offset: offset from base for flagmux register
	82	* @l3_targ: array indexed by flagmux index (bit offset) pointing to the
	83	* target data. unsupported ones are marked with
	84	* L3_TARGET_NOT_SUPPORTED
	85	* @num_targ_data: number of entries in target data
2100b595 AM	86	* @mask_app_bits: ignore these from raw application irq status
2100b595 AM	87	* @mask_dbg_bits: ignore these from raw debug irq status
97708c08 NM	88	*/
	89	struct l3_flagmux_data {
	90	u32 offset;
	91	struct l3_target_data *l3_targ;
	92	u8 num_targ_data;
2100b595 AM	93	u32 mask_app_bits;
2100b595 AM	94	u32 mask_dbg_bits;
97708c08 NM	95	};
97708c08 NM	96
0659452d S	97
	98	/**
	99	* struct omap_l3 - Description of data relevant for L3 bus.
	100	* @dev: device representing the bus (populated runtime)
f33ddf74 NM	101	* @l3_base: base addresses of modules (populated runtime if 0)
	102	* if set to L3_BASE_IS_SUBMODULE, then uses previous
	103	* module index as the base address
97708c08	104	* @l3_flag_mux: array containing flag mux data per module
0659452d S	105	* offset from corresponding module base indexed per
	106	* module.
	107	* @num_modules: number of clock domains / modules.
	108	* @l3_masters: array pointing to master data containing name and register
	109	* offset for the master.
	110	* @num_master: number of masters
d4d8819e	111	* @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
0659452d S	112	* @debug_irq: irq number of the debug interrupt (populated runtime)
	113	* @app_irq: irq number of the application interrupt (populated runtime)
	114	*/
	115	struct omap_l3 {
	116	struct device *dev;
	117
	118	void __iomem *l3_base[MAX_L3_MODULES];
97708c08	119	struct l3_flagmux_data **l3_flagmux;
0659452d S	120	int num_modules;
	121
	122	struct l3_masters_data *l3_masters;
	123	int num_masters;
d4d8819e	124	u32 mst_addr_mask;
0659452d	125
0659452d S	126	int debug_irq;
	127	int app_irq;
	128	};
	129
97708c08	130	static struct l3_target_data omap_l3_target_data_clk1[] = {
3ae9af7c NM	131	{0x100, "DMM1",},
	132	{0x200, "DMM2",},
	133	{0x300, "ABE",},
	134	{0x400, "L4CFG",},
	135	{0x600, "CLK2PWRDISC",},
	136	{0x0, "HOSTCLK1",},
	137	{0x900, "L4WAKEUP",},
2722e56d SS	138	};
2722e56d SS	139
97708c08 NM	140	static struct l3_flagmux_data omap_l3_flagmux_clk1 = {
	141	.offset = 0x500,
	142	.l3_targ = omap_l3_target_data_clk1,
	143	.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1),
	144	};
	145
	146
	147	static struct l3_target_data omap_l3_target_data_clk2[] = {
3ae9af7c NM	148	{0x500, "CORTEXM3",},
	149	{0x300, "DSS",},
	150	{0x100, "GPMC",},
	151	{0x400, "ISS",},
	152	{0x700, "IVAHD",},
	153	{0xD00, "AES1",},
	154	{0x900, "L4PER0",},
	155	{0x200, "OCMRAM",},
	156	{0x100, "GPMCsERROR",},
	157	{0x600, "SGX",},
	158	{0x800, "SL2",},
	159	{0x1600, "C2C",},
	160	{0x1100, "PWRDISCCLK1",},
	161	{0xF00, "SHA1",},
	162	{0xE00, "AES2",},
	163	{0xC00, "L4PER3",},
	164	{0xA00, "L4PER1",},
	165	{0xB00, "L4PER2",},
	166	{0x0, "HOSTCLK2",},
	167	{0x1800, "CAL",},
	168	{0x1700, "LLI",},
2722e56d SS	169	};
2722e56d SS	170
97708c08 NM	171	static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
	172	.offset = 0x1000,
	173	.l3_targ = omap_l3_target_data_clk2,
	174	.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2),
	175	};
	176
	177
	178	static struct l3_target_data omap_l3_target_data_clk3[] = {
3ae9af7c NM	179	{0x0100, "EMUSS",},
	180	{0x0300, "DEBUG SOURCE",},
	181	{0x0, "HOST CLK3",},
2722e56d SS	182	};
2722e56d SS	183
97708c08 NM	184	static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
	185	.offset = 0x0200,
	186	.l3_targ = omap_l3_target_data_clk3,
	187	.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
	188	};
	189
0659452d	190	static struct l3_masters_data omap_l3_masters[] = {
551a9fa9	191	{ 0x0 , "MPU"},
	192	{ 0x10, "CS_ADP"},
	193	{ 0x14, "xxx"},
	194	{ 0x20, "DSP"},
	195	{ 0x30, "IVAHD"},
	196	{ 0x40, "ISS"},
	197	{ 0x44, "DucatiM3"},
	198	{ 0x48, "FaceDetect"},
	199	{ 0x50, "SDMA_Rd"},
	200	{ 0x54, "SDMA_Wr"},
	201	{ 0x58, "xxx"},
	202	{ 0x5C, "xxx"},
	203	{ 0x60, "SGX"},
	204	{ 0x70, "DSS"},
	205	{ 0x80, "C2C"},
	206	{ 0x88, "xxx"},
	207	{ 0x8C, "xxx"},
	208	{ 0x90, "HSI"},
	209	{ 0xA0, "MMC1"},
	210	{ 0xA4, "MMC2"},
	211	{ 0xA8, "MMC6"},
	212	{ 0xB0, "UNIPRO1"},
	213	{ 0xC0, "USBHOSTHS"},
	214	{ 0xC4, "USBOTGHS"},
	215	{ 0xC8, "USBHOSTFS"}
	216	};
	217
97708c08 NM	218	static struct l3_flagmux_data *omap_l3_flagmux[] = {
	219	&omap_l3_flagmux_clk1,
	220	&omap_l3_flagmux_clk2,
	221	&omap_l3_flagmux_clk3,
2722e56d SS	222	};
2722e56d SS	223
0659452d S	224	static const struct omap_l3 omap_l3_data = {
0659452d S	225	.l3_flagmux = omap_l3_flagmux,
97708c08	226	.num_modules = ARRAY_SIZE(omap_l3_flagmux),
0659452d S	227	.l3_masters = omap_l3_masters,
0659452d S	228	.num_masters = ARRAY_SIZE(omap_l3_masters),
d4d8819e NM	229	/* The 6 MSBs of register field used to distinguish initiator */
d4d8819e NM	230	.mst_addr_mask = 0xFC,
2722e56d	231	};
c10d5c9e S	232
c10d5c9e S	233	#endif /* __OMAP_L3_NOC_H */