Commit | Line | Data |
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ed0e3520 | 1 | /* |
c10d5c9e | 2 | * OMAP L3 Interconnect error handling driver header |
ed0e3520 | 3 | * |
e7309c26 | 4 | * Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/ |
ed0e3520 | 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
6 | * sricharan <r.sricharan@ti.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
c5f2aea0 NM |
9 | * it under the terms of the GNU General Public License version 2 as |
10 | * published by the Free Software Foundation. | |
ed0e3520 | 11 | * |
c5f2aea0 NM |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
ed0e3520 | 15 | * GNU General Public License for more details. |
ed0e3520 | 16 | */ |
c10d5c9e S |
17 | #ifndef __OMAP_L3_NOC_H |
18 | #define __OMAP_L3_NOC_H | |
2722e56d | 19 | |
0659452d | 20 | #define MAX_L3_MODULES 3 |
97708c08 | 21 | #define MAX_CLKDM_TARGETS 31 |
0659452d | 22 | |
2722e56d SS |
23 | #define CLEAR_STDERR_LOG (1 << 31) |
24 | #define CUSTOM_ERROR 0x2 | |
25 | #define STANDARD_ERROR 0x0 | |
26 | #define INBAND_ERROR 0x0 | |
2722e56d SS |
27 | #define L3_APPLICATION_ERROR 0x0 |
28 | #define L3_DEBUG_ERROR 0x1 | |
29 | ||
342fd144 | 30 | /* L3 TARG register offsets */ |
ed0e3520 | 31 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
7f9de02d | 32 | #define L3_TARG_STDERRLOG_HDR 0x4c |
c98aa7aa | 33 | #define L3_TARG_STDERRLOG_MSTADDR 0x50 |
cf52b2ec | 34 | #define L3_TARG_STDERRLOG_INFO 0x58 |
ed0e3520 | 35 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
cf52b2ec | 36 | #define L3_TARG_STDERRLOG_CINFO_INFO 0x64 |
c98aa7aa | 37 | #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68 |
7f9de02d | 38 | #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c |
ed0e3520 | 39 | #define L3_FLAGMUX_REGERR0 0xc |
3340d739 RN |
40 | #define L3_FLAGMUX_MASK0 0x8 |
41 | ||
42 | #define L3_TARGET_NOT_SUPPORTED NULL | |
43 | ||
f33ddf74 NM |
44 | #define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0)) |
45 | ||
7f9de02d NM |
46 | static const char * const l3_transaction_type[] = { |
47 | /* 0 0 0 */ "Idle", | |
48 | /* 0 0 1 */ "Write", | |
49 | /* 0 1 0 */ "Read", | |
50 | /* 0 1 1 */ "ReadEx", | |
51 | /* 1 0 0 */ "Read Link", | |
52 | /* 1 0 1 */ "Write Non-Posted", | |
53 | /* 1 1 0 */ "Write Conditional", | |
54 | /* 1 1 1 */ "Write Broadcast", | |
55 | }; | |
56 | ||
f0a6e654 NM |
57 | /** |
58 | * struct l3_masters_data - L3 Master information | |
59 | * @id: ID of the L3 Master | |
60 | * @name: master name | |
61 | */ | |
62 | struct l3_masters_data { | |
63 | u32 id; | |
64 | char *name; | |
65 | }; | |
66 | ||
3ae9af7c NM |
67 | /** |
68 | * struct l3_target_data - L3 Target information | |
69 | * @offset: Offset from base for L3 Target | |
70 | * @name: Target name | |
71 | * | |
72 | * Target information is organized indexed by bit field definitions. | |
73 | */ | |
74 | struct l3_target_data { | |
75 | u32 offset; | |
76 | char *name; | |
77 | }; | |
78 | ||
97708c08 NM |
79 | /** |
80 | * struct l3_flagmux_data - Flag Mux information | |
81 | * @offset: offset from base for flagmux register | |
82 | * @l3_targ: array indexed by flagmux index (bit offset) pointing to the | |
83 | * target data. unsupported ones are marked with | |
84 | * L3_TARGET_NOT_SUPPORTED | |
85 | * @num_targ_data: number of entries in target data | |
2100b595 AM |
86 | * @mask_app_bits: ignore these from raw application irq status |
87 | * @mask_dbg_bits: ignore these from raw debug irq status | |
97708c08 NM |
88 | */ |
89 | struct l3_flagmux_data { | |
90 | u32 offset; | |
91 | struct l3_target_data *l3_targ; | |
92 | u8 num_targ_data; | |
2100b595 AM |
93 | u32 mask_app_bits; |
94 | u32 mask_dbg_bits; | |
97708c08 NM |
95 | }; |
96 | ||
0659452d S |
97 | |
98 | /** | |
99 | * struct omap_l3 - Description of data relevant for L3 bus. | |
100 | * @dev: device representing the bus (populated runtime) | |
f33ddf74 NM |
101 | * @l3_base: base addresses of modules (populated runtime if 0) |
102 | * if set to L3_BASE_IS_SUBMODULE, then uses previous | |
103 | * module index as the base address | |
97708c08 | 104 | * @l3_flag_mux: array containing flag mux data per module |
0659452d S |
105 | * offset from corresponding module base indexed per |
106 | * module. | |
107 | * @num_modules: number of clock domains / modules. | |
108 | * @l3_masters: array pointing to master data containing name and register | |
109 | * offset for the master. | |
110 | * @num_master: number of masters | |
d4d8819e | 111 | * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet |
0659452d S |
112 | * @debug_irq: irq number of the debug interrupt (populated runtime) |
113 | * @app_irq: irq number of the application interrupt (populated runtime) | |
114 | */ | |
115 | struct omap_l3 { | |
116 | struct device *dev; | |
117 | ||
118 | void __iomem *l3_base[MAX_L3_MODULES]; | |
97708c08 | 119 | struct l3_flagmux_data **l3_flagmux; |
0659452d S |
120 | int num_modules; |
121 | ||
122 | struct l3_masters_data *l3_masters; | |
123 | int num_masters; | |
d4d8819e | 124 | u32 mst_addr_mask; |
0659452d | 125 | |
0659452d S |
126 | int debug_irq; |
127 | int app_irq; | |
128 | }; | |
129 | ||
97708c08 | 130 | static struct l3_target_data omap_l3_target_data_clk1[] = { |
3ae9af7c NM |
131 | {0x100, "DMM1",}, |
132 | {0x200, "DMM2",}, | |
133 | {0x300, "ABE",}, | |
134 | {0x400, "L4CFG",}, | |
135 | {0x600, "CLK2PWRDISC",}, | |
136 | {0x0, "HOSTCLK1",}, | |
137 | {0x900, "L4WAKEUP",}, | |
2722e56d SS |
138 | }; |
139 | ||
97708c08 NM |
140 | static struct l3_flagmux_data omap_l3_flagmux_clk1 = { |
141 | .offset = 0x500, | |
142 | .l3_targ = omap_l3_target_data_clk1, | |
143 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk1), | |
144 | }; | |
145 | ||
146 | ||
147 | static struct l3_target_data omap_l3_target_data_clk2[] = { | |
3ae9af7c NM |
148 | {0x500, "CORTEXM3",}, |
149 | {0x300, "DSS",}, | |
150 | {0x100, "GPMC",}, | |
151 | {0x400, "ISS",}, | |
152 | {0x700, "IVAHD",}, | |
153 | {0xD00, "AES1",}, | |
154 | {0x900, "L4PER0",}, | |
155 | {0x200, "OCMRAM",}, | |
156 | {0x100, "GPMCsERROR",}, | |
157 | {0x600, "SGX",}, | |
158 | {0x800, "SL2",}, | |
159 | {0x1600, "C2C",}, | |
160 | {0x1100, "PWRDISCCLK1",}, | |
161 | {0xF00, "SHA1",}, | |
162 | {0xE00, "AES2",}, | |
163 | {0xC00, "L4PER3",}, | |
164 | {0xA00, "L4PER1",}, | |
165 | {0xB00, "L4PER2",}, | |
166 | {0x0, "HOSTCLK2",}, | |
167 | {0x1800, "CAL",}, | |
168 | {0x1700, "LLI",}, | |
2722e56d SS |
169 | }; |
170 | ||
97708c08 NM |
171 | static struct l3_flagmux_data omap_l3_flagmux_clk2 = { |
172 | .offset = 0x1000, | |
173 | .l3_targ = omap_l3_target_data_clk2, | |
174 | .num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk2), | |
175 | }; | |
176 | ||
177 | ||
e7309c26 SA |
178 | static struct l3_target_data omap4_l3_target_data_clk3[] = { |
179 | {0x0100, "DEBUGSS",}, | |
2722e56d SS |
180 | }; |
181 | ||
e7309c26 | 182 | static struct l3_flagmux_data omap4_l3_flagmux_clk3 = { |
97708c08 | 183 | .offset = 0x0200, |
e7309c26 SA |
184 | .l3_targ = omap4_l3_target_data_clk3, |
185 | .num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3), | |
97708c08 NM |
186 | }; |
187 | ||
0659452d | 188 | static struct l3_masters_data omap_l3_masters[] = { |
41fc619d NM |
189 | { 0x00, "MPU"}, |
190 | { 0x04, "CS_ADP"}, | |
191 | { 0x05, "xxx"}, | |
192 | { 0x08, "DSP"}, | |
193 | { 0x0C, "IVAHD"}, | |
194 | { 0x10, "ISS"}, | |
195 | { 0x11, "DucatiM3"}, | |
196 | { 0x12, "FaceDetect"}, | |
197 | { 0x14, "SDMA_Rd"}, | |
198 | { 0x15, "SDMA_Wr"}, | |
199 | { 0x16, "xxx"}, | |
200 | { 0x17, "xxx"}, | |
201 | { 0x18, "SGX"}, | |
202 | { 0x1C, "DSS"}, | |
203 | { 0x20, "C2C"}, | |
204 | { 0x22, "xxx"}, | |
205 | { 0x23, "xxx"}, | |
206 | { 0x24, "HSI"}, | |
207 | { 0x28, "MMC1"}, | |
208 | { 0x29, "MMC2"}, | |
209 | { 0x2A, "MMC6"}, | |
210 | { 0x2C, "UNIPRO1"}, | |
211 | { 0x30, "USBHOSTHS"}, | |
212 | { 0x31, "USBOTGHS"}, | |
213 | { 0x32, "USBHOSTFS"} | |
551a9fa9 | 214 | }; |
215 | ||
e7309c26 | 216 | static struct l3_flagmux_data *omap4_l3_flagmux[] = { |
97708c08 NM |
217 | &omap_l3_flagmux_clk1, |
218 | &omap_l3_flagmux_clk2, | |
e7309c26 | 219 | &omap4_l3_flagmux_clk3, |
2722e56d SS |
220 | }; |
221 | ||
e7309c26 SA |
222 | static const struct omap_l3 omap4_l3_data = { |
223 | .l3_flagmux = omap4_l3_flagmux, | |
224 | .num_modules = ARRAY_SIZE(omap4_l3_flagmux), | |
0659452d S |
225 | .l3_masters = omap_l3_masters, |
226 | .num_masters = ARRAY_SIZE(omap_l3_masters), | |
d4d8819e NM |
227 | /* The 6 MSBs of register field used to distinguish initiator */ |
228 | .mst_addr_mask = 0xFC, | |
2722e56d | 229 | }; |
c10d5c9e | 230 | |
e7309c26 SA |
231 | /* OMAP5 data */ |
232 | static struct l3_target_data omap5_l3_target_data_clk3[] = { | |
233 | {0x0100, "L3INSTR",}, | |
234 | {0x0300, "DEBUGSS",}, | |
235 | {0x0, "HOSTCLK3",}, | |
236 | }; | |
237 | ||
238 | static struct l3_flagmux_data omap5_l3_flagmux_clk3 = { | |
239 | .offset = 0x0200, | |
240 | .l3_targ = omap5_l3_target_data_clk3, | |
241 | .num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3), | |
242 | }; | |
243 | ||
244 | static struct l3_flagmux_data *omap5_l3_flagmux[] = { | |
245 | &omap_l3_flagmux_clk1, | |
246 | &omap_l3_flagmux_clk2, | |
247 | &omap5_l3_flagmux_clk3, | |
248 | }; | |
249 | ||
250 | static const struct omap_l3 omap5_l3_data = { | |
251 | .l3_flagmux = omap5_l3_flagmux, | |
252 | .num_modules = ARRAY_SIZE(omap5_l3_flagmux), | |
253 | .l3_masters = omap_l3_masters, | |
254 | .num_masters = ARRAY_SIZE(omap_l3_masters), | |
255 | /* The 6 MSBs of register field used to distinguish initiator */ | |
256 | .mst_addr_mask = 0x7E0, | |
257 | }; | |
258 | ||
53a848be RN |
259 | /* DRA7 data */ |
260 | static struct l3_target_data dra_l3_target_data_clk1[] = { | |
261 | {0x2a00, "AES1",}, | |
262 | {0x0200, "DMM_P1",}, | |
263 | {0x0600, "DSP2_SDMA",}, | |
264 | {0x0b00, "EVE2",}, | |
265 | {0x1300, "DMM_P2",}, | |
266 | {0x2c00, "AES2",}, | |
267 | {0x0300, "DSP1_SDMA",}, | |
268 | {0x0a00, "EVE1",}, | |
269 | {0x0c00, "EVE3",}, | |
270 | {0x0d00, "EVE4",}, | |
271 | {0x2900, "DSS",}, | |
272 | {0x0100, "GPMC",}, | |
273 | {0x3700, "PCIE1",}, | |
274 | {0x1600, "IVA_CONFIG",}, | |
275 | {0x1800, "IVA_SL2IF",}, | |
276 | {0x0500, "L4_CFG",}, | |
277 | {0x1d00, "L4_WKUP",}, | |
278 | {0x3800, "PCIE2",}, | |
279 | {0x3300, "SHA2_1",}, | |
280 | {0x1200, "GPU",}, | |
281 | {0x1000, "IPU1",}, | |
282 | {0x1100, "IPU2",}, | |
283 | {0x2000, "TPCC_EDMA",}, | |
284 | {0x2e00, "TPTC1_EDMA",}, | |
285 | {0x2b00, "TPTC2_EDMA",}, | |
286 | {0x0700, "VCP1",}, | |
287 | {0x2500, "L4_PER2_P3",}, | |
288 | {0x0e00, "L4_PER3_P3",}, | |
289 | {0x2200, "MMU1",}, | |
290 | {0x1400, "PRUSS1",}, | |
291 | {0x1500, "PRUSS2"}, | |
292 | {0x0800, "VCP1",}, | |
293 | }; | |
294 | ||
295 | static struct l3_flagmux_data dra_l3_flagmux_clk1 = { | |
296 | .offset = 0x803500, | |
297 | .l3_targ = dra_l3_target_data_clk1, | |
298 | .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk1), | |
299 | }; | |
300 | ||
301 | static struct l3_target_data dra_l3_target_data_clk2[] = { | |
302 | {0x0, "HOST CLK1",}, | |
4adf82c3 | 303 | {0x800000, "HOST CLK2",}, |
53a848be RN |
304 | {0xdead, L3_TARGET_NOT_SUPPORTED,}, |
305 | {0x3400, "SHA2_2",}, | |
306 | {0x0900, "BB2D",}, | |
307 | {0xdead, L3_TARGET_NOT_SUPPORTED,}, | |
308 | {0x2100, "L4_PER1_P3",}, | |
309 | {0x1c00, "L4_PER1_P1",}, | |
310 | {0x1f00, "L4_PER1_P2",}, | |
311 | {0x2300, "L4_PER2_P1",}, | |
312 | {0x2400, "L4_PER2_P2",}, | |
313 | {0x2600, "L4_PER3_P1",}, | |
314 | {0x2700, "L4_PER3_P2",}, | |
315 | {0x2f00, "MCASP1",}, | |
316 | {0x3000, "MCASP2",}, | |
317 | {0x3100, "MCASP3",}, | |
318 | {0x2800, "MMU2",}, | |
319 | {0x0f00, "OCMC_RAM1",}, | |
320 | {0x1700, "OCMC_RAM2",}, | |
321 | {0x1900, "OCMC_RAM3",}, | |
322 | {0x1e00, "OCMC_ROM",}, | |
323 | {0x3900, "QSPI",}, | |
324 | }; | |
325 | ||
326 | static struct l3_flagmux_data dra_l3_flagmux_clk2 = { | |
327 | .offset = 0x803600, | |
328 | .l3_targ = dra_l3_target_data_clk2, | |
329 | .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk2), | |
330 | }; | |
331 | ||
332 | static struct l3_target_data dra_l3_target_data_clk3[] = { | |
333 | {0x0100, "L3_INSTR"}, | |
334 | {0x0300, "DEBUGSS_CT_TBR"}, | |
335 | {0x0, "HOST CLK3"}, | |
336 | }; | |
337 | ||
338 | static struct l3_flagmux_data dra_l3_flagmux_clk3 = { | |
339 | .offset = 0x200, | |
340 | .l3_targ = dra_l3_target_data_clk3, | |
341 | .num_targ_data = ARRAY_SIZE(dra_l3_target_data_clk3), | |
342 | }; | |
343 | ||
344 | static struct l3_masters_data dra_l3_masters[] = { | |
345 | { 0x0, "MPU" }, | |
346 | { 0x4, "CS_DAP" }, | |
347 | { 0x5, "IEEE1500_2_OCP" }, | |
348 | { 0x8, "DSP1_MDMA" }, | |
349 | { 0x9, "DSP1_CFG" }, | |
350 | { 0xA, "DSP1_DMA" }, | |
351 | { 0xB, "DSP2_MDMA" }, | |
352 | { 0xC, "DSP2_CFG" }, | |
353 | { 0xD, "DSP2_DMA" }, | |
354 | { 0xE, "IVA" }, | |
355 | { 0x10, "EVE1_P1" }, | |
356 | { 0x11, "EVE2_P1" }, | |
357 | { 0x12, "EVE3_P1" }, | |
358 | { 0x13, "EVE4_P1" }, | |
359 | { 0x14, "PRUSS1 PRU1" }, | |
360 | { 0x15, "PRUSS1 PRU2" }, | |
361 | { 0x16, "PRUSS2 PRU1" }, | |
362 | { 0x17, "PRUSS2 PRU2" }, | |
363 | { 0x18, "IPU1" }, | |
364 | { 0x19, "IPU2" }, | |
365 | { 0x1A, "SDMA" }, | |
366 | { 0x1B, "CDMA" }, | |
367 | { 0x1C, "TC1_EDMA" }, | |
368 | { 0x1D, "TC2_EDMA" }, | |
369 | { 0x20, "DSS" }, | |
370 | { 0x21, "MMU1" }, | |
371 | { 0x22, "PCIE1" }, | |
372 | { 0x23, "MMU2" }, | |
373 | { 0x24, "VIP1" }, | |
374 | { 0x25, "VIP2" }, | |
375 | { 0x26, "VIP3" }, | |
376 | { 0x27, "VPE" }, | |
377 | { 0x28, "GPU_P1" }, | |
378 | { 0x29, "BB2D" }, | |
379 | { 0x29, "GPU_P2" }, | |
380 | { 0x2B, "GMAC_SW" }, | |
381 | { 0x2C, "USB3" }, | |
382 | { 0x2D, "USB2_SS" }, | |
383 | { 0x2E, "USB2_ULPI_SS1" }, | |
384 | { 0x2F, "USB2_ULPI_SS2" }, | |
385 | { 0x30, "CSI2_1" }, | |
386 | { 0x31, "CSI2_2" }, | |
387 | { 0x33, "SATA" }, | |
388 | { 0x34, "EVE1_P2" }, | |
389 | { 0x35, "EVE2_P2" }, | |
390 | { 0x36, "EVE3_P2" }, | |
391 | { 0x37, "EVE4_P2" } | |
392 | }; | |
393 | ||
394 | static struct l3_flagmux_data *dra_l3_flagmux[] = { | |
395 | &dra_l3_flagmux_clk1, | |
396 | &dra_l3_flagmux_clk2, | |
397 | &dra_l3_flagmux_clk3, | |
398 | }; | |
399 | ||
400 | static const struct omap_l3 dra_l3_data = { | |
401 | .l3_base = { [1] = L3_BASE_IS_SUBMODULE }, | |
402 | .l3_flagmux = dra_l3_flagmux, | |
403 | .num_modules = ARRAY_SIZE(dra_l3_flagmux), | |
404 | .l3_masters = dra_l3_masters, | |
405 | .num_masters = ARRAY_SIZE(dra_l3_masters), | |
406 | /* The 6 MSBs of register field used to distinguish initiator */ | |
407 | .mst_addr_mask = 0xFC, | |
408 | }; | |
409 | ||
27b7d5f3 AM |
410 | /* AM4372 data */ |
411 | static struct l3_target_data am4372_l3_target_data_200f[] = { | |
412 | {0xf00, "EMIF",}, | |
413 | {0x1200, "DES",}, | |
414 | {0x400, "OCMCRAM",}, | |
415 | {0x700, "TPTC0",}, | |
416 | {0x800, "TPTC1",}, | |
417 | {0x900, "TPTC2"}, | |
418 | {0xb00, "TPCC",}, | |
419 | {0xd00, "DEBUGSS",}, | |
420 | {0xdead, L3_TARGET_NOT_SUPPORTED,}, | |
421 | {0x200, "SHA",}, | |
422 | {0xc00, "SGX530",}, | |
423 | {0x500, "AES0",}, | |
424 | {0xa00, "L4_FAST",}, | |
425 | {0x300, "MPUSS_L2_RAM",}, | |
426 | {0x100, "ICSS",}, | |
427 | }; | |
428 | ||
429 | static struct l3_flagmux_data am4372_l3_flagmux_200f = { | |
430 | .offset = 0x1000, | |
431 | .l3_targ = am4372_l3_target_data_200f, | |
432 | .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_200f), | |
433 | }; | |
434 | ||
435 | static struct l3_target_data am4372_l3_target_data_100s[] = { | |
436 | {0x100, "L4_PER_0",}, | |
437 | {0x200, "L4_PER_1",}, | |
438 | {0x300, "L4_PER_2",}, | |
439 | {0x400, "L4_PER_3",}, | |
440 | {0x800, "McASP0",}, | |
441 | {0x900, "McASP1",}, | |
442 | {0xC00, "MMCHS2",}, | |
443 | {0x700, "GPMC",}, | |
444 | {0xD00, "L4_FW",}, | |
445 | {0xdead, L3_TARGET_NOT_SUPPORTED,}, | |
446 | {0x500, "ADCTSC",}, | |
447 | {0xE00, "L4_WKUP",}, | |
448 | {0xA00, "MAG_CARD",}, | |
449 | }; | |
450 | ||
451 | static struct l3_flagmux_data am4372_l3_flagmux_100s = { | |
452 | .offset = 0x600, | |
453 | .l3_targ = am4372_l3_target_data_100s, | |
454 | .num_targ_data = ARRAY_SIZE(am4372_l3_target_data_100s), | |
455 | }; | |
456 | ||
457 | static struct l3_masters_data am4372_l3_masters[] = { | |
458 | { 0x0, "M1 (128-bit)"}, | |
459 | { 0x1, "M2 (64-bit)"}, | |
460 | { 0x4, "DAP"}, | |
461 | { 0x5, "P1500"}, | |
462 | { 0xC, "ICSS0"}, | |
463 | { 0xD, "ICSS1"}, | |
464 | { 0x14, "Wakeup Processor"}, | |
465 | { 0x18, "TPTC0 Read"}, | |
466 | { 0x19, "TPTC0 Write"}, | |
467 | { 0x1A, "TPTC1 Read"}, | |
468 | { 0x1B, "TPTC1 Write"}, | |
469 | { 0x1C, "TPTC2 Read"}, | |
470 | { 0x1D, "TPTC2 Write"}, | |
471 | { 0x20, "SGX530"}, | |
472 | { 0x21, "OCP WP Traffic Probe"}, | |
473 | { 0x22, "OCP WP DMA Profiling"}, | |
474 | { 0x23, "OCP WP Event Trace"}, | |
475 | { 0x25, "DSS"}, | |
476 | { 0x28, "Crypto DMA RD"}, | |
477 | { 0x29, "Crypto DMA WR"}, | |
478 | { 0x2C, "VPFE0"}, | |
479 | { 0x2D, "VPFE1"}, | |
480 | { 0x30, "GEMAC"}, | |
481 | { 0x34, "USB0 RD"}, | |
482 | { 0x35, "USB0 WR"}, | |
483 | { 0x36, "USB1 RD"}, | |
484 | { 0x37, "USB1 WR"}, | |
485 | }; | |
486 | ||
487 | static struct l3_flagmux_data *am4372_l3_flagmux[] = { | |
488 | &am4372_l3_flagmux_200f, | |
489 | &am4372_l3_flagmux_100s, | |
490 | }; | |
491 | ||
492 | static const struct omap_l3 am4372_l3_data = { | |
493 | .l3_flagmux = am4372_l3_flagmux, | |
494 | .num_modules = ARRAY_SIZE(am4372_l3_flagmux), | |
495 | .l3_masters = am4372_l3_masters, | |
496 | .num_masters = ARRAY_SIZE(am4372_l3_masters), | |
497 | /* All 6 bits of register field used to distinguish initiator */ | |
498 | .mst_addr_mask = 0x3F, | |
499 | }; | |
500 | ||
c10d5c9e | 501 | #endif /* __OMAP_L3_NOC_H */ |