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bus: mvebu-mbus: suspend/resume support
[linux-2.6-block.git] / drivers / bus / mvebu-mbus.c
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fddddb52
TP		 1/*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
6275afef
TP		 38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
fddddb52
TP		 41 *
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
46 */
47
b15d0b52
EG		 48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
fddddb52
TP		 50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/init.h>
53#include <linux/mbus.h>
54#include <linux/io.h>
55#include <linux/ioport.h>
56#include <linux/of.h>
57#include <linux/of_address.h>
58#include <linux/debugfs.h>
09752a12 59#include <linux/log2.h>
a0e89c02 60#include <linux/syscore_ops.h>
fddddb52
TP		 61
62/*
63 * DDR target is the same on all platforms.
64 */
65#define TARGET_DDR 0
66
67/*
68 * CPU Address Decode Windows registers
69 */
70#define WIN_CTRL_OFF 0x0000
71#define WIN_CTRL_ENABLE BIT(0)
72#define WIN_CTRL_TGT_MASK 0xf0
73#define WIN_CTRL_TGT_SHIFT 4
74#define WIN_CTRL_ATTR_MASK 0xff00
75#define WIN_CTRL_ATTR_SHIFT 8
76#define WIN_CTRL_SIZE_MASK 0xffff0000
77#define WIN_CTRL_SIZE_SHIFT 16
78#define WIN_BASE_OFF 0x0004
79#define WIN_BASE_LOW 0xffff0000
80#define WIN_BASE_HIGH 0xf
81#define WIN_REMAP_LO_OFF 0x0008
82#define WIN_REMAP_LOW 0xffff0000
83#define WIN_REMAP_HI_OFF 0x000c
84
85#define ATTR_HW_COHERENCY (0x1 << 4)
86
87#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
88#define DDR_BASE_CS_HIGH_MASK 0xf
89#define DDR_BASE_CS_LOW_MASK 0xff000000
90#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
91#define DDR_SIZE_ENABLED BIT(0)
92#define DDR_SIZE_CS_MASK 0x1c
93#define DDR_SIZE_CS_SHIFT 2
94#define DDR_SIZE_MASK 0xff000000
95
96#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
97
a0e89c02
TP		 98/* Relative to mbusbridge_base */
99#define MBUS_BRIDGE_CTRL_OFF 0x0
100#define MBUS_BRIDGE_BASE_OFF 0x4
101
102/* Maximum number of windows, for all known platforms */
103#define MBUS_WINS_MAX 20
104
fddddb52
TP		 105struct mvebu_mbus_state;
106
107struct mvebu_mbus_soc_data {
108 unsigned int num_wins;
109 unsigned int num_remappable_wins;
a0e89c02 110 bool has_mbus_bridge;
fddddb52
TP		 111 unsigned int (*win_cfg_offset)(const int win);
112 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
113 int (*show_cpu_target)(struct mvebu_mbus_state *s,
114 struct seq_file *seq, void *v);
fddddb52
TP		 115};
116
a0e89c02
TP		 117/*
118 * Used to store the state of one MBus window accross suspend/resume.
119 */
120struct mvebu_mbus_win_data {
121 u32 ctrl;
122 u32 base;
123 u32 remap_lo;
124 u32 remap_hi;
125};
126
fddddb52
TP		 127struct mvebu_mbus_state {
128 void __iomem *mbuswins_base;
129 void __iomem *sdramwins_base;
a0e89c02 130 void __iomem *mbusbridge_base;
fddddb52
TP		 131 struct dentry *debugfs_root;
132 struct dentry *debugfs_sdram;
133 struct dentry *debugfs_devs;
79d94683
EG		 134 struct resource pcie_mem_aperture;
135 struct resource pcie_io_aperture;
fddddb52
TP		 136 const struct mvebu_mbus_soc_data *soc;
137 int hw_io_coherency;
a0e89c02
TP		 138
139 /* Used during suspend/resume */
140 u32 mbus_bridge_ctrl;
141 u32 mbus_bridge_base;
142 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
fddddb52
TP		 143};
144
145static struct mvebu_mbus_state mbus_state;
146
147static struct mbus_dram_target_info mvebu_mbus_dram_info;
148const struct mbus_dram_target_info *mv_mbus_dram_info(void)
149{
150 return &mvebu_mbus_dram_info;
151}
152EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
153
154/*
155 * Functions to manipulate the address decoding windows
156 */
157
158static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
159 int win, int *enabled, u64 *base,
160 u32 *size, u8 *target, u8 *attr,
161 u64 *remap)
162{
163 void __iomem *addr = mbus->mbuswins_base +
164 mbus->soc->win_cfg_offset(win);
165 u32 basereg = readl(addr + WIN_BASE_OFF);
166 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
167
168 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
169 *enabled = 0;
170 return;
171 }
172
173 *enabled = 1;
174 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
175 *base |= (basereg & WIN_BASE_LOW);
176 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
177
178 if (target)
179 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
180
181 if (attr)
182 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
183
184 if (remap) {
185 if (win < mbus->soc->num_remappable_wins) {
186 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
187 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
188 *remap = ((u64)remap_hi << 32) | remap_low;
189 } else
190 *remap = 0;
191 }
192}
193
194static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
195 int win)
196{
197 void __iomem *addr;
198
199 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
200
201 writel(0, addr + WIN_BASE_OFF);
202 writel(0, addr + WIN_CTRL_OFF);
203 if (win < mbus->soc->num_remappable_wins) {
204 writel(0, addr + WIN_REMAP_LO_OFF);
205 writel(0, addr + WIN_REMAP_HI_OFF);
206 }
207}
208
209/* Checks whether the given window number is available */
210static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
211 const int win)
212{
213 void __iomem *addr = mbus->mbuswins_base +
214 mbus->soc->win_cfg_offset(win);
215 u32 ctrl = readl(addr + WIN_CTRL_OFF);
216 return !(ctrl & WIN_CTRL_ENABLE);
217}
218
219/*
220 * Checks whether the given (base, base+size) area doesn't overlap an
221 * existing region
222 */
223static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
224 phys_addr_t base, size_t size,
225 u8 target, u8 attr)
226{
227 u64 end = (u64)base + size;
228 int win;
229
230 for (win = 0; win < mbus->soc->num_wins; win++) {
231 u64 wbase, wend;
232 u32 wsize;
233 u8 wtarget, wattr;
234 int enabled;
235
236 mvebu_mbus_read_window(mbus, win,
237 &enabled, &wbase, &wsize,
238 &wtarget, &wattr, NULL);
239
240 if (!enabled)
241 continue;
242
243 wend = wbase + wsize;
244
245 /*
246 * Check if the current window overlaps with the
247 * proposed physical range
248 */
249 if ((u64)base < wend && end > wbase)
250 return 0;
fddddb52
TP		 251 }
252
253 return 1;
254}
255
256static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
257 phys_addr_t base, size_t size)
258{
259 int win;
260
261 for (win = 0; win < mbus->soc->num_wins; win++) {
262 u64 wbase;
263 u32 wsize;
264 int enabled;
265
266 mvebu_mbus_read_window(mbus, win,
267 &enabled, &wbase, &wsize,
268 NULL, NULL, NULL);
269
270 if (!enabled)
271 continue;
272
273 if (base == wbase && size == wsize)
274 return win;
275 }
276
277 return -ENODEV;
278}
279
280static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
281 int win, phys_addr_t base, size_t size,
282 phys_addr_t remap, u8 target,
283 u8 attr)
284{
285 void __iomem *addr = mbus->mbuswins_base +
286 mbus->soc->win_cfg_offset(win);
287 u32 ctrl, remap_addr;
288
09752a12
JG		 289 if (!is_power_of_2(size)) {
290 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
291 return -EINVAL;
292 }
293
294 if ((base & (phys_addr_t)(size - 1)) != 0) {
295 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
296 size);
297 return -EINVAL;
298 }
299
fddddb52
TP		 300 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
301 (attr << WIN_CTRL_ATTR_SHIFT) |
302 (target << WIN_CTRL_TGT_SHIFT) |
303 WIN_CTRL_ENABLE;
304
305 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
306 writel(ctrl, addr + WIN_CTRL_OFF);
307 if (win < mbus->soc->num_remappable_wins) {
308 if (remap == MVEBU_MBUS_NO_REMAP)
309 remap_addr = base;
310 else
311 remap_addr = remap;
312 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
313 writel(0, addr + WIN_REMAP_HI_OFF);
314 }
315
316 return 0;
317}
318
319static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
320 phys_addr_t base, size_t size,
321 phys_addr_t remap, u8 target,
322 u8 attr)
323{
324 int win;
325
326 if (remap == MVEBU_MBUS_NO_REMAP) {
327 for (win = mbus->soc->num_remappable_wins;
328 win < mbus->soc->num_wins; win++)
329 if (mvebu_mbus_window_is_free(mbus, win))
330 return mvebu_mbus_setup_window(mbus, win, base,
331 size, remap,
332 target, attr);
333 }
334
335
336 for (win = 0; win < mbus->soc->num_wins; win++)
337 if (mvebu_mbus_window_is_free(mbus, win))
338 return mvebu_mbus_setup_window(mbus, win, base, size,
339 remap, target, attr);
340
341 return -ENOMEM;
342}
343
344/*
345 * Debugfs debugging
346 */
347
348/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
349static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
350 struct seq_file *seq, void *v)
351{
352 int i;
353
354 for (i = 0; i < 4; i++) {
355 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
356 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
357 u64 base;
358 u32 size;
359
360 if (!(sizereg & DDR_SIZE_ENABLED)) {
361 seq_printf(seq, "[%d] disabled\n", i);
362 continue;
363 }
364
365 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
366 base |= basereg & DDR_BASE_CS_LOW_MASK;
367 size = (sizereg | ~DDR_SIZE_MASK);
368
369 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
370 i, (unsigned long long)base,
371 (unsigned long long)base + size + 1,
372 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
373 }
374
375 return 0;
376}
377
378/* Special function for Dove */
379static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
380 struct seq_file *seq, void *v)
381{
382 int i;
383
384 for (i = 0; i < 2; i++) {
385 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
386 u64 base;
387 u32 size;
388
389 if (!(map & 1)) {
390 seq_printf(seq, "[%d] disabled\n", i);
391 continue;
392 }
393
394 base = map & 0xff800000;
395 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
396
397 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
398 i, (unsigned long long)base,
399 (unsigned long long)base + size, i);
400 }
401
402 return 0;
403}
404
405static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
406{
407 struct mvebu_mbus_state *mbus = &mbus_state;
408 return mbus->soc->show_cpu_target(mbus, seq, v);
409}
410
411static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
412{
413 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
414}
415
416static const struct file_operations mvebu_sdram_debug_fops = {
417 .open = mvebu_sdram_debug_open,
418 .read = seq_read,
419 .llseek = seq_lseek,
420 .release = single_release,
421};
422
423static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
424{
425 struct mvebu_mbus_state *mbus = &mbus_state;
426 int win;
427
428 for (win = 0; win < mbus->soc->num_wins; win++) {
429 u64 wbase, wremap;
430 u32 wsize;
431 u8 wtarget, wattr;
ed843a7d 432 int enabled;
fddddb52
TP		 433
434 mvebu_mbus_read_window(mbus, win,
435 &enabled, &wbase, &wsize,
436 &wtarget, &wattr, &wremap);
437
438 if (!enabled) {
439 seq_printf(seq, "[%02d] disabled\n", win);
440 continue;
441 }
442
ed843a7d 443 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
fddddb52 444 win, (unsigned long long)wbase,
ed843a7d 445 (unsigned long long)(wbase + wsize), wtarget, wattr);
fddddb52 446
09752a12
JG		 447 if (!is_power_of_2(wsize) ||
448 ((wbase & (u64)(wsize - 1)) != 0))
449 seq_puts(seq, " (Invalid base/size!!)");
450
fddddb52
TP		 451 if (win < mbus->soc->num_remappable_wins) {
452 seq_printf(seq, " (remap %016llx)\n",
453 (unsigned long long)wremap);
454 } else
455 seq_printf(seq, "\n");
456 }
457
458 return 0;
459}
460
461static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
462{
463 return single_open(file, mvebu_devs_debug_show, inode->i_private);
464}
465
466static const struct file_operations mvebu_devs_debug_fops = {
467 .open = mvebu_devs_debug_open,
468 .read = seq_read,
469 .llseek = seq_lseek,
470 .release = single_release,
471};
472
473/*
474 * SoC-specific functions and definitions
475 */
476
477static unsigned int orion_mbus_win_offset(int win)
478{
479 return win << 4;
480}
481
482static unsigned int armada_370_xp_mbus_win_offset(int win)
483{
484 /* The register layout is a bit annoying and the below code
485 * tries to cope with it.
486 * - At offset 0x0, there are the registers for the first 8
487 * windows, with 4 registers of 32 bits per window (ctrl,
488 * base, remap low, remap high)
489 * - Then at offset 0x80, there is a hole of 0x10 bytes for
490 * the internal registers base address and internal units
491 * sync barrier register.
492 * - Then at offset 0x90, there the registers for 12
493 * windows, with only 2 registers of 32 bits per window
494 * (ctrl, base).
495 */
496 if (win < 8)
497 return win << 4;
498 else
499 return 0x90 + ((win - 8) << 3);
500}
501
502static unsigned int mv78xx0_mbus_win_offset(int win)
503{
504 if (win < 8)
505 return win << 4;
506 else
507 return 0x900 + ((win - 8) << 4);
508}
509
510static void __init
511mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
512{
513 int i;
514 int cs;
515
516 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
517
518 for (i = 0, cs = 0; i < 4; i++) {
519 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
520 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
521
522 /*
523 * We only take care of entries for which the chip
524 * select is enabled, and that don't have high base
525 * address bits set (devices can only access the first
526 * 32 bits of the memory).
527 */
528 if ((size & DDR_SIZE_ENABLED) &&
529 !(base & DDR_BASE_CS_HIGH_MASK)) {
530 struct mbus_dram_window *w;
531
532 w = &mvebu_mbus_dram_info.cs[cs++];
533 w->cs_index = i;
534 w->mbus_attr = 0xf & ~(1 << i);
535 if (mbus->hw_io_coherency)
536 w->mbus_attr |= ATTR_HW_COHERENCY;
537 w->base = base & DDR_BASE_CS_LOW_MASK;
538 w->size = (size | ~DDR_SIZE_MASK) + 1;
539 }
540 }
541 mvebu_mbus_dram_info.num_cs = cs;
542}
543
544static void __init
545mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
546{
547 int i;
548 int cs;
549
550 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
551
552 for (i = 0, cs = 0; i < 2; i++) {
553 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
554
555 /*
556 * Chip select enabled?
557 */
558 if (map & 1) {
559 struct mbus_dram_window *w;
560
561 w = &mvebu_mbus_dram_info.cs[cs++];
562 w->cs_index = i;
563 w->mbus_attr = 0; /* CS address decoding done inside */
564 /* the DDR controller, no need to */
565 /* provide attributes */
566 w->base = map & 0xff800000;
567 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
568 }
569 }
570
571 mvebu_mbus_dram_info.num_cs = cs;
572}
573
59cb2fc6 574static const struct mvebu_mbus_soc_data armada_370_xp_mbus_data = {
fddddb52
TP		 575 .num_wins = 20,
576 .num_remappable_wins = 8,
a0e89c02 577 .has_mbus_bridge = true,
fddddb52
TP		 578 .win_cfg_offset = armada_370_xp_mbus_win_offset,
579 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
580 .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52
TP		 581};
582
583static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
584 .num_wins = 8,
585 .num_remappable_wins = 4,
586 .win_cfg_offset = orion_mbus_win_offset,
587 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
588 .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52
TP		 589};
590
591static const struct mvebu_mbus_soc_data dove_mbus_data = {
592 .num_wins = 8,
593 .num_remappable_wins = 4,
594 .win_cfg_offset = orion_mbus_win_offset,
595 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
596 .show_cpu_target = mvebu_sdram_debug_show_dove,
fddddb52
TP		 597};
598
599/*
600 * Some variants of Orion5x have 4 remappable windows, some other have
601 * only two of them.
602 */
603static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
604 .num_wins = 8,
605 .num_remappable_wins = 4,
606 .win_cfg_offset = orion_mbus_win_offset,
607 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
608 .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52
TP		 609};
610
611static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
612 .num_wins = 8,
613 .num_remappable_wins = 2,
614 .win_cfg_offset = orion_mbus_win_offset,
615 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
616 .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52
TP		 617};
618
619static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
620 .num_wins = 14,
621 .num_remappable_wins = 8,
622 .win_cfg_offset = mv78xx0_mbus_win_offset,
623 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
624 .show_cpu_target = mvebu_sdram_debug_show_orion,
fddddb52
TP		 625};
626
fddddb52
TP		 627static const struct of_device_id of_mvebu_mbus_ids[] = {
628 { .compatible = "marvell,armada370-mbus",
59cb2fc6 629 .data = &armada_370_xp_mbus_data, },
fddddb52 630 { .compatible = "marvell,armadaxp-mbus",
59cb2fc6 631 .data = &armada_370_xp_mbus_data, },
fddddb52
TP		 632 { .compatible = "marvell,kirkwood-mbus",
633 .data = &kirkwood_mbus_data, },
634 { .compatible = "marvell,dove-mbus",
635 .data = &dove_mbus_data, },
636 { .compatible = "marvell,orion5x-88f5281-mbus",
637 .data = &orion5x_4win_mbus_data, },
638 { .compatible = "marvell,orion5x-88f5182-mbus",
639 .data = &orion5x_2win_mbus_data, },
640 { .compatible = "marvell,orion5x-88f5181-mbus",
641 .data = &orion5x_2win_mbus_data, },
642 { .compatible = "marvell,orion5x-88f6183-mbus",
643 .data = &orion5x_4win_mbus_data, },
644 { .compatible = "marvell,mv78xx0-mbus",
645 .data = &mv78xx0_mbus_data, },
646 { },
647};
648
649/*
650 * Public API of the driver
651 */
6a63b098
TP		 652int mvebu_mbus_add_window_remap_by_id(unsigned int target,
653 unsigned int attribute,
654 phys_addr_t base, size_t size,
655 phys_addr_t remap)
656{
657 struct mvebu_mbus_state *s = &mbus_state;
658
659 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
660 pr_err("cannot add window '%x:%x', conflicts with another window\n",
661 target, attribute);
662 return -EINVAL;
663 }
664
665 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
666}
667
6a63b098
TP		 668int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
669 phys_addr_t base, size_t size)
670{
671 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
672 size, MVEBU_MBUS_NO_REMAP);
673}
674
fddddb52
TP		 675int mvebu_mbus_del_window(phys_addr_t base, size_t size)
676{
677 int win;
678
679 win = mvebu_mbus_find_window(&mbus_state, base, size);
680 if (win < 0)
681 return win;
682
683 mvebu_mbus_disable_window(&mbus_state, win);
684 return 0;
685}
686
79d94683
EG		 687void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
688{
689 if (!res)
690 return;
691 *res = mbus_state.pcie_mem_aperture;
692}
693
694void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
695{
696 if (!res)
697 return;
698 *res = mbus_state.pcie_io_aperture;
699}
700
fddddb52
TP		 701static __init int mvebu_mbus_debugfs_init(void)
702{
703 struct mvebu_mbus_state *s = &mbus_state;
704
705 /*
706 * If no base has been initialized, doesn't make sense to
707 * register the debugfs entries. We may be on a multiplatform
708 * kernel that isn't running a Marvell EBU SoC.
709 */
710 if (!s->mbuswins_base)
711 return 0;
712
713 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
714 if (s->debugfs_root) {
715 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
716 s->debugfs_root, NULL,
717 &mvebu_sdram_debug_fops);
718 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
719 s->debugfs_root, NULL,
720 &mvebu_devs_debug_fops);
721 }
722
723 return 0;
724}
725fs_initcall(mvebu_mbus_debugfs_init);
726
a0e89c02
TP		 727static int mvebu_mbus_suspend(void)
728{
729 struct mvebu_mbus_state *s = &mbus_state;
730 int win;
731
732 if (!s->mbusbridge_base)
733 return -ENODEV;
734
735 for (win = 0; win < s->soc->num_wins; win++) {
736 void __iomem *addr = s->mbuswins_base +
737 s->soc->win_cfg_offset(win);
738
739 s->wins[win].base = readl(addr + WIN_BASE_OFF);
740 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
741
742 if (win >= s->soc->num_remappable_wins)
743 continue;
744
745 s->wins[win].remap_lo = readl(addr + WIN_REMAP_LO_OFF);
746 s->wins[win].remap_hi = readl(addr + WIN_REMAP_HI_OFF);
747 }
748
749 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
750 MBUS_BRIDGE_CTRL_OFF);
751 s->mbus_bridge_base = readl(s->mbusbridge_base +
752 MBUS_BRIDGE_BASE_OFF);
753
754 return 0;
755}
756
757static void mvebu_mbus_resume(void)
758{
759 struct mvebu_mbus_state *s = &mbus_state;
760 int win;
761
762 writel(s->mbus_bridge_ctrl,
763 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
764 writel(s->mbus_bridge_base,
765 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
766
767 for (win = 0; win < s->soc->num_wins; win++) {
768 void __iomem *addr = s->mbuswins_base +
769 s->soc->win_cfg_offset(win);
770
771 writel(s->wins[win].base, addr + WIN_BASE_OFF);
772 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
773
774 if (win >= s->soc->num_remappable_wins)
775 continue;
776
777 writel(s->wins[win].remap_lo, addr + WIN_REMAP_LO_OFF);
778 writel(s->wins[win].remap_hi, addr + WIN_REMAP_HI_OFF);
779 }
780}
781
782struct syscore_ops mvebu_mbus_syscore_ops = {
783 .suspend = mvebu_mbus_suspend,
784 .resume = mvebu_mbus_resume,
785};
786
6bd6b3cb
EG		 787static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
788 phys_addr_t mbuswins_phys_base,
789 size_t mbuswins_size,
790 phys_addr_t sdramwins_phys_base,
a0e89c02
TP		 791 size_t sdramwins_size,
792 phys_addr_t mbusbridge_phys_base,
793 size_t mbusbridge_size)
fddddb52 794{
fddddb52
TP		 795 int win;
796
fddddb52
TP		 797 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
798 if (!mbus->mbuswins_base)
799 return -ENOMEM;
800
801 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
802 if (!mbus->sdramwins_base) {
803 iounmap(mbus_state.mbuswins_base);
804 return -ENOMEM;
805 }
806
a0e89c02
TP		 807 if (mbusbridge_phys_base) {
808 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
809 mbusbridge_size);
810 if (!mbus->mbusbridge_base) {
811 iounmap(mbus->sdramwins_base);
812 iounmap(mbus->mbuswins_base);
813 return -ENOMEM;
814 }
815 } else
816 mbus->mbusbridge_base = NULL;
817
fddddb52
TP		 818 for (win = 0; win < mbus->soc->num_wins; win++)
819 mvebu_mbus_disable_window(mbus, win);
820
821 mbus->soc->setup_cpu_target(mbus);
822
a0e89c02
TP		 823 register_syscore_ops(&mvebu_mbus_syscore_ops);
824
fddddb52
TP		 825 return 0;
826}
6bd6b3cb
EG		 827
828int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
829 size_t mbuswins_size,
830 phys_addr_t sdramwins_phys_base,
831 size_t sdramwins_size)
832{
833 const struct of_device_id *of_id;
834
7663cfd3 835 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
6bd6b3cb
EG		 836 if (!strcmp(of_id->compatible, soc))
837 break;
838
7663cfd3 839 if (!of_id->compatible[0]) {
6bd6b3cb
EG		 840 pr_err("could not find a matching SoC family\n");
841 return -ENODEV;
842 }
843
844 mbus_state.soc = of_id->data;
845
846 return mvebu_mbus_common_init(&mbus_state,
847 mbuswins_phys_base,
848 mbuswins_size,
849 sdramwins_phys_base,
a0e89c02 850 sdramwins_size, 0, 0);
6bd6b3cb 851}
6839cfa8
EG		 852
853#ifdef CONFIG_OF
bb24cab3
EG		 854/*
855 * The window IDs in the ranges DT property have the following format:
856 * - bits 28 to 31: MBus custom field
857 * - bits 24 to 27: window target ID
858 * - bits 16 to 23: window attribute ID
859 * - bits 0 to 15: unused
860 */
861#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
862#define TARGET(id) (((id) & 0x0F000000) >> 24)
863#define ATTR(id) (((id) & 0x00FF0000) >> 16)
864
865static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
866 u32 base, u32 size,
867 u8 target, u8 attr)
868{
bb24cab3 869 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
ed843a7d
TP		 870 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
871 target, attr);
bb24cab3
EG		 872 return -EBUSY;
873 }
874
875 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
876 target, attr)) {
ed843a7d
TP		 877 pr_err("cannot add window '%04x:%04x', too many windows\n",
878 target, attr);
bb24cab3
EG		 879 return -ENOMEM;
880 }
881 return 0;
882}
883
884static int __init
885mbus_parse_ranges(struct device_node *node,
886 int *addr_cells, int *c_addr_cells, int *c_size_cells,
887 int *cell_count, const __be32 **ranges_start,
888 const __be32 **ranges_end)
889{
890 const __be32 *prop;
891 int ranges_len, tuple_len;
892
893 /* Allow a node with no 'ranges' property */
894 *ranges_start = of_get_property(node, "ranges", &ranges_len);
895 if (*ranges_start == NULL) {
896 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
897 *ranges_start = *ranges_end = NULL;
898 return 0;
899 }
900 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
901
902 *addr_cells = of_n_addr_cells(node);
903
904 prop = of_get_property(node, "#address-cells", NULL);
905 *c_addr_cells = be32_to_cpup(prop);
906
907 prop = of_get_property(node, "#size-cells", NULL);
908 *c_size_cells = be32_to_cpup(prop);
909
910 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
911 tuple_len = (*cell_count) * sizeof(__be32);
912
913 if (ranges_len % tuple_len) {
914 pr_warn("malformed ranges entry '%s'\n", node->name);
915 return -EINVAL;
916 }
917 return 0;
918}
919
920static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
921 struct device_node *np)
922{
923 int addr_cells, c_addr_cells, c_size_cells;
924 int i, ret, cell_count;
925 const __be32 *r, *ranges_start, *ranges_end;
926
927 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
928 &c_size_cells, &cell_count,
929 &ranges_start, &ranges_end);
930 if (ret < 0)
931 return ret;
932
933 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
934 u32 windowid, base, size;
935 u8 target, attr;
936
937 /*
938 * An entry with a non-zero custom field do not
939 * correspond to a static window, so skip it.
940 */
941 windowid = of_read_number(r, 1);
942 if (CUSTOM(windowid))
943 continue;
944
945 target = TARGET(windowid);
946 attr = ATTR(windowid);
947
948 base = of_read_number(r + c_addr_cells, addr_cells);
949 size = of_read_number(r + c_addr_cells + addr_cells,
950 c_size_cells);
951 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
952 if (ret < 0)
953 return ret;
954 }
955 return 0;
956}
957
79d94683
EG		 958static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
959 struct resource *mem,
960 struct resource *io)
961{
962 u32 reg[2];
963 int ret;
964
965 /*
8553bcad
JG		 966 * These are optional, so we make sure that resource_size(x) will
967 * return 0.
79d94683
EG		 968 */
969 memset(mem, 0, sizeof(struct resource));
8553bcad 970 mem->end = -1;
79d94683 971 memset(io, 0, sizeof(struct resource));
8553bcad 972 io->end = -1;
79d94683
EG		 973
974 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
975 if (!ret) {
976 mem->start = reg[0];
a723e752 977 mem->end = mem->start + reg[1] - 1;
79d94683
EG		 978 mem->flags = IORESOURCE_MEM;
979 }
980
981 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
982 if (!ret) {
983 io->start = reg[0];
a723e752 984 io->end = io->start + reg[1] - 1;
79d94683
EG		 985 io->flags = IORESOURCE_IO;
986 }
987}
988
5686a1e5 989int __init mvebu_mbus_dt_init(bool is_coherent)
6839cfa8 990{
a0e89c02 991 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
6839cfa8
EG		 992 struct device_node *np, *controller;
993 const struct of_device_id *of_id;
994 const __be32 *prop;
995 int ret;
996
087a4ab2 997 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
6839cfa8
EG		 998 if (!np) {
999 pr_err("could not find a matching SoC family\n");
1000 return -ENODEV;
1001 }
1002
6839cfa8
EG		 1003 mbus_state.soc = of_id->data;
1004
1005 prop = of_get_property(np, "controller", NULL);
1006 if (!prop) {
1007 pr_err("required 'controller' property missing\n");
1008 return -EINVAL;
1009 }
1010
1011 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1012 if (!controller) {
1013 pr_err("could not find an 'mbus-controller' node\n");
1014 return -ENODEV;
1015 }
1016
1017 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1018 pr_err("cannot get MBUS register address\n");
1019 return -EINVAL;
1020 }
1021
1022 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1023 pr_err("cannot get SDRAM register address\n");
1024 return -EINVAL;
1025 }
1026
a0e89c02
TP		 1027 /*
1028 * Set the resource to 0 so that it can be left unmapped by
1029 * mvebu_mbus_common_init() if the DT doesn't carry the
1030 * necessary information. This is needed to preserve backward
1031 * compatibility.
1032 */
1033 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1034
1035 if (mbus_state.soc->has_mbus_bridge) {
1036 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1037 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1038 }
1039
5686a1e5
TP		 1040 mbus_state.hw_io_coherency = is_coherent;
1041
79d94683
EG		 1042 /* Get optional pcie-{mem,io}-aperture properties */
1043 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1044 &mbus_state.pcie_io_aperture);
1045
6839cfa8
EG		 1046 ret = mvebu_mbus_common_init(&mbus_state,
1047 mbuswins_res.start,
1048 resource_size(&mbuswins_res),
1049 sdramwins_res.start,
a0e89c02
TP		 1050 resource_size(&sdramwins_res),
1051 mbusbridge_res.start,
1052 resource_size(&mbusbridge_res));
bb24cab3
EG		 1053 if (ret)
1054 return ret;
1055
1056 /* Setup statically declared windows in the DT */
1057 return mbus_dt_setup(&mbus_state, np);
6839cfa8
EG		 1058}
1059#endif
Linux 6.x block layer and io_uring tree(s)