[linux-2.6-block.git] / drivers / bus / imx-weim.c

/*
 * EIM driver for Freescale's i.MX chips
 *
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/regmap.h>

struct imx_weim_devtype {
	unsigned int	cs_count;
	unsigned int	cs_regs_count;
	unsigned int	cs_stride;
	unsigned int	wcr_offset;
	unsigned int	wcr_bcm;
	unsigned int	wcr_cont_bclk;
};

static const struct imx_weim_devtype imx1_weim_devtype = {
	.cs_count	= 6,
	.cs_regs_count	= 2,
	.cs_stride	= 0x08,
};

static const struct imx_weim_devtype imx27_weim_devtype = {
	.cs_count	= 6,
	.cs_regs_count	= 3,
	.cs_stride	= 0x10,
};

static const struct imx_weim_devtype imx50_weim_devtype = {
	.cs_count	= 4,
	.cs_regs_count	= 6,
	.cs_stride	= 0x18,
	.wcr_offset	= 0x90,
	.wcr_bcm	= BIT(0),
	.wcr_cont_bclk	= BIT(3),
};

static const struct imx_weim_devtype imx51_weim_devtype = {
	.cs_count	= 6,
	.cs_regs_count	= 6,
	.cs_stride	= 0x18,
};

#define MAX_CS_REGS_COUNT	6
#define MAX_CS_COUNT		6
#define OF_REG_SIZE		3

struct cs_timing {
	bool is_applied;
	u32 regs[MAX_CS_REGS_COUNT];
};

struct cs_timing_state {
	struct cs_timing cs[MAX_CS_COUNT];
};

static const struct of_device_id weim_id_table[] = {
	/* i.MX1/21 */
	{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
	/* i.MX25/27/31/35 */
	{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
	/* i.MX50/53/6Q */
	{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
	{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
	/* i.MX51 */
	{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
	{ }
};
MODULE_DEVICE_TABLE(of, weim_id_table);

static int imx_weim_gpr_setup(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct property *prop;
	const __be32 *p;
	struct regmap *gpr;
	u32 gprvals[4] = {
		05,	/* CS0(128M) CS1(0M)  CS2(0M)  CS3(0M)  */
		033,	/* CS0(64M)  CS1(64M) CS2(0M)  CS3(0M)  */
		0113,	/* CS0(64M)  CS1(32M) CS2(32M) CS3(0M)  */
		01111,	/* CS0(32M)  CS1(32M) CS2(32M) CS3(32M) */
	};
	u32 gprval = 0;
	u32 val;
	int cs = 0;
	int i = 0;

	gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
	if (IS_ERR(gpr)) {
		dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
		return 0;
	}

	of_property_for_each_u32(np, "ranges", prop, p, val) {
		if (i % 4 == 0) {
			cs = val;
		} else if (i % 4 == 3 && val) {
			val = (val / SZ_32M) | 1;
			gprval |= val << cs * 3;
		}
		i++;
	}

	if (i == 0 || i % 4)
		goto err;

	for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
		if (gprval == gprvals[i]) {
			/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
			regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
			return 0;
		}
	}

err:
	dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
	return -EINVAL;
}

/* Parse and set the timing for this device. */
static int weim_timing_setup(struct device *dev,
			     struct device_node *np, void __iomem *base,
			     const struct imx_weim_devtype *devtype,
			     struct cs_timing_state *ts)
{
	u32 cs_idx, value[MAX_CS_REGS_COUNT];
	int i, ret;
	int reg_idx, num_regs;
	struct cs_timing *cst;

	if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
		return -EINVAL;
	if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
		return -EINVAL;

	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
					 value, devtype->cs_regs_count);
	if (ret)
		return ret;

	/*
	 * the child node's "reg" property may contain multiple address ranges,
	 * extract the chip select for each.
	 */
	num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
	if (num_regs < 0)
		return num_regs;
	if (!num_regs)
		return -EINVAL;
	for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
		/* get the CS index from this child node's "reg" property. */
		ret = of_property_read_u32_index(np, "reg",
					reg_idx * OF_REG_SIZE, &cs_idx);
		if (ret)
			break;

		if (cs_idx >= devtype->cs_count)
			return -EINVAL;

		/* prevent re-configuring a CS that's already been configured */
		cst = &ts->cs[cs_idx];
		if (cst->is_applied && memcmp(value, cst->regs,
					devtype->cs_regs_count * sizeof(u32))) {
			dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
			return -EINVAL;
		}

		/* set the timing for WEIM */
		for (i = 0; i < devtype->cs_regs_count; i++)
			writel(value[i],
				base + cs_idx * devtype->cs_stride + i * 4);
		if (!cst->is_applied) {
			cst->is_applied = true;
			memcpy(cst->regs, value,
				devtype->cs_regs_count * sizeof(u32));
		}
	}

	return 0;
}

static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
{
	const struct of_device_id *of_id = of_match_device(weim_id_table,
							   &pdev->dev);
	const struct imx_weim_devtype *devtype = of_id->data;
	struct device_node *child;
	int ret, have_child = 0;
	struct cs_timing_state ts = {};
	u32 reg;

	if (devtype == &imx50_weim_devtype) {
		ret = imx_weim_gpr_setup(pdev);
		if (ret)
			return ret;
	}

	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
		if (devtype->wcr_bcm) {
			reg = readl(base + devtype->wcr_offset);
			reg |= devtype->wcr_bcm;

			if (of_property_read_bool(pdev->dev.of_node,
						"fsl,continuous-burst-clk")) {
				if (devtype->wcr_cont_bclk) {
					reg |= devtype->wcr_cont_bclk;
				} else {
					dev_err(&pdev->dev,
						"continuous burst clk not supported.\n");
					return -EINVAL;
				}
			}

			writel(reg, base + devtype->wcr_offset);
		} else {
			dev_err(&pdev->dev, "burst clk mode not supported.\n");
			return -EINVAL;
		}
	}

	for_each_available_child_of_node(pdev->dev.of_node, child) {
		ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
		if (ret)
			dev_warn(&pdev->dev, "%pOF set timing failed.\n",
				child);
		else
			have_child = 1;
	}

	if (have_child)
		ret = of_platform_default_populate(pdev->dev.of_node,
						   NULL, &pdev->dev);
	if (ret)
		dev_err(&pdev->dev, "%pOF fail to create devices.\n",
			pdev->dev.of_node);
	return ret;
}

static int weim_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct clk *clk;
	void __iomem *base;
	int ret;

	/* get the resource */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	/* get the clock */
	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	/* parse the device node */
	ret = weim_parse_dt(pdev, base);
	if (ret)
		clk_disable_unprepare(clk);
	else
		dev_info(&pdev->dev, "Driver registered.\n");

	return ret;
}

static struct platform_driver weim_driver = {
	.driver = {
		.name		= "imx-weim",
		.of_match_table	= weim_id_table,
	},
	.probe = weim_probe,
};
module_platform_driver(weim_driver);

MODULE_AUTHOR("Freescale Semiconductor Inc.");
MODULE_DESCRIPTION("i.MX EIM Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
85bf6d4e HS	1	/*
	2	* EIM driver for Freescale's i.MX chips
	3	*
	4	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#include <linux/module.h>
	11	#include <linux/clk.h>
	12	#include <linux/io.h>
	13	#include <linux/of_device.h>
8d9ee21e SG	14	#include <linux/mfd/syscon.h>
	15	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	16	#include <linux/regmap.h>
85bf6d4e	17
3f98b6ba AS	18	struct imx_weim_devtype {
	19	unsigned int cs_count;
	20	unsigned int cs_regs_count;
	21	unsigned int cs_stride;
77266e72 SVA	22	unsigned int wcr_offset;
77266e72 SVA	23	unsigned int wcr_bcm;
7b983da3	24	unsigned int wcr_cont_bclk;
3f98b6ba AS	25	};
	26
	27	static const struct imx_weim_devtype imx1_weim_devtype = {
	28	.cs_count = 6,
	29	.cs_regs_count = 2,
	30	.cs_stride = 0x08,
	31	};
	32
	33	static const struct imx_weim_devtype imx27_weim_devtype = {
	34	.cs_count = 6,
	35	.cs_regs_count = 3,
	36	.cs_stride = 0x10,
	37	};
	38
	39	static const struct imx_weim_devtype imx50_weim_devtype = {
	40	.cs_count = 4,
	41	.cs_regs_count = 6,
	42	.cs_stride = 0x18,
77266e72 SVA	43	.wcr_offset = 0x90,
77266e72 SVA	44	.wcr_bcm = BIT(0),
7b983da3	45	.wcr_cont_bclk = BIT(3),
3f98b6ba AS	46	};
	47
	48	static const struct imx_weim_devtype imx51_weim_devtype = {
	49	.cs_count = 6,
	50	.cs_regs_count = 6,
	51	.cs_stride = 0x18,
	52	};
	53
d8dfa59f	54	#define MAX_CS_REGS_COUNT 6
c7995bcb	55	#define MAX_CS_COUNT 6
8b8cb52a	56	#define OF_REG_SIZE 3
d8dfa59f	57
c7995bcb SVA	58	struct cs_timing {
	59	bool is_applied;
	60	u32 regs[MAX_CS_REGS_COUNT];
	61	};
	62
	63	struct cs_timing_state {
	64	struct cs_timing cs[MAX_CS_COUNT];
	65	};
	66
85bf6d4e	67	static const struct of_device_id weim_id_table[] = {
3f98b6ba AS	68	/* i.MX1/21 */
	69	{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
	70	/* i.MX25/27/31/35 */
	71	{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
	72	/* i.MX50/53/6Q */
	73	{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
	74	{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
	75	/* i.MX51 */
	76	{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
	77	{ }
85bf6d4e HS	78	};
	79	MODULE_DEVICE_TABLE(of, weim_id_table);
	80
3b1261fb	81	static int imx_weim_gpr_setup(struct platform_device *pdev)
8d9ee21e SG	82	{
	83	struct device_node *np = pdev->dev.of_node;
	84	struct property *prop;
	85	const __be32 *p;
	86	struct regmap *gpr;
	87	u32 gprvals[4] = {
	88	05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */
	89	033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */
	90	0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */
	91	01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */
	92	};
	93	u32 gprval = 0;
	94	u32 val;
	95	int cs = 0;
	96	int i = 0;
	97
	98	gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
	99	if (IS_ERR(gpr)) {
	100	dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
	101	return 0;
	102	}
	103
	104	of_property_for_each_u32(np, "ranges", prop, p, val) {
	105	if (i % 4 == 0) {
	106	cs = val;
	107	} else if (i % 4 == 3 && val) {
	108	val = (val / SZ_32M) \| 1;
	109	gprval \|= val << cs * 3;
	110	}
	111	i++;
	112	}
	113
	114	if (i == 0 \|\| i % 4)
	115	goto err;
	116
	117	for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
	118	if (gprval == gprvals[i]) {
	119	/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
	120	regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
	121	return 0;
	122	}
	123	}
	124
	125	err:
	126	dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
	127	return -EINVAL;
	128	}
	129
85bf6d4e	130	/* Parse and set the timing for this device. */
3b1261fb AB	131	static int weim_timing_setup(struct device *dev,
	132	struct device_node np, void __iomem base,
	133	const struct imx_weim_devtype *devtype,
	134	struct cs_timing_state *ts)
85bf6d4e	135	{
d8dfa59f	136	u32 cs_idx, value[MAX_CS_REGS_COUNT];
3f98b6ba	137	int i, ret;
8b8cb52a	138	int reg_idx, num_regs;
c7995bcb	139	struct cs_timing *cst;
85bf6d4e	140
d8dfa59f KC	141	if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
d8dfa59f KC	142	return -EINVAL;
c7995bcb SVA	143	if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
c7995bcb SVA	144	return -EINVAL;
d8dfa59f	145
8b8cb52a SVA	146	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
8b8cb52a SVA	147	value, devtype->cs_regs_count);
85bf6d4e HS	148	if (ret)
	149	return ret;
	150
8b8cb52a SVA	151	/*
	152	* the child node's "reg" property may contain multiple address ranges,
	153	* extract the chip select for each.
	154	*/
	155	num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
	156	if (num_regs < 0)
	157	return num_regs;
	158	if (!num_regs)
85bf6d4e	159	return -EINVAL;
8b8cb52a SVA	160	for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
	161	/* get the CS index from this child node's "reg" property. */
	162	ret = of_property_read_u32_index(np, "reg",
	163	reg_idx * OF_REG_SIZE, &cs_idx);
	164	if (ret)
	165	break;
85bf6d4e	166
8b8cb52a SVA	167	if (cs_idx >= devtype->cs_count)
8b8cb52a SVA	168	return -EINVAL;
85bf6d4e	169
c7995bcb SVA	170	/* prevent re-configuring a CS that's already been configured */
	171	cst = &ts->cs[cs_idx];
	172	if (cst->is_applied && memcmp(value, cst->regs,
	173	devtype->cs_regs_count * sizeof(u32))) {
	174	dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
	175	return -EINVAL;
	176	}
	177
8b8cb52a SVA	178	/* set the timing for WEIM */
	179	for (i = 0; i < devtype->cs_regs_count; i++)
	180	writel(value[i],
	181	base + cs_idx * devtype->cs_stride + i * 4);
c7995bcb SVA	182	if (!cst->is_applied) {
	183	cst->is_applied = true;
	184	memcpy(cst->regs, value,
	185	devtype->cs_regs_count * sizeof(u32));
	186	}
8b8cb52a	187	}
3f98b6ba	188
85bf6d4e HS	189	return 0;
	190	}
	191
4a92f078	192	static int weim_parse_dt(struct platform_device pdev, void __iomem base)
85bf6d4e	193	{
3f98b6ba AS	194	const struct of_device_id *of_id = of_match_device(weim_id_table,
	195	&pdev->dev);
	196	const struct imx_weim_devtype *devtype = of_id->data;
85bf6d4e	197	struct device_node *child;
52c47b63	198	int ret, have_child = 0;
c7995bcb	199	struct cs_timing_state ts = {};
77266e72	200	u32 reg;
85bf6d4e	201
8d9ee21e SG	202	if (devtype == &imx50_weim_devtype) {
	203	ret = imx_weim_gpr_setup(pdev);
	204	if (ret)
	205	return ret;
	206	}
	207
77266e72 SVA	208	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
	209	if (devtype->wcr_bcm) {
	210	reg = readl(base + devtype->wcr_offset);
7b983da3 IB	211	reg \|= devtype->wcr_bcm;
	212
	213	if (of_property_read_bool(pdev->dev.of_node,
	214	"fsl,continuous-burst-clk")) {
	215	if (devtype->wcr_cont_bclk) {
	216	reg \|= devtype->wcr_cont_bclk;
	217	} else {
	218	dev_err(&pdev->dev,
	219	"continuous burst clk not supported.\n");
	220	return -EINVAL;
	221	}
	222	}
	223
	224	writel(reg, base + devtype->wcr_offset);
77266e72 SVA	225	} else {
	226	dev_err(&pdev->dev, "burst clk mode not supported.\n");
	227	return -EINVAL;
	228	}
	229	}
	230
33b96d2c	231	for_each_available_child_of_node(pdev->dev.of_node, child) {
c7995bcb	232	ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
52c47b63	233	if (ret)
9c0982d8 RH	234	dev_warn(&pdev->dev, "%pOF set timing failed.\n",
9c0982d8 RH	235	child);
52c47b63 AC	236	else
52c47b63 AC	237	have_child = 1;
85bf6d4e HS	238	}
85bf6d4e HS	239
52c47b63	240	if (have_child)
39ec8d38 KW	241	ret = of_platform_default_populate(pdev->dev.of_node,
39ec8d38 KW	242	NULL, &pdev->dev);
85bf6d4e	243	if (ret)
9c0982d8 RH	244	dev_err(&pdev->dev, "%pOF fail to create devices.\n",
9c0982d8 RH	245	pdev->dev.of_node);
85bf6d4e HS	246	return ret;
	247	}
	248
4a92f078	249	static int weim_probe(struct platform_device *pdev)
85bf6d4e	250	{
85bf6d4e	251	struct resource *res;
70ac98da AS	252	struct clk *clk;
70ac98da AS	253	void __iomem *base;
b2d1fb73	254	int ret;
85bf6d4e	255
85bf6d4e HS	256	/* get the resource */
85bf6d4e HS	257	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
70ac98da	258	base = devm_ioremap_resource(&pdev->dev, res);
b2d1fb73 AS	259	if (IS_ERR(base))
b2d1fb73 AS	260	return PTR_ERR(base);
85bf6d4e HS	261
85bf6d4e HS	262	/* get the clock */
70ac98da AS	263	clk = devm_clk_get(&pdev->dev, NULL);
70ac98da AS	264	if (IS_ERR(clk))
b2d1fb73	265	return PTR_ERR(clk);
85bf6d4e	266
70ac98da	267	ret = clk_prepare_enable(clk);
85bf6d4e	268	if (ret)
b2d1fb73	269	return ret;
85bf6d4e HS	270
85bf6d4e HS	271	/* parse the device node */
70ac98da	272	ret = weim_parse_dt(pdev, base);
b2d1fb73	273	if (ret)
70ac98da	274	clk_disable_unprepare(clk);
b2d1fb73 AS	275	else
b2d1fb73 AS	276	dev_info(&pdev->dev, "Driver registered.\n");
85bf6d4e	277
85bf6d4e HS	278	return ret;
	279	}
	280
	281	static struct platform_driver weim_driver = {
	282	.driver = {
fc608c74	283	.name = "imx-weim",
fc608c74	284	.of_match_table = weim_id_table,
85bf6d4e	285	},
4a92f078	286	.probe = weim_probe,
85bf6d4e	287	};
4a92f078	288	module_platform_driver(weim_driver);
85bf6d4e	289
85bf6d4e HS	290	MODULE_AUTHOR("Freescale Semiconductor Inc.");
	291	MODULE_DESCRIPTION("i.MX EIM Controller Driver");
	292	MODULE_LICENSE("GPL");