[linux-2.6-block.git] / drivers / bus / imx-weim.c

/*
 * EIM driver for Freescale's i.MX chips
 *
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_device.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/regmap.h>

struct imx_weim_devtype {
	unsigned int	cs_count;
	unsigned int	cs_regs_count;
	unsigned int	cs_stride;
	unsigned int	wcr_offset;
	unsigned int	wcr_bcm;
};

static const struct imx_weim_devtype imx1_weim_devtype = {
	.cs_count	= 6,
	.cs_regs_count	= 2,
	.cs_stride	= 0x08,
};

static const struct imx_weim_devtype imx27_weim_devtype = {
	.cs_count	= 6,
	.cs_regs_count	= 3,
	.cs_stride	= 0x10,
};

static const struct imx_weim_devtype imx50_weim_devtype = {
	.cs_count	= 4,
	.cs_regs_count	= 6,
	.cs_stride	= 0x18,
	.wcr_offset	= 0x90,
	.wcr_bcm	= BIT(0),
};

static const struct imx_weim_devtype imx51_weim_devtype = {
	.cs_count	= 6,
	.cs_regs_count	= 6,
	.cs_stride	= 0x18,
};

#define MAX_CS_REGS_COUNT	6
#define MAX_CS_COUNT		6
#define OF_REG_SIZE		3

struct cs_timing {
	bool is_applied;
	u32 regs[MAX_CS_REGS_COUNT];
};

struct cs_timing_state {
	struct cs_timing cs[MAX_CS_COUNT];
};

static const struct of_device_id weim_id_table[] = {
	/* i.MX1/21 */
	{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
	/* i.MX25/27/31/35 */
	{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
	/* i.MX50/53/6Q */
	{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
	{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
	/* i.MX51 */
	{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
	{ }
};
MODULE_DEVICE_TABLE(of, weim_id_table);

static int imx_weim_gpr_setup(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct property *prop;
	const __be32 *p;
	struct regmap *gpr;
	u32 gprvals[4] = {
		05,	/* CS0(128M) CS1(0M)  CS2(0M)  CS3(0M)  */
		033,	/* CS0(64M)  CS1(64M) CS2(0M)  CS3(0M)  */
		0113,	/* CS0(64M)  CS1(32M) CS2(32M) CS3(0M)  */
		01111,	/* CS0(32M)  CS1(32M) CS2(32M) CS3(32M) */
	};
	u32 gprval = 0;
	u32 val;
	int cs = 0;
	int i = 0;

	gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
	if (IS_ERR(gpr)) {
		dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
		return 0;
	}

	of_property_for_each_u32(np, "ranges", prop, p, val) {
		if (i % 4 == 0) {
			cs = val;
		} else if (i % 4 == 3 && val) {
			val = (val / SZ_32M) | 1;
			gprval |= val << cs * 3;
		}
		i++;
	}

	if (i == 0 || i % 4)
		goto err;

	for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
		if (gprval == gprvals[i]) {
			/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
			regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
			return 0;
		}
	}

err:
	dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
	return -EINVAL;
}

/* Parse and set the timing for this device. */
static int weim_timing_setup(struct device *dev,
			     struct device_node *np, void __iomem *base,
			     const struct imx_weim_devtype *devtype,
			     struct cs_timing_state *ts)
{
	u32 cs_idx, value[MAX_CS_REGS_COUNT];
	int i, ret;
	int reg_idx, num_regs;
	struct cs_timing *cst;

	if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
		return -EINVAL;
	if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
		return -EINVAL;

	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
					 value, devtype->cs_regs_count);
	if (ret)
		return ret;

	/*
	 * the child node's "reg" property may contain multiple address ranges,
	 * extract the chip select for each.
	 */
	num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
	if (num_regs < 0)
		return num_regs;
	if (!num_regs)
		return -EINVAL;
	for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
		/* get the CS index from this child node's "reg" property. */
		ret = of_property_read_u32_index(np, "reg",
					reg_idx * OF_REG_SIZE, &cs_idx);
		if (ret)
			break;

		if (cs_idx >= devtype->cs_count)
			return -EINVAL;

		/* prevent re-configuring a CS that's already been configured */
		cst = &ts->cs[cs_idx];
		if (cst->is_applied && memcmp(value, cst->regs,
					devtype->cs_regs_count * sizeof(u32))) {
			dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
			return -EINVAL;
		}

		/* set the timing for WEIM */
		for (i = 0; i < devtype->cs_regs_count; i++)
			writel(value[i],
				base + cs_idx * devtype->cs_stride + i * 4);
		if (!cst->is_applied) {
			cst->is_applied = true;
			memcpy(cst->regs, value,
				devtype->cs_regs_count * sizeof(u32));
		}
	}

	return 0;
}

static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
{
	const struct of_device_id *of_id = of_match_device(weim_id_table,
							   &pdev->dev);
	const struct imx_weim_devtype *devtype = of_id->data;
	struct device_node *child;
	int ret, have_child = 0;
	struct cs_timing_state ts = {};
	u32 reg;

	if (devtype == &imx50_weim_devtype) {
		ret = imx_weim_gpr_setup(pdev);
		if (ret)
			return ret;
	}

	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
		if (devtype->wcr_bcm) {
			reg = readl(base + devtype->wcr_offset);
			writel(reg | devtype->wcr_bcm,
				base + devtype->wcr_offset);
		} else {
			dev_err(&pdev->dev, "burst clk mode not supported.\n");
			return -EINVAL;
		}
	}

	for_each_available_child_of_node(pdev->dev.of_node, child) {
		ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
		if (ret)
			dev_warn(&pdev->dev, "%pOF set timing failed.\n",
				child);
		else
			have_child = 1;
	}

	if (have_child)
		ret = of_platform_default_populate(pdev->dev.of_node,
						   NULL, &pdev->dev);
	if (ret)
		dev_err(&pdev->dev, "%pOF fail to create devices.\n",
			pdev->dev.of_node);
	return ret;
}

static int weim_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct clk *clk;
	void __iomem *base;
	int ret;

	/* get the resource */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	/* get the clock */
	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	/* parse the device node */
	ret = weim_parse_dt(pdev, base);
	if (ret)
		clk_disable_unprepare(clk);
	else
		dev_info(&pdev->dev, "Driver registered.\n");

	return ret;
}

static struct platform_driver weim_driver = {
	.driver = {
		.name		= "imx-weim",
		.of_match_table	= weim_id_table,
	},
	.probe = weim_probe,
};
module_platform_driver(weim_driver);

MODULE_AUTHOR("Freescale Semiconductor Inc.");
MODULE_DESCRIPTION("i.MX EIM Controller Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
85bf6d4e HS	1	/*
	2	* EIM driver for Freescale's i.MX chips
	3	*
	4	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without any
	8	* warranty of any kind, whether express or implied.
	9	*/
	10	#include <linux/module.h>
	11	#include <linux/clk.h>
	12	#include <linux/io.h>
	13	#include <linux/of_device.h>
8d9ee21e SG	14	#include <linux/mfd/syscon.h>
	15	#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
	16	#include <linux/regmap.h>
85bf6d4e	17
3f98b6ba AS	18	struct imx_weim_devtype {
	19	unsigned int cs_count;
	20	unsigned int cs_regs_count;
	21	unsigned int cs_stride;
77266e72 SVA	22	unsigned int wcr_offset;
77266e72 SVA	23	unsigned int wcr_bcm;
3f98b6ba AS	24	};
	25
	26	static const struct imx_weim_devtype imx1_weim_devtype = {
	27	.cs_count = 6,
	28	.cs_regs_count = 2,
	29	.cs_stride = 0x08,
	30	};
	31
	32	static const struct imx_weim_devtype imx27_weim_devtype = {
	33	.cs_count = 6,
	34	.cs_regs_count = 3,
	35	.cs_stride = 0x10,
	36	};
	37
	38	static const struct imx_weim_devtype imx50_weim_devtype = {
	39	.cs_count = 4,
	40	.cs_regs_count = 6,
	41	.cs_stride = 0x18,
77266e72 SVA	42	.wcr_offset = 0x90,
77266e72 SVA	43	.wcr_bcm = BIT(0),
3f98b6ba AS	44	};
	45
	46	static const struct imx_weim_devtype imx51_weim_devtype = {
	47	.cs_count = 6,
	48	.cs_regs_count = 6,
	49	.cs_stride = 0x18,
	50	};
	51
d8dfa59f	52	#define MAX_CS_REGS_COUNT 6
c7995bcb	53	#define MAX_CS_COUNT 6
8b8cb52a	54	#define OF_REG_SIZE 3
d8dfa59f	55
c7995bcb SVA	56	struct cs_timing {
	57	bool is_applied;
	58	u32 regs[MAX_CS_REGS_COUNT];
	59	};
	60
	61	struct cs_timing_state {
	62	struct cs_timing cs[MAX_CS_COUNT];
	63	};
	64
85bf6d4e	65	static const struct of_device_id weim_id_table[] = {
3f98b6ba AS	66	/* i.MX1/21 */
	67	{ .compatible = "fsl,imx1-weim", .data = &imx1_weim_devtype, },
	68	/* i.MX25/27/31/35 */
	69	{ .compatible = "fsl,imx27-weim", .data = &imx27_weim_devtype, },
	70	/* i.MX50/53/6Q */
	71	{ .compatible = "fsl,imx50-weim", .data = &imx50_weim_devtype, },
	72	{ .compatible = "fsl,imx6q-weim", .data = &imx50_weim_devtype, },
	73	/* i.MX51 */
	74	{ .compatible = "fsl,imx51-weim", .data = &imx51_weim_devtype, },
	75	{ }
85bf6d4e HS	76	};
	77	MODULE_DEVICE_TABLE(of, weim_id_table);
	78
3b1261fb	79	static int imx_weim_gpr_setup(struct platform_device *pdev)
8d9ee21e SG	80	{
	81	struct device_node *np = pdev->dev.of_node;
	82	struct property *prop;
	83	const __be32 *p;
	84	struct regmap *gpr;
	85	u32 gprvals[4] = {
	86	05, /* CS0(128M) CS1(0M) CS2(0M) CS3(0M) */
	87	033, /* CS0(64M) CS1(64M) CS2(0M) CS3(0M) */
	88	0113, /* CS0(64M) CS1(32M) CS2(32M) CS3(0M) */
	89	01111, /* CS0(32M) CS1(32M) CS2(32M) CS3(32M) */
	90	};
	91	u32 gprval = 0;
	92	u32 val;
	93	int cs = 0;
	94	int i = 0;
	95
	96	gpr = syscon_regmap_lookup_by_phandle(np, "fsl,weim-cs-gpr");
	97	if (IS_ERR(gpr)) {
	98	dev_dbg(&pdev->dev, "failed to find weim-cs-gpr\n");
	99	return 0;
	100	}
	101
	102	of_property_for_each_u32(np, "ranges", prop, p, val) {
	103	if (i % 4 == 0) {
	104	cs = val;
	105	} else if (i % 4 == 3 && val) {
	106	val = (val / SZ_32M) \| 1;
	107	gprval \|= val << cs * 3;
	108	}
	109	i++;
	110	}
	111
	112	if (i == 0 \|\| i % 4)
	113	goto err;
	114
	115	for (i = 0; i < ARRAY_SIZE(gprvals); i++) {
	116	if (gprval == gprvals[i]) {
	117	/* Found it. Set up IOMUXC_GPR1[11:0] with it. */
	118	regmap_update_bits(gpr, IOMUXC_GPR1, 0xfff, gprval);
	119	return 0;
	120	}
	121	}
	122
	123	err:
	124	dev_err(&pdev->dev, "Invalid 'ranges' configuration\n");
	125	return -EINVAL;
	126	}
	127
85bf6d4e	128	/* Parse and set the timing for this device. */
3b1261fb AB	129	static int weim_timing_setup(struct device *dev,
	130	struct device_node np, void __iomem base,
	131	const struct imx_weim_devtype *devtype,
	132	struct cs_timing_state *ts)
85bf6d4e	133	{
d8dfa59f	134	u32 cs_idx, value[MAX_CS_REGS_COUNT];
3f98b6ba	135	int i, ret;
8b8cb52a	136	int reg_idx, num_regs;
c7995bcb	137	struct cs_timing *cst;
85bf6d4e	138
d8dfa59f KC	139	if (WARN_ON(devtype->cs_regs_count > MAX_CS_REGS_COUNT))
d8dfa59f KC	140	return -EINVAL;
c7995bcb SVA	141	if (WARN_ON(devtype->cs_count > MAX_CS_COUNT))
c7995bcb SVA	142	return -EINVAL;
d8dfa59f	143
8b8cb52a SVA	144	ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
8b8cb52a SVA	145	value, devtype->cs_regs_count);
85bf6d4e HS	146	if (ret)
	147	return ret;
	148
8b8cb52a SVA	149	/*
	150	* the child node's "reg" property may contain multiple address ranges,
	151	* extract the chip select for each.
	152	*/
	153	num_regs = of_property_count_elems_of_size(np, "reg", OF_REG_SIZE);
	154	if (num_regs < 0)
	155	return num_regs;
	156	if (!num_regs)
85bf6d4e	157	return -EINVAL;
8b8cb52a SVA	158	for (reg_idx = 0; reg_idx < num_regs; reg_idx++) {
	159	/* get the CS index from this child node's "reg" property. */
	160	ret = of_property_read_u32_index(np, "reg",
	161	reg_idx * OF_REG_SIZE, &cs_idx);
	162	if (ret)
	163	break;
85bf6d4e	164
8b8cb52a SVA	165	if (cs_idx >= devtype->cs_count)
8b8cb52a SVA	166	return -EINVAL;
85bf6d4e	167
c7995bcb SVA	168	/* prevent re-configuring a CS that's already been configured */
	169	cst = &ts->cs[cs_idx];
	170	if (cst->is_applied && memcmp(value, cst->regs,
	171	devtype->cs_regs_count * sizeof(u32))) {
	172	dev_err(dev, "fsl,weim-cs-timing conflict on %pOF", np);
	173	return -EINVAL;
	174	}
	175
8b8cb52a SVA	176	/* set the timing for WEIM */
	177	for (i = 0; i < devtype->cs_regs_count; i++)
	178	writel(value[i],
	179	base + cs_idx * devtype->cs_stride + i * 4);
c7995bcb SVA	180	if (!cst->is_applied) {
	181	cst->is_applied = true;
	182	memcpy(cst->regs, value,
	183	devtype->cs_regs_count * sizeof(u32));
	184	}
8b8cb52a	185	}
3f98b6ba	186
85bf6d4e HS	187	return 0;
	188	}
	189
4a92f078	190	static int weim_parse_dt(struct platform_device pdev, void __iomem base)
85bf6d4e	191	{
3f98b6ba AS	192	const struct of_device_id *of_id = of_match_device(weim_id_table,
	193	&pdev->dev);
	194	const struct imx_weim_devtype *devtype = of_id->data;
85bf6d4e	195	struct device_node *child;
52c47b63	196	int ret, have_child = 0;
c7995bcb	197	struct cs_timing_state ts = {};
77266e72	198	u32 reg;
85bf6d4e	199
8d9ee21e SG	200	if (devtype == &imx50_weim_devtype) {
	201	ret = imx_weim_gpr_setup(pdev);
	202	if (ret)
	203	return ret;
	204	}
	205
77266e72 SVA	206	if (of_property_read_bool(pdev->dev.of_node, "fsl,burst-clk-enable")) {
	207	if (devtype->wcr_bcm) {
	208	reg = readl(base + devtype->wcr_offset);
	209	writel(reg \| devtype->wcr_bcm,
	210	base + devtype->wcr_offset);
	211	} else {
	212	dev_err(&pdev->dev, "burst clk mode not supported.\n");
	213	return -EINVAL;
	214	}
	215	}
	216
33b96d2c	217	for_each_available_child_of_node(pdev->dev.of_node, child) {
c7995bcb	218	ret = weim_timing_setup(&pdev->dev, child, base, devtype, &ts);
52c47b63	219	if (ret)
9c0982d8 RH	220	dev_warn(&pdev->dev, "%pOF set timing failed.\n",
9c0982d8 RH	221	child);
52c47b63 AC	222	else
52c47b63 AC	223	have_child = 1;
85bf6d4e HS	224	}
85bf6d4e HS	225
52c47b63	226	if (have_child)
39ec8d38 KW	227	ret = of_platform_default_populate(pdev->dev.of_node,
39ec8d38 KW	228	NULL, &pdev->dev);
85bf6d4e	229	if (ret)
9c0982d8 RH	230	dev_err(&pdev->dev, "%pOF fail to create devices.\n",
9c0982d8 RH	231	pdev->dev.of_node);
85bf6d4e HS	232	return ret;
	233	}
	234
4a92f078	235	static int weim_probe(struct platform_device *pdev)
85bf6d4e	236	{
85bf6d4e	237	struct resource *res;
70ac98da AS	238	struct clk *clk;
70ac98da AS	239	void __iomem *base;
b2d1fb73	240	int ret;
85bf6d4e	241
85bf6d4e HS	242	/* get the resource */
85bf6d4e HS	243	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
70ac98da	244	base = devm_ioremap_resource(&pdev->dev, res);
b2d1fb73 AS	245	if (IS_ERR(base))
b2d1fb73 AS	246	return PTR_ERR(base);
85bf6d4e HS	247
85bf6d4e HS	248	/* get the clock */
70ac98da AS	249	clk = devm_clk_get(&pdev->dev, NULL);
70ac98da AS	250	if (IS_ERR(clk))
b2d1fb73	251	return PTR_ERR(clk);
85bf6d4e	252
70ac98da	253	ret = clk_prepare_enable(clk);
85bf6d4e	254	if (ret)
b2d1fb73	255	return ret;
85bf6d4e HS	256
85bf6d4e HS	257	/* parse the device node */
70ac98da	258	ret = weim_parse_dt(pdev, base);
b2d1fb73	259	if (ret)
70ac98da	260	clk_disable_unprepare(clk);
b2d1fb73 AS	261	else
b2d1fb73 AS	262	dev_info(&pdev->dev, "Driver registered.\n");
85bf6d4e	263
85bf6d4e HS	264	return ret;
	265	}
	266
	267	static struct platform_driver weim_driver = {
	268	.driver = {
fc608c74	269	.name = "imx-weim",
fc608c74	270	.of_match_table = weim_id_table,
85bf6d4e	271	},
4a92f078	272	.probe = weim_probe,
85bf6d4e	273	};
4a92f078	274	module_platform_driver(weim_driver);
85bf6d4e	275
85bf6d4e HS	276	MODULE_AUTHOR("Freescale Semiconductor Inc.");
	277	MODULE_DESCRIPTION("i.MX EIM Controller Driver");
	278	MODULE_LICENSE("GPL");