[linux-2.6-block.git] / drivers / bus / brcmstb_gisb.c

/*
 * Copyright (C) 2014-2017 Broadcom
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/bitops.h>
#include <linux/pm.h>
#include <linux/kernel.h>
#include <linux/kdebug.h>
#include <linux/notifier.h>

#ifdef CONFIG_MIPS
#include <asm/traps.h>
#endif

#define  ARB_ERR_CAP_CLEAR		(1 << 0)
#define  ARB_ERR_CAP_STATUS_TIMEOUT	(1 << 12)
#define  ARB_ERR_CAP_STATUS_TEA		(1 << 11)
#define  ARB_ERR_CAP_STATUS_WRITE	(1 << 1)
#define  ARB_ERR_CAP_STATUS_VALID	(1 << 0)

enum {
	ARB_TIMER,
	ARB_ERR_CAP_CLR,
	ARB_ERR_CAP_HI_ADDR,
	ARB_ERR_CAP_ADDR,
	ARB_ERR_CAP_STATUS,
	ARB_ERR_CAP_MASTER,
};

static const int gisb_offsets_bcm7038[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_ERR_CAP_CLR]	= 0x0c4,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x0c8,
	[ARB_ERR_CAP_STATUS]	= 0x0d0,
	[ARB_ERR_CAP_MASTER]	= -1,
};

static const int gisb_offsets_bcm7278[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_ERR_CAP_CLR]	= 0x7f8,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x7e0,
	[ARB_ERR_CAP_STATUS]	= 0x7f0,
	[ARB_ERR_CAP_MASTER]	= 0x7f4,
};

static const int gisb_offsets_bcm7400[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_ERR_CAP_CLR]	= 0x0c8,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x0cc,
	[ARB_ERR_CAP_STATUS]	= 0x0d4,
	[ARB_ERR_CAP_MASTER]	= 0x0d8,
};

static const int gisb_offsets_bcm7435[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_ERR_CAP_CLR]	= 0x168,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x16c,
	[ARB_ERR_CAP_STATUS]	= 0x174,
	[ARB_ERR_CAP_MASTER]	= 0x178,
};

static const int gisb_offsets_bcm7445[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_ERR_CAP_CLR]	= 0x7e4,
	[ARB_ERR_CAP_HI_ADDR]	= 0x7e8,
	[ARB_ERR_CAP_ADDR]	= 0x7ec,
	[ARB_ERR_CAP_STATUS]	= 0x7f4,
	[ARB_ERR_CAP_MASTER]	= 0x7f8,
};

struct brcmstb_gisb_arb_device {
	void __iomem	*base;
	const int	*gisb_offsets;
	bool		big_endian;
	struct mutex	lock;
	struct list_head next;
	u32 valid_mask;
	const char *master_names[sizeof(u32) * BITS_PER_BYTE];
	u32 saved_timeout;
};

static LIST_HEAD(brcmstb_gisb_arb_device_list);

static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset < 0) {
		/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
		if (reg == ARB_ERR_CAP_MASTER)
			return 1;
		else
			return 0;
	}

	if (gdev->big_endian)
		return ioread32be(gdev->base + offset);
	else
		return ioread32(gdev->base + offset);
}

static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
{
	u64 value;

	value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
	value |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;

	return value;
}

static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset == -1)
		return;

	if (gdev->big_endian)
		iowrite32be(val, gdev->base + offset);
	else
		iowrite32(val, gdev->base + offset);
}

static ssize_t gisb_arb_get_timeout(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
	u32 timeout;

	mutex_lock(&gdev->lock);
	timeout = gisb_read(gdev, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return sprintf(buf, "%d", timeout);
}

static ssize_t gisb_arb_set_timeout(struct device *dev,
				    struct device_attribute *attr,
				    const char *buf, size_t count)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
	int val, ret;

	ret = kstrtoint(buf, 10, &val);
	if (ret < 0)
		return ret;

	if (val == 0 || val >= 0xffffffff)
		return -EINVAL;

	mutex_lock(&gdev->lock);
	gisb_write(gdev, val, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return count;
}

static const char *
brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
						u32 masters)
{
	u32 mask = gdev->valid_mask & masters;

	if (hweight_long(mask) != 1)
		return NULL;

	return gdev->master_names[ffs(mask) - 1];
}

static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
					const char *reason)
{
	u32 cap_status;
	u64 arb_addr;
	u32 master;
	const char *m_name;
	char m_fmt[11];

	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

	/* Invalid captured address, bail out */
	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
		return 1;

	/* Read the address and master */
	arb_addr = gisb_read_address(gdev);
	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);

	m_name = brcmstb_gisb_master_to_str(gdev, master);
	if (!m_name) {
		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
		m_name = m_fmt;
	}

	pr_crit("%s: %s at 0x%llx [%c %s], core: %s\n",
		__func__, reason, arb_addr,
		cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
		cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
		m_name);

	/* clear the GISB error */
	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);

	return 0;
}

#ifdef CONFIG_MIPS
static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
{
	int ret = 0;
	struct brcmstb_gisb_arb_device *gdev;
	u32 cap_status;

	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
		cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

		/* Invalid captured address, bail out */
		if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
			is_fixup = 1;
			goto out;
		}

		ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	}
out:
	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
}
#endif

static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");

	return IRQ_HANDLED;
}

static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");

	return IRQ_HANDLED;
}

/*
 * Dump out gisb errors on die or panic.
 */
static int dump_gisb_error(struct notifier_block *self, unsigned long v,
			   void *p);

static struct notifier_block gisb_die_notifier = {
	.notifier_call = dump_gisb_error,
};

static struct notifier_block gisb_panic_notifier = {
	.notifier_call = dump_gisb_error,
};

static int dump_gisb_error(struct notifier_block *self, unsigned long v,
			   void *p)
{
	struct brcmstb_gisb_arb_device *gdev;
	const char *reason = "panic";

	if (self == &gisb_die_notifier)
		reason = "die";

	/* iterate over each GISB arb registered handlers */
	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
		brcmstb_gisb_arb_decode_addr(gdev, reason);

	return NOTIFY_DONE;
}

static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
		gisb_arb_get_timeout, gisb_arb_set_timeout);

static struct attribute *gisb_arb_sysfs_attrs[] = {
	&dev_attr_gisb_arb_timeout.attr,
	NULL,
};

static struct attribute_group gisb_arb_sysfs_attr_group = {
	.attrs = gisb_arb_sysfs_attrs,
};

static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	{ .compatible = "brcm,gisb-arb",         .data = gisb_offsets_bcm7445 },
	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
	{ },
};

static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
{
	struct device_node *dn = pdev->dev.of_node;
	struct brcmstb_gisb_arb_device *gdev;
	const struct of_device_id *of_id;
	struct resource *r;
	int err, timeout_irq, tea_irq;
	unsigned int num_masters, j = 0;
	int i, first, last;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	timeout_irq = platform_get_irq(pdev, 0);
	tea_irq = platform_get_irq(pdev, 1);

	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	if (!gdev)
		return -ENOMEM;

	mutex_init(&gdev->lock);
	INIT_LIST_HEAD(&gdev->next);

	gdev->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(gdev->base))
		return PTR_ERR(gdev->base);

	of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
	if (!of_id) {
		pr_err("failed to look up compatible string\n");
		return -EINVAL;
	}
	gdev->gisb_offsets = of_id->data;
	gdev->big_endian = of_device_is_big_endian(dn);

	err = devm_request_irq(&pdev->dev, timeout_irq,
				brcmstb_gisb_timeout_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	err = devm_request_irq(&pdev->dev, tea_irq,
				brcmstb_gisb_tea_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	/* If we do not have a valid mask, assume all masters are enabled */
	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
				&gdev->valid_mask))
		gdev->valid_mask = 0xffffffff;

	/* Proceed with reading the litteral names if we agree on the
	 * number of masters
	 */
	num_masters = of_property_count_strings(dn,
			"brcm,gisb-arb-master-names");
	if (hweight_long(gdev->valid_mask) == num_masters) {
		first = ffs(gdev->valid_mask) - 1;
		last = fls(gdev->valid_mask) - 1;

		for (i = first; i < last; i++) {
			if (!(gdev->valid_mask & BIT(i)))
				continue;

			of_property_read_string_index(dn,
					"brcm,gisb-arb-master-names", j,
					&gdev->master_names[i]);
			j++;
		}
	}

	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	if (err)
		return err;

	platform_set_drvdata(pdev, gdev);

	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);

#ifdef CONFIG_MIPS
	board_be_handler = brcmstb_bus_error_handler;
#endif

	if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
		register_die_notifier(&gisb_die_notifier);
		atomic_notifier_chain_register(&panic_notifier_list,
					       &gisb_panic_notifier);
	}

	dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
			gdev->base, timeout_irq, tea_irq);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int brcmstb_gisb_arb_suspend(struct device *dev)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);

	gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);

	return 0;
}

/* Make sure we provide the same timeout value that was configured before, and
 * do this before the GISB timeout interrupt handler has any chance to run.
 */
static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);

	gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);

	return 0;
}
#else
#define brcmstb_gisb_arb_suspend       NULL
#define brcmstb_gisb_arb_resume_noirq  NULL
#endif

static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
	.suspend	= brcmstb_gisb_arb_suspend,
	.resume_noirq	= brcmstb_gisb_arb_resume_noirq,
};

static struct platform_driver brcmstb_gisb_arb_driver = {
	.driver = {
		.name	= "brcm-gisb-arb",
		.of_match_table = brcmstb_gisb_arb_of_match,
		.pm	= &brcmstb_gisb_arb_pm_ops,
	},
};

static int __init brcm_gisb_driver_init(void)
{
	return platform_driver_probe(&brcmstb_gisb_arb_driver,
				     brcmstb_gisb_arb_probe);
}

module_init(brcm_gisb_driver_init);
Commit	Line	Data
44127b77	1	/*
856c7ccb	2	* Copyright (C) 2014-2017 Broadcom
44127b77 FF	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/types.h>
	16	#include <linux/module.h>
	17	#include <linux/platform_device.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/sysfs.h>
	20	#include <linux/io.h>
	21	#include <linux/string.h>
	22	#include <linux/device.h>
	23	#include <linux/list.h>
	24	#include <linux/of.h>
	25	#include <linux/bitops.h>
203bb85e	26	#include <linux/pm.h>
9eb60880 DB	27	#include <linux/kernel.h>
	28	#include <linux/kdebug.h>
	29	#include <linux/notifier.h>
44127b77	30
c400d5eb FF	31	#ifdef CONFIG_MIPS
	32	#include <asm/traps.h>
	33	#endif
	34
44127b77	35	#define ARB_ERR_CAP_CLEAR (1 << 0)
44127b77 FF	36	#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
44127b77 FF	37	#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
44127b77 FF	38	#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
44127b77 FF	39	#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
f8083587 KC	40
	41	enum {
	42	ARB_TIMER,
	43	ARB_ERR_CAP_CLR,
	44	ARB_ERR_CAP_HI_ADDR,
	45	ARB_ERR_CAP_ADDR,
f8083587 KC	46	ARB_ERR_CAP_STATUS,
	47	ARB_ERR_CAP_MASTER,
	48	};
	49
d1d67868 KC	50	static const int gisb_offsets_bcm7038[] = {
	51	[ARB_TIMER] = 0x00c,
	52	[ARB_ERR_CAP_CLR] = 0x0c4,
	53	[ARB_ERR_CAP_HI_ADDR] = -1,
	54	[ARB_ERR_CAP_ADDR] = 0x0c8,
d1d67868 KC	55	[ARB_ERR_CAP_STATUS] = 0x0d0,
	56	[ARB_ERR_CAP_MASTER] = -1,
	57	};
	58
d523e0cf DB	59	static const int gisb_offsets_bcm7278[] = {
	60	[ARB_TIMER] = 0x008,
	61	[ARB_ERR_CAP_CLR] = 0x7f8,
	62	[ARB_ERR_CAP_HI_ADDR] = -1,
	63	[ARB_ERR_CAP_ADDR] = 0x7e0,
	64	[ARB_ERR_CAP_STATUS] = 0x7f0,
	65	[ARB_ERR_CAP_MASTER] = 0x7f4,
	66	};
	67
d1d67868 KC	68	static const int gisb_offsets_bcm7400[] = {
	69	[ARB_TIMER] = 0x00c,
	70	[ARB_ERR_CAP_CLR] = 0x0c8,
	71	[ARB_ERR_CAP_HI_ADDR] = -1,
	72	[ARB_ERR_CAP_ADDR] = 0x0cc,
d1d67868 KC	73	[ARB_ERR_CAP_STATUS] = 0x0d4,
	74	[ARB_ERR_CAP_MASTER] = 0x0d8,
	75	};
	76
	77	static const int gisb_offsets_bcm7435[] = {
	78	[ARB_TIMER] = 0x00c,
	79	[ARB_ERR_CAP_CLR] = 0x168,
	80	[ARB_ERR_CAP_HI_ADDR] = -1,
	81	[ARB_ERR_CAP_ADDR] = 0x16c,
d1d67868 KC	82	[ARB_ERR_CAP_STATUS] = 0x174,
	83	[ARB_ERR_CAP_MASTER] = 0x178,
	84	};
	85
f8083587 KC	86	static const int gisb_offsets_bcm7445[] = {
	87	[ARB_TIMER] = 0x008,
	88	[ARB_ERR_CAP_CLR] = 0x7e4,
	89	[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
	90	[ARB_ERR_CAP_ADDR] = 0x7ec,
f8083587 KC	91	[ARB_ERR_CAP_STATUS] = 0x7f4,
	92	[ARB_ERR_CAP_MASTER] = 0x7f8,
	93	};
44127b77 FF	94
	95	struct brcmstb_gisb_arb_device {
	96	void __iomem *base;
f8083587	97	const int *gisb_offsets;
fbf4e262	98	bool big_endian;
44127b77 FF	99	struct mutex lock;
	100	struct list_head next;
	101	u32 valid_mask;
	102	const char master_names[sizeof(u32) BITS_PER_BYTE];
203bb85e	103	u32 saved_timeout;
44127b77 FF	104	};
	105
	106	static LIST_HEAD(brcmstb_gisb_arb_device_list);
	107
2b53eadc KC	108	static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
2b53eadc KC	109	{
f8083587 KC	110	int offset = gdev->gisb_offsets[reg];
f8083587 KC	111
0c2aa0e4 DB	112	if (offset < 0) {
	113	/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
	114	if (reg == ARB_ERR_CAP_MASTER)
	115	return 1;
	116	else
	117	return 0;
	118	}
f8083587	119
fbf4e262 KC	120	if (gdev->big_endian)
	121	return ioread32be(gdev->base + offset);
	122	else
	123	return ioread32(gdev->base + offset);
2b53eadc KC	124	}
2b53eadc KC	125
0c2aa0e4 DB	126	static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
	127	{
	128	u64 value;
	129
	130	value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
	131	value \|= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
	132
	133	return value;
	134	}
	135
2b53eadc KC	136	static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
2b53eadc KC	137	{
f8083587 KC	138	int offset = gdev->gisb_offsets[reg];
	139
	140	if (offset == -1)
	141	return;
fbf4e262 KC	142
fbf4e262 KC	143	if (gdev->big_endian)
856c7ccb	144	iowrite32be(val, gdev->base + offset);
fbf4e262	145	else
856c7ccb	146	iowrite32(val, gdev->base + offset);
2b53eadc KC	147	}
2b53eadc KC	148
44127b77 FF	149	static ssize_t gisb_arb_get_timeout(struct device *dev,
	150	struct device_attribute *attr,
	151	char *buf)
	152	{
0810d5cc	153	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
44127b77 FF	154	u32 timeout;
	155
	156	mutex_lock(&gdev->lock);
2b53eadc	157	timeout = gisb_read(gdev, ARB_TIMER);
44127b77 FF	158	mutex_unlock(&gdev->lock);
	159
	160	return sprintf(buf, "%d", timeout);
	161	}
	162
	163	static ssize_t gisb_arb_set_timeout(struct device *dev,
	164	struct device_attribute *attr,
	165	const char *buf, size_t count)
	166	{
0810d5cc	167	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
44127b77 FF	168	int val, ret;
	169
	170	ret = kstrtoint(buf, 10, &val);
	171	if (ret < 0)
	172	return ret;
	173
	174	if (val == 0 \|\| val >= 0xffffffff)
	175	return -EINVAL;
	176
	177	mutex_lock(&gdev->lock);
2b53eadc	178	gisb_write(gdev, val, ARB_TIMER);
44127b77 FF	179	mutex_unlock(&gdev->lock);
	180
	181	return count;
	182	}
	183
	184	static const char *
	185	brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
	186	u32 masters)
	187	{
	188	u32 mask = gdev->valid_mask & masters;
	189
	190	if (hweight_long(mask) != 1)
	191	return NULL;
	192
	193	return gdev->master_names[ffs(mask) - 1];
	194	}
	195
	196	static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
	197	const char *reason)
	198	{
	199	u32 cap_status;
0c2aa0e4	200	u64 arb_addr;
44127b77 FF	201	u32 master;
	202	const char *m_name;
	203	char m_fmt[11];
	204
2b53eadc	205	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
44127b77 FF	206
	207	/* Invalid captured address, bail out */
	208	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
	209	return 1;
	210
	211	/* Read the address and master */
0c2aa0e4	212	arb_addr = gisb_read_address(gdev);
2b53eadc	213	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
44127b77 FF	214
	215	m_name = brcmstb_gisb_master_to_str(gdev, master);
	216	if (!m_name) {
	217	snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
	218	m_name = m_fmt;
	219	}
	220
0c2aa0e4	221	pr_crit("%s: %s at 0x%llx [%c %s], core: %s\n",
44127b77 FF	222	__func__, reason, arb_addr,
	223	cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
	224	cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
	225	m_name);
	226
	227	/* clear the GISB error */
2b53eadc	228	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
44127b77 FF	229
	230	return 0;
	231	}
	232
c400d5eb FF	233	#ifdef CONFIG_MIPS
	234	static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
	235	{
	236	int ret = 0;
	237	struct brcmstb_gisb_arb_device *gdev;
	238	u32 cap_status;
	239
	240	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
	241	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
	242
	243	/* Invalid captured address, bail out */
	244	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
	245	is_fixup = 1;
	246	goto out;
	247	}
	248
	249	ret \|= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	250	}
	251	out:
	252	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
	253	}
	254	#endif
	255
44127b77 FF	256	static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
	257	{
	258	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
	259
	260	return IRQ_HANDLED;
	261	}
	262
	263	static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
	264	{
	265	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
	266
	267	return IRQ_HANDLED;
	268	}
	269
9eb60880 DB	270	/*
	271	* Dump out gisb errors on die or panic.
	272	*/
	273	static int dump_gisb_error(struct notifier_block *self, unsigned long v,
	274	void *p);
	275
	276	static struct notifier_block gisb_die_notifier = {
	277	.notifier_call = dump_gisb_error,
	278	};
	279
	280	static struct notifier_block gisb_panic_notifier = {
	281	.notifier_call = dump_gisb_error,
	282	};
	283
	284	static int dump_gisb_error(struct notifier_block *self, unsigned long v,
	285	void *p)
	286	{
	287	struct brcmstb_gisb_arb_device *gdev;
	288	const char *reason = "panic";
	289
	290	if (self == &gisb_die_notifier)
	291	reason = "die";
	292
	293	/* iterate over each GISB arb registered handlers */
	294	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
	295	brcmstb_gisb_arb_decode_addr(gdev, reason);
	296
	297	return NOTIFY_DONE;
	298	}
	299
44127b77 FF	300	static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR \| S_IRUGO,
	301	gisb_arb_get_timeout, gisb_arb_set_timeout);
	302
	303	static struct attribute *gisb_arb_sysfs_attrs[] = {
	304	&dev_attr_gisb_arb_timeout.attr,
	305	NULL,
	306	};
	307
	308	static struct attribute_group gisb_arb_sysfs_attr_group = {
	309	.attrs = gisb_arb_sysfs_attrs,
	310	};
	311
d1d67868 KC	312	static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	313	{ .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 },
	314	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
	315	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
	316	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
d523e0cf	317	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
d1d67868 KC	318	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
	319	{ },
	320	};
	321
2e8a29a1	322	static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
44127b77 FF	323	{
	324	struct device_node *dn = pdev->dev.of_node;
	325	struct brcmstb_gisb_arb_device *gdev;
d1d67868	326	const struct of_device_id *of_id;
44127b77 FF	327	struct resource *r;
	328	int err, timeout_irq, tea_irq;
	329	unsigned int num_masters, j = 0;
	330	int i, first, last;
	331
	332	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	333	timeout_irq = platform_get_irq(pdev, 0);
	334	tea_irq = platform_get_irq(pdev, 1);
	335
	336	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	337	if (!gdev)
	338	return -ENOMEM;
	339
	340	mutex_init(&gdev->lock);
	341	INIT_LIST_HEAD(&gdev->next);
	342
c9d53c0f JH	343	gdev->base = devm_ioremap_resource(&pdev->dev, r);
	344	if (IS_ERR(gdev->base))
	345	return PTR_ERR(gdev->base);
44127b77	346
d1d67868 KC	347	of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
	348	if (!of_id) {
	349	pr_err("failed to look up compatible string\n");
	350	return -EINVAL;
	351	}
	352	gdev->gisb_offsets = of_id->data;
fbf4e262	353	gdev->big_endian = of_device_is_big_endian(dn);
f8083587	354
44127b77 FF	355	err = devm_request_irq(&pdev->dev, timeout_irq,
	356	brcmstb_gisb_timeout_handler, 0, pdev->name,
	357	gdev);
	358	if (err < 0)
	359	return err;
	360
	361	err = devm_request_irq(&pdev->dev, tea_irq,
	362	brcmstb_gisb_tea_handler, 0, pdev->name,
	363	gdev);
	364	if (err < 0)
	365	return err;
	366
	367	/* If we do not have a valid mask, assume all masters are enabled */
	368	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
	369	&gdev->valid_mask))
	370	gdev->valid_mask = 0xffffffff;
	371
	372	/* Proceed with reading the litteral names if we agree on the
	373	* number of masters
	374	*/
	375	num_masters = of_property_count_strings(dn,
	376	"brcm,gisb-arb-master-names");
	377	if (hweight_long(gdev->valid_mask) == num_masters) {
	378	first = ffs(gdev->valid_mask) - 1;
	379	last = fls(gdev->valid_mask) - 1;
	380
	381	for (i = first; i < last; i++) {
	382	if (!(gdev->valid_mask & BIT(i)))
	383	continue;
	384
	385	of_property_read_string_index(dn,
	386	"brcm,gisb-arb-master-names", j,
	387	&gdev->master_names[i]);
	388	j++;
	389	}
	390	}
	391
	392	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	393	if (err)
	394	return err;
	395
	396	platform_set_drvdata(pdev, gdev);
	397
	398	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
	399
c400d5eb FF	400	#ifdef CONFIG_MIPS
	401	board_be_handler = brcmstb_bus_error_handler;
	402	#endif
f1bee783	403
9eb60880 DB	404	if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
	405	register_die_notifier(&gisb_die_notifier);
	406	atomic_notifier_chain_register(&panic_notifier_list,
	407	&gisb_panic_notifier);
	408	}
	409
44127b77 FF	410	dev_info(&pdev->dev, "registered mem: %p, irqs: %d, %d\n",
	411	gdev->base, timeout_irq, tea_irq);
	412
	413	return 0;
	414	}
	415
203bb85e FF	416	#ifdef CONFIG_PM_SLEEP
	417	static int brcmstb_gisb_arb_suspend(struct device *dev)
	418	{
0810d5cc	419	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
203bb85e	420
71354661	421	gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
203bb85e FF	422
	423	return 0;
	424	}
	425
	426	/* Make sure we provide the same timeout value that was configured before, and
	427	* do this before the GISB timeout interrupt handler has any chance to run.
	428	*/
	429	static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
	430	{
0810d5cc	431	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
203bb85e	432
71354661	433	gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
203bb85e FF	434
	435	return 0;
	436	}
	437	#else
	438	#define brcmstb_gisb_arb_suspend NULL
	439	#define brcmstb_gisb_arb_resume_noirq NULL
	440	#endif
	441
	442	static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
	443	.suspend = brcmstb_gisb_arb_suspend,
	444	.resume_noirq = brcmstb_gisb_arb_resume_noirq,
	445	};
	446
44127b77	447	static struct platform_driver brcmstb_gisb_arb_driver = {
44127b77 FF	448	.driver = {
44127b77 FF	449	.name = "brcm-gisb-arb",
44127b77	450	.of_match_table = brcmstb_gisb_arb_of_match,
203bb85e	451	.pm = &brcmstb_gisb_arb_pm_ops,
44127b77 FF	452	},
	453	};
	454
	455	static int __init brcm_gisb_driver_init(void)
	456	{
2e8a29a1 FF	457	return platform_driver_probe(&brcmstb_gisb_arb_driver,
2e8a29a1 FF	458	brcmstb_gisb_arb_probe);
44127b77 FF	459	}
	460
	461	module_init(brcm_gisb_driver_init);