[linux-block.git] / drivers / bus / brcmstb_gisb.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014-2021 Broadcom
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/module.h>
#include <linux/panic_notifier.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/io.h>
#include <linux/string.h>
#include <linux/device.h>
#include <linux/list.h>
#include <linux/of.h>
#include <linux/bitops.h>
#include <linux/pm.h>
#include <linux/kernel.h>
#include <linux/kdebug.h>
#include <linux/notifier.h>

#ifdef CONFIG_MIPS
#include <asm/traps.h>
#endif

#define  ARB_ERR_CAP_CLEAR		(1 << 0)
#define  ARB_ERR_CAP_STATUS_TIMEOUT	(1 << 12)
#define  ARB_ERR_CAP_STATUS_TEA		(1 << 11)
#define  ARB_ERR_CAP_STATUS_WRITE	(1 << 1)
#define  ARB_ERR_CAP_STATUS_VALID	(1 << 0)

#define  ARB_BP_CAP_CLEAR		(1 << 0)
#define  ARB_BP_CAP_STATUS_PROT_SHIFT	14
#define  ARB_BP_CAP_STATUS_TYPE		(1 << 13)
#define  ARB_BP_CAP_STATUS_RSP_SHIFT	10
#define  ARB_BP_CAP_STATUS_MASK		GENMASK(1, 0)
#define  ARB_BP_CAP_STATUS_BS_SHIFT	2
#define  ARB_BP_CAP_STATUS_WRITE	(1 << 1)
#define  ARB_BP_CAP_STATUS_VALID	(1 << 0)

enum {
	ARB_TIMER,
	ARB_BP_CAP_CLR,
	ARB_BP_CAP_HI_ADDR,
	ARB_BP_CAP_ADDR,
	ARB_BP_CAP_STATUS,
	ARB_BP_CAP_MASTER,
	ARB_ERR_CAP_CLR,
	ARB_ERR_CAP_HI_ADDR,
	ARB_ERR_CAP_ADDR,
	ARB_ERR_CAP_STATUS,
	ARB_ERR_CAP_MASTER,
};

static const int gisb_offsets_bcm7038[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_BP_CAP_CLR]	= 0x014,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x0b8,
	[ARB_BP_CAP_STATUS]	= 0x0c0,
	[ARB_BP_CAP_MASTER]	= -1,
	[ARB_ERR_CAP_CLR]	= 0x0c4,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x0c8,
	[ARB_ERR_CAP_STATUS]	= 0x0d0,
	[ARB_ERR_CAP_MASTER]	= -1,
};

static const int gisb_offsets_bcm7278[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_BP_CAP_CLR]	= 0x01c,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x220,
	[ARB_BP_CAP_STATUS]	= 0x230,
	[ARB_BP_CAP_MASTER]	= 0x234,
	[ARB_ERR_CAP_CLR]	= 0x7f8,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x7e0,
	[ARB_ERR_CAP_STATUS]	= 0x7f0,
	[ARB_ERR_CAP_MASTER]	= 0x7f4,
};

static const int gisb_offsets_bcm7400[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_BP_CAP_CLR]	= 0x014,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x0b8,
	[ARB_BP_CAP_STATUS]	= 0x0c0,
	[ARB_BP_CAP_MASTER]	= 0x0c4,
	[ARB_ERR_CAP_CLR]	= 0x0c8,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x0cc,
	[ARB_ERR_CAP_STATUS]	= 0x0d4,
	[ARB_ERR_CAP_MASTER]	= 0x0d8,
};

static const int gisb_offsets_bcm7435[] = {
	[ARB_TIMER]		= 0x00c,
	[ARB_BP_CAP_CLR]	= 0x014,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x158,
	[ARB_BP_CAP_STATUS]	= 0x160,
	[ARB_BP_CAP_MASTER]	= 0x164,
	[ARB_ERR_CAP_CLR]	= 0x168,
	[ARB_ERR_CAP_HI_ADDR]	= -1,
	[ARB_ERR_CAP_ADDR]	= 0x16c,
	[ARB_ERR_CAP_STATUS]	= 0x174,
	[ARB_ERR_CAP_MASTER]	= 0x178,
};

static const int gisb_offsets_bcm7445[] = {
	[ARB_TIMER]		= 0x008,
	[ARB_BP_CAP_CLR]	= 0x010,
	[ARB_BP_CAP_HI_ADDR]	= -1,
	[ARB_BP_CAP_ADDR]	= 0x1d8,
	[ARB_BP_CAP_STATUS]	= 0x1e0,
	[ARB_BP_CAP_MASTER]	= 0x1e4,
	[ARB_ERR_CAP_CLR]	= 0x7e4,
	[ARB_ERR_CAP_HI_ADDR]	= 0x7e8,
	[ARB_ERR_CAP_ADDR]	= 0x7ec,
	[ARB_ERR_CAP_STATUS]	= 0x7f4,
	[ARB_ERR_CAP_MASTER]	= 0x7f8,
};

struct brcmstb_gisb_arb_device {
	void __iomem	*base;
	const int	*gisb_offsets;
	bool		big_endian;
	struct mutex	lock;
	struct list_head next;
	u32 valid_mask;
	const char *master_names[sizeof(u32) * BITS_PER_BYTE];
	u32 saved_timeout;
};

static LIST_HEAD(brcmstb_gisb_arb_device_list);

static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset < 0) {
		/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
		if (reg == ARB_ERR_CAP_MASTER)
			return 1;
		else
			return 0;
	}

	if (gdev->big_endian)
		return ioread32be(gdev->base + offset);
	else
		return ioread32(gdev->base + offset);
}

static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
{
	u64 value;

	value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
	value |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;

	return value;
}

static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
{
	u64 value;

	value = gisb_read(gdev, ARB_BP_CAP_ADDR);
	value |= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;

	return value;
}

static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
{
	int offset = gdev->gisb_offsets[reg];

	if (offset == -1)
		return;

	if (gdev->big_endian)
		iowrite32be(val, gdev->base + offset);
	else
		iowrite32(val, gdev->base + offset);
}

static ssize_t gisb_arb_get_timeout(struct device *dev,
				    struct device_attribute *attr,
				    char *buf)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
	u32 timeout;

	mutex_lock(&gdev->lock);
	timeout = gisb_read(gdev, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return sprintf(buf, "%d", timeout);
}

static ssize_t gisb_arb_set_timeout(struct device *dev,
				    struct device_attribute *attr,
				    const char *buf, size_t count)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
	int val, ret;

	ret = kstrtoint(buf, 10, &val);
	if (ret < 0)
		return ret;

	if (val == 0 || val >= 0xffffffff)
		return -EINVAL;

	mutex_lock(&gdev->lock);
	gisb_write(gdev, val, ARB_TIMER);
	mutex_unlock(&gdev->lock);

	return count;
}

static const char *
brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
						u32 masters)
{
	u32 mask = gdev->valid_mask & masters;

	if (hweight_long(mask) != 1)
		return NULL;

	return gdev->master_names[ffs(mask) - 1];
}

static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
					const char *reason)
{
	u32 cap_status;
	u64 arb_addr;
	u32 master;
	const char *m_name;
	char m_fmt[11];

	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

	/* Invalid captured address, bail out */
	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
		return 1;

	/* Read the address and master */
	arb_addr = gisb_read_address(gdev);
	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);

	m_name = brcmstb_gisb_master_to_str(gdev, master);
	if (!m_name) {
		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
		m_name = m_fmt;
	}

	pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
		reason, arb_addr,
		cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
		cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
		m_name);

	/* clear the GISB error */
	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);

	return 0;
}

#ifdef CONFIG_MIPS
static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
{
	int ret = 0;
	struct brcmstb_gisb_arb_device *gdev;
	u32 cap_status;

	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
		cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);

		/* Invalid captured address, bail out */
		if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
			is_fixup = 1;
			goto out;
		}

		ret |= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	}
out:
	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
}
#endif

static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");

	return IRQ_HANDLED;
}

static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
{
	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");

	return IRQ_HANDLED;
}

static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
{
	struct brcmstb_gisb_arb_device *gdev = dev_id;
	const char *m_name;
	u32 bp_status;
	u64 arb_addr;
	u32 master;
	char m_fmt[11];

	bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);

	/* Invalid captured address, bail out */
	if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
		return IRQ_HANDLED;

	/* Read the address and master */
	arb_addr = gisb_read_bp_address(gdev);
	master = gisb_read(gdev, ARB_BP_CAP_MASTER);

	m_name = brcmstb_gisb_master_to_str(gdev, master);
	if (!m_name) {
		snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
		m_name = m_fmt;
	}

	pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
		arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
		m_name);

	/* clear the GISB error */
	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);

	return IRQ_HANDLED;
}

/*
 * Dump out gisb errors on die or panic.
 */
static int dump_gisb_error(struct notifier_block *self, unsigned long v,
			   void *p);

static struct notifier_block gisb_die_notifier = {
	.notifier_call = dump_gisb_error,
};

static struct notifier_block gisb_panic_notifier = {
	.notifier_call = dump_gisb_error,
};

static int dump_gisb_error(struct notifier_block *self, unsigned long v,
			   void *p)
{
	struct brcmstb_gisb_arb_device *gdev;
	const char *reason = "panic";

	if (self == &gisb_die_notifier)
		reason = "die";

	/* iterate over each GISB arb registered handlers */
	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
		brcmstb_gisb_arb_decode_addr(gdev, reason);

	return NOTIFY_DONE;
}

static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR | S_IRUGO,
		gisb_arb_get_timeout, gisb_arb_set_timeout);

static struct attribute *gisb_arb_sysfs_attrs[] = {
	&dev_attr_gisb_arb_timeout.attr,
	NULL,
};

static struct attribute_group gisb_arb_sysfs_attr_group = {
	.attrs = gisb_arb_sysfs_attrs,
};

static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	{ .compatible = "brcm,gisb-arb",         .data = gisb_offsets_bcm7445 },
	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
	{ },
};

static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
{
	struct device_node *dn = pdev->dev.of_node;
	struct brcmstb_gisb_arb_device *gdev;
	const struct of_device_id *of_id;
	struct resource *r;
	int err, timeout_irq, tea_irq, bp_irq;
	unsigned int num_masters, j = 0;
	int i, first, last;

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	timeout_irq = platform_get_irq(pdev, 0);
	tea_irq = platform_get_irq(pdev, 1);
	bp_irq = platform_get_irq(pdev, 2);

	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	if (!gdev)
		return -ENOMEM;

	mutex_init(&gdev->lock);
	INIT_LIST_HEAD(&gdev->next);

	gdev->base = devm_ioremap_resource(&pdev->dev, r);
	if (IS_ERR(gdev->base))
		return PTR_ERR(gdev->base);

	of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
	if (!of_id) {
		pr_err("failed to look up compatible string\n");
		return -EINVAL;
	}
	gdev->gisb_offsets = of_id->data;
	gdev->big_endian = of_device_is_big_endian(dn);

	err = devm_request_irq(&pdev->dev, timeout_irq,
				brcmstb_gisb_timeout_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	err = devm_request_irq(&pdev->dev, tea_irq,
				brcmstb_gisb_tea_handler, 0, pdev->name,
				gdev);
	if (err < 0)
		return err;

	/* Interrupt is optional */
	if (bp_irq > 0) {
		err = devm_request_irq(&pdev->dev, bp_irq,
				       brcmstb_gisb_bp_handler, 0, pdev->name,
				       gdev);
		if (err < 0)
			return err;
	}

	/* If we do not have a valid mask, assume all masters are enabled */
	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
				&gdev->valid_mask))
		gdev->valid_mask = 0xffffffff;

	/* Proceed with reading the litteral names if we agree on the
	 * number of masters
	 */
	num_masters = of_property_count_strings(dn,
			"brcm,gisb-arb-master-names");
	if (hweight_long(gdev->valid_mask) == num_masters) {
		first = ffs(gdev->valid_mask) - 1;
		last = fls(gdev->valid_mask) - 1;

		for (i = first; i < last; i++) {
			if (!(gdev->valid_mask & BIT(i)))
				continue;

			of_property_read_string_index(dn,
					"brcm,gisb-arb-master-names", j,
					&gdev->master_names[i]);
			j++;
		}
	}

	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	if (err)
		return err;

	platform_set_drvdata(pdev, gdev);

	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);

#ifdef CONFIG_MIPS
	mips_set_be_handler(brcmstb_bus_error_handler);
#endif

	if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
		register_die_notifier(&gisb_die_notifier);
		atomic_notifier_chain_register(&panic_notifier_list,
					       &gisb_panic_notifier);
	}

	dev_info(&pdev->dev, "registered irqs: %d, %d\n",
		 timeout_irq, tea_irq);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int brcmstb_gisb_arb_suspend(struct device *dev)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);

	gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);

	return 0;
}

/* Make sure we provide the same timeout value that was configured before, and
 * do this before the GISB timeout interrupt handler has any chance to run.
 */
static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
{
	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);

	gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);

	return 0;
}
#else
#define brcmstb_gisb_arb_suspend       NULL
#define brcmstb_gisb_arb_resume_noirq  NULL
#endif

static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
	.suspend	= brcmstb_gisb_arb_suspend,
	.resume_noirq	= brcmstb_gisb_arb_resume_noirq,
};

static struct platform_driver brcmstb_gisb_arb_driver = {
	.driver = {
		.name	= "brcm-gisb-arb",
		.of_match_table = brcmstb_gisb_arb_of_match,
		.pm	= &brcmstb_gisb_arb_pm_ops,
	},
};

static int __init brcm_gisb_driver_init(void)
{
	return platform_driver_probe(&brcmstb_gisb_arb_driver,
				     brcmstb_gisb_arb_probe);
}

module_init(brcm_gisb_driver_init);

MODULE_AUTHOR("Broadcom");
MODULE_DESCRIPTION("Broadcom STB GISB arbiter driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
1802d0be	1	// SPDX-License-Identifier: GPL-2.0-only
44127b77	2	/*
707a4cdf	3	* Copyright (C) 2014-2021 Broadcom
44127b77 FF	4	*/
	5
	6	#include <linux/init.h>
	7	#include <linux/types.h>
	8	#include <linux/module.h>
f39650de	9	#include <linux/panic_notifier.h>
44127b77 FF	10	#include <linux/platform_device.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/sysfs.h>
	13	#include <linux/io.h>
	14	#include <linux/string.h>
	15	#include <linux/device.h>
	16	#include <linux/list.h>
	17	#include <linux/of.h>
	18	#include <linux/bitops.h>
203bb85e	19	#include <linux/pm.h>
9eb60880 DB	20	#include <linux/kernel.h>
	21	#include <linux/kdebug.h>
	22	#include <linux/notifier.h>
44127b77	23
c400d5eb FF	24	#ifdef CONFIG_MIPS
	25	#include <asm/traps.h>
	26	#endif
	27
44127b77	28	#define ARB_ERR_CAP_CLEAR (1 << 0)
44127b77 FF	29	#define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12)
44127b77 FF	30	#define ARB_ERR_CAP_STATUS_TEA (1 << 11)
44127b77 FF	31	#define ARB_ERR_CAP_STATUS_WRITE (1 << 1)
44127b77 FF	32	#define ARB_ERR_CAP_STATUS_VALID (1 << 0)
f8083587	33
fb8a0b80 FF	34	#define ARB_BP_CAP_CLEAR (1 << 0)
	35	#define ARB_BP_CAP_STATUS_PROT_SHIFT 14
	36	#define ARB_BP_CAP_STATUS_TYPE (1 << 13)
	37	#define ARB_BP_CAP_STATUS_RSP_SHIFT 10
	38	#define ARB_BP_CAP_STATUS_MASK GENMASK(1, 0)
	39	#define ARB_BP_CAP_STATUS_BS_SHIFT 2
	40	#define ARB_BP_CAP_STATUS_WRITE (1 << 1)
	41	#define ARB_BP_CAP_STATUS_VALID (1 << 0)
	42
f8083587 KC	43	enum {
f8083587 KC	44	ARB_TIMER,
fb8a0b80 FF	45	ARB_BP_CAP_CLR,
	46	ARB_BP_CAP_HI_ADDR,
	47	ARB_BP_CAP_ADDR,
	48	ARB_BP_CAP_STATUS,
	49	ARB_BP_CAP_MASTER,
f8083587 KC	50	ARB_ERR_CAP_CLR,
	51	ARB_ERR_CAP_HI_ADDR,
	52	ARB_ERR_CAP_ADDR,
f8083587 KC	53	ARB_ERR_CAP_STATUS,
	54	ARB_ERR_CAP_MASTER,
	55	};
	56
d1d67868 KC	57	static const int gisb_offsets_bcm7038[] = {
d1d67868 KC	58	[ARB_TIMER] = 0x00c,
fb8a0b80 FF	59	[ARB_BP_CAP_CLR] = 0x014,
	60	[ARB_BP_CAP_HI_ADDR] = -1,
	61	[ARB_BP_CAP_ADDR] = 0x0b8,
	62	[ARB_BP_CAP_STATUS] = 0x0c0,
	63	[ARB_BP_CAP_MASTER] = -1,
d1d67868 KC	64	[ARB_ERR_CAP_CLR] = 0x0c4,
	65	[ARB_ERR_CAP_HI_ADDR] = -1,
	66	[ARB_ERR_CAP_ADDR] = 0x0c8,
d1d67868 KC	67	[ARB_ERR_CAP_STATUS] = 0x0d0,
	68	[ARB_ERR_CAP_MASTER] = -1,
	69	};
	70
d523e0cf DB	71	static const int gisb_offsets_bcm7278[] = {
d523e0cf DB	72	[ARB_TIMER] = 0x008,
fb8a0b80 FF	73	[ARB_BP_CAP_CLR] = 0x01c,
	74	[ARB_BP_CAP_HI_ADDR] = -1,
	75	[ARB_BP_CAP_ADDR] = 0x220,
	76	[ARB_BP_CAP_STATUS] = 0x230,
	77	[ARB_BP_CAP_MASTER] = 0x234,
d523e0cf DB	78	[ARB_ERR_CAP_CLR] = 0x7f8,
	79	[ARB_ERR_CAP_HI_ADDR] = -1,
	80	[ARB_ERR_CAP_ADDR] = 0x7e0,
	81	[ARB_ERR_CAP_STATUS] = 0x7f0,
	82	[ARB_ERR_CAP_MASTER] = 0x7f4,
	83	};
	84
d1d67868 KC	85	static const int gisb_offsets_bcm7400[] = {
d1d67868 KC	86	[ARB_TIMER] = 0x00c,
fb8a0b80 FF	87	[ARB_BP_CAP_CLR] = 0x014,
	88	[ARB_BP_CAP_HI_ADDR] = -1,
	89	[ARB_BP_CAP_ADDR] = 0x0b8,
	90	[ARB_BP_CAP_STATUS] = 0x0c0,
	91	[ARB_BP_CAP_MASTER] = 0x0c4,
d1d67868 KC	92	[ARB_ERR_CAP_CLR] = 0x0c8,
	93	[ARB_ERR_CAP_HI_ADDR] = -1,
	94	[ARB_ERR_CAP_ADDR] = 0x0cc,
d1d67868 KC	95	[ARB_ERR_CAP_STATUS] = 0x0d4,
	96	[ARB_ERR_CAP_MASTER] = 0x0d8,
	97	};
	98
	99	static const int gisb_offsets_bcm7435[] = {
	100	[ARB_TIMER] = 0x00c,
fb8a0b80 FF	101	[ARB_BP_CAP_CLR] = 0x014,
	102	[ARB_BP_CAP_HI_ADDR] = -1,
	103	[ARB_BP_CAP_ADDR] = 0x158,
	104	[ARB_BP_CAP_STATUS] = 0x160,
	105	[ARB_BP_CAP_MASTER] = 0x164,
d1d67868 KC	106	[ARB_ERR_CAP_CLR] = 0x168,
	107	[ARB_ERR_CAP_HI_ADDR] = -1,
	108	[ARB_ERR_CAP_ADDR] = 0x16c,
d1d67868 KC	109	[ARB_ERR_CAP_STATUS] = 0x174,
	110	[ARB_ERR_CAP_MASTER] = 0x178,
	111	};
	112
f8083587 KC	113	static const int gisb_offsets_bcm7445[] = {
f8083587 KC	114	[ARB_TIMER] = 0x008,
fb8a0b80 FF	115	[ARB_BP_CAP_CLR] = 0x010,
	116	[ARB_BP_CAP_HI_ADDR] = -1,
	117	[ARB_BP_CAP_ADDR] = 0x1d8,
	118	[ARB_BP_CAP_STATUS] = 0x1e0,
	119	[ARB_BP_CAP_MASTER] = 0x1e4,
f8083587 KC	120	[ARB_ERR_CAP_CLR] = 0x7e4,
	121	[ARB_ERR_CAP_HI_ADDR] = 0x7e8,
	122	[ARB_ERR_CAP_ADDR] = 0x7ec,
f8083587 KC	123	[ARB_ERR_CAP_STATUS] = 0x7f4,
	124	[ARB_ERR_CAP_MASTER] = 0x7f8,
	125	};
44127b77 FF	126
	127	struct brcmstb_gisb_arb_device {
	128	void __iomem *base;
f8083587	129	const int *gisb_offsets;
fbf4e262	130	bool big_endian;
44127b77 FF	131	struct mutex lock;
	132	struct list_head next;
	133	u32 valid_mask;
	134	const char master_names[sizeof(u32) BITS_PER_BYTE];
203bb85e	135	u32 saved_timeout;
44127b77 FF	136	};
	137
	138	static LIST_HEAD(brcmstb_gisb_arb_device_list);
	139
2b53eadc KC	140	static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg)
2b53eadc KC	141	{
f8083587 KC	142	int offset = gdev->gisb_offsets[reg];
f8083587 KC	143
0c2aa0e4 DB	144	if (offset < 0) {
	145	/* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */
	146	if (reg == ARB_ERR_CAP_MASTER)
	147	return 1;
	148	else
	149	return 0;
	150	}
f8083587	151
fbf4e262 KC	152	if (gdev->big_endian)
	153	return ioread32be(gdev->base + offset);
	154	else
	155	return ioread32(gdev->base + offset);
2b53eadc KC	156	}
2b53eadc KC	157
0c2aa0e4 DB	158	static u64 gisb_read_address(struct brcmstb_gisb_arb_device *gdev)
	159	{
	160	u64 value;
	161
	162	value = gisb_read(gdev, ARB_ERR_CAP_ADDR);
	163	value \|= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32;
	164
	165	return value;
	166	}
	167
fb8a0b80 FF	168	static u64 gisb_read_bp_address(struct brcmstb_gisb_arb_device *gdev)
	169	{
	170	u64 value;
	171
	172	value = gisb_read(gdev, ARB_BP_CAP_ADDR);
	173	value \|= (u64)gisb_read(gdev, ARB_BP_CAP_HI_ADDR) << 32;
	174
	175	return value;
	176	}
	177
2b53eadc KC	178	static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg)
2b53eadc KC	179	{
f8083587 KC	180	int offset = gdev->gisb_offsets[reg];
	181
	182	if (offset == -1)
	183	return;
fbf4e262 KC	184
fbf4e262 KC	185	if (gdev->big_endian)
856c7ccb	186	iowrite32be(val, gdev->base + offset);
fbf4e262	187	else
856c7ccb	188	iowrite32(val, gdev->base + offset);
2b53eadc KC	189	}
2b53eadc KC	190
44127b77 FF	191	static ssize_t gisb_arb_get_timeout(struct device *dev,
	192	struct device_attribute *attr,
	193	char *buf)
	194	{
0810d5cc	195	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
44127b77 FF	196	u32 timeout;
	197
	198	mutex_lock(&gdev->lock);
2b53eadc	199	timeout = gisb_read(gdev, ARB_TIMER);
44127b77 FF	200	mutex_unlock(&gdev->lock);
	201
	202	return sprintf(buf, "%d", timeout);
	203	}
	204
	205	static ssize_t gisb_arb_set_timeout(struct device *dev,
	206	struct device_attribute *attr,
	207	const char *buf, size_t count)
	208	{
0810d5cc	209	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
44127b77 FF	210	int val, ret;
	211
	212	ret = kstrtoint(buf, 10, &val);
	213	if (ret < 0)
	214	return ret;
	215
	216	if (val == 0 \|\| val >= 0xffffffff)
	217	return -EINVAL;
	218
	219	mutex_lock(&gdev->lock);
2b53eadc	220	gisb_write(gdev, val, ARB_TIMER);
44127b77 FF	221	mutex_unlock(&gdev->lock);
	222
	223	return count;
	224	}
	225
	226	static const char *
	227	brcmstb_gisb_master_to_str(struct brcmstb_gisb_arb_device *gdev,
	228	u32 masters)
	229	{
	230	u32 mask = gdev->valid_mask & masters;
	231
	232	if (hweight_long(mask) != 1)
	233	return NULL;
	234
	235	return gdev->master_names[ffs(mask) - 1];
	236	}
	237
	238	static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev,
	239	const char *reason)
	240	{
	241	u32 cap_status;
0c2aa0e4	242	u64 arb_addr;
44127b77 FF	243	u32 master;
	244	const char *m_name;
	245	char m_fmt[11];
	246
2b53eadc	247	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
44127b77 FF	248
	249	/* Invalid captured address, bail out */
	250	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID))
	251	return 1;
	252
	253	/* Read the address and master */
0c2aa0e4	254	arb_addr = gisb_read_address(gdev);
2b53eadc	255	master = gisb_read(gdev, ARB_ERR_CAP_MASTER);
44127b77 FF	256
	257	m_name = brcmstb_gisb_master_to_str(gdev, master);
	258	if (!m_name) {
	259	snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
	260	m_name = m_fmt;
	261	}
	262
c9864df4 FF	263	pr_crit("GISB: %s at 0x%llx [%c %s], core: %s\n",
c9864df4 FF	264	reason, arb_addr,
44127b77 FF	265	cap_status & ARB_ERR_CAP_STATUS_WRITE ? 'W' : 'R',
	266	cap_status & ARB_ERR_CAP_STATUS_TIMEOUT ? "timeout" : "",
	267	m_name);
	268
	269	/* clear the GISB error */
2b53eadc	270	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
44127b77 FF	271
	272	return 0;
	273	}
	274
c400d5eb FF	275	#ifdef CONFIG_MIPS
	276	static int brcmstb_bus_error_handler(struct pt_regs *regs, int is_fixup)
	277	{
	278	int ret = 0;
	279	struct brcmstb_gisb_arb_device *gdev;
	280	u32 cap_status;
	281
	282	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next) {
	283	cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS);
	284
	285	/* Invalid captured address, bail out */
	286	if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) {
	287	is_fixup = 1;
	288	goto out;
	289	}
	290
	291	ret \|= brcmstb_gisb_arb_decode_addr(gdev, "bus error");
	292	}
	293	out:
	294	return is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
	295	}
	296	#endif
	297
44127b77 FF	298	static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id)
	299	{
	300	brcmstb_gisb_arb_decode_addr(dev_id, "timeout");
	301
	302	return IRQ_HANDLED;
	303	}
	304
	305	static irqreturn_t brcmstb_gisb_tea_handler(int irq, void *dev_id)
	306	{
	307	brcmstb_gisb_arb_decode_addr(dev_id, "target abort");
	308
	309	return IRQ_HANDLED;
	310	}
	311
fb8a0b80 FF	312	static irqreturn_t brcmstb_gisb_bp_handler(int irq, void *dev_id)
	313	{
	314	struct brcmstb_gisb_arb_device *gdev = dev_id;
	315	const char *m_name;
	316	u32 bp_status;
	317	u64 arb_addr;
	318	u32 master;
	319	char m_fmt[11];
	320
	321	bp_status = gisb_read(gdev, ARB_BP_CAP_STATUS);
	322
	323	/* Invalid captured address, bail out */
	324	if (!(bp_status & ARB_BP_CAP_STATUS_VALID))
	325	return IRQ_HANDLED;
	326
	327	/* Read the address and master */
	328	arb_addr = gisb_read_bp_address(gdev);
	329	master = gisb_read(gdev, ARB_BP_CAP_MASTER);
	330
	331	m_name = brcmstb_gisb_master_to_str(gdev, master);
	332	if (!m_name) {
	333	snprintf(m_fmt, sizeof(m_fmt), "0x%08x", master);
	334	m_name = m_fmt;
	335	}
	336
	337	pr_crit("GISB: breakpoint at 0x%llx [%c], core: %s\n",
	338	arb_addr, bp_status & ARB_BP_CAP_STATUS_WRITE ? 'W' : 'R',
	339	m_name);
	340
	341	/* clear the GISB error */
	342	gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR);
	343
	344	return IRQ_HANDLED;
	345	}
	346
9eb60880 DB	347	/*
	348	* Dump out gisb errors on die or panic.
	349	*/
	350	static int dump_gisb_error(struct notifier_block *self, unsigned long v,
	351	void *p);
	352
	353	static struct notifier_block gisb_die_notifier = {
	354	.notifier_call = dump_gisb_error,
	355	};
	356
	357	static struct notifier_block gisb_panic_notifier = {
	358	.notifier_call = dump_gisb_error,
	359	};
	360
	361	static int dump_gisb_error(struct notifier_block *self, unsigned long v,
	362	void *p)
	363	{
	364	struct brcmstb_gisb_arb_device *gdev;
	365	const char *reason = "panic";
	366
	367	if (self == &gisb_die_notifier)
	368	reason = "die";
	369
	370	/* iterate over each GISB arb registered handlers */
	371	list_for_each_entry(gdev, &brcmstb_gisb_arb_device_list, next)
	372	brcmstb_gisb_arb_decode_addr(gdev, reason);
	373
	374	return NOTIFY_DONE;
	375	}
	376
44127b77 FF	377	static DEVICE_ATTR(gisb_arb_timeout, S_IWUSR \| S_IRUGO,
	378	gisb_arb_get_timeout, gisb_arb_set_timeout);
	379
	380	static struct attribute *gisb_arb_sysfs_attrs[] = {
	381	&dev_attr_gisb_arb_timeout.attr,
	382	NULL,
	383	};
	384
	385	static struct attribute_group gisb_arb_sysfs_attr_group = {
	386	.attrs = gisb_arb_sysfs_attrs,
	387	};
	388
d1d67868 KC	389	static const struct of_device_id brcmstb_gisb_arb_of_match[] = {
	390	{ .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 },
	391	{ .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 },
	392	{ .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 },
	393	{ .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 },
d523e0cf	394	{ .compatible = "brcm,bcm7278-gisb-arb", .data = gisb_offsets_bcm7278 },
d1d67868 KC	395	{ .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 },
	396	{ },
	397	};
	398
2e8a29a1	399	static int __init brcmstb_gisb_arb_probe(struct platform_device *pdev)
44127b77 FF	400	{
	401	struct device_node *dn = pdev->dev.of_node;
	402	struct brcmstb_gisb_arb_device *gdev;
d1d67868	403	const struct of_device_id *of_id;
44127b77	404	struct resource *r;
fb8a0b80	405	int err, timeout_irq, tea_irq, bp_irq;
44127b77 FF	406	unsigned int num_masters, j = 0;
	407	int i, first, last;
	408
	409	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	410	timeout_irq = platform_get_irq(pdev, 0);
	411	tea_irq = platform_get_irq(pdev, 1);
fb8a0b80	412	bp_irq = platform_get_irq(pdev, 2);
44127b77 FF	413
	414	gdev = devm_kzalloc(&pdev->dev, sizeof(*gdev), GFP_KERNEL);
	415	if (!gdev)
	416	return -ENOMEM;
	417
	418	mutex_init(&gdev->lock);
	419	INIT_LIST_HEAD(&gdev->next);
	420
c9d53c0f JH	421	gdev->base = devm_ioremap_resource(&pdev->dev, r);
	422	if (IS_ERR(gdev->base))
	423	return PTR_ERR(gdev->base);
44127b77	424
d1d67868 KC	425	of_id = of_match_node(brcmstb_gisb_arb_of_match, dn);
	426	if (!of_id) {
	427	pr_err("failed to look up compatible string\n");
	428	return -EINVAL;
	429	}
	430	gdev->gisb_offsets = of_id->data;
fbf4e262	431	gdev->big_endian = of_device_is_big_endian(dn);
f8083587	432
44127b77 FF	433	err = devm_request_irq(&pdev->dev, timeout_irq,
	434	brcmstb_gisb_timeout_handler, 0, pdev->name,
	435	gdev);
	436	if (err < 0)
	437	return err;
	438
	439	err = devm_request_irq(&pdev->dev, tea_irq,
	440	brcmstb_gisb_tea_handler, 0, pdev->name,
	441	gdev);
	442	if (err < 0)
	443	return err;
	444
fb8a0b80 FF	445	/* Interrupt is optional */
	446	if (bp_irq > 0) {
	447	err = devm_request_irq(&pdev->dev, bp_irq,
	448	brcmstb_gisb_bp_handler, 0, pdev->name,
	449	gdev);
	450	if (err < 0)
	451	return err;
	452	}
	453
44127b77 FF	454	/* If we do not have a valid mask, assume all masters are enabled */
	455	if (of_property_read_u32(dn, "brcm,gisb-arb-master-mask",
	456	&gdev->valid_mask))
	457	gdev->valid_mask = 0xffffffff;
	458
	459	/* Proceed with reading the litteral names if we agree on the
	460	* number of masters
	461	*/
	462	num_masters = of_property_count_strings(dn,
	463	"brcm,gisb-arb-master-names");
	464	if (hweight_long(gdev->valid_mask) == num_masters) {
	465	first = ffs(gdev->valid_mask) - 1;
	466	last = fls(gdev->valid_mask) - 1;
	467
	468	for (i = first; i < last; i++) {
	469	if (!(gdev->valid_mask & BIT(i)))
	470	continue;
	471
	472	of_property_read_string_index(dn,
	473	"brcm,gisb-arb-master-names", j,
	474	&gdev->master_names[i]);
	475	j++;
	476	}
	477	}
	478
	479	err = sysfs_create_group(&pdev->dev.kobj, &gisb_arb_sysfs_attr_group);
	480	if (err)
	481	return err;
	482
	483	platform_set_drvdata(pdev, gdev);
	484
	485	list_add_tail(&gdev->next, &brcmstb_gisb_arb_device_list);
	486
c400d5eb	487	#ifdef CONFIG_MIPS
1f761b3e	488	mips_set_be_handler(brcmstb_bus_error_handler);
c400d5eb	489	#endif
f1bee783	490
9eb60880 DB	491	if (list_is_singular(&brcmstb_gisb_arb_device_list)) {
	492	register_die_notifier(&gisb_die_notifier);
	493	atomic_notifier_chain_register(&panic_notifier_list,
	494	&gisb_panic_notifier);
	495	}
	496
3087974a FF	497	dev_info(&pdev->dev, "registered irqs: %d, %d\n",
3087974a FF	498	timeout_irq, tea_irq);
44127b77 FF	499
	500	return 0;
	501	}
	502
203bb85e FF	503	#ifdef CONFIG_PM_SLEEP
	504	static int brcmstb_gisb_arb_suspend(struct device *dev)
	505	{
0810d5cc	506	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
203bb85e	507
71354661	508	gdev->saved_timeout = gisb_read(gdev, ARB_TIMER);
203bb85e FF	509
	510	return 0;
	511	}
	512
	513	/* Make sure we provide the same timeout value that was configured before, and
	514	* do this before the GISB timeout interrupt handler has any chance to run.
	515	*/
	516	static int brcmstb_gisb_arb_resume_noirq(struct device *dev)
	517	{
0810d5cc	518	struct brcmstb_gisb_arb_device *gdev = dev_get_drvdata(dev);
203bb85e	519
71354661	520	gisb_write(gdev, gdev->saved_timeout, ARB_TIMER);
203bb85e FF	521
	522	return 0;
	523	}
	524	#else
	525	#define brcmstb_gisb_arb_suspend NULL
	526	#define brcmstb_gisb_arb_resume_noirq NULL
	527	#endif
	528
	529	static const struct dev_pm_ops brcmstb_gisb_arb_pm_ops = {
	530	.suspend = brcmstb_gisb_arb_suspend,
	531	.resume_noirq = brcmstb_gisb_arb_resume_noirq,
	532	};
	533
44127b77	534	static struct platform_driver brcmstb_gisb_arb_driver = {
44127b77 FF	535	.driver = {
44127b77 FF	536	.name = "brcm-gisb-arb",
44127b77	537	.of_match_table = brcmstb_gisb_arb_of_match,
203bb85e	538	.pm = &brcmstb_gisb_arb_pm_ops,
44127b77 FF	539	},
	540	};
	541
	542	static int __init brcm_gisb_driver_init(void)
	543	{
2e8a29a1 FF	544	return platform_driver_probe(&brcmstb_gisb_arb_driver,
2e8a29a1 FF	545	brcmstb_gisb_arb_probe);
44127b77 FF	546	}
	547
	548	module_init(brcm_gisb_driver_init);
707a4cdf FF	549
	550	MODULE_AUTHOR("Broadcom");
	551	MODULE_DESCRIPTION("Broadcom STB GISB arbiter driver");
	552	MODULE_LICENSE("GPL v2");