Commit | Line | Data |
---|---|---|
b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
26a84b3e KVA |
2 | # |
3 | # Bus Devices | |
4 | # | |
5 | ||
6 | menu "Bus devices" | |
7 | ||
13fbf3c8 | 8 | config ARM_CCI |
47f36e49 OJ |
9 | bool |
10 | ||
f4d58938 SP |
11 | config ARM_CCI_PMU |
12 | bool | |
13 | select ARM_CCI | |
14 | ||
47f36e49 OJ |
15 | config ARM_CCI400_COMMON |
16 | bool | |
17 | select ARM_CCI | |
18 | ||
19 | config ARM_CCI400_PMU | |
20 | bool "ARM CCI400 PMU support" | |
85bbba70 SP |
21 | depends on (ARM && CPU_V7) || ARM64 |
22 | depends on PERF_EVENTS | |
47f36e49 | 23 | select ARM_CCI400_COMMON |
f4d58938 | 24 | select ARM_CCI_PMU |
47f36e49 | 25 | help |
85bbba70 SP |
26 | Support for PMU events monitoring on the ARM CCI-400 (cache coherent |
27 | interconnect). CCI-400 supports counting events related to the | |
28 | connected slave/master interfaces. | |
47f36e49 OJ |
29 | |
30 | config ARM_CCI400_PORT_CTRL | |
31 | bool | |
13fbf3c8 | 32 | depends on ARM && OF && CPU_V7 |
47f36e49 | 33 | select ARM_CCI400_COMMON |
13fbf3c8 | 34 | help |
47f36e49 OJ |
35 | Low level power management driver for CCI400 cache coherent |
36 | interconnect for ARM platforms. | |
13fbf3c8 | 37 | |
3d2e8701 | 38 | config ARM_CCI5xx_PMU |
d7dd5fd7 | 39 | bool "ARM CCI-500/CCI-550 PMU support" |
a95791ef SP |
40 | depends on (ARM && CPU_V7) || ARM64 |
41 | depends on PERF_EVENTS | |
42 | select ARM_CCI_PMU | |
43 | help | |
d7dd5fd7 SP |
44 | Support for PMU events monitoring on the ARM CCI-500/CCI-550 cache |
45 | coherent interconnects. Both of them provide 8 independent event counters, | |
46 | which can count events pertaining to the slave/master interfaces as well | |
a95791ef SP |
47 | as the internal events to the CCI. |
48 | ||
49 | If unsure, say Y | |
50 | ||
13fbf3c8 | 51 | config ARM_CCN |
5420f9fd | 52 | tristate "ARM CCN driver support" |
13fbf3c8 GU |
53 | depends on ARM || ARM64 |
54 | depends on PERF_EVENTS | |
55 | help | |
56 | PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) | |
57 | interconnect. | |
58 | ||
44127b77 FF |
59 | config BRCMSTB_GISB_ARB |
60 | bool "Broadcom STB GISB bus arbiter" | |
8c7aa17a | 61 | depends on ARM || ARM64 || MIPS |
b0ec633c | 62 | default ARCH_BRCMSTB || BMIPS_GENERIC |
44127b77 FF |
63 | help |
64 | Driver for the Broadcom Set Top Box System-on-a-chip internal bus | |
65 | arbiter. This driver provides timeout and target abort error handling | |
66 | and internal bus master decoding. | |
67 | ||
85bf6d4e HS |
68 | config IMX_WEIM |
69 | bool "Freescale EIM DRIVER" | |
70 | depends on ARCH_MXC | |
71 | help | |
3f98b6ba | 72 | Driver for i.MX WEIM controller. |
85bf6d4e HS |
73 | The WEIM(Wireless External Interface Module) works like a bus. |
74 | You can attach many different devices on it, such as NOR, onenand. | |
85bf6d4e | 75 | |
8286ae03 JH |
76 | config MIPS_CDMM |
77 | bool "MIPS Common Device Memory Map (CDMM) Driver" | |
78 | depends on CPU_MIPSR2 | |
79 | help | |
80 | Driver needed for the MIPS Common Device Memory Map bus in MIPS | |
81 | cores. This bus is for per-CPU tightly coupled devices such as the | |
82 | Fast Debug Channel (FDC). | |
83 | ||
84 | For this to work, either your bootloader needs to enable the CDMM | |
85 | region at an unused physical address on the boot CPU, or else your | |
86 | platform code needs to implement mips_cdmm_phys_base() (see | |
87 | asm/cdmm.h). | |
88 | ||
fddddb52 TP |
89 | config MVEBU_MBUS |
90 | bool | |
91 | depends on PLAT_ORION | |
92 | help | |
93 | Driver needed for the MBus configuration on Marvell EBU SoCs | |
94 | (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). | |
95 | ||
0ee7261c SS |
96 | config OMAP_INTERCONNECT |
97 | tristate "OMAP INTERCONNECT DRIVER" | |
98 | depends on ARCH_OMAP2PLUS | |
99 | ||
100 | help | |
101 | Driver to enable OMAP interconnect error handling driver. | |
ed69bdd8 | 102 | |
13fbf3c8 GU |
103 | config OMAP_OCP2SCP |
104 | tristate "OMAP OCP2SCP DRIVER" | |
105 | depends on ARCH_OMAP2PLUS | |
ed69bdd8 | 106 | help |
13fbf3c8 GU |
107 | Driver to enable ocp2scp module which transforms ocp interface |
108 | protocol to scp protocol. In OMAP4, USB PHY is connected via | |
109 | OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via | |
110 | OCP2SCP. | |
3b9334ac | 111 | |
335a1275 LW |
112 | config QCOM_EBI2 |
113 | bool "Qualcomm External Bus Interface 2 (EBI2)" | |
d6db68b2 | 114 | depends on HAS_IOMEM |
5fac7e84 | 115 | depends on ARCH_QCOM || COMPILE_TEST |
c5d8ccfe | 116 | default ARCH_QCOM |
335a1275 LW |
117 | help |
118 | Say y here to enable support for the Qualcomm External Bus | |
119 | Interface 2, which can be used to connect things like NAND Flash, | |
120 | SRAM, ethernet adapters, FPGAs and LCD displays. | |
121 | ||
89d463ea GU |
122 | config SIMPLE_PM_BUS |
123 | bool "Simple Power-Managed Bus Driver" | |
124 | depends on OF && PM | |
a33b0daa | 125 | help |
89d463ea GU |
126 | Driver for transparent busses that don't need a real driver, but |
127 | where the bus controller is part of a PM domain, or under the control | |
128 | of a functional clock, and thus relies on runtime PM for managing | |
129 | this PM domain and/or clock. | |
130 | An example of such a bus controller is the Renesas Bus State | |
131 | Controller (BSC, sometimes called "LBSC within Bus Bridge", or | |
132 | "External Bus Interface") as found on several Renesas ARM SoCs. | |
a33b0daa | 133 | |
d787dcdb CYT |
134 | config SUNXI_RSB |
135 | tristate "Allwinner sunXi Reduced Serial Bus Driver" | |
dc1a37b2 | 136 | default MACH_SUN8I || MACH_SUN9I || ARM64 |
d787dcdb CYT |
137 | depends on ARCH_SUNXI |
138 | select REGMAP | |
139 | help | |
140 | Say y here to enable support for Allwinner's Reduced Serial Bus | |
141 | (RSB) support. This controller is responsible for communicating | |
142 | with various RSB based devices, such as AXP223, AXP8XX PMICs, | |
143 | and AC100/AC200 ICs. | |
144 | ||
46a88534 | 145 | config TEGRA_ACONNECT |
2d301c07 | 146 | tristate "Tegra ACONNECT Bus Driver" |
46a88534 JH |
147 | depends on ARCH_TEGRA_210_SOC |
148 | depends on OF && PM | |
149 | select PM_CLK | |
150 | help | |
151 | Driver for the Tegra ACONNECT bus which is used to interface with | |
152 | the devices inside the Audio Processing Engine (APE) for Tegra210. | |
153 | ||
40eb4776 MK |
154 | config TEGRA_GMI |
155 | tristate "Tegra Generic Memory Interface bus driver" | |
156 | depends on ARCH_TEGRA | |
157 | help | |
158 | Driver for the Tegra Generic Memory Interface bus which can be used | |
159 | to attach devices such as NOR, UART, FPGA and more. | |
160 | ||
4b7f48d3 | 161 | config UNIPHIER_SYSTEM_BUS |
047a555f | 162 | tristate "UniPhier System Bus driver" |
4b7f48d3 MY |
163 | depends on ARCH_UNIPHIER && OF |
164 | default y | |
165 | help | |
166 | Support for UniPhier System Bus, a simple external bus. This is | |
167 | needed to use on-board devices connected to UniPhier SoCs. | |
168 | ||
3b9334ac PM |
169 | config VEXPRESS_CONFIG |
170 | bool "Versatile Express configuration bus" | |
171 | default y if ARCH_VEXPRESS | |
172 | depends on ARM || ARM64 | |
b33cdd28 | 173 | depends on OF |
3b9334ac PM |
174 | select REGMAP |
175 | help | |
176 | Platform configuration infrastructure for the ARM Ltd. | |
177 | Versatile Express. | |
8e7223fc BG |
178 | |
179 | config DA8XX_MSTPRI | |
180 | bool "TI da8xx master peripheral priority driver" | |
181 | depends on ARCH_DAVINCI_DA8XX | |
182 | help | |
183 | Driver for Texas Instruments da8xx master peripheral priority | |
184 | configuration. Allows to adjust the priorities of all master | |
185 | peripherals. | |
186 | ||
26a84b3e | 187 | endmenu |