stmmac: intel: change all EHL/TGL to auto detect phy addr
[linux-2.6-block.git] / drivers / bluetooth / hci_qca.c
CommitLineData
45051539 1// SPDX-License-Identifier: GPL-2.0-only
0ff252c1
BYTK
2/*
3 * Bluetooth Software UART Qualcomm protocol
4 *
5 * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management
6 * protocol extension to H4.
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
fa9ad876 9 * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved.
0ff252c1
BYTK
10 *
11 * Acknowledgements:
12 * This file is based on hci_ll.c, which was...
13 * Written by Ohad Ben-Cohen <ohad@bencohen.org>
14 * which was in turn based on hci_h4.c, which was written
15 * by Maxim Krasnyansky and Marcel Holtmann.
0ff252c1
BYTK
16 */
17
18#include <linux/kernel.h>
05ba533c 19#include <linux/clk.h>
2faa3f15 20#include <linux/completion.h>
0ff252c1 21#include <linux/debugfs.h>
fa9ad876 22#include <linux/delay.h>
d841502c 23#include <linux/devcoredump.h>
fa9ad876 24#include <linux/device.h>
05ba533c
TE
25#include <linux/gpio/consumer.h>
26#include <linux/mod_devicetable.h>
27#include <linux/module.h>
fa9ad876 28#include <linux/of_device.h>
e5d6468f 29#include <linux/acpi.h>
fa9ad876
BG
30#include <linux/platform_device.h>
31#include <linux/regulator/consumer.h>
05ba533c 32#include <linux/serdev.h>
7c2c3e63 33#include <linux/mutex.h>
c614ca3f 34#include <asm/unaligned.h>
0ff252c1
BYTK
35
36#include <net/bluetooth/bluetooth.h>
37#include <net/bluetooth/hci_core.h>
38
39#include "hci_uart.h"
40#include "btqca.h"
41
42/* HCI_IBS protocol messages */
43#define HCI_IBS_SLEEP_IND 0xFE
44#define HCI_IBS_WAKE_IND 0xFD
45#define HCI_IBS_WAKE_ACK 0xFC
f81b001a 46#define HCI_MAX_IBS_SIZE 10
0ff252c1 47
f81b001a 48#define IBS_WAKE_RETRANS_TIMEOUT_MS 100
2d68476c 49#define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200
41d5b25f 50#define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000
94d66714 51#define CMD_TRANS_TIMEOUT_MS 100
d841502c 52#define MEMDUMP_TIMEOUT_MS 8000
0ff252c1 53
05ba533c
TE
54/* susclk rate */
55#define SUSCLK_RATE_32KHZ 32768
56
c614ca3f
BG
57/* Controller debug log header */
58#define QCA_DEBUG_HANDLE 0x2EDC
59
bb2500ab
RL
60/* max retry count when init fails */
61#define MAX_INIT_RETRIES 3
62
d841502c
BG
63/* Controller dump header */
64#define QCA_SSR_DUMP_HANDLE 0x0108
65#define QCA_DUMP_PACKET_SIZE 255
66#define QCA_LAST_SEQUENCE_NUM 0xFFFF
67#define QCA_CRASHBYTE_PACKET_LEN 1096
68#define QCA_MEMDUMP_BYTE 0xFB
69
62a91990
MK
70enum qca_flags {
71 QCA_IBS_ENABLED,
2faa3f15 72 QCA_DROP_VENDOR_EVENT,
41d5b25f 73 QCA_SUSPENDING,
7c2c3e63 74 QCA_MEMDUMP_COLLECTION,
3344537f
VLNG
75 QCA_HW_ERROR_EVENT,
76 QCA_SSR_TRIGGERED
62a91990
MK
77};
78
a228f7a4
APS
79enum qca_capabilities {
80 QCA_CAP_WIDEBAND_SPEECH = BIT(0),
81};
d841502c 82
0ff252c1
BYTK
83/* HCI_IBS transmit side sleep protocol states */
84enum tx_ibs_states {
85 HCI_IBS_TX_ASLEEP,
86 HCI_IBS_TX_WAKING,
87 HCI_IBS_TX_AWAKE,
88};
89
90/* HCI_IBS receive side sleep protocol states */
91enum rx_states {
92 HCI_IBS_RX_ASLEEP,
93 HCI_IBS_RX_AWAKE,
94};
95
96/* HCI_IBS transmit and receive side clock state vote */
97enum hci_ibs_clock_state_vote {
98 HCI_IBS_VOTE_STATS_UPDATE,
99 HCI_IBS_TX_VOTE_CLOCK_ON,
100 HCI_IBS_TX_VOTE_CLOCK_OFF,
101 HCI_IBS_RX_VOTE_CLOCK_ON,
102 HCI_IBS_RX_VOTE_CLOCK_OFF,
103};
104
d841502c
BG
105/* Controller memory dump states */
106enum qca_memdump_states {
107 QCA_MEMDUMP_IDLE,
108 QCA_MEMDUMP_COLLECTING,
109 QCA_MEMDUMP_COLLECTED,
110 QCA_MEMDUMP_TIMEOUT,
111};
112
113struct qca_memdump_data {
114 char *memdump_buf_head;
115 char *memdump_buf_tail;
116 u32 current_seq_no;
117 u32 received_dump;
e5aeebdd 118 u32 ram_dump_size;
d841502c
BG
119};
120
121struct qca_memdump_event_hdr {
122 __u8 evt;
123 __u8 plen;
124 __u16 opcode;
125 __u16 seq_no;
126 __u8 reserved;
127} __packed;
128
129
130struct qca_dump_size {
131 u32 dump_size;
132} __packed;
133
0ff252c1
BYTK
134struct qca_data {
135 struct hci_uart *hu;
136 struct sk_buff *rx_skb;
137 struct sk_buff_head txq;
138 struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */
d841502c 139 struct sk_buff_head rx_memdump_q; /* Memdump wait queue */
0ff252c1
BYTK
140 spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
141 u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
142 u8 rx_ibs_state; /* HCI_IBS receive side power state */
621a5f7a
VK
143 bool tx_vote; /* Clock must be on for TX */
144 bool rx_vote; /* Clock must be on for RX */
0ff252c1
BYTK
145 struct timer_list tx_idle_timer;
146 u32 tx_idle_delay;
147 struct timer_list wake_retrans_timer;
148 u32 wake_retrans;
149 struct workqueue_struct *workqueue;
150 struct work_struct ws_awake_rx;
151 struct work_struct ws_awake_device;
152 struct work_struct ws_rx_vote_off;
153 struct work_struct ws_tx_vote_off;
d841502c 154 struct work_struct ctrl_memdump_evt;
7c2c3e63 155 struct delayed_work ctrl_memdump_timeout;
d841502c 156 struct qca_memdump_data *qca_memdump;
0ff252c1 157 unsigned long flags;
2faa3f15 158 struct completion drop_ev_comp;
41d5b25f 159 wait_queue_head_t suspend_wait_q;
d841502c 160 enum qca_memdump_states memdump_state;
7c2c3e63 161 struct mutex hci_memdump_lock;
0ff252c1
BYTK
162
163 /* For debugging purpose */
164 u64 ibs_sent_wacks;
165 u64 ibs_sent_slps;
166 u64 ibs_sent_wakes;
167 u64 ibs_recv_wacks;
168 u64 ibs_recv_slps;
169 u64 ibs_recv_wakes;
170 u64 vote_last_jif;
171 u32 vote_on_ms;
172 u32 vote_off_ms;
173 u64 tx_votes_on;
174 u64 rx_votes_on;
175 u64 tx_votes_off;
176 u64 rx_votes_off;
177 u64 votes_on;
178 u64 votes_off;
179};
180
83d9c5e5
BG
181enum qca_speed_type {
182 QCA_INIT_SPEED = 1,
183 QCA_OPER_SPEED
184};
185
fa9ad876
BG
186/*
187 * Voltage regulator information required for configuring the
188 * QCA Bluetooth chipset
189 */
190struct qca_vreg {
191 const char *name;
fa9ad876
BG
192 unsigned int load_uA;
193};
194
a228f7a4 195struct qca_device_data {
fa9ad876
BG
196 enum qca_btsoc_type soc_type;
197 struct qca_vreg *vregs;
198 size_t num_vregs;
a228f7a4 199 uint32_t capabilities;
fa9ad876
BG
200};
201
202/*
203 * Platform data for the QCA Bluetooth power driver.
204 */
205struct qca_power {
206 struct device *dev;
fa9ad876 207 struct regulator_bulk_data *vreg_bulk;
163d42fa 208 int num_vregs;
fa9ad876
BG
209 bool vregs_on;
210};
211
05ba533c
TE
212struct qca_serdev {
213 struct hci_uart serdev_hu;
214 struct gpio_desc *bt_en;
215 struct clk *susclk;
fa9ad876
BG
216 enum qca_btsoc_type btsoc_type;
217 struct qca_power *bt_power;
218 u32 init_speed;
219 u32 oper_speed;
99c905c6 220 const char *firmware_name;
05ba533c
TE
221};
222
a9314e76
BA
223static int qca_regulator_enable(struct qca_serdev *qcadev);
224static void qca_regulator_disable(struct qca_serdev *qcadev);
c2d78273 225static void qca_power_shutdown(struct hci_uart *hu);
3e4be65e 226static int qca_power_off(struct hci_dev *hdev);
d841502c 227static void qca_controller_memdump(struct work_struct *work);
fa9ad876 228
4fdd5a4f
MK
229static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu)
230{
231 enum qca_btsoc_type soc_type;
232
233 if (hu->serdev) {
234 struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
235
236 soc_type = qsd->btsoc_type;
237 } else {
238 soc_type = QCA_ROME;
239 }
240
241 return soc_type;
242}
243
99c905c6
RL
244static const char *qca_get_firmware_name(struct hci_uart *hu)
245{
246 if (hu->serdev) {
247 struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
248
249 return qsd->firmware_name;
250 } else {
251 return NULL;
252 }
253}
254
0ff252c1
BYTK
255static void __serial_clock_on(struct tty_struct *tty)
256{
257 /* TODO: Some chipset requires to enable UART clock on client
258 * side to save power consumption or manual work is required.
259 * Please put your code to control UART clock here if needed
260 */
261}
262
263static void __serial_clock_off(struct tty_struct *tty)
264{
265 /* TODO: Some chipset requires to disable UART clock on client
266 * side to save power consumption or manual work is required.
267 * Please put your code to control UART clock off here if needed
268 */
269}
270
271/* serial_clock_vote needs to be called with the ibs lock held */
272static void serial_clock_vote(unsigned long vote, struct hci_uart *hu)
273{
274 struct qca_data *qca = hu->priv;
275 unsigned int diff;
276
277 bool old_vote = (qca->tx_vote | qca->rx_vote);
278 bool new_vote;
279
280 switch (vote) {
281 case HCI_IBS_VOTE_STATS_UPDATE:
282 diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
283
284 if (old_vote)
285 qca->vote_off_ms += diff;
286 else
287 qca->vote_on_ms += diff;
288 return;
289
290 case HCI_IBS_TX_VOTE_CLOCK_ON:
291 qca->tx_vote = true;
292 qca->tx_votes_on++;
0ff252c1
BYTK
293 break;
294
295 case HCI_IBS_RX_VOTE_CLOCK_ON:
296 qca->rx_vote = true;
297 qca->rx_votes_on++;
0ff252c1
BYTK
298 break;
299
300 case HCI_IBS_TX_VOTE_CLOCK_OFF:
301 qca->tx_vote = false;
302 qca->tx_votes_off++;
0ff252c1
BYTK
303 break;
304
305 case HCI_IBS_RX_VOTE_CLOCK_OFF:
306 qca->rx_vote = false;
307 qca->rx_votes_off++;
0ff252c1
BYTK
308 break;
309
310 default:
311 BT_ERR("Voting irregularity");
312 return;
313 }
314
7310dd3f
MK
315 new_vote = qca->rx_vote | qca->tx_vote;
316
0ff252c1
BYTK
317 if (new_vote != old_vote) {
318 if (new_vote)
319 __serial_clock_on(hu->tty);
320 else
321 __serial_clock_off(hu->tty);
322
ce26d813
PK
323 BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false",
324 vote ? "true" : "false");
0ff252c1
BYTK
325
326 diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
327
328 if (new_vote) {
329 qca->votes_on++;
330 qca->vote_off_ms += diff;
331 } else {
332 qca->votes_off++;
333 qca->vote_on_ms += diff;
334 }
335 qca->vote_last_jif = jiffies;
336 }
337}
338
339/* Builds and sends an HCI_IBS command packet.
340 * These are very simple packets with only 1 cmd byte.
341 */
342static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu)
343{
344 int err = 0;
345 struct sk_buff *skb = NULL;
346 struct qca_data *qca = hu->priv;
347
348 BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd);
349
350 skb = bt_skb_alloc(1, GFP_ATOMIC);
351 if (!skb) {
352 BT_ERR("Failed to allocate memory for HCI_IBS packet");
353 return -ENOMEM;
354 }
355
356 /* Assign HCI_IBS type */
634fef61 357 skb_put_u8(skb, cmd);
0ff252c1
BYTK
358
359 skb_queue_tail(&qca->txq, skb);
360
361 return err;
362}
363
364static void qca_wq_awake_device(struct work_struct *work)
365{
366 struct qca_data *qca = container_of(work, struct qca_data,
367 ws_awake_device);
368 struct hci_uart *hu = qca->hu;
369 unsigned long retrans_delay;
31fb1bbd 370 unsigned long flags;
0ff252c1
BYTK
371
372 BT_DBG("hu %p wq awake device", hu);
373
374 /* Vote for serial clock */
375 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu);
376
31fb1bbd 377 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
378
379 /* Send wake indication to device */
380 if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0)
381 BT_ERR("Failed to send WAKE to device");
382
383 qca->ibs_sent_wakes++;
384
385 /* Start retransmit timer */
386 retrans_delay = msecs_to_jiffies(qca->wake_retrans);
387 mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
388
31fb1bbd 389 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
390
391 /* Actually send the packets */
392 hci_uart_tx_wakeup(hu);
393}
394
395static void qca_wq_awake_rx(struct work_struct *work)
396{
397 struct qca_data *qca = container_of(work, struct qca_data,
398 ws_awake_rx);
399 struct hci_uart *hu = qca->hu;
31fb1bbd 400 unsigned long flags;
0ff252c1
BYTK
401
402 BT_DBG("hu %p wq awake rx", hu);
403
404 serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu);
405
31fb1bbd 406 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
407 qca->rx_ibs_state = HCI_IBS_RX_AWAKE;
408
409 /* Always acknowledge device wake up,
410 * sending IBS message doesn't count as TX ON.
411 */
412 if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0)
413 BT_ERR("Failed to acknowledge device wake up");
414
415 qca->ibs_sent_wacks++;
416
31fb1bbd 417 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
418
419 /* Actually send the packets */
420 hci_uart_tx_wakeup(hu);
421}
422
423static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work)
424{
425 struct qca_data *qca = container_of(work, struct qca_data,
426 ws_rx_vote_off);
427 struct hci_uart *hu = qca->hu;
428
429 BT_DBG("hu %p rx clock vote off", hu);
430
431 serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu);
432}
433
434static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work)
435{
436 struct qca_data *qca = container_of(work, struct qca_data,
437 ws_tx_vote_off);
438 struct hci_uart *hu = qca->hu;
439
440 BT_DBG("hu %p tx clock vote off", hu);
441
442 /* Run HCI tx handling unlocked */
443 hci_uart_tx_wakeup(hu);
444
445 /* Now that message queued to tty driver, vote for tty clocks off.
446 * It is up to the tty driver to pend the clocks off until tx done.
447 */
448 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
449}
450
04356052 451static void hci_ibs_tx_idle_timeout(struct timer_list *t)
0ff252c1 452{
04356052
KC
453 struct qca_data *qca = from_timer(qca, t, tx_idle_timer);
454 struct hci_uart *hu = qca->hu;
0ff252c1
BYTK
455 unsigned long flags;
456
457 BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
458
459 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
460 flags, SINGLE_DEPTH_NESTING);
461
462 switch (qca->tx_ibs_state) {
463 case HCI_IBS_TX_AWAKE:
464 /* TX_IDLE, go to SLEEP */
465 if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) {
466 BT_ERR("Failed to send SLEEP to device");
467 break;
468 }
469 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
470 qca->ibs_sent_slps++;
471 queue_work(qca->workqueue, &qca->ws_tx_vote_off);
472 break;
473
474 case HCI_IBS_TX_ASLEEP:
475 case HCI_IBS_TX_WAKING:
0ff252c1 476 default:
e059a465 477 BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
0ff252c1
BYTK
478 break;
479 }
480
481 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
482}
483
04356052 484static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
0ff252c1 485{
04356052
KC
486 struct qca_data *qca = from_timer(qca, t, wake_retrans_timer);
487 struct hci_uart *hu = qca->hu;
0ff252c1 488 unsigned long flags, retrans_delay;
a9137188 489 bool retransmit = false;
0ff252c1
BYTK
490
491 BT_DBG("hu %p wake retransmit timeout in %d state",
492 hu, qca->tx_ibs_state);
493
494 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
495 flags, SINGLE_DEPTH_NESTING);
496
41d5b25f
CC
497 /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */
498 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
499 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
500 return;
501 }
502
0ff252c1
BYTK
503 switch (qca->tx_ibs_state) {
504 case HCI_IBS_TX_WAKING:
505 /* No WAKE_ACK, retransmit WAKE */
a9137188 506 retransmit = true;
0ff252c1
BYTK
507 if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) {
508 BT_ERR("Failed to acknowledge device wake up");
509 break;
510 }
511 qca->ibs_sent_wakes++;
512 retrans_delay = msecs_to_jiffies(qca->wake_retrans);
513 mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
514 break;
515
516 case HCI_IBS_TX_ASLEEP:
517 case HCI_IBS_TX_AWAKE:
0ff252c1 518 default:
e059a465 519 BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
0ff252c1
BYTK
520 break;
521 }
522
523 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
524
525 if (retransmit)
526 hci_uart_tx_wakeup(hu);
527}
528
7c2c3e63
VLNG
529
530static void qca_controller_memdump_timeout(struct work_struct *work)
d841502c 531{
7c2c3e63
VLNG
532 struct qca_data *qca = container_of(work, struct qca_data,
533 ctrl_memdump_timeout.work);
d841502c 534 struct hci_uart *hu = qca->hu;
7c2c3e63
VLNG
535
536 mutex_lock(&qca->hci_memdump_lock);
537 if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
538 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
539 if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
540 /* Inject hw error event to reset the device
541 * and driver.
542 */
543 hci_reset_dev(hu->hdev);
544 }
545 }
546
547 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
548}
549
7c2c3e63 550
0ff252c1
BYTK
551/* Initialize protocol */
552static int qca_open(struct hci_uart *hu)
553{
05ba533c 554 struct qca_serdev *qcadev;
0ff252c1
BYTK
555 struct qca_data *qca;
556
557 BT_DBG("hu %p qca_open", hu);
558
b36a1552
VD
559 if (!hci_uart_has_flow_control(hu))
560 return -EOPNOTSUPP;
561
25a13e38 562 qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL);
0ff252c1
BYTK
563 if (!qca)
564 return -ENOMEM;
565
566 skb_queue_head_init(&qca->txq);
567 skb_queue_head_init(&qca->tx_wait_q);
d841502c 568 skb_queue_head_init(&qca->rx_memdump_q);
0ff252c1 569 spin_lock_init(&qca->hci_ibs_lock);
7c2c3e63 570 mutex_init(&qca->hci_memdump_lock);
fac9a602 571 qca->workqueue = alloc_ordered_workqueue("qca_wq", 0);
0ff252c1
BYTK
572 if (!qca->workqueue) {
573 BT_ERR("QCA Workqueue not initialized properly");
574 kfree(qca);
575 return -ENOMEM;
576 }
577
578 INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx);
579 INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device);
580 INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off);
581 INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off);
d841502c 582 INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump);
7c2c3e63
VLNG
583 INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout,
584 qca_controller_memdump_timeout);
41d5b25f
CC
585 init_waitqueue_head(&qca->suspend_wait_q);
586
0ff252c1 587 qca->hu = hu;
2faa3f15 588 init_completion(&qca->drop_ev_comp);
0ff252c1
BYTK
589
590 /* Assume we start with both sides asleep -- extra wakes OK */
591 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
592 qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
593
0ff252c1 594 qca->vote_last_jif = jiffies;
0ff252c1
BYTK
595
596 hu->priv = qca;
597
05ba533c 598 if (hu->serdev) {
05ba533c 599 qcadev = serdev_device_get_drvdata(hu->serdev);
37aee136
CH
600
601 if (qca_is_wcn399x(qcadev->btsoc_type))
fa9ad876 602 hu->init_speed = qcadev->init_speed;
37aee136
CH
603
604 if (qcadev->oper_speed)
fa9ad876 605 hu->oper_speed = qcadev->oper_speed;
05ba533c
TE
606 }
607
fa9ad876
BG
608 timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
609 qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
610
611 timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
41d5b25f 612 qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS;
fa9ad876 613
0ff252c1
BYTK
614 BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u",
615 qca->tx_idle_delay, qca->wake_retrans);
616
617 return 0;
618}
619
620static void qca_debugfs_init(struct hci_dev *hdev)
621{
622 struct hci_uart *hu = hci_get_drvdata(hdev);
623 struct qca_data *qca = hu->priv;
624 struct dentry *ibs_dir;
625 umode_t mode;
626
627 if (!hdev->debugfs)
628 return;
629
630 ibs_dir = debugfs_create_dir("ibs", hdev->debugfs);
631
632 /* read only */
633 mode = S_IRUGO;
634 debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state);
635 debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state);
636 debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir,
637 &qca->ibs_sent_slps);
638 debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir,
639 &qca->ibs_sent_wakes);
640 debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir,
641 &qca->ibs_sent_wacks);
642 debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir,
643 &qca->ibs_recv_slps);
644 debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir,
645 &qca->ibs_recv_wakes);
646 debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir,
647 &qca->ibs_recv_wacks);
10be6c0f 648 debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote);
0ff252c1
BYTK
649 debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on);
650 debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off);
10be6c0f 651 debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote);
0ff252c1
BYTK
652 debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on);
653 debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off);
654 debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on);
655 debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off);
656 debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms);
657 debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms);
658
659 /* read/write */
660 mode = S_IRUGO | S_IWUSR;
661 debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans);
662 debugfs_create_u32("tx_idle_delay", mode, ibs_dir,
663 &qca->tx_idle_delay);
664}
665
666/* Flush protocol data */
667static int qca_flush(struct hci_uart *hu)
668{
669 struct qca_data *qca = hu->priv;
670
671 BT_DBG("hu %p qca flush", hu);
672
673 skb_queue_purge(&qca->tx_wait_q);
674 skb_queue_purge(&qca->txq);
675
676 return 0;
677}
678
679/* Close protocol */
680static int qca_close(struct hci_uart *hu)
681{
682 struct qca_data *qca = hu->priv;
683
684 BT_DBG("hu %p qca close", hu);
685
686 serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu);
687
688 skb_queue_purge(&qca->tx_wait_q);
689 skb_queue_purge(&qca->txq);
d841502c 690 skb_queue_purge(&qca->rx_memdump_q);
0ff252c1
BYTK
691 del_timer(&qca->tx_idle_timer);
692 del_timer(&qca->wake_retrans_timer);
693 destroy_workqueue(qca->workqueue);
694 qca->hu = NULL;
695
696 kfree_skb(qca->rx_skb);
697
698 hu->priv = NULL;
699
700 kfree(qca);
701
702 return 0;
703}
704
705/* Called upon a wake-up-indication from the device.
706 */
707static void device_want_to_wakeup(struct hci_uart *hu)
708{
709 unsigned long flags;
710 struct qca_data *qca = hu->priv;
711
712 BT_DBG("hu %p want to wake up", hu);
713
714 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
715
716 qca->ibs_recv_wakes++;
717
41d5b25f
CC
718 /* Don't wake the rx up when suspending. */
719 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
720 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
721 return;
722 }
723
0ff252c1
BYTK
724 switch (qca->rx_ibs_state) {
725 case HCI_IBS_RX_ASLEEP:
726 /* Make sure clock is on - we may have turned clock off since
727 * receiving the wake up indicator awake rx clock.
728 */
729 queue_work(qca->workqueue, &qca->ws_awake_rx);
730 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
731 return;
732
733 case HCI_IBS_RX_AWAKE:
734 /* Always acknowledge device wake up,
735 * sending IBS message doesn't count as TX ON.
736 */
737 if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) {
738 BT_ERR("Failed to acknowledge device wake up");
739 break;
740 }
741 qca->ibs_sent_wacks++;
742 break;
743
744 default:
745 /* Any other state is illegal */
746 BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d",
747 qca->rx_ibs_state);
748 break;
749 }
750
751 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
752
753 /* Actually send the packets */
754 hci_uart_tx_wakeup(hu);
755}
756
757/* Called upon a sleep-indication from the device.
758 */
759static void device_want_to_sleep(struct hci_uart *hu)
760{
761 unsigned long flags;
762 struct qca_data *qca = hu->priv;
763
6600c080 764 BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state);
0ff252c1
BYTK
765
766 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
767
768 qca->ibs_recv_slps++;
769
770 switch (qca->rx_ibs_state) {
771 case HCI_IBS_RX_AWAKE:
772 /* Update state */
773 qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
774 /* Vote off rx clock under workqueue */
775 queue_work(qca->workqueue, &qca->ws_rx_vote_off);
776 break;
777
778 case HCI_IBS_RX_ASLEEP:
6600c080 779 break;
0ff252c1
BYTK
780
781 default:
782 /* Any other state is illegal */
783 BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d",
784 qca->rx_ibs_state);
785 break;
786 }
787
41d5b25f
CC
788 wake_up_interruptible(&qca->suspend_wait_q);
789
0ff252c1
BYTK
790 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
791}
792
793/* Called upon wake-up-acknowledgement from the device
794 */
795static void device_woke_up(struct hci_uart *hu)
796{
797 unsigned long flags, idle_delay;
798 struct qca_data *qca = hu->priv;
799 struct sk_buff *skb = NULL;
800
801 BT_DBG("hu %p woke up", hu);
802
803 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
804
805 qca->ibs_recv_wacks++;
806
41d5b25f
CC
807 /* Don't react to the wake-up-acknowledgment when suspending. */
808 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
809 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
810 return;
811 }
812
0ff252c1
BYTK
813 switch (qca->tx_ibs_state) {
814 case HCI_IBS_TX_AWAKE:
815 /* Expect one if we send 2 WAKEs */
816 BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d",
817 qca->tx_ibs_state);
818 break;
819
820 case HCI_IBS_TX_WAKING:
821 /* Send pending packets */
822 while ((skb = skb_dequeue(&qca->tx_wait_q)))
823 skb_queue_tail(&qca->txq, skb);
824
825 /* Switch timers and change state to HCI_IBS_TX_AWAKE */
826 del_timer(&qca->wake_retrans_timer);
827 idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
828 mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
829 qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
830 break;
831
832 case HCI_IBS_TX_ASLEEP:
0ff252c1
BYTK
833 default:
834 BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d",
835 qca->tx_ibs_state);
836 break;
837 }
838
839 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
840
841 /* Actually send the packets */
842 hci_uart_tx_wakeup(hu);
843}
844
845/* Enqueue frame for transmittion (padding, crc, etc) may be called from
846 * two simultaneous tasklets.
847 */
848static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb)
849{
850 unsigned long flags = 0, idle_delay;
851 struct qca_data *qca = hu->priv;
852
853 BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb,
854 qca->tx_ibs_state);
855
3344537f
VLNG
856 if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
857 /* As SSR is in progress, ignore the packets */
858 bt_dev_dbg(hu->hdev, "SSR is in progress");
859 kfree_skb(skb);
860 return 0;
861 }
862
0ff252c1 863 /* Prepend skb with frame type */
618e8bc2 864 memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
0ff252c1 865
035a960e
BG
866 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
867
0ff252c1
BYTK
868 /* Don't go to sleep in middle of patch download or
869 * Out-Of-Band(GPIOs control) sleep is selected.
41d5b25f 870 * Don't wake the device up when suspending.
0ff252c1 871 */
41d5b25f
CC
872 if (!test_bit(QCA_IBS_ENABLED, &qca->flags) ||
873 test_bit(QCA_SUSPENDING, &qca->flags)) {
0ff252c1 874 skb_queue_tail(&qca->txq, skb);
035a960e 875 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
876 return 0;
877 }
878
0ff252c1
BYTK
879 /* Act according to current state */
880 switch (qca->tx_ibs_state) {
881 case HCI_IBS_TX_AWAKE:
882 BT_DBG("Device awake, sending normally");
883 skb_queue_tail(&qca->txq, skb);
884 idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
885 mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
886 break;
887
888 case HCI_IBS_TX_ASLEEP:
889 BT_DBG("Device asleep, waking up and queueing packet");
890 /* Save packet for later */
891 skb_queue_tail(&qca->tx_wait_q, skb);
892
893 qca->tx_ibs_state = HCI_IBS_TX_WAKING;
894 /* Schedule a work queue to wake up device */
895 queue_work(qca->workqueue, &qca->ws_awake_device);
896 break;
897
898 case HCI_IBS_TX_WAKING:
899 BT_DBG("Device waking up, queueing packet");
900 /* Transient state; just keep packet for later */
901 skb_queue_tail(&qca->tx_wait_q, skb);
902 break;
903
904 default:
905 BT_ERR("Illegal tx state: %d (losing packet)",
906 qca->tx_ibs_state);
907 kfree_skb(skb);
908 break;
909 }
910
911 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
912
913 return 0;
914}
915
916static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb)
917{
918 struct hci_uart *hu = hci_get_drvdata(hdev);
919
920 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND);
921
922 device_want_to_sleep(hu);
923
924 kfree_skb(skb);
925 return 0;
926}
927
928static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb)
929{
930 struct hci_uart *hu = hci_get_drvdata(hdev);
931
932 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND);
933
934 device_want_to_wakeup(hu);
935
936 kfree_skb(skb);
937 return 0;
938}
939
940static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb)
941{
942 struct hci_uart *hu = hci_get_drvdata(hdev);
943
944 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK);
945
946 device_woke_up(hu);
947
948 kfree_skb(skb);
949 return 0;
950}
951
c614ca3f
BG
952static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb)
953{
954 /* We receive debug logs from chip as an ACL packets.
955 * Instead of sending the data to ACL to decode the
956 * received data, we are pushing them to the above layers
957 * as a diagnostic packet.
958 */
959 if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE)
960 return hci_recv_diag(hdev, skb);
961
962 return hci_recv_frame(hdev, skb);
963}
964
d841502c
BG
965static void qca_controller_memdump(struct work_struct *work)
966{
967 struct qca_data *qca = container_of(work, struct qca_data,
968 ctrl_memdump_evt);
969 struct hci_uart *hu = qca->hu;
970 struct sk_buff *skb;
971 struct qca_memdump_event_hdr *cmd_hdr;
972 struct qca_memdump_data *qca_memdump = qca->qca_memdump;
973 struct qca_dump_size *dump;
974 char *memdump_buf;
975 char nullBuff[QCA_DUMP_PACKET_SIZE] = { 0 };
56b084ed 976 u16 seq_no;
d841502c 977 u32 dump_size;
e5aeebdd
ZH
978 u32 rx_size;
979 enum qca_btsoc_type soc_type = qca_soc_type(hu);
d841502c
BG
980
981 while ((skb = skb_dequeue(&qca->rx_memdump_q))) {
982
7c2c3e63 983 mutex_lock(&qca->hci_memdump_lock);
f98aa80f
VLNG
984 /* Skip processing the received packets if timeout detected
985 * or memdump collection completed.
986 */
987 if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
988 qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
7c2c3e63
VLNG
989 mutex_unlock(&qca->hci_memdump_lock);
990 return;
991 }
992
d841502c
BG
993 if (!qca_memdump) {
994 qca_memdump = kzalloc(sizeof(struct qca_memdump_data),
995 GFP_ATOMIC);
7c2c3e63
VLNG
996 if (!qca_memdump) {
997 mutex_unlock(&qca->hci_memdump_lock);
d841502c 998 return;
7c2c3e63 999 }
d841502c
BG
1000
1001 qca->qca_memdump = qca_memdump;
1002 }
1003
1004 qca->memdump_state = QCA_MEMDUMP_COLLECTING;
1005 cmd_hdr = (void *) skb->data;
d841502c
BG
1006 seq_no = __le16_to_cpu(cmd_hdr->seq_no);
1007 skb_pull(skb, sizeof(struct qca_memdump_event_hdr));
1008
1009 if (!seq_no) {
1010
1011 /* This is the first frame of memdump packet from
1012 * the controller, Disable IBS to recevie dump
1013 * with out any interruption, ideally time required for
1014 * the controller to send the dump is 8 seconds. let us
1015 * start timer to handle this asynchronous activity.
1016 */
1017 clear_bit(QCA_IBS_ENABLED, &qca->flags);
1018 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1019 dump = (void *) skb->data;
1020 dump_size = __le32_to_cpu(dump->dump_size);
1021 if (!(dump_size)) {
1022 bt_dev_err(hu->hdev, "Rx invalid memdump size");
1023 kfree_skb(skb);
7c2c3e63 1024 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1025 return;
1026 }
1027
1028 bt_dev_info(hu->hdev, "QCA collecting dump of size:%u",
1029 dump_size);
7c2c3e63
VLNG
1030 queue_delayed_work(qca->workqueue,
1031 &qca->ctrl_memdump_timeout,
e5aeebdd
ZH
1032 msecs_to_jiffies(MEMDUMP_TIMEOUT_MS)
1033 );
d841502c
BG
1034
1035 skb_pull(skb, sizeof(dump_size));
1036 memdump_buf = vmalloc(dump_size);
e5aeebdd 1037 qca_memdump->ram_dump_size = dump_size;
d841502c
BG
1038 qca_memdump->memdump_buf_head = memdump_buf;
1039 qca_memdump->memdump_buf_tail = memdump_buf;
1040 }
1041
1042 memdump_buf = qca_memdump->memdump_buf_tail;
1043
1044 /* If sequence no 0 is missed then there is no point in
1045 * accepting the other sequences.
1046 */
1047 if (!memdump_buf) {
1048 bt_dev_err(hu->hdev, "QCA: Discarding other packets");
1049 kfree(qca_memdump);
1050 kfree_skb(skb);
1051 qca->qca_memdump = NULL;
7c2c3e63 1052 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1053 return;
1054 }
1055
1056 /* There could be chance of missing some packets from
1057 * the controller. In such cases let us store the dummy
1058 * packets in the buffer.
1059 */
e5aeebdd
ZH
1060 /* For QCA6390, controller does not lost packets but
1061 * sequence number field of packat sometimes has error
1062 * bits, so skip this checking for missing packet.
1063 */
d841502c 1064 while ((seq_no > qca_memdump->current_seq_no + 1) &&
e5aeebdd
ZH
1065 (soc_type != QCA_QCA6390) &&
1066 seq_no != QCA_LAST_SEQUENCE_NUM) {
d841502c
BG
1067 bt_dev_err(hu->hdev, "QCA controller missed packet:%d",
1068 qca_memdump->current_seq_no);
e5aeebdd
ZH
1069 rx_size = qca_memdump->received_dump;
1070 rx_size += QCA_DUMP_PACKET_SIZE;
1071 if (rx_size > qca_memdump->ram_dump_size) {
1072 bt_dev_err(hu->hdev,
1073 "QCA memdump received %d, no space for missed packet",
1074 qca_memdump->received_dump);
1075 break;
1076 }
d841502c
BG
1077 memcpy(memdump_buf, nullBuff, QCA_DUMP_PACKET_SIZE);
1078 memdump_buf = memdump_buf + QCA_DUMP_PACKET_SIZE;
1079 qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE;
1080 qca_memdump->current_seq_no++;
1081 }
1082
e5aeebdd
ZH
1083 rx_size = qca_memdump->received_dump + skb->len;
1084 if (rx_size <= qca_memdump->ram_dump_size) {
1085 if ((seq_no != QCA_LAST_SEQUENCE_NUM) &&
1086 (seq_no != qca_memdump->current_seq_no))
1087 bt_dev_err(hu->hdev,
1088 "QCA memdump unexpected packet %d",
1089 seq_no);
1090 bt_dev_dbg(hu->hdev,
1091 "QCA memdump packet %d with length %d",
1092 seq_no, skb->len);
1093 memcpy(memdump_buf, (unsigned char *)skb->data,
1094 skb->len);
1095 memdump_buf = memdump_buf + skb->len;
1096 qca_memdump->memdump_buf_tail = memdump_buf;
1097 qca_memdump->current_seq_no = seq_no + 1;
1098 qca_memdump->received_dump += skb->len;
1099 } else {
1100 bt_dev_err(hu->hdev,
1101 "QCA memdump received %d, no space for packet %d",
1102 qca_memdump->received_dump, seq_no);
1103 }
d841502c
BG
1104 qca->qca_memdump = qca_memdump;
1105 kfree_skb(skb);
1106 if (seq_no == QCA_LAST_SEQUENCE_NUM) {
e5aeebdd
ZH
1107 bt_dev_info(hu->hdev,
1108 "QCA memdump Done, received %d, total %d",
1109 qca_memdump->received_dump,
1110 qca_memdump->ram_dump_size);
d841502c
BG
1111 memdump_buf = qca_memdump->memdump_buf_head;
1112 dev_coredumpv(&hu->serdev->dev, memdump_buf,
1113 qca_memdump->received_dump, GFP_KERNEL);
7c2c3e63 1114 cancel_delayed_work(&qca->ctrl_memdump_timeout);
d841502c
BG
1115 kfree(qca->qca_memdump);
1116 qca->qca_memdump = NULL;
1117 qca->memdump_state = QCA_MEMDUMP_COLLECTED;
7c2c3e63 1118 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c 1119 }
7c2c3e63
VLNG
1120
1121 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1122 }
1123
1124}
1125
7c2c3e63
VLNG
1126static int qca_controller_memdump_event(struct hci_dev *hdev,
1127 struct sk_buff *skb)
d841502c
BG
1128{
1129 struct hci_uart *hu = hci_get_drvdata(hdev);
1130 struct qca_data *qca = hu->priv;
1131
3344537f 1132 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
d841502c
BG
1133 skb_queue_tail(&qca->rx_memdump_q, skb);
1134 queue_work(qca->workqueue, &qca->ctrl_memdump_evt);
1135
1136 return 0;
1137}
1138
2faa3f15
MK
1139static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
1140{
1141 struct hci_uart *hu = hci_get_drvdata(hdev);
1142 struct qca_data *qca = hu->priv;
1143
1144 if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) {
1145 struct hci_event_hdr *hdr = (void *)skb->data;
1146
1147 /* For the WCN3990 the vendor command for a baudrate change
1148 * isn't sent as synchronous HCI command, because the
1149 * controller sends the corresponding vendor event with the
1150 * new baudrate. The event is received and properly decoded
1151 * after changing the baudrate of the host port. It needs to
1152 * be dropped, otherwise it can be misinterpreted as
1153 * response to a later firmware download command (also a
1154 * vendor command).
1155 */
1156
1157 if (hdr->evt == HCI_EV_VENDOR)
1158 complete(&qca->drop_ev_comp);
1159
4974c839 1160 kfree_skb(skb);
2faa3f15
MK
1161
1162 return 0;
1163 }
d841502c
BG
1164 /* We receive chip memory dump as an event packet, With a dedicated
1165 * handler followed by a hardware error event. When this event is
1166 * received we store dump into a file before closing hci. This
1167 * dump will help in triaging the issues.
1168 */
1169 if ((skb->data[0] == HCI_VENDOR_PKT) &&
1170 (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE))
1171 return qca_controller_memdump_event(hdev, skb);
2faa3f15
MK
1172
1173 return hci_recv_frame(hdev, skb);
1174}
1175
0ff252c1
BYTK
1176#define QCA_IBS_SLEEP_IND_EVENT \
1177 .type = HCI_IBS_SLEEP_IND, \
1178 .hlen = 0, \
1179 .loff = 0, \
1180 .lsize = 0, \
1181 .maxlen = HCI_MAX_IBS_SIZE
1182
1183#define QCA_IBS_WAKE_IND_EVENT \
1184 .type = HCI_IBS_WAKE_IND, \
1185 .hlen = 0, \
1186 .loff = 0, \
1187 .lsize = 0, \
1188 .maxlen = HCI_MAX_IBS_SIZE
1189
1190#define QCA_IBS_WAKE_ACK_EVENT \
1191 .type = HCI_IBS_WAKE_ACK, \
1192 .hlen = 0, \
1193 .loff = 0, \
1194 .lsize = 0, \
1195 .maxlen = HCI_MAX_IBS_SIZE
1196
1197static const struct h4_recv_pkt qca_recv_pkts[] = {
c614ca3f 1198 { H4_RECV_ACL, .recv = qca_recv_acl_data },
0ff252c1 1199 { H4_RECV_SCO, .recv = hci_recv_frame },
2faa3f15 1200 { H4_RECV_EVENT, .recv = qca_recv_event },
0ff252c1
BYTK
1201 { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind },
1202 { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack },
1203 { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind },
1204};
1205
1206static int qca_recv(struct hci_uart *hu, const void *data, int count)
1207{
1208 struct qca_data *qca = hu->priv;
1209
1210 if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
1211 return -EUNATCH;
1212
1213 qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count,
1214 qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts));
1215 if (IS_ERR(qca->rx_skb)) {
1216 int err = PTR_ERR(qca->rx_skb);
2064ee33 1217 bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
0ff252c1
BYTK
1218 qca->rx_skb = NULL;
1219 return err;
1220 }
1221
1222 return count;
1223}
1224
1225static struct sk_buff *qca_dequeue(struct hci_uart *hu)
1226{
1227 struct qca_data *qca = hu->priv;
1228
1229 return skb_dequeue(&qca->txq);
1230}
1231
1232static uint8_t qca_get_baudrate_value(int speed)
1233{
ce26d813 1234 switch (speed) {
0ff252c1
BYTK
1235 case 9600:
1236 return QCA_BAUDRATE_9600;
1237 case 19200:
1238 return QCA_BAUDRATE_19200;
1239 case 38400:
1240 return QCA_BAUDRATE_38400;
1241 case 57600:
1242 return QCA_BAUDRATE_57600;
1243 case 115200:
1244 return QCA_BAUDRATE_115200;
1245 case 230400:
1246 return QCA_BAUDRATE_230400;
1247 case 460800:
1248 return QCA_BAUDRATE_460800;
1249 case 500000:
1250 return QCA_BAUDRATE_500000;
1251 case 921600:
1252 return QCA_BAUDRATE_921600;
1253 case 1000000:
1254 return QCA_BAUDRATE_1000000;
1255 case 2000000:
1256 return QCA_BAUDRATE_2000000;
1257 case 3000000:
1258 return QCA_BAUDRATE_3000000;
be93a497
BG
1259 case 3200000:
1260 return QCA_BAUDRATE_3200000;
0ff252c1
BYTK
1261 case 3500000:
1262 return QCA_BAUDRATE_3500000;
1263 default:
1264 return QCA_BAUDRATE_115200;
1265 }
1266}
1267
1268static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)
1269{
1270 struct hci_uart *hu = hci_get_drvdata(hdev);
1271 struct qca_data *qca = hu->priv;
1272 struct sk_buff *skb;
1273 u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 };
1274
be93a497 1275 if (baudrate > QCA_BAUDRATE_3200000)
0ff252c1
BYTK
1276 return -EINVAL;
1277
1278 cmd[4] = baudrate;
1279
25a13e38 1280 skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
0ff252c1 1281 if (!skb) {
2064ee33 1282 bt_dev_err(hdev, "Failed to allocate baudrate packet");
0ff252c1
BYTK
1283 return -ENOMEM;
1284 }
1285
1286 /* Assign commands to change baudrate and packet type. */
59ae1d12 1287 skb_put_data(skb, cmd, sizeof(cmd));
618e8bc2 1288 hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
0ff252c1
BYTK
1289
1290 skb_queue_tail(&qca->txq, skb);
1291 hci_uart_tx_wakeup(hu);
1292
94d66714
MK
1293 /* Wait for the baudrate change request to be sent */
1294
1295 while (!skb_queue_empty(&qca->txq))
1296 usleep_range(100, 200);
1297
ecf2b768
MK
1298 if (hu->serdev)
1299 serdev_device_wait_until_sent(hu->serdev,
94d66714
MK
1300 msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
1301
1302 /* Give the controller time to process the request */
523760b7 1303 if (qca_is_wcn399x(qca_soc_type(hu)))
94d66714
MK
1304 msleep(10);
1305 else
1306 msleep(300);
0ff252c1
BYTK
1307
1308 return 0;
1309}
1310
05ba533c
TE
1311static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed)
1312{
1313 if (hu->serdev)
1314 serdev_device_set_baudrate(hu->serdev, speed);
1315 else
1316 hci_uart_set_baudrate(hu, speed);
1317}
1318
9836b802 1319static int qca_send_power_pulse(struct hci_uart *hu, bool on)
fa9ad876 1320{
f9558270 1321 int ret;
94d66714 1322 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
9836b802 1323 u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE;
fa9ad876
BG
1324
1325 /* These power pulses are single byte command which are sent
1326 * at required baudrate to wcn3990. On wcn3990, we have an external
1327 * circuit at Tx pin which decodes the pulse sent at specific baudrate.
1328 * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT
1329 * and also we use the same power inputs to turn on and off for
1330 * Wi-Fi/BT. Powering up the power sources will not enable BT, until
1331 * we send a power on pulse at 115200 bps. This algorithm will help to
1332 * save power. Disabling hardware flow control is mandatory while
1333 * sending power pulses to SoC.
1334 */
f9558270 1335 bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd);
fa9ad876 1336
f9558270 1337 serdev_device_write_flush(hu->serdev);
fa9ad876 1338 hci_uart_set_flow_control(hu, true);
f9558270
BG
1339 ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
1340 if (ret < 0) {
1341 bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd);
1342 return ret;
1343 }
fa9ad876 1344
f9558270 1345 serdev_device_wait_until_sent(hu->serdev, timeout);
fa9ad876
BG
1346 hci_uart_set_flow_control(hu, false);
1347
0ebcddd8 1348 /* Give to controller time to boot/shutdown */
ad571d72
MK
1349 if (on)
1350 msleep(100);
0ebcddd8
MK
1351 else
1352 msleep(10);
ad571d72 1353
fa9ad876
BG
1354 return 0;
1355}
1356
83d9c5e5
BG
1357static unsigned int qca_get_speed(struct hci_uart *hu,
1358 enum qca_speed_type speed_type)
1359{
1360 unsigned int speed = 0;
1361
1362 if (speed_type == QCA_INIT_SPEED) {
1363 if (hu->init_speed)
1364 speed = hu->init_speed;
1365 else if (hu->proto->init_speed)
1366 speed = hu->proto->init_speed;
1367 } else {
1368 if (hu->oper_speed)
1369 speed = hu->oper_speed;
1370 else if (hu->proto->oper_speed)
1371 speed = hu->proto->oper_speed;
1372 }
1373
1374 return speed;
1375}
1376
1377static int qca_check_speeds(struct hci_uart *hu)
1378{
523760b7 1379 if (qca_is_wcn399x(qca_soc_type(hu))) {
fa9ad876
BG
1380 if (!qca_get_speed(hu, QCA_INIT_SPEED) &&
1381 !qca_get_speed(hu, QCA_OPER_SPEED))
1382 return -EINVAL;
1383 } else {
1384 if (!qca_get_speed(hu, QCA_INIT_SPEED) ||
1385 !qca_get_speed(hu, QCA_OPER_SPEED))
1386 return -EINVAL;
1387 }
83d9c5e5
BG
1388
1389 return 0;
1390}
1391
1392static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type)
1393{
1394 unsigned int speed, qca_baudrate;
2faa3f15 1395 struct qca_data *qca = hu->priv;
78e8fa29 1396 int ret = 0;
83d9c5e5
BG
1397
1398 if (speed_type == QCA_INIT_SPEED) {
1399 speed = qca_get_speed(hu, QCA_INIT_SPEED);
1400 if (speed)
1401 host_set_baudrate(hu, speed);
1402 } else {
4fdd5a4f
MK
1403 enum qca_btsoc_type soc_type = qca_soc_type(hu);
1404
83d9c5e5
BG
1405 speed = qca_get_speed(hu, QCA_OPER_SPEED);
1406 if (!speed)
1407 return 0;
1408
78e8fa29
BG
1409 /* Disable flow control for wcn3990 to deassert RTS while
1410 * changing the baudrate of chip and host.
1411 */
523760b7 1412 if (qca_is_wcn399x(soc_type))
78e8fa29
BG
1413 hci_uart_set_flow_control(hu, true);
1414
2faa3f15
MK
1415 if (soc_type == QCA_WCN3990) {
1416 reinit_completion(&qca->drop_ev_comp);
1417 set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
1418 }
1419
83d9c5e5 1420 qca_baudrate = qca_get_baudrate_value(speed);
fa9ad876 1421 bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed);
83d9c5e5
BG
1422 ret = qca_set_baudrate(hu->hdev, qca_baudrate);
1423 if (ret)
78e8fa29 1424 goto error;
83d9c5e5
BG
1425
1426 host_set_baudrate(hu, speed);
78e8fa29
BG
1427
1428error:
bba79fee 1429 if (qca_is_wcn399x(soc_type))
78e8fa29 1430 hci_uart_set_flow_control(hu, false);
2faa3f15
MK
1431
1432 if (soc_type == QCA_WCN3990) {
1433 /* Wait for the controller to send the vendor event
1434 * for the baudrate change command.
1435 */
1436 if (!wait_for_completion_timeout(&qca->drop_ev_comp,
1437 msecs_to_jiffies(100))) {
1438 bt_dev_err(hu->hdev,
1439 "Failed to change controller baudrate\n");
1440 ret = -ETIMEDOUT;
1441 }
1442
1443 clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
1444 }
83d9c5e5
BG
1445 }
1446
78e8fa29 1447 return ret;
83d9c5e5
BG
1448}
1449
d841502c
BG
1450static int qca_send_crashbuffer(struct hci_uart *hu)
1451{
1452 struct qca_data *qca = hu->priv;
1453 struct sk_buff *skb;
1454
1455 skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL);
1456 if (!skb) {
1457 bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet");
1458 return -ENOMEM;
1459 }
1460
1461 /* We forcefully crash the controller, by sending 0xfb byte for
1462 * 1024 times. We also might have chance of losing data, To be
1463 * on safer side we send 1096 bytes to the SoC.
1464 */
1465 memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE,
1466 QCA_CRASHBYTE_PACKET_LEN);
1467 hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
1468 bt_dev_info(hu->hdev, "crash the soc to collect controller dump");
1469 skb_queue_tail(&qca->txq, skb);
1470 hci_uart_tx_wakeup(hu);
1471
1472 return 0;
1473}
1474
1475static void qca_wait_for_dump_collection(struct hci_dev *hdev)
1476{
1477 struct hci_uart *hu = hci_get_drvdata(hdev);
1478 struct qca_data *qca = hu->priv;
d841502c
BG
1479
1480 wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION,
1481 TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS);
1482
1483 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c
BG
1484}
1485
1486static void qca_hw_error(struct hci_dev *hdev, u8 code)
1487{
1488 struct hci_uart *hu = hci_get_drvdata(hdev);
1489 struct qca_data *qca = hu->priv;
1490
3344537f 1491 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
7c2c3e63 1492 set_bit(QCA_HW_ERROR_EVENT, &qca->flags);
d841502c
BG
1493 bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state);
1494
1495 if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
1496 /* If hardware error event received for other than QCA
1497 * soc memory dump event, then we need to crash the SOC
1498 * and wait here for 8 seconds to get the dump packets.
1499 * This will block main thread to be on hold until we
1500 * collect dump.
1501 */
1502 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1503 qca_send_crashbuffer(hu);
1504 qca_wait_for_dump_collection(hdev);
1505 } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
1506 /* Let us wait here until memory dump collected or
1507 * memory dump timer expired.
1508 */
1509 bt_dev_info(hdev, "waiting for dump to complete");
1510 qca_wait_for_dump_collection(hdev);
1511 }
7c2c3e63 1512
f98aa80f 1513 mutex_lock(&qca->hci_memdump_lock);
7c2c3e63
VLNG
1514 if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
1515 bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout");
f98aa80f
VLNG
1516 if (qca->qca_memdump) {
1517 vfree(qca->qca_memdump->memdump_buf_head);
1518 kfree(qca->qca_memdump);
1519 qca->qca_memdump = NULL;
1520 }
7c2c3e63
VLNG
1521 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
1522 cancel_delayed_work(&qca->ctrl_memdump_timeout);
f98aa80f
VLNG
1523 }
1524 mutex_unlock(&qca->hci_memdump_lock);
1525
1526 if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
1527 qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
7c2c3e63 1528 cancel_work_sync(&qca->ctrl_memdump_evt);
f98aa80f 1529 skb_queue_purge(&qca->rx_memdump_q);
7c2c3e63
VLNG
1530 }
1531
1532 clear_bit(QCA_HW_ERROR_EVENT, &qca->flags);
d841502c
BG
1533}
1534
1535static void qca_cmd_timeout(struct hci_dev *hdev)
1536{
1537 struct hci_uart *hu = hci_get_drvdata(hdev);
1538 struct qca_data *qca = hu->priv;
1539
3344537f
VLNG
1540 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
1541 if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
1542 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c 1543 qca_send_crashbuffer(hu);
3344537f
VLNG
1544 qca_wait_for_dump_collection(hdev);
1545 } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
1546 /* Let us wait here until memory dump collected or
1547 * memory dump timer expired.
1548 */
1549 bt_dev_info(hdev, "waiting for dump to complete");
1550 qca_wait_for_dump_collection(hdev);
1551 }
1552
1553 mutex_lock(&qca->hci_memdump_lock);
1554 if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
1555 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
1556 if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
1557 /* Inject hw error event to reset the device
1558 * and driver.
1559 */
1560 hci_reset_dev(hu->hdev);
1561 }
1562 }
1563 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1564}
1565
fa9ad876
BG
1566static int qca_wcn3990_init(struct hci_uart *hu)
1567{
3e4be65e 1568 struct qca_serdev *qcadev;
fa9ad876
BG
1569 int ret;
1570
3e4be65e
BG
1571 /* Check for vregs status, may be hci down has turned
1572 * off the voltage regulator.
1573 */
1574 qcadev = serdev_device_get_drvdata(hu->serdev);
1575 if (!qcadev->bt_power->vregs_on) {
1576 serdev_device_close(hu->serdev);
a9314e76 1577 ret = qca_regulator_enable(qcadev);
3e4be65e
BG
1578 if (ret)
1579 return ret;
1580
1581 ret = serdev_device_open(hu->serdev);
1582 if (ret) {
1583 bt_dev_err(hu->hdev, "failed to open port");
1584 return ret;
1585 }
1586 }
1587
fa9ad876
BG
1588 /* Forcefully enable wcn3990 to enter in to boot mode. */
1589 host_set_baudrate(hu, 2400);
9836b802 1590 ret = qca_send_power_pulse(hu, false);
fa9ad876
BG
1591 if (ret)
1592 return ret;
1593
1594 qca_set_speed(hu, QCA_INIT_SPEED);
9836b802 1595 ret = qca_send_power_pulse(hu, true);
fa9ad876
BG
1596 if (ret)
1597 return ret;
1598
fa9ad876
BG
1599 /* Now the device is in ready state to communicate with host.
1600 * To sync host with device we need to reopen port.
1601 * Without this, we will have RTS and CTS synchronization
1602 * issues.
1603 */
1604 serdev_device_close(hu->serdev);
1605 ret = serdev_device_open(hu->serdev);
1606 if (ret) {
1607 bt_dev_err(hu->hdev, "failed to open port");
1608 return ret;
1609 }
1610
1611 hci_uart_set_flow_control(hu, false);
1612
1613 return 0;
1614}
1615
5e6d8401
RL
1616static int qca_power_on(struct hci_dev *hdev)
1617{
1618 struct hci_uart *hu = hci_get_drvdata(hdev);
1619 enum qca_btsoc_type soc_type = qca_soc_type(hu);
1620 struct qca_serdev *qcadev;
1621 int ret = 0;
1622
1623 /* Non-serdev device usually is powered by external power
1624 * and don't need additional action in driver for power on
1625 */
1626 if (!hu->serdev)
1627 return 0;
1628
1629 if (qca_is_wcn399x(soc_type)) {
1630 ret = qca_wcn3990_init(hu);
1631 } else {
1632 qcadev = serdev_device_get_drvdata(hu->serdev);
77131dfe 1633 if (qcadev->bt_en) {
8a208b24
RL
1634 gpiod_set_value_cansleep(qcadev->bt_en, 1);
1635 /* Controller needs time to bootup. */
1636 msleep(150);
1637 }
5e6d8401
RL
1638 }
1639
1640 return ret;
1641}
1642
0ff252c1
BYTK
1643static int qca_setup(struct hci_uart *hu)
1644{
1645 struct hci_dev *hdev = hu->hdev;
1646 struct qca_data *qca = hu->priv;
1647 unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200;
bb2500ab 1648 unsigned int retries = 0;
4fdd5a4f 1649 enum qca_btsoc_type soc_type = qca_soc_type(hu);
99c905c6 1650 const char *firmware_name = qca_get_firmware_name(hu);
0ff252c1 1651 int ret;
aadebac4 1652 int soc_ver = 0;
0ff252c1 1653
83d9c5e5
BG
1654 ret = qca_check_speeds(hu);
1655 if (ret)
1656 return ret;
1657
0ff252c1 1658 /* Patch downloading has to be done without IBS mode */
62a91990 1659 clear_bit(QCA_IBS_ENABLED, &qca->flags);
0ff252c1 1660
e14c167a
RL
1661 /* Enable controller to do both LE scan and BR/EDR inquiry
1662 * simultaneously.
1663 */
1664 set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks);
1665
5e6d8401 1666 bt_dev_info(hdev, "setting up %s",
e5d6468f 1667 qca_is_wcn399x(soc_type) ? "wcn399x" : "ROME/QCA6390");
3e4be65e 1668
58789a19
VLNG
1669 qca->memdump_state = QCA_MEMDUMP_IDLE;
1670
bb2500ab 1671retry:
5e6d8401
RL
1672 ret = qca_power_on(hdev);
1673 if (ret)
1674 return ret;
1675
3344537f
VLNG
1676 clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
1677
5e6d8401 1678 if (qca_is_wcn399x(soc_type)) {
5971752d 1679 set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks);
fa9ad876 1680
7d250a06 1681 ret = qca_read_soc_version(hdev, &soc_ver, soc_type);
fa9ad876
BG
1682 if (ret)
1683 return ret;
1684 } else {
fa9ad876
BG
1685 qca_set_speed(hu, QCA_INIT_SPEED);
1686 }
0ff252c1
BYTK
1687
1688 /* Setup user speed if needed */
83d9c5e5 1689 speed = qca_get_speed(hu, QCA_OPER_SPEED);
0ff252c1 1690 if (speed) {
83d9c5e5
BG
1691 ret = qca_set_speed(hu, QCA_OPER_SPEED);
1692 if (ret)
0ff252c1 1693 return ret;
83d9c5e5
BG
1694
1695 qca_baudrate = qca_get_baudrate_value(speed);
0ff252c1
BYTK
1696 }
1697
523760b7 1698 if (!qca_is_wcn399x(soc_type)) {
fa9ad876 1699 /* Get QCA version information */
7d250a06 1700 ret = qca_read_soc_version(hdev, &soc_ver, soc_type);
fa9ad876
BG
1701 if (ret)
1702 return ret;
1703 }
aadebac4
BG
1704
1705 bt_dev_info(hdev, "QCA controller version 0x%08x", soc_ver);
0ff252c1 1706 /* Setup patch / NVM configurations */
99c905c6
RL
1707 ret = qca_uart_setup(hdev, qca_baudrate, soc_type, soc_ver,
1708 firmware_name);
0ff252c1 1709 if (!ret) {
62a91990 1710 set_bit(QCA_IBS_ENABLED, &qca->flags);
0ff252c1 1711 qca_debugfs_init(hdev);
d841502c
BG
1712 hu->hdev->hw_error = qca_hw_error;
1713 hu->hdev->cmd_timeout = qca_cmd_timeout;
ba8f3597
LP
1714 } else if (ret == -ENOENT) {
1715 /* No patch/nvm-config found, run with original fw/config */
1716 ret = 0;
7dc5fe08
AP
1717 } else if (ret == -EAGAIN) {
1718 /*
1719 * Userspace firmware loader will return -EAGAIN in case no
1720 * patch/nvm-config is found, so run with original fw/config.
1721 */
1722 ret = 0;
bb2500ab
RL
1723 } else {
1724 if (retries < MAX_INIT_RETRIES) {
1725 qca_power_shutdown(hu);
1726 if (hu->serdev) {
1727 serdev_device_close(hu->serdev);
1728 ret = serdev_device_open(hu->serdev);
1729 if (ret) {
1730 bt_dev_err(hdev, "failed to open port");
1731 return ret;
1732 }
1733 }
1734 retries++;
1735 goto retry;
1736 }
0ff252c1
BYTK
1737 }
1738
1739 /* Setup bdaddr */
e5d6468f 1740 if (soc_type == QCA_ROME)
5c0a1001 1741 hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
e5d6468f
RL
1742 else
1743 hu->hdev->set_bdaddr = qca_set_bdaddr;
0ff252c1
BYTK
1744
1745 return ret;
1746}
1747
2edc9c5c 1748static const struct hci_uart_proto qca_proto = {
0ff252c1
BYTK
1749 .id = HCI_UART_QCA,
1750 .name = "QCA",
aee61f7a 1751 .manufacturer = 29,
0ff252c1
BYTK
1752 .init_speed = 115200,
1753 .oper_speed = 3000000,
1754 .open = qca_open,
1755 .close = qca_close,
1756 .flush = qca_flush,
1757 .setup = qca_setup,
1758 .recv = qca_recv,
1759 .enqueue = qca_enqueue,
1760 .dequeue = qca_dequeue,
1761};
1762
a228f7a4 1763static const struct qca_device_data qca_soc_data_wcn3990 = {
fa9ad876
BG
1764 .soc_type = QCA_WCN3990,
1765 .vregs = (struct qca_vreg []) {
f2edd66e
BA
1766 { "vddio", 15000 },
1767 { "vddxo", 80000 },
1768 { "vddrf", 300000 },
1769 { "vddch0", 450000 },
fa9ad876
BG
1770 },
1771 .num_vregs = 4,
1772};
1773
a228f7a4 1774static const struct qca_device_data qca_soc_data_wcn3991 = {
7d250a06
BG
1775 .soc_type = QCA_WCN3991,
1776 .vregs = (struct qca_vreg []) {
1777 { "vddio", 15000 },
1778 { "vddxo", 80000 },
1779 { "vddrf", 300000 },
1780 { "vddch0", 450000 },
1781 },
1782 .num_vregs = 4,
a228f7a4 1783 .capabilities = QCA_CAP_WIDEBAND_SPEECH,
7d250a06
BG
1784};
1785
a228f7a4 1786static const struct qca_device_data qca_soc_data_wcn3998 = {
523760b7
HB
1787 .soc_type = QCA_WCN3998,
1788 .vregs = (struct qca_vreg []) {
f2edd66e
BA
1789 { "vddio", 10000 },
1790 { "vddxo", 80000 },
1791 { "vddrf", 300000 },
1792 { "vddch0", 450000 },
523760b7
HB
1793 },
1794 .num_vregs = 4,
1795};
1796
a228f7a4 1797static const struct qca_device_data qca_soc_data_qca6390 = {
e5d6468f
RL
1798 .soc_type = QCA_QCA6390,
1799 .num_vregs = 0,
1800};
1801
c2d78273 1802static void qca_power_shutdown(struct hci_uart *hu)
fa9ad876 1803{
a9314e76 1804 struct qca_serdev *qcadev;
035a960e
BG
1805 struct qca_data *qca = hu->priv;
1806 unsigned long flags;
5559904c 1807 enum qca_btsoc_type soc_type = qca_soc_type(hu);
035a960e 1808
a9314e76
BA
1809 qcadev = serdev_device_get_drvdata(hu->serdev);
1810
035a960e
BG
1811 /* From this point we go into power off state. But serial port is
1812 * still open, stop queueing the IBS data and flush all the buffered
1813 * data in skb's.
1814 */
1815 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
62a91990 1816 clear_bit(QCA_IBS_ENABLED, &qca->flags);
035a960e
BG
1817 qca_flush(hu);
1818 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
1819
5559904c
RL
1820 /* Non-serdev device usually is powered by external power
1821 * and don't need additional action in driver for power down
1822 */
1823 if (!hu->serdev)
1824 return;
1825
1826 if (qca_is_wcn399x(soc_type)) {
1827 host_set_baudrate(hu, 2400);
1828 qca_send_power_pulse(hu, false);
1829 qca_regulator_disable(qcadev);
77131dfe 1830 } else if (qcadev->bt_en) {
5559904c
RL
1831 gpiod_set_value_cansleep(qcadev->bt_en, 0);
1832 }
fa9ad876
BG
1833}
1834
3e4be65e
BG
1835static int qca_power_off(struct hci_dev *hdev)
1836{
1837 struct hci_uart *hu = hci_get_drvdata(hdev);
d841502c 1838 struct qca_data *qca = hu->priv;
4f9ed5bd 1839 enum qca_btsoc_type soc_type = qca_soc_type(hu);
3e4be65e 1840
58789a19
VLNG
1841 hu->hdev->hw_error = NULL;
1842 hu->hdev->cmd_timeout = NULL;
1843
d841502c 1844 /* Stop sending shutdown command if soc crashes. */
e5d6468f 1845 if (soc_type != QCA_ROME
4f9ed5bd 1846 && qca->memdump_state == QCA_MEMDUMP_IDLE) {
d841502c
BG
1847 qca_send_pre_shutdown_cmd(hdev);
1848 usleep_range(8000, 10000);
1849 }
010376ab 1850
3e4be65e
BG
1851 qca_power_shutdown(hu);
1852 return 0;
1853}
1854
a9314e76 1855static int qca_regulator_enable(struct qca_serdev *qcadev)
fa9ad876 1856{
a9314e76
BA
1857 struct qca_power *power = qcadev->bt_power;
1858 int ret;
fa9ad876 1859
a9314e76
BA
1860 /* Already enabled */
1861 if (power->vregs_on)
1862 return 0;
fa9ad876 1863
a9314e76 1864 BT_DBG("enabling %d regulators)", power->num_vregs);
fa9ad876 1865
a9314e76
BA
1866 ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk);
1867 if (ret)
1868 return ret;
fa9ad876 1869
a9314e76 1870 power->vregs_on = true;
fa9ad876 1871
66cb7051 1872 ret = clk_prepare_enable(qcadev->susclk);
f3d63f50 1873 if (ret)
66cb7051 1874 qca_regulator_disable(qcadev);
66cb7051 1875
f3d63f50 1876 return ret;
fa9ad876
BG
1877}
1878
a9314e76
BA
1879static void qca_regulator_disable(struct qca_serdev *qcadev)
1880{
1881 struct qca_power *power;
1882
1883 if (!qcadev)
1884 return;
1885
1886 power = qcadev->bt_power;
1887
1888 /* Already disabled? */
1889 if (!power->vregs_on)
1890 return;
1891
1892 regulator_bulk_disable(power->num_vregs, power->vreg_bulk);
1893 power->vregs_on = false;
66cb7051 1894
f3d63f50 1895 clk_disable_unprepare(qcadev->susclk);
a9314e76
BA
1896}
1897
fa9ad876
BG
1898static int qca_init_regulators(struct qca_power *qca,
1899 const struct qca_vreg *vregs, size_t num_vregs)
1900{
c29ff107
BA
1901 struct regulator_bulk_data *bulk;
1902 int ret;
fa9ad876
BG
1903 int i;
1904
c29ff107
BA
1905 bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL);
1906 if (!bulk)
fa9ad876
BG
1907 return -ENOMEM;
1908
1909 for (i = 0; i < num_vregs; i++)
c29ff107
BA
1910 bulk[i].supply = vregs[i].name;
1911
1912 ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk);
1913 if (ret < 0)
1914 return ret;
fa9ad876 1915
c29ff107
BA
1916 for (i = 0; i < num_vregs; i++) {
1917 ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA);
1918 if (ret)
1919 return ret;
1920 }
1921
1922 qca->vreg_bulk = bulk;
163d42fa 1923 qca->num_vregs = num_vregs;
c29ff107
BA
1924
1925 return 0;
fa9ad876
BG
1926}
1927
05ba533c
TE
1928static int qca_serdev_probe(struct serdev_device *serdev)
1929{
1930 struct qca_serdev *qcadev;
ae563183 1931 struct hci_dev *hdev;
a228f7a4 1932 const struct qca_device_data *data;
05ba533c 1933 int err;
8a208b24 1934 bool power_ctrl_enabled = true;
05ba533c
TE
1935
1936 qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL);
1937 if (!qcadev)
1938 return -ENOMEM;
1939
1940 qcadev->serdev_hu.serdev = serdev;
9f3565b8 1941 data = device_get_match_data(&serdev->dev);
05ba533c 1942 serdev_device_set_drvdata(serdev, qcadev);
99c905c6
RL
1943 device_property_read_string(&serdev->dev, "firmware-name",
1944 &qcadev->firmware_name);
37aee136
CH
1945 device_property_read_u32(&serdev->dev, "max-speed",
1946 &qcadev->oper_speed);
1947 if (!qcadev->oper_speed)
1948 BT_DBG("UART will pick default operating speed");
1949
523760b7
HB
1950 if (data && qca_is_wcn399x(data->soc_type)) {
1951 qcadev->btsoc_type = data->soc_type;
fa9ad876
BG
1952 qcadev->bt_power = devm_kzalloc(&serdev->dev,
1953 sizeof(struct qca_power),
1954 GFP_KERNEL);
1955 if (!qcadev->bt_power)
1956 return -ENOMEM;
1957
1958 qcadev->bt_power->dev = &serdev->dev;
fa9ad876
BG
1959 err = qca_init_regulators(qcadev->bt_power, data->vregs,
1960 data->num_vregs);
1961 if (err) {
1962 BT_ERR("Failed to init regulators:%d", err);
ae563183 1963 return err;
fa9ad876 1964 }
05ba533c 1965
fa9ad876 1966 qcadev->bt_power->vregs_on = false;
05ba533c 1967
66cb7051
VLNG
1968 qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
1969 if (IS_ERR(qcadev->susclk)) {
1970 dev_err(&serdev->dev, "failed to acquire clk\n");
1971 return PTR_ERR(qcadev->susclk);
1972 }
1973
fa9ad876
BG
1974 err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
1975 if (err) {
1976 BT_ERR("wcn3990 serdev registration failed");
ae563183 1977 return err;
fa9ad876
BG
1978 }
1979 } else {
e5d6468f
RL
1980 if (data)
1981 qcadev->btsoc_type = data->soc_type;
1982 else
1983 qcadev->btsoc_type = QCA_ROME;
1984
77131dfe 1985 qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
fa9ad876 1986 GPIOD_OUT_LOW);
77131dfe 1987 if (!qcadev->bt_en) {
8a208b24
RL
1988 dev_warn(&serdev->dev, "failed to acquire enable gpio\n");
1989 power_ctrl_enabled = false;
fa9ad876 1990 }
05ba533c 1991
77131dfe 1992 qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
4c07a5d7 1993 if (IS_ERR(qcadev->susclk)) {
8a208b24 1994 dev_warn(&serdev->dev, "failed to acquire clk\n");
4c07a5d7 1995 return PTR_ERR(qcadev->susclk);
8a208b24 1996 }
4c07a5d7
DC
1997 err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ);
1998 if (err)
1999 return err;
2000
2001 err = clk_prepare_enable(qcadev->susclk);
2002 if (err)
2003 return err;
fa9ad876
BG
2004
2005 err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
ae563183
RL
2006 if (err) {
2007 BT_ERR("Rome serdev registration failed");
65a24d4c 2008 clk_disable_unprepare(qcadev->susclk);
ae563183
RL
2009 return err;
2010 }
fa9ad876
BG
2011 }
2012
85e90d93
APS
2013 hdev = qcadev->serdev_hu.hdev;
2014
8a208b24 2015 if (power_ctrl_enabled) {
8a208b24
RL
2016 set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks);
2017 hdev->shutdown = qca_power_off;
2018 }
05ba533c 2019
a228f7a4
APS
2020 /* Wideband speech support must be set per driver since it can't be
2021 * queried via hci.
2022 */
2023 if (data && (data->capabilities & QCA_CAP_WIDEBAND_SPEECH))
2024 set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED, &hdev->quirks);
2025
ae563183 2026 return 0;
05ba533c
TE
2027}
2028
2029static void qca_serdev_remove(struct serdev_device *serdev)
2030{
2031 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
054ec5e9 2032 struct qca_power *power = qcadev->bt_power;
05ba533c 2033
054ec5e9 2034 if (qca_is_wcn399x(qcadev->btsoc_type) && power->vregs_on)
c2d78273 2035 qca_power_shutdown(&qcadev->serdev_hu);
77131dfe 2036 else if (qcadev->susclk)
fa9ad876 2037 clk_disable_unprepare(qcadev->susclk);
05ba533c 2038
fa9ad876 2039 hci_uart_unregister_device(&qcadev->serdev_hu);
05ba533c
TE
2040}
2041
7e7bbddd
ZH
2042static void qca_serdev_shutdown(struct device *dev)
2043{
2044 int ret;
2045 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
2046 struct serdev_device *serdev = to_serdev_device(dev);
2047 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2048 const u8 ibs_wake_cmd[] = { 0xFD };
2049 const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 };
2050
2051 if (qcadev->btsoc_type == QCA_QCA6390) {
2052 serdev_device_write_flush(serdev);
2053 ret = serdev_device_write_buf(serdev, ibs_wake_cmd,
2054 sizeof(ibs_wake_cmd));
2055 if (ret < 0) {
2056 BT_ERR("QCA send IBS_WAKE_IND error: %d", ret);
2057 return;
2058 }
2059 serdev_device_wait_until_sent(serdev, timeout);
2060 usleep_range(8000, 10000);
2061
2062 serdev_device_write_flush(serdev);
2063 ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd,
2064 sizeof(edl_reset_soc_cmd));
2065 if (ret < 0) {
2066 BT_ERR("QCA send EDL_RESET_REQ error: %d", ret);
2067 return;
2068 }
2069 serdev_device_wait_until_sent(serdev, timeout);
2070 usleep_range(8000, 10000);
2071 }
2072}
2073
41d5b25f
CC
2074static int __maybe_unused qca_suspend(struct device *dev)
2075{
feac90d7
ZH
2076 struct serdev_device *serdev = to_serdev_device(dev);
2077 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2078 struct hci_uart *hu = &qcadev->serdev_hu;
41d5b25f
CC
2079 struct qca_data *qca = hu->priv;
2080 unsigned long flags;
e2a119cd 2081 bool tx_pending = false;
41d5b25f
CC
2082 int ret = 0;
2083 u8 cmd;
2084
2085 set_bit(QCA_SUSPENDING, &qca->flags);
2086
2087 /* Device is downloading patch or doesn't support in-band sleep. */
2088 if (!test_bit(QCA_IBS_ENABLED, &qca->flags))
2089 return 0;
2090
2091 cancel_work_sync(&qca->ws_awake_device);
2092 cancel_work_sync(&qca->ws_awake_rx);
2093
2094 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
2095 flags, SINGLE_DEPTH_NESTING);
2096
2097 switch (qca->tx_ibs_state) {
2098 case HCI_IBS_TX_WAKING:
2099 del_timer(&qca->wake_retrans_timer);
a3b4cbfc 2100 fallthrough;
41d5b25f
CC
2101 case HCI_IBS_TX_AWAKE:
2102 del_timer(&qca->tx_idle_timer);
2103
2104 serdev_device_write_flush(hu->serdev);
2105 cmd = HCI_IBS_SLEEP_IND;
2106 ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
2107
2108 if (ret < 0) {
2109 BT_ERR("Failed to send SLEEP to device");
2110 break;
2111 }
2112
2113 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
2114 qca->ibs_sent_slps++;
e2a119cd 2115 tx_pending = true;
41d5b25f
CC
2116 break;
2117
2118 case HCI_IBS_TX_ASLEEP:
2119 break;
2120
2121 default:
2122 BT_ERR("Spurious tx state %d", qca->tx_ibs_state);
2123 ret = -EINVAL;
2124 break;
2125 }
2126
2127 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
2128
2129 if (ret < 0)
2130 goto error;
2131
e2a119cd
MK
2132 if (tx_pending) {
2133 serdev_device_wait_until_sent(hu->serdev,
2134 msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
201a1124 2135 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
e2a119cd 2136 }
41d5b25f
CC
2137
2138 /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going
2139 * to sleep, so that the packet does not wake the system later.
2140 */
41d5b25f
CC
2141 ret = wait_event_interruptible_timeout(qca->suspend_wait_q,
2142 qca->rx_ibs_state == HCI_IBS_RX_ASLEEP,
2143 msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS));
4da385f7
MK
2144 if (ret == 0) {
2145 ret = -ETIMEDOUT;
2146 goto error;
eff981f6 2147 }
41d5b25f 2148
4da385f7 2149 return 0;
41d5b25f
CC
2150
2151error:
2152 clear_bit(QCA_SUSPENDING, &qca->flags);
2153
2154 return ret;
2155}
2156
2157static int __maybe_unused qca_resume(struct device *dev)
2158{
feac90d7
ZH
2159 struct serdev_device *serdev = to_serdev_device(dev);
2160 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2161 struct hci_uart *hu = &qcadev->serdev_hu;
41d5b25f
CC
2162 struct qca_data *qca = hu->priv;
2163
2164 clear_bit(QCA_SUSPENDING, &qca->flags);
2165
2166 return 0;
2167}
2168
2169static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume);
2170
e5d6468f 2171#ifdef CONFIG_OF
05ba533c
TE
2172static const struct of_device_id qca_bluetooth_of_match[] = {
2173 { .compatible = "qcom,qca6174-bt" },
e5d6468f 2174 { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390},
31d4ab85 2175 { .compatible = "qcom,qca9377-bt" },
523760b7 2176 { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990},
7d250a06 2177 { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991},
523760b7 2178 { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998},
05ba533c
TE
2179 { /* sentinel */ }
2180};
2181MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match);
e5d6468f
RL
2182#endif
2183
2184#ifdef CONFIG_ACPI
2185static const struct acpi_device_id qca_bluetooth_acpi_match[] = {
2186 { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2187 { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2188 { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2189 { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2190 { },
2191};
2192MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match);
2193#endif
2194
05ba533c
TE
2195
2196static struct serdev_device_driver qca_serdev_driver = {
2197 .probe = qca_serdev_probe,
2198 .remove = qca_serdev_remove,
2199 .driver = {
2200 .name = "hci_uart_qca",
e5d6468f
RL
2201 .of_match_table = of_match_ptr(qca_bluetooth_of_match),
2202 .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match),
7e7bbddd 2203 .shutdown = qca_serdev_shutdown,
41d5b25f 2204 .pm = &qca_pm_ops,
05ba533c
TE
2205 },
2206};
2207
0ff252c1
BYTK
2208int __init qca_init(void)
2209{
05ba533c
TE
2210 serdev_device_driver_register(&qca_serdev_driver);
2211
0ff252c1
BYTK
2212 return hci_uart_register_proto(&qca_proto);
2213}
2214
2215int __exit qca_deinit(void)
2216{
05ba533c
TE
2217 serdev_device_driver_unregister(&qca_serdev_driver);
2218
0ff252c1
BYTK
2219 return hci_uart_unregister_proto(&qca_proto);
2220}