Commit | Line | Data |
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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0ff252c1 BYTK |
2 | /* |
3 | * Bluetooth Software UART Qualcomm protocol | |
4 | * | |
5 | * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management | |
6 | * protocol extension to H4. | |
7 | * | |
8 | * Copyright (C) 2007 Texas Instruments, Inc. | |
fa9ad876 | 9 | * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved. |
0ff252c1 BYTK |
10 | * |
11 | * Acknowledgements: | |
12 | * This file is based on hci_ll.c, which was... | |
13 | * Written by Ohad Ben-Cohen <ohad@bencohen.org> | |
14 | * which was in turn based on hci_h4.c, which was written | |
15 | * by Maxim Krasnyansky and Marcel Holtmann. | |
0ff252c1 BYTK |
16 | */ |
17 | ||
18 | #include <linux/kernel.h> | |
05ba533c | 19 | #include <linux/clk.h> |
2faa3f15 | 20 | #include <linux/completion.h> |
0ff252c1 | 21 | #include <linux/debugfs.h> |
fa9ad876 | 22 | #include <linux/delay.h> |
d841502c | 23 | #include <linux/devcoredump.h> |
fa9ad876 | 24 | #include <linux/device.h> |
05ba533c TE |
25 | #include <linux/gpio/consumer.h> |
26 | #include <linux/mod_devicetable.h> | |
27 | #include <linux/module.h> | |
fa9ad876 | 28 | #include <linux/of_device.h> |
e5d6468f | 29 | #include <linux/acpi.h> |
fa9ad876 BG |
30 | #include <linux/platform_device.h> |
31 | #include <linux/regulator/consumer.h> | |
05ba533c | 32 | #include <linux/serdev.h> |
7c2c3e63 | 33 | #include <linux/mutex.h> |
c614ca3f | 34 | #include <asm/unaligned.h> |
0ff252c1 BYTK |
35 | |
36 | #include <net/bluetooth/bluetooth.h> | |
37 | #include <net/bluetooth/hci_core.h> | |
38 | ||
39 | #include "hci_uart.h" | |
40 | #include "btqca.h" | |
41 | ||
42 | /* HCI_IBS protocol messages */ | |
43 | #define HCI_IBS_SLEEP_IND 0xFE | |
44 | #define HCI_IBS_WAKE_IND 0xFD | |
45 | #define HCI_IBS_WAKE_ACK 0xFC | |
f81b001a | 46 | #define HCI_MAX_IBS_SIZE 10 |
0ff252c1 | 47 | |
f81b001a | 48 | #define IBS_WAKE_RETRANS_TIMEOUT_MS 100 |
41d5b25f CC |
49 | #define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 40 |
50 | #define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000 | |
94d66714 | 51 | #define CMD_TRANS_TIMEOUT_MS 100 |
d841502c | 52 | #define MEMDUMP_TIMEOUT_MS 8000 |
0ff252c1 | 53 | |
05ba533c TE |
54 | /* susclk rate */ |
55 | #define SUSCLK_RATE_32KHZ 32768 | |
56 | ||
c614ca3f BG |
57 | /* Controller debug log header */ |
58 | #define QCA_DEBUG_HANDLE 0x2EDC | |
59 | ||
bb2500ab RL |
60 | /* max retry count when init fails */ |
61 | #define MAX_INIT_RETRIES 3 | |
62 | ||
d841502c BG |
63 | /* Controller dump header */ |
64 | #define QCA_SSR_DUMP_HANDLE 0x0108 | |
65 | #define QCA_DUMP_PACKET_SIZE 255 | |
66 | #define QCA_LAST_SEQUENCE_NUM 0xFFFF | |
67 | #define QCA_CRASHBYTE_PACKET_LEN 1096 | |
68 | #define QCA_MEMDUMP_BYTE 0xFB | |
69 | ||
62a91990 MK |
70 | enum qca_flags { |
71 | QCA_IBS_ENABLED, | |
2faa3f15 | 72 | QCA_DROP_VENDOR_EVENT, |
41d5b25f | 73 | QCA_SUSPENDING, |
7c2c3e63 VLNG |
74 | QCA_MEMDUMP_COLLECTION, |
75 | QCA_HW_ERROR_EVENT | |
62a91990 MK |
76 | }; |
77 | ||
a228f7a4 APS |
78 | enum qca_capabilities { |
79 | QCA_CAP_WIDEBAND_SPEECH = BIT(0), | |
80 | }; | |
d841502c | 81 | |
0ff252c1 BYTK |
82 | /* HCI_IBS transmit side sleep protocol states */ |
83 | enum tx_ibs_states { | |
84 | HCI_IBS_TX_ASLEEP, | |
85 | HCI_IBS_TX_WAKING, | |
86 | HCI_IBS_TX_AWAKE, | |
87 | }; | |
88 | ||
89 | /* HCI_IBS receive side sleep protocol states */ | |
90 | enum rx_states { | |
91 | HCI_IBS_RX_ASLEEP, | |
92 | HCI_IBS_RX_AWAKE, | |
93 | }; | |
94 | ||
95 | /* HCI_IBS transmit and receive side clock state vote */ | |
96 | enum hci_ibs_clock_state_vote { | |
97 | HCI_IBS_VOTE_STATS_UPDATE, | |
98 | HCI_IBS_TX_VOTE_CLOCK_ON, | |
99 | HCI_IBS_TX_VOTE_CLOCK_OFF, | |
100 | HCI_IBS_RX_VOTE_CLOCK_ON, | |
101 | HCI_IBS_RX_VOTE_CLOCK_OFF, | |
102 | }; | |
103 | ||
d841502c BG |
104 | /* Controller memory dump states */ |
105 | enum qca_memdump_states { | |
106 | QCA_MEMDUMP_IDLE, | |
107 | QCA_MEMDUMP_COLLECTING, | |
108 | QCA_MEMDUMP_COLLECTED, | |
109 | QCA_MEMDUMP_TIMEOUT, | |
110 | }; | |
111 | ||
112 | struct qca_memdump_data { | |
113 | char *memdump_buf_head; | |
114 | char *memdump_buf_tail; | |
115 | u32 current_seq_no; | |
116 | u32 received_dump; | |
e5aeebdd | 117 | u32 ram_dump_size; |
d841502c BG |
118 | }; |
119 | ||
120 | struct qca_memdump_event_hdr { | |
121 | __u8 evt; | |
122 | __u8 plen; | |
123 | __u16 opcode; | |
124 | __u16 seq_no; | |
125 | __u8 reserved; | |
126 | } __packed; | |
127 | ||
128 | ||
129 | struct qca_dump_size { | |
130 | u32 dump_size; | |
131 | } __packed; | |
132 | ||
0ff252c1 BYTK |
133 | struct qca_data { |
134 | struct hci_uart *hu; | |
135 | struct sk_buff *rx_skb; | |
136 | struct sk_buff_head txq; | |
137 | struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */ | |
d841502c | 138 | struct sk_buff_head rx_memdump_q; /* Memdump wait queue */ |
0ff252c1 BYTK |
139 | spinlock_t hci_ibs_lock; /* HCI_IBS state lock */ |
140 | u8 tx_ibs_state; /* HCI_IBS transmit side power state*/ | |
141 | u8 rx_ibs_state; /* HCI_IBS receive side power state */ | |
621a5f7a VK |
142 | bool tx_vote; /* Clock must be on for TX */ |
143 | bool rx_vote; /* Clock must be on for RX */ | |
0ff252c1 BYTK |
144 | struct timer_list tx_idle_timer; |
145 | u32 tx_idle_delay; | |
146 | struct timer_list wake_retrans_timer; | |
147 | u32 wake_retrans; | |
148 | struct workqueue_struct *workqueue; | |
149 | struct work_struct ws_awake_rx; | |
150 | struct work_struct ws_awake_device; | |
151 | struct work_struct ws_rx_vote_off; | |
152 | struct work_struct ws_tx_vote_off; | |
d841502c | 153 | struct work_struct ctrl_memdump_evt; |
7c2c3e63 | 154 | struct delayed_work ctrl_memdump_timeout; |
d841502c | 155 | struct qca_memdump_data *qca_memdump; |
0ff252c1 | 156 | unsigned long flags; |
2faa3f15 | 157 | struct completion drop_ev_comp; |
41d5b25f | 158 | wait_queue_head_t suspend_wait_q; |
d841502c | 159 | enum qca_memdump_states memdump_state; |
7c2c3e63 | 160 | struct mutex hci_memdump_lock; |
0ff252c1 BYTK |
161 | |
162 | /* For debugging purpose */ | |
163 | u64 ibs_sent_wacks; | |
164 | u64 ibs_sent_slps; | |
165 | u64 ibs_sent_wakes; | |
166 | u64 ibs_recv_wacks; | |
167 | u64 ibs_recv_slps; | |
168 | u64 ibs_recv_wakes; | |
169 | u64 vote_last_jif; | |
170 | u32 vote_on_ms; | |
171 | u32 vote_off_ms; | |
172 | u64 tx_votes_on; | |
173 | u64 rx_votes_on; | |
174 | u64 tx_votes_off; | |
175 | u64 rx_votes_off; | |
176 | u64 votes_on; | |
177 | u64 votes_off; | |
178 | }; | |
179 | ||
83d9c5e5 BG |
180 | enum qca_speed_type { |
181 | QCA_INIT_SPEED = 1, | |
182 | QCA_OPER_SPEED | |
183 | }; | |
184 | ||
fa9ad876 BG |
185 | /* |
186 | * Voltage regulator information required for configuring the | |
187 | * QCA Bluetooth chipset | |
188 | */ | |
189 | struct qca_vreg { | |
190 | const char *name; | |
fa9ad876 BG |
191 | unsigned int load_uA; |
192 | }; | |
193 | ||
a228f7a4 | 194 | struct qca_device_data { |
fa9ad876 BG |
195 | enum qca_btsoc_type soc_type; |
196 | struct qca_vreg *vregs; | |
197 | size_t num_vregs; | |
a228f7a4 | 198 | uint32_t capabilities; |
fa9ad876 BG |
199 | }; |
200 | ||
201 | /* | |
202 | * Platform data for the QCA Bluetooth power driver. | |
203 | */ | |
204 | struct qca_power { | |
205 | struct device *dev; | |
fa9ad876 | 206 | struct regulator_bulk_data *vreg_bulk; |
163d42fa | 207 | int num_vregs; |
fa9ad876 BG |
208 | bool vregs_on; |
209 | }; | |
210 | ||
05ba533c TE |
211 | struct qca_serdev { |
212 | struct hci_uart serdev_hu; | |
213 | struct gpio_desc *bt_en; | |
214 | struct clk *susclk; | |
fa9ad876 BG |
215 | enum qca_btsoc_type btsoc_type; |
216 | struct qca_power *bt_power; | |
217 | u32 init_speed; | |
218 | u32 oper_speed; | |
99c905c6 | 219 | const char *firmware_name; |
05ba533c TE |
220 | }; |
221 | ||
a9314e76 BA |
222 | static int qca_regulator_enable(struct qca_serdev *qcadev); |
223 | static void qca_regulator_disable(struct qca_serdev *qcadev); | |
c2d78273 | 224 | static void qca_power_shutdown(struct hci_uart *hu); |
3e4be65e | 225 | static int qca_power_off(struct hci_dev *hdev); |
d841502c | 226 | static void qca_controller_memdump(struct work_struct *work); |
fa9ad876 | 227 | |
4fdd5a4f MK |
228 | static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu) |
229 | { | |
230 | enum qca_btsoc_type soc_type; | |
231 | ||
232 | if (hu->serdev) { | |
233 | struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev); | |
234 | ||
235 | soc_type = qsd->btsoc_type; | |
236 | } else { | |
237 | soc_type = QCA_ROME; | |
238 | } | |
239 | ||
240 | return soc_type; | |
241 | } | |
242 | ||
99c905c6 RL |
243 | static const char *qca_get_firmware_name(struct hci_uart *hu) |
244 | { | |
245 | if (hu->serdev) { | |
246 | struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev); | |
247 | ||
248 | return qsd->firmware_name; | |
249 | } else { | |
250 | return NULL; | |
251 | } | |
252 | } | |
253 | ||
0ff252c1 BYTK |
254 | static void __serial_clock_on(struct tty_struct *tty) |
255 | { | |
256 | /* TODO: Some chipset requires to enable UART clock on client | |
257 | * side to save power consumption or manual work is required. | |
258 | * Please put your code to control UART clock here if needed | |
259 | */ | |
260 | } | |
261 | ||
262 | static void __serial_clock_off(struct tty_struct *tty) | |
263 | { | |
264 | /* TODO: Some chipset requires to disable UART clock on client | |
265 | * side to save power consumption or manual work is required. | |
266 | * Please put your code to control UART clock off here if needed | |
267 | */ | |
268 | } | |
269 | ||
270 | /* serial_clock_vote needs to be called with the ibs lock held */ | |
271 | static void serial_clock_vote(unsigned long vote, struct hci_uart *hu) | |
272 | { | |
273 | struct qca_data *qca = hu->priv; | |
274 | unsigned int diff; | |
275 | ||
276 | bool old_vote = (qca->tx_vote | qca->rx_vote); | |
277 | bool new_vote; | |
278 | ||
279 | switch (vote) { | |
280 | case HCI_IBS_VOTE_STATS_UPDATE: | |
281 | diff = jiffies_to_msecs(jiffies - qca->vote_last_jif); | |
282 | ||
283 | if (old_vote) | |
284 | qca->vote_off_ms += diff; | |
285 | else | |
286 | qca->vote_on_ms += diff; | |
287 | return; | |
288 | ||
289 | case HCI_IBS_TX_VOTE_CLOCK_ON: | |
290 | qca->tx_vote = true; | |
291 | qca->tx_votes_on++; | |
292 | new_vote = true; | |
293 | break; | |
294 | ||
295 | case HCI_IBS_RX_VOTE_CLOCK_ON: | |
296 | qca->rx_vote = true; | |
297 | qca->rx_votes_on++; | |
298 | new_vote = true; | |
299 | break; | |
300 | ||
301 | case HCI_IBS_TX_VOTE_CLOCK_OFF: | |
302 | qca->tx_vote = false; | |
303 | qca->tx_votes_off++; | |
304 | new_vote = qca->rx_vote | qca->tx_vote; | |
305 | break; | |
306 | ||
307 | case HCI_IBS_RX_VOTE_CLOCK_OFF: | |
308 | qca->rx_vote = false; | |
309 | qca->rx_votes_off++; | |
310 | new_vote = qca->rx_vote | qca->tx_vote; | |
311 | break; | |
312 | ||
313 | default: | |
314 | BT_ERR("Voting irregularity"); | |
315 | return; | |
316 | } | |
317 | ||
318 | if (new_vote != old_vote) { | |
319 | if (new_vote) | |
320 | __serial_clock_on(hu->tty); | |
321 | else | |
322 | __serial_clock_off(hu->tty); | |
323 | ||
ce26d813 PK |
324 | BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false", |
325 | vote ? "true" : "false"); | |
0ff252c1 BYTK |
326 | |
327 | diff = jiffies_to_msecs(jiffies - qca->vote_last_jif); | |
328 | ||
329 | if (new_vote) { | |
330 | qca->votes_on++; | |
331 | qca->vote_off_ms += diff; | |
332 | } else { | |
333 | qca->votes_off++; | |
334 | qca->vote_on_ms += diff; | |
335 | } | |
336 | qca->vote_last_jif = jiffies; | |
337 | } | |
338 | } | |
339 | ||
340 | /* Builds and sends an HCI_IBS command packet. | |
341 | * These are very simple packets with only 1 cmd byte. | |
342 | */ | |
343 | static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu) | |
344 | { | |
345 | int err = 0; | |
346 | struct sk_buff *skb = NULL; | |
347 | struct qca_data *qca = hu->priv; | |
348 | ||
349 | BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd); | |
350 | ||
351 | skb = bt_skb_alloc(1, GFP_ATOMIC); | |
352 | if (!skb) { | |
353 | BT_ERR("Failed to allocate memory for HCI_IBS packet"); | |
354 | return -ENOMEM; | |
355 | } | |
356 | ||
357 | /* Assign HCI_IBS type */ | |
634fef61 | 358 | skb_put_u8(skb, cmd); |
0ff252c1 BYTK |
359 | |
360 | skb_queue_tail(&qca->txq, skb); | |
361 | ||
362 | return err; | |
363 | } | |
364 | ||
365 | static void qca_wq_awake_device(struct work_struct *work) | |
366 | { | |
367 | struct qca_data *qca = container_of(work, struct qca_data, | |
368 | ws_awake_device); | |
369 | struct hci_uart *hu = qca->hu; | |
370 | unsigned long retrans_delay; | |
31fb1bbd | 371 | unsigned long flags; |
0ff252c1 BYTK |
372 | |
373 | BT_DBG("hu %p wq awake device", hu); | |
374 | ||
375 | /* Vote for serial clock */ | |
376 | serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu); | |
377 | ||
31fb1bbd | 378 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
379 | |
380 | /* Send wake indication to device */ | |
381 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) | |
382 | BT_ERR("Failed to send WAKE to device"); | |
383 | ||
384 | qca->ibs_sent_wakes++; | |
385 | ||
386 | /* Start retransmit timer */ | |
387 | retrans_delay = msecs_to_jiffies(qca->wake_retrans); | |
388 | mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay); | |
389 | ||
31fb1bbd | 390 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
391 | |
392 | /* Actually send the packets */ | |
393 | hci_uart_tx_wakeup(hu); | |
394 | } | |
395 | ||
396 | static void qca_wq_awake_rx(struct work_struct *work) | |
397 | { | |
398 | struct qca_data *qca = container_of(work, struct qca_data, | |
399 | ws_awake_rx); | |
400 | struct hci_uart *hu = qca->hu; | |
31fb1bbd | 401 | unsigned long flags; |
0ff252c1 BYTK |
402 | |
403 | BT_DBG("hu %p wq awake rx", hu); | |
404 | ||
405 | serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu); | |
406 | ||
31fb1bbd | 407 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
408 | qca->rx_ibs_state = HCI_IBS_RX_AWAKE; |
409 | ||
410 | /* Always acknowledge device wake up, | |
411 | * sending IBS message doesn't count as TX ON. | |
412 | */ | |
413 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) | |
414 | BT_ERR("Failed to acknowledge device wake up"); | |
415 | ||
416 | qca->ibs_sent_wacks++; | |
417 | ||
31fb1bbd | 418 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
419 | |
420 | /* Actually send the packets */ | |
421 | hci_uart_tx_wakeup(hu); | |
422 | } | |
423 | ||
424 | static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work) | |
425 | { | |
426 | struct qca_data *qca = container_of(work, struct qca_data, | |
427 | ws_rx_vote_off); | |
428 | struct hci_uart *hu = qca->hu; | |
429 | ||
430 | BT_DBG("hu %p rx clock vote off", hu); | |
431 | ||
432 | serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu); | |
433 | } | |
434 | ||
435 | static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work) | |
436 | { | |
437 | struct qca_data *qca = container_of(work, struct qca_data, | |
438 | ws_tx_vote_off); | |
439 | struct hci_uart *hu = qca->hu; | |
440 | ||
441 | BT_DBG("hu %p tx clock vote off", hu); | |
442 | ||
443 | /* Run HCI tx handling unlocked */ | |
444 | hci_uart_tx_wakeup(hu); | |
445 | ||
446 | /* Now that message queued to tty driver, vote for tty clocks off. | |
447 | * It is up to the tty driver to pend the clocks off until tx done. | |
448 | */ | |
449 | serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu); | |
450 | } | |
451 | ||
04356052 | 452 | static void hci_ibs_tx_idle_timeout(struct timer_list *t) |
0ff252c1 | 453 | { |
04356052 KC |
454 | struct qca_data *qca = from_timer(qca, t, tx_idle_timer); |
455 | struct hci_uart *hu = qca->hu; | |
0ff252c1 BYTK |
456 | unsigned long flags; |
457 | ||
458 | BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state); | |
459 | ||
460 | spin_lock_irqsave_nested(&qca->hci_ibs_lock, | |
461 | flags, SINGLE_DEPTH_NESTING); | |
462 | ||
463 | switch (qca->tx_ibs_state) { | |
464 | case HCI_IBS_TX_AWAKE: | |
465 | /* TX_IDLE, go to SLEEP */ | |
466 | if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) { | |
467 | BT_ERR("Failed to send SLEEP to device"); | |
468 | break; | |
469 | } | |
470 | qca->tx_ibs_state = HCI_IBS_TX_ASLEEP; | |
471 | qca->ibs_sent_slps++; | |
472 | queue_work(qca->workqueue, &qca->ws_tx_vote_off); | |
473 | break; | |
474 | ||
475 | case HCI_IBS_TX_ASLEEP: | |
476 | case HCI_IBS_TX_WAKING: | |
477 | /* Fall through */ | |
478 | ||
479 | default: | |
e059a465 | 480 | BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state); |
0ff252c1 BYTK |
481 | break; |
482 | } | |
483 | ||
484 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
485 | } | |
486 | ||
04356052 | 487 | static void hci_ibs_wake_retrans_timeout(struct timer_list *t) |
0ff252c1 | 488 | { |
04356052 KC |
489 | struct qca_data *qca = from_timer(qca, t, wake_retrans_timer); |
490 | struct hci_uart *hu = qca->hu; | |
0ff252c1 | 491 | unsigned long flags, retrans_delay; |
a9137188 | 492 | bool retransmit = false; |
0ff252c1 BYTK |
493 | |
494 | BT_DBG("hu %p wake retransmit timeout in %d state", | |
495 | hu, qca->tx_ibs_state); | |
496 | ||
497 | spin_lock_irqsave_nested(&qca->hci_ibs_lock, | |
498 | flags, SINGLE_DEPTH_NESTING); | |
499 | ||
41d5b25f CC |
500 | /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */ |
501 | if (test_bit(QCA_SUSPENDING, &qca->flags)) { | |
502 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
503 | return; | |
504 | } | |
505 | ||
0ff252c1 BYTK |
506 | switch (qca->tx_ibs_state) { |
507 | case HCI_IBS_TX_WAKING: | |
508 | /* No WAKE_ACK, retransmit WAKE */ | |
a9137188 | 509 | retransmit = true; |
0ff252c1 BYTK |
510 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) { |
511 | BT_ERR("Failed to acknowledge device wake up"); | |
512 | break; | |
513 | } | |
514 | qca->ibs_sent_wakes++; | |
515 | retrans_delay = msecs_to_jiffies(qca->wake_retrans); | |
516 | mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay); | |
517 | break; | |
518 | ||
519 | case HCI_IBS_TX_ASLEEP: | |
520 | case HCI_IBS_TX_AWAKE: | |
521 | /* Fall through */ | |
522 | ||
523 | default: | |
e059a465 | 524 | BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state); |
0ff252c1 BYTK |
525 | break; |
526 | } | |
527 | ||
528 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
529 | ||
530 | if (retransmit) | |
531 | hci_uart_tx_wakeup(hu); | |
532 | } | |
533 | ||
7c2c3e63 VLNG |
534 | |
535 | static void qca_controller_memdump_timeout(struct work_struct *work) | |
d841502c | 536 | { |
7c2c3e63 VLNG |
537 | struct qca_data *qca = container_of(work, struct qca_data, |
538 | ctrl_memdump_timeout.work); | |
d841502c | 539 | struct hci_uart *hu = qca->hu; |
7c2c3e63 VLNG |
540 | |
541 | mutex_lock(&qca->hci_memdump_lock); | |
542 | if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) { | |
543 | qca->memdump_state = QCA_MEMDUMP_TIMEOUT; | |
544 | if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) { | |
545 | /* Inject hw error event to reset the device | |
546 | * and driver. | |
547 | */ | |
548 | hci_reset_dev(hu->hdev); | |
549 | } | |
550 | } | |
551 | ||
552 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c BG |
553 | } |
554 | ||
7c2c3e63 | 555 | |
0ff252c1 BYTK |
556 | /* Initialize protocol */ |
557 | static int qca_open(struct hci_uart *hu) | |
558 | { | |
05ba533c | 559 | struct qca_serdev *qcadev; |
0ff252c1 BYTK |
560 | struct qca_data *qca; |
561 | ||
562 | BT_DBG("hu %p qca_open", hu); | |
563 | ||
b36a1552 VD |
564 | if (!hci_uart_has_flow_control(hu)) |
565 | return -EOPNOTSUPP; | |
566 | ||
25a13e38 | 567 | qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL); |
0ff252c1 BYTK |
568 | if (!qca) |
569 | return -ENOMEM; | |
570 | ||
571 | skb_queue_head_init(&qca->txq); | |
572 | skb_queue_head_init(&qca->tx_wait_q); | |
d841502c | 573 | skb_queue_head_init(&qca->rx_memdump_q); |
0ff252c1 | 574 | spin_lock_init(&qca->hci_ibs_lock); |
7c2c3e63 | 575 | mutex_init(&qca->hci_memdump_lock); |
fac9a602 | 576 | qca->workqueue = alloc_ordered_workqueue("qca_wq", 0); |
0ff252c1 BYTK |
577 | if (!qca->workqueue) { |
578 | BT_ERR("QCA Workqueue not initialized properly"); | |
579 | kfree(qca); | |
580 | return -ENOMEM; | |
581 | } | |
582 | ||
583 | INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx); | |
584 | INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device); | |
585 | INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off); | |
586 | INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off); | |
d841502c | 587 | INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump); |
7c2c3e63 VLNG |
588 | INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout, |
589 | qca_controller_memdump_timeout); | |
41d5b25f CC |
590 | init_waitqueue_head(&qca->suspend_wait_q); |
591 | ||
0ff252c1 | 592 | qca->hu = hu; |
2faa3f15 | 593 | init_completion(&qca->drop_ev_comp); |
0ff252c1 BYTK |
594 | |
595 | /* Assume we start with both sides asleep -- extra wakes OK */ | |
596 | qca->tx_ibs_state = HCI_IBS_TX_ASLEEP; | |
597 | qca->rx_ibs_state = HCI_IBS_RX_ASLEEP; | |
598 | ||
0ff252c1 | 599 | qca->vote_last_jif = jiffies; |
0ff252c1 BYTK |
600 | |
601 | hu->priv = qca; | |
602 | ||
05ba533c | 603 | if (hu->serdev) { |
05ba533c | 604 | qcadev = serdev_device_get_drvdata(hu->serdev); |
37aee136 CH |
605 | |
606 | if (qca_is_wcn399x(qcadev->btsoc_type)) | |
fa9ad876 | 607 | hu->init_speed = qcadev->init_speed; |
37aee136 CH |
608 | |
609 | if (qcadev->oper_speed) | |
fa9ad876 | 610 | hu->oper_speed = qcadev->oper_speed; |
05ba533c TE |
611 | } |
612 | ||
fa9ad876 BG |
613 | timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0); |
614 | qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS; | |
615 | ||
616 | timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0); | |
41d5b25f | 617 | qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS; |
fa9ad876 | 618 | |
0ff252c1 BYTK |
619 | BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u", |
620 | qca->tx_idle_delay, qca->wake_retrans); | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | static void qca_debugfs_init(struct hci_dev *hdev) | |
626 | { | |
627 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
628 | struct qca_data *qca = hu->priv; | |
629 | struct dentry *ibs_dir; | |
630 | umode_t mode; | |
631 | ||
632 | if (!hdev->debugfs) | |
633 | return; | |
634 | ||
635 | ibs_dir = debugfs_create_dir("ibs", hdev->debugfs); | |
636 | ||
637 | /* read only */ | |
638 | mode = S_IRUGO; | |
639 | debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state); | |
640 | debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state); | |
641 | debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir, | |
642 | &qca->ibs_sent_slps); | |
643 | debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir, | |
644 | &qca->ibs_sent_wakes); | |
645 | debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir, | |
646 | &qca->ibs_sent_wacks); | |
647 | debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir, | |
648 | &qca->ibs_recv_slps); | |
649 | debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir, | |
650 | &qca->ibs_recv_wakes); | |
651 | debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir, | |
652 | &qca->ibs_recv_wacks); | |
10be6c0f | 653 | debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote); |
0ff252c1 BYTK |
654 | debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on); |
655 | debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off); | |
10be6c0f | 656 | debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote); |
0ff252c1 BYTK |
657 | debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on); |
658 | debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off); | |
659 | debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on); | |
660 | debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off); | |
661 | debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms); | |
662 | debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms); | |
663 | ||
664 | /* read/write */ | |
665 | mode = S_IRUGO | S_IWUSR; | |
666 | debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans); | |
667 | debugfs_create_u32("tx_idle_delay", mode, ibs_dir, | |
668 | &qca->tx_idle_delay); | |
669 | } | |
670 | ||
671 | /* Flush protocol data */ | |
672 | static int qca_flush(struct hci_uart *hu) | |
673 | { | |
674 | struct qca_data *qca = hu->priv; | |
675 | ||
676 | BT_DBG("hu %p qca flush", hu); | |
677 | ||
678 | skb_queue_purge(&qca->tx_wait_q); | |
679 | skb_queue_purge(&qca->txq); | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
684 | /* Close protocol */ | |
685 | static int qca_close(struct hci_uart *hu) | |
686 | { | |
687 | struct qca_data *qca = hu->priv; | |
688 | ||
689 | BT_DBG("hu %p qca close", hu); | |
690 | ||
691 | serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu); | |
692 | ||
693 | skb_queue_purge(&qca->tx_wait_q); | |
694 | skb_queue_purge(&qca->txq); | |
d841502c | 695 | skb_queue_purge(&qca->rx_memdump_q); |
0ff252c1 BYTK |
696 | del_timer(&qca->tx_idle_timer); |
697 | del_timer(&qca->wake_retrans_timer); | |
698 | destroy_workqueue(qca->workqueue); | |
699 | qca->hu = NULL; | |
700 | ||
5559904c | 701 | qca_power_shutdown(hu); |
05ba533c | 702 | |
0ff252c1 BYTK |
703 | kfree_skb(qca->rx_skb); |
704 | ||
705 | hu->priv = NULL; | |
706 | ||
707 | kfree(qca); | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | /* Called upon a wake-up-indication from the device. | |
713 | */ | |
714 | static void device_want_to_wakeup(struct hci_uart *hu) | |
715 | { | |
716 | unsigned long flags; | |
717 | struct qca_data *qca = hu->priv; | |
718 | ||
719 | BT_DBG("hu %p want to wake up", hu); | |
720 | ||
721 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
722 | ||
723 | qca->ibs_recv_wakes++; | |
724 | ||
41d5b25f CC |
725 | /* Don't wake the rx up when suspending. */ |
726 | if (test_bit(QCA_SUSPENDING, &qca->flags)) { | |
727 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
728 | return; | |
729 | } | |
730 | ||
0ff252c1 BYTK |
731 | switch (qca->rx_ibs_state) { |
732 | case HCI_IBS_RX_ASLEEP: | |
733 | /* Make sure clock is on - we may have turned clock off since | |
734 | * receiving the wake up indicator awake rx clock. | |
735 | */ | |
736 | queue_work(qca->workqueue, &qca->ws_awake_rx); | |
737 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
738 | return; | |
739 | ||
740 | case HCI_IBS_RX_AWAKE: | |
741 | /* Always acknowledge device wake up, | |
742 | * sending IBS message doesn't count as TX ON. | |
743 | */ | |
744 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) { | |
745 | BT_ERR("Failed to acknowledge device wake up"); | |
746 | break; | |
747 | } | |
748 | qca->ibs_sent_wacks++; | |
749 | break; | |
750 | ||
751 | default: | |
752 | /* Any other state is illegal */ | |
753 | BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d", | |
754 | qca->rx_ibs_state); | |
755 | break; | |
756 | } | |
757 | ||
758 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
759 | ||
760 | /* Actually send the packets */ | |
761 | hci_uart_tx_wakeup(hu); | |
762 | } | |
763 | ||
764 | /* Called upon a sleep-indication from the device. | |
765 | */ | |
766 | static void device_want_to_sleep(struct hci_uart *hu) | |
767 | { | |
768 | unsigned long flags; | |
769 | struct qca_data *qca = hu->priv; | |
770 | ||
6600c080 | 771 | BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state); |
0ff252c1 BYTK |
772 | |
773 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
774 | ||
775 | qca->ibs_recv_slps++; | |
776 | ||
777 | switch (qca->rx_ibs_state) { | |
778 | case HCI_IBS_RX_AWAKE: | |
779 | /* Update state */ | |
780 | qca->rx_ibs_state = HCI_IBS_RX_ASLEEP; | |
781 | /* Vote off rx clock under workqueue */ | |
782 | queue_work(qca->workqueue, &qca->ws_rx_vote_off); | |
783 | break; | |
784 | ||
785 | case HCI_IBS_RX_ASLEEP: | |
6600c080 | 786 | break; |
0ff252c1 BYTK |
787 | |
788 | default: | |
789 | /* Any other state is illegal */ | |
790 | BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d", | |
791 | qca->rx_ibs_state); | |
792 | break; | |
793 | } | |
794 | ||
41d5b25f CC |
795 | wake_up_interruptible(&qca->suspend_wait_q); |
796 | ||
0ff252c1 BYTK |
797 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
798 | } | |
799 | ||
800 | /* Called upon wake-up-acknowledgement from the device | |
801 | */ | |
802 | static void device_woke_up(struct hci_uart *hu) | |
803 | { | |
804 | unsigned long flags, idle_delay; | |
805 | struct qca_data *qca = hu->priv; | |
806 | struct sk_buff *skb = NULL; | |
807 | ||
808 | BT_DBG("hu %p woke up", hu); | |
809 | ||
810 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
811 | ||
812 | qca->ibs_recv_wacks++; | |
813 | ||
41d5b25f CC |
814 | /* Don't react to the wake-up-acknowledgment when suspending. */ |
815 | if (test_bit(QCA_SUSPENDING, &qca->flags)) { | |
816 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
817 | return; | |
818 | } | |
819 | ||
0ff252c1 BYTK |
820 | switch (qca->tx_ibs_state) { |
821 | case HCI_IBS_TX_AWAKE: | |
822 | /* Expect one if we send 2 WAKEs */ | |
823 | BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d", | |
824 | qca->tx_ibs_state); | |
825 | break; | |
826 | ||
827 | case HCI_IBS_TX_WAKING: | |
828 | /* Send pending packets */ | |
829 | while ((skb = skb_dequeue(&qca->tx_wait_q))) | |
830 | skb_queue_tail(&qca->txq, skb); | |
831 | ||
832 | /* Switch timers and change state to HCI_IBS_TX_AWAKE */ | |
833 | del_timer(&qca->wake_retrans_timer); | |
834 | idle_delay = msecs_to_jiffies(qca->tx_idle_delay); | |
835 | mod_timer(&qca->tx_idle_timer, jiffies + idle_delay); | |
836 | qca->tx_ibs_state = HCI_IBS_TX_AWAKE; | |
837 | break; | |
838 | ||
839 | case HCI_IBS_TX_ASLEEP: | |
840 | /* Fall through */ | |
841 | ||
842 | default: | |
843 | BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d", | |
844 | qca->tx_ibs_state); | |
845 | break; | |
846 | } | |
847 | ||
848 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
849 | ||
850 | /* Actually send the packets */ | |
851 | hci_uart_tx_wakeup(hu); | |
852 | } | |
853 | ||
854 | /* Enqueue frame for transmittion (padding, crc, etc) may be called from | |
855 | * two simultaneous tasklets. | |
856 | */ | |
857 | static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb) | |
858 | { | |
859 | unsigned long flags = 0, idle_delay; | |
860 | struct qca_data *qca = hu->priv; | |
861 | ||
862 | BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb, | |
863 | qca->tx_ibs_state); | |
864 | ||
865 | /* Prepend skb with frame type */ | |
618e8bc2 | 866 | memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); |
0ff252c1 | 867 | |
035a960e BG |
868 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); |
869 | ||
0ff252c1 BYTK |
870 | /* Don't go to sleep in middle of patch download or |
871 | * Out-Of-Band(GPIOs control) sleep is selected. | |
41d5b25f | 872 | * Don't wake the device up when suspending. |
0ff252c1 | 873 | */ |
41d5b25f CC |
874 | if (!test_bit(QCA_IBS_ENABLED, &qca->flags) || |
875 | test_bit(QCA_SUSPENDING, &qca->flags)) { | |
0ff252c1 | 876 | skb_queue_tail(&qca->txq, skb); |
035a960e | 877 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
878 | return 0; |
879 | } | |
880 | ||
0ff252c1 BYTK |
881 | /* Act according to current state */ |
882 | switch (qca->tx_ibs_state) { | |
883 | case HCI_IBS_TX_AWAKE: | |
884 | BT_DBG("Device awake, sending normally"); | |
885 | skb_queue_tail(&qca->txq, skb); | |
886 | idle_delay = msecs_to_jiffies(qca->tx_idle_delay); | |
887 | mod_timer(&qca->tx_idle_timer, jiffies + idle_delay); | |
888 | break; | |
889 | ||
890 | case HCI_IBS_TX_ASLEEP: | |
891 | BT_DBG("Device asleep, waking up and queueing packet"); | |
892 | /* Save packet for later */ | |
893 | skb_queue_tail(&qca->tx_wait_q, skb); | |
894 | ||
895 | qca->tx_ibs_state = HCI_IBS_TX_WAKING; | |
896 | /* Schedule a work queue to wake up device */ | |
897 | queue_work(qca->workqueue, &qca->ws_awake_device); | |
898 | break; | |
899 | ||
900 | case HCI_IBS_TX_WAKING: | |
901 | BT_DBG("Device waking up, queueing packet"); | |
902 | /* Transient state; just keep packet for later */ | |
903 | skb_queue_tail(&qca->tx_wait_q, skb); | |
904 | break; | |
905 | ||
906 | default: | |
907 | BT_ERR("Illegal tx state: %d (losing packet)", | |
908 | qca->tx_ibs_state); | |
909 | kfree_skb(skb); | |
910 | break; | |
911 | } | |
912 | ||
913 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
914 | ||
915 | return 0; | |
916 | } | |
917 | ||
918 | static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb) | |
919 | { | |
920 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
921 | ||
922 | BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND); | |
923 | ||
924 | device_want_to_sleep(hu); | |
925 | ||
926 | kfree_skb(skb); | |
927 | return 0; | |
928 | } | |
929 | ||
930 | static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb) | |
931 | { | |
932 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
933 | ||
934 | BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND); | |
935 | ||
936 | device_want_to_wakeup(hu); | |
937 | ||
938 | kfree_skb(skb); | |
939 | return 0; | |
940 | } | |
941 | ||
942 | static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb) | |
943 | { | |
944 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
945 | ||
946 | BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK); | |
947 | ||
948 | device_woke_up(hu); | |
949 | ||
950 | kfree_skb(skb); | |
951 | return 0; | |
952 | } | |
953 | ||
c614ca3f BG |
954 | static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb) |
955 | { | |
956 | /* We receive debug logs from chip as an ACL packets. | |
957 | * Instead of sending the data to ACL to decode the | |
958 | * received data, we are pushing them to the above layers | |
959 | * as a diagnostic packet. | |
960 | */ | |
961 | if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE) | |
962 | return hci_recv_diag(hdev, skb); | |
963 | ||
964 | return hci_recv_frame(hdev, skb); | |
965 | } | |
966 | ||
d841502c BG |
967 | static void qca_controller_memdump(struct work_struct *work) |
968 | { | |
969 | struct qca_data *qca = container_of(work, struct qca_data, | |
970 | ctrl_memdump_evt); | |
971 | struct hci_uart *hu = qca->hu; | |
972 | struct sk_buff *skb; | |
973 | struct qca_memdump_event_hdr *cmd_hdr; | |
974 | struct qca_memdump_data *qca_memdump = qca->qca_memdump; | |
975 | struct qca_dump_size *dump; | |
976 | char *memdump_buf; | |
977 | char nullBuff[QCA_DUMP_PACKET_SIZE] = { 0 }; | |
56b084ed | 978 | u16 seq_no; |
d841502c | 979 | u32 dump_size; |
e5aeebdd ZH |
980 | u32 rx_size; |
981 | enum qca_btsoc_type soc_type = qca_soc_type(hu); | |
d841502c BG |
982 | |
983 | while ((skb = skb_dequeue(&qca->rx_memdump_q))) { | |
984 | ||
7c2c3e63 VLNG |
985 | mutex_lock(&qca->hci_memdump_lock); |
986 | /* Skip processing the received packets if timeout detected. */ | |
987 | if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT) { | |
988 | mutex_unlock(&qca->hci_memdump_lock); | |
989 | return; | |
990 | } | |
991 | ||
d841502c BG |
992 | if (!qca_memdump) { |
993 | qca_memdump = kzalloc(sizeof(struct qca_memdump_data), | |
994 | GFP_ATOMIC); | |
7c2c3e63 VLNG |
995 | if (!qca_memdump) { |
996 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c | 997 | return; |
7c2c3e63 | 998 | } |
d841502c BG |
999 | |
1000 | qca->qca_memdump = qca_memdump; | |
1001 | } | |
1002 | ||
1003 | qca->memdump_state = QCA_MEMDUMP_COLLECTING; | |
1004 | cmd_hdr = (void *) skb->data; | |
d841502c BG |
1005 | seq_no = __le16_to_cpu(cmd_hdr->seq_no); |
1006 | skb_pull(skb, sizeof(struct qca_memdump_event_hdr)); | |
1007 | ||
1008 | if (!seq_no) { | |
1009 | ||
1010 | /* This is the first frame of memdump packet from | |
1011 | * the controller, Disable IBS to recevie dump | |
1012 | * with out any interruption, ideally time required for | |
1013 | * the controller to send the dump is 8 seconds. let us | |
1014 | * start timer to handle this asynchronous activity. | |
1015 | */ | |
1016 | clear_bit(QCA_IBS_ENABLED, &qca->flags); | |
1017 | set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); | |
1018 | dump = (void *) skb->data; | |
1019 | dump_size = __le32_to_cpu(dump->dump_size); | |
1020 | if (!(dump_size)) { | |
1021 | bt_dev_err(hu->hdev, "Rx invalid memdump size"); | |
1022 | kfree_skb(skb); | |
7c2c3e63 | 1023 | mutex_unlock(&qca->hci_memdump_lock); |
d841502c BG |
1024 | return; |
1025 | } | |
1026 | ||
1027 | bt_dev_info(hu->hdev, "QCA collecting dump of size:%u", | |
1028 | dump_size); | |
7c2c3e63 VLNG |
1029 | queue_delayed_work(qca->workqueue, |
1030 | &qca->ctrl_memdump_timeout, | |
e5aeebdd ZH |
1031 | msecs_to_jiffies(MEMDUMP_TIMEOUT_MS) |
1032 | ); | |
d841502c BG |
1033 | |
1034 | skb_pull(skb, sizeof(dump_size)); | |
1035 | memdump_buf = vmalloc(dump_size); | |
e5aeebdd | 1036 | qca_memdump->ram_dump_size = dump_size; |
d841502c BG |
1037 | qca_memdump->memdump_buf_head = memdump_buf; |
1038 | qca_memdump->memdump_buf_tail = memdump_buf; | |
1039 | } | |
1040 | ||
1041 | memdump_buf = qca_memdump->memdump_buf_tail; | |
1042 | ||
1043 | /* If sequence no 0 is missed then there is no point in | |
1044 | * accepting the other sequences. | |
1045 | */ | |
1046 | if (!memdump_buf) { | |
1047 | bt_dev_err(hu->hdev, "QCA: Discarding other packets"); | |
1048 | kfree(qca_memdump); | |
1049 | kfree_skb(skb); | |
1050 | qca->qca_memdump = NULL; | |
7c2c3e63 | 1051 | mutex_unlock(&qca->hci_memdump_lock); |
d841502c BG |
1052 | return; |
1053 | } | |
1054 | ||
1055 | /* There could be chance of missing some packets from | |
1056 | * the controller. In such cases let us store the dummy | |
1057 | * packets in the buffer. | |
1058 | */ | |
e5aeebdd ZH |
1059 | /* For QCA6390, controller does not lost packets but |
1060 | * sequence number field of packat sometimes has error | |
1061 | * bits, so skip this checking for missing packet. | |
1062 | */ | |
d841502c | 1063 | while ((seq_no > qca_memdump->current_seq_no + 1) && |
e5aeebdd ZH |
1064 | (soc_type != QCA_QCA6390) && |
1065 | seq_no != QCA_LAST_SEQUENCE_NUM) { | |
d841502c BG |
1066 | bt_dev_err(hu->hdev, "QCA controller missed packet:%d", |
1067 | qca_memdump->current_seq_no); | |
e5aeebdd ZH |
1068 | rx_size = qca_memdump->received_dump; |
1069 | rx_size += QCA_DUMP_PACKET_SIZE; | |
1070 | if (rx_size > qca_memdump->ram_dump_size) { | |
1071 | bt_dev_err(hu->hdev, | |
1072 | "QCA memdump received %d, no space for missed packet", | |
1073 | qca_memdump->received_dump); | |
1074 | break; | |
1075 | } | |
d841502c BG |
1076 | memcpy(memdump_buf, nullBuff, QCA_DUMP_PACKET_SIZE); |
1077 | memdump_buf = memdump_buf + QCA_DUMP_PACKET_SIZE; | |
1078 | qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE; | |
1079 | qca_memdump->current_seq_no++; | |
1080 | } | |
1081 | ||
e5aeebdd ZH |
1082 | rx_size = qca_memdump->received_dump + skb->len; |
1083 | if (rx_size <= qca_memdump->ram_dump_size) { | |
1084 | if ((seq_no != QCA_LAST_SEQUENCE_NUM) && | |
1085 | (seq_no != qca_memdump->current_seq_no)) | |
1086 | bt_dev_err(hu->hdev, | |
1087 | "QCA memdump unexpected packet %d", | |
1088 | seq_no); | |
1089 | bt_dev_dbg(hu->hdev, | |
1090 | "QCA memdump packet %d with length %d", | |
1091 | seq_no, skb->len); | |
1092 | memcpy(memdump_buf, (unsigned char *)skb->data, | |
1093 | skb->len); | |
1094 | memdump_buf = memdump_buf + skb->len; | |
1095 | qca_memdump->memdump_buf_tail = memdump_buf; | |
1096 | qca_memdump->current_seq_no = seq_no + 1; | |
1097 | qca_memdump->received_dump += skb->len; | |
1098 | } else { | |
1099 | bt_dev_err(hu->hdev, | |
1100 | "QCA memdump received %d, no space for packet %d", | |
1101 | qca_memdump->received_dump, seq_no); | |
1102 | } | |
d841502c BG |
1103 | qca->qca_memdump = qca_memdump; |
1104 | kfree_skb(skb); | |
1105 | if (seq_no == QCA_LAST_SEQUENCE_NUM) { | |
e5aeebdd ZH |
1106 | bt_dev_info(hu->hdev, |
1107 | "QCA memdump Done, received %d, total %d", | |
1108 | qca_memdump->received_dump, | |
1109 | qca_memdump->ram_dump_size); | |
d841502c BG |
1110 | memdump_buf = qca_memdump->memdump_buf_head; |
1111 | dev_coredumpv(&hu->serdev->dev, memdump_buf, | |
1112 | qca_memdump->received_dump, GFP_KERNEL); | |
7c2c3e63 | 1113 | cancel_delayed_work(&qca->ctrl_memdump_timeout); |
d841502c BG |
1114 | kfree(qca->qca_memdump); |
1115 | qca->qca_memdump = NULL; | |
1116 | qca->memdump_state = QCA_MEMDUMP_COLLECTED; | |
7c2c3e63 | 1117 | clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); |
d841502c | 1118 | } |
7c2c3e63 VLNG |
1119 | |
1120 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c BG |
1121 | } |
1122 | ||
1123 | } | |
1124 | ||
7c2c3e63 VLNG |
1125 | static int qca_controller_memdump_event(struct hci_dev *hdev, |
1126 | struct sk_buff *skb) | |
d841502c BG |
1127 | { |
1128 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1129 | struct qca_data *qca = hu->priv; | |
1130 | ||
1131 | skb_queue_tail(&qca->rx_memdump_q, skb); | |
1132 | queue_work(qca->workqueue, &qca->ctrl_memdump_evt); | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
2faa3f15 MK |
1137 | static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb) |
1138 | { | |
1139 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1140 | struct qca_data *qca = hu->priv; | |
1141 | ||
1142 | if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) { | |
1143 | struct hci_event_hdr *hdr = (void *)skb->data; | |
1144 | ||
1145 | /* For the WCN3990 the vendor command for a baudrate change | |
1146 | * isn't sent as synchronous HCI command, because the | |
1147 | * controller sends the corresponding vendor event with the | |
1148 | * new baudrate. The event is received and properly decoded | |
1149 | * after changing the baudrate of the host port. It needs to | |
1150 | * be dropped, otherwise it can be misinterpreted as | |
1151 | * response to a later firmware download command (also a | |
1152 | * vendor command). | |
1153 | */ | |
1154 | ||
1155 | if (hdr->evt == HCI_EV_VENDOR) | |
1156 | complete(&qca->drop_ev_comp); | |
1157 | ||
4974c839 | 1158 | kfree_skb(skb); |
2faa3f15 MK |
1159 | |
1160 | return 0; | |
1161 | } | |
d841502c BG |
1162 | /* We receive chip memory dump as an event packet, With a dedicated |
1163 | * handler followed by a hardware error event. When this event is | |
1164 | * received we store dump into a file before closing hci. This | |
1165 | * dump will help in triaging the issues. | |
1166 | */ | |
1167 | if ((skb->data[0] == HCI_VENDOR_PKT) && | |
1168 | (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE)) | |
1169 | return qca_controller_memdump_event(hdev, skb); | |
2faa3f15 MK |
1170 | |
1171 | return hci_recv_frame(hdev, skb); | |
1172 | } | |
1173 | ||
0ff252c1 BYTK |
1174 | #define QCA_IBS_SLEEP_IND_EVENT \ |
1175 | .type = HCI_IBS_SLEEP_IND, \ | |
1176 | .hlen = 0, \ | |
1177 | .loff = 0, \ | |
1178 | .lsize = 0, \ | |
1179 | .maxlen = HCI_MAX_IBS_SIZE | |
1180 | ||
1181 | #define QCA_IBS_WAKE_IND_EVENT \ | |
1182 | .type = HCI_IBS_WAKE_IND, \ | |
1183 | .hlen = 0, \ | |
1184 | .loff = 0, \ | |
1185 | .lsize = 0, \ | |
1186 | .maxlen = HCI_MAX_IBS_SIZE | |
1187 | ||
1188 | #define QCA_IBS_WAKE_ACK_EVENT \ | |
1189 | .type = HCI_IBS_WAKE_ACK, \ | |
1190 | .hlen = 0, \ | |
1191 | .loff = 0, \ | |
1192 | .lsize = 0, \ | |
1193 | .maxlen = HCI_MAX_IBS_SIZE | |
1194 | ||
1195 | static const struct h4_recv_pkt qca_recv_pkts[] = { | |
c614ca3f | 1196 | { H4_RECV_ACL, .recv = qca_recv_acl_data }, |
0ff252c1 | 1197 | { H4_RECV_SCO, .recv = hci_recv_frame }, |
2faa3f15 | 1198 | { H4_RECV_EVENT, .recv = qca_recv_event }, |
0ff252c1 BYTK |
1199 | { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind }, |
1200 | { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack }, | |
1201 | { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind }, | |
1202 | }; | |
1203 | ||
1204 | static int qca_recv(struct hci_uart *hu, const void *data, int count) | |
1205 | { | |
1206 | struct qca_data *qca = hu->priv; | |
1207 | ||
1208 | if (!test_bit(HCI_UART_REGISTERED, &hu->flags)) | |
1209 | return -EUNATCH; | |
1210 | ||
1211 | qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count, | |
1212 | qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts)); | |
1213 | if (IS_ERR(qca->rx_skb)) { | |
1214 | int err = PTR_ERR(qca->rx_skb); | |
2064ee33 | 1215 | bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err); |
0ff252c1 BYTK |
1216 | qca->rx_skb = NULL; |
1217 | return err; | |
1218 | } | |
1219 | ||
1220 | return count; | |
1221 | } | |
1222 | ||
1223 | static struct sk_buff *qca_dequeue(struct hci_uart *hu) | |
1224 | { | |
1225 | struct qca_data *qca = hu->priv; | |
1226 | ||
1227 | return skb_dequeue(&qca->txq); | |
1228 | } | |
1229 | ||
1230 | static uint8_t qca_get_baudrate_value(int speed) | |
1231 | { | |
ce26d813 | 1232 | switch (speed) { |
0ff252c1 BYTK |
1233 | case 9600: |
1234 | return QCA_BAUDRATE_9600; | |
1235 | case 19200: | |
1236 | return QCA_BAUDRATE_19200; | |
1237 | case 38400: | |
1238 | return QCA_BAUDRATE_38400; | |
1239 | case 57600: | |
1240 | return QCA_BAUDRATE_57600; | |
1241 | case 115200: | |
1242 | return QCA_BAUDRATE_115200; | |
1243 | case 230400: | |
1244 | return QCA_BAUDRATE_230400; | |
1245 | case 460800: | |
1246 | return QCA_BAUDRATE_460800; | |
1247 | case 500000: | |
1248 | return QCA_BAUDRATE_500000; | |
1249 | case 921600: | |
1250 | return QCA_BAUDRATE_921600; | |
1251 | case 1000000: | |
1252 | return QCA_BAUDRATE_1000000; | |
1253 | case 2000000: | |
1254 | return QCA_BAUDRATE_2000000; | |
1255 | case 3000000: | |
1256 | return QCA_BAUDRATE_3000000; | |
be93a497 BG |
1257 | case 3200000: |
1258 | return QCA_BAUDRATE_3200000; | |
0ff252c1 BYTK |
1259 | case 3500000: |
1260 | return QCA_BAUDRATE_3500000; | |
1261 | default: | |
1262 | return QCA_BAUDRATE_115200; | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate) | |
1267 | { | |
1268 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1269 | struct qca_data *qca = hu->priv; | |
1270 | struct sk_buff *skb; | |
1271 | u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 }; | |
1272 | ||
be93a497 | 1273 | if (baudrate > QCA_BAUDRATE_3200000) |
0ff252c1 BYTK |
1274 | return -EINVAL; |
1275 | ||
1276 | cmd[4] = baudrate; | |
1277 | ||
25a13e38 | 1278 | skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL); |
0ff252c1 | 1279 | if (!skb) { |
2064ee33 | 1280 | bt_dev_err(hdev, "Failed to allocate baudrate packet"); |
0ff252c1 BYTK |
1281 | return -ENOMEM; |
1282 | } | |
1283 | ||
1284 | /* Assign commands to change baudrate and packet type. */ | |
59ae1d12 | 1285 | skb_put_data(skb, cmd, sizeof(cmd)); |
618e8bc2 | 1286 | hci_skb_pkt_type(skb) = HCI_COMMAND_PKT; |
0ff252c1 BYTK |
1287 | |
1288 | skb_queue_tail(&qca->txq, skb); | |
1289 | hci_uart_tx_wakeup(hu); | |
1290 | ||
94d66714 MK |
1291 | /* Wait for the baudrate change request to be sent */ |
1292 | ||
1293 | while (!skb_queue_empty(&qca->txq)) | |
1294 | usleep_range(100, 200); | |
1295 | ||
ecf2b768 MK |
1296 | if (hu->serdev) |
1297 | serdev_device_wait_until_sent(hu->serdev, | |
94d66714 MK |
1298 | msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS)); |
1299 | ||
1300 | /* Give the controller time to process the request */ | |
523760b7 | 1301 | if (qca_is_wcn399x(qca_soc_type(hu))) |
94d66714 MK |
1302 | msleep(10); |
1303 | else | |
1304 | msleep(300); | |
0ff252c1 BYTK |
1305 | |
1306 | return 0; | |
1307 | } | |
1308 | ||
05ba533c TE |
1309 | static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed) |
1310 | { | |
1311 | if (hu->serdev) | |
1312 | serdev_device_set_baudrate(hu->serdev, speed); | |
1313 | else | |
1314 | hci_uart_set_baudrate(hu, speed); | |
1315 | } | |
1316 | ||
9836b802 | 1317 | static int qca_send_power_pulse(struct hci_uart *hu, bool on) |
fa9ad876 | 1318 | { |
f9558270 | 1319 | int ret; |
94d66714 | 1320 | int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); |
9836b802 | 1321 | u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE; |
fa9ad876 BG |
1322 | |
1323 | /* These power pulses are single byte command which are sent | |
1324 | * at required baudrate to wcn3990. On wcn3990, we have an external | |
1325 | * circuit at Tx pin which decodes the pulse sent at specific baudrate. | |
1326 | * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT | |
1327 | * and also we use the same power inputs to turn on and off for | |
1328 | * Wi-Fi/BT. Powering up the power sources will not enable BT, until | |
1329 | * we send a power on pulse at 115200 bps. This algorithm will help to | |
1330 | * save power. Disabling hardware flow control is mandatory while | |
1331 | * sending power pulses to SoC. | |
1332 | */ | |
f9558270 | 1333 | bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd); |
fa9ad876 | 1334 | |
f9558270 | 1335 | serdev_device_write_flush(hu->serdev); |
fa9ad876 | 1336 | hci_uart_set_flow_control(hu, true); |
f9558270 BG |
1337 | ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd)); |
1338 | if (ret < 0) { | |
1339 | bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd); | |
1340 | return ret; | |
1341 | } | |
fa9ad876 | 1342 | |
f9558270 | 1343 | serdev_device_wait_until_sent(hu->serdev, timeout); |
fa9ad876 BG |
1344 | hci_uart_set_flow_control(hu, false); |
1345 | ||
0ebcddd8 | 1346 | /* Give to controller time to boot/shutdown */ |
ad571d72 MK |
1347 | if (on) |
1348 | msleep(100); | |
0ebcddd8 MK |
1349 | else |
1350 | msleep(10); | |
ad571d72 | 1351 | |
fa9ad876 BG |
1352 | return 0; |
1353 | } | |
1354 | ||
83d9c5e5 BG |
1355 | static unsigned int qca_get_speed(struct hci_uart *hu, |
1356 | enum qca_speed_type speed_type) | |
1357 | { | |
1358 | unsigned int speed = 0; | |
1359 | ||
1360 | if (speed_type == QCA_INIT_SPEED) { | |
1361 | if (hu->init_speed) | |
1362 | speed = hu->init_speed; | |
1363 | else if (hu->proto->init_speed) | |
1364 | speed = hu->proto->init_speed; | |
1365 | } else { | |
1366 | if (hu->oper_speed) | |
1367 | speed = hu->oper_speed; | |
1368 | else if (hu->proto->oper_speed) | |
1369 | speed = hu->proto->oper_speed; | |
1370 | } | |
1371 | ||
1372 | return speed; | |
1373 | } | |
1374 | ||
1375 | static int qca_check_speeds(struct hci_uart *hu) | |
1376 | { | |
523760b7 | 1377 | if (qca_is_wcn399x(qca_soc_type(hu))) { |
fa9ad876 BG |
1378 | if (!qca_get_speed(hu, QCA_INIT_SPEED) && |
1379 | !qca_get_speed(hu, QCA_OPER_SPEED)) | |
1380 | return -EINVAL; | |
1381 | } else { | |
1382 | if (!qca_get_speed(hu, QCA_INIT_SPEED) || | |
1383 | !qca_get_speed(hu, QCA_OPER_SPEED)) | |
1384 | return -EINVAL; | |
1385 | } | |
83d9c5e5 BG |
1386 | |
1387 | return 0; | |
1388 | } | |
1389 | ||
1390 | static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type) | |
1391 | { | |
1392 | unsigned int speed, qca_baudrate; | |
2faa3f15 | 1393 | struct qca_data *qca = hu->priv; |
78e8fa29 | 1394 | int ret = 0; |
83d9c5e5 BG |
1395 | |
1396 | if (speed_type == QCA_INIT_SPEED) { | |
1397 | speed = qca_get_speed(hu, QCA_INIT_SPEED); | |
1398 | if (speed) | |
1399 | host_set_baudrate(hu, speed); | |
1400 | } else { | |
4fdd5a4f MK |
1401 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
1402 | ||
83d9c5e5 BG |
1403 | speed = qca_get_speed(hu, QCA_OPER_SPEED); |
1404 | if (!speed) | |
1405 | return 0; | |
1406 | ||
78e8fa29 BG |
1407 | /* Disable flow control for wcn3990 to deassert RTS while |
1408 | * changing the baudrate of chip and host. | |
1409 | */ | |
523760b7 | 1410 | if (qca_is_wcn399x(soc_type)) |
78e8fa29 BG |
1411 | hci_uart_set_flow_control(hu, true); |
1412 | ||
2faa3f15 MK |
1413 | if (soc_type == QCA_WCN3990) { |
1414 | reinit_completion(&qca->drop_ev_comp); | |
1415 | set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags); | |
1416 | } | |
1417 | ||
83d9c5e5 | 1418 | qca_baudrate = qca_get_baudrate_value(speed); |
fa9ad876 | 1419 | bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed); |
83d9c5e5 BG |
1420 | ret = qca_set_baudrate(hu->hdev, qca_baudrate); |
1421 | if (ret) | |
78e8fa29 | 1422 | goto error; |
83d9c5e5 BG |
1423 | |
1424 | host_set_baudrate(hu, speed); | |
78e8fa29 BG |
1425 | |
1426 | error: | |
bba79fee | 1427 | if (qca_is_wcn399x(soc_type)) |
78e8fa29 | 1428 | hci_uart_set_flow_control(hu, false); |
2faa3f15 MK |
1429 | |
1430 | if (soc_type == QCA_WCN3990) { | |
1431 | /* Wait for the controller to send the vendor event | |
1432 | * for the baudrate change command. | |
1433 | */ | |
1434 | if (!wait_for_completion_timeout(&qca->drop_ev_comp, | |
1435 | msecs_to_jiffies(100))) { | |
1436 | bt_dev_err(hu->hdev, | |
1437 | "Failed to change controller baudrate\n"); | |
1438 | ret = -ETIMEDOUT; | |
1439 | } | |
1440 | ||
1441 | clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags); | |
1442 | } | |
83d9c5e5 BG |
1443 | } |
1444 | ||
78e8fa29 | 1445 | return ret; |
83d9c5e5 BG |
1446 | } |
1447 | ||
d841502c BG |
1448 | static int qca_send_crashbuffer(struct hci_uart *hu) |
1449 | { | |
1450 | struct qca_data *qca = hu->priv; | |
1451 | struct sk_buff *skb; | |
1452 | ||
1453 | skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL); | |
1454 | if (!skb) { | |
1455 | bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet"); | |
1456 | return -ENOMEM; | |
1457 | } | |
1458 | ||
1459 | /* We forcefully crash the controller, by sending 0xfb byte for | |
1460 | * 1024 times. We also might have chance of losing data, To be | |
1461 | * on safer side we send 1096 bytes to the SoC. | |
1462 | */ | |
1463 | memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE, | |
1464 | QCA_CRASHBYTE_PACKET_LEN); | |
1465 | hci_skb_pkt_type(skb) = HCI_COMMAND_PKT; | |
1466 | bt_dev_info(hu->hdev, "crash the soc to collect controller dump"); | |
1467 | skb_queue_tail(&qca->txq, skb); | |
1468 | hci_uart_tx_wakeup(hu); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static void qca_wait_for_dump_collection(struct hci_dev *hdev) | |
1474 | { | |
1475 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1476 | struct qca_data *qca = hu->priv; | |
d841502c BG |
1477 | |
1478 | wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION, | |
1479 | TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS); | |
1480 | ||
1481 | clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); | |
d841502c BG |
1482 | } |
1483 | ||
1484 | static void qca_hw_error(struct hci_dev *hdev, u8 code) | |
1485 | { | |
1486 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1487 | struct qca_data *qca = hu->priv; | |
7c2c3e63 VLNG |
1488 | struct qca_memdump_data *qca_memdump = qca->qca_memdump; |
1489 | char *memdump_buf = NULL; | |
d841502c | 1490 | |
7c2c3e63 | 1491 | set_bit(QCA_HW_ERROR_EVENT, &qca->flags); |
d841502c BG |
1492 | bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state); |
1493 | ||
1494 | if (qca->memdump_state == QCA_MEMDUMP_IDLE) { | |
1495 | /* If hardware error event received for other than QCA | |
1496 | * soc memory dump event, then we need to crash the SOC | |
1497 | * and wait here for 8 seconds to get the dump packets. | |
1498 | * This will block main thread to be on hold until we | |
1499 | * collect dump. | |
1500 | */ | |
1501 | set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); | |
1502 | qca_send_crashbuffer(hu); | |
1503 | qca_wait_for_dump_collection(hdev); | |
1504 | } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) { | |
1505 | /* Let us wait here until memory dump collected or | |
1506 | * memory dump timer expired. | |
1507 | */ | |
1508 | bt_dev_info(hdev, "waiting for dump to complete"); | |
1509 | qca_wait_for_dump_collection(hdev); | |
1510 | } | |
7c2c3e63 VLNG |
1511 | |
1512 | if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) { | |
1513 | bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout"); | |
1514 | mutex_lock(&qca->hci_memdump_lock); | |
1515 | if (qca_memdump) | |
1516 | memdump_buf = qca_memdump->memdump_buf_head; | |
1517 | vfree(memdump_buf); | |
1518 | kfree(qca_memdump); | |
1519 | qca->qca_memdump = NULL; | |
1520 | qca->memdump_state = QCA_MEMDUMP_TIMEOUT; | |
1521 | cancel_delayed_work(&qca->ctrl_memdump_timeout); | |
1522 | skb_queue_purge(&qca->rx_memdump_q); | |
1523 | mutex_unlock(&qca->hci_memdump_lock); | |
1524 | cancel_work_sync(&qca->ctrl_memdump_evt); | |
1525 | } | |
1526 | ||
1527 | clear_bit(QCA_HW_ERROR_EVENT, &qca->flags); | |
d841502c BG |
1528 | } |
1529 | ||
1530 | static void qca_cmd_timeout(struct hci_dev *hdev) | |
1531 | { | |
1532 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1533 | struct qca_data *qca = hu->priv; | |
1534 | ||
1535 | if (qca->memdump_state == QCA_MEMDUMP_IDLE) | |
1536 | qca_send_crashbuffer(hu); | |
1537 | else | |
1538 | bt_dev_info(hdev, "Dump collection is in process"); | |
1539 | } | |
1540 | ||
fa9ad876 BG |
1541 | static int qca_wcn3990_init(struct hci_uart *hu) |
1542 | { | |
3e4be65e | 1543 | struct qca_serdev *qcadev; |
fa9ad876 BG |
1544 | int ret; |
1545 | ||
3e4be65e BG |
1546 | /* Check for vregs status, may be hci down has turned |
1547 | * off the voltage regulator. | |
1548 | */ | |
1549 | qcadev = serdev_device_get_drvdata(hu->serdev); | |
1550 | if (!qcadev->bt_power->vregs_on) { | |
1551 | serdev_device_close(hu->serdev); | |
a9314e76 | 1552 | ret = qca_regulator_enable(qcadev); |
3e4be65e BG |
1553 | if (ret) |
1554 | return ret; | |
1555 | ||
1556 | ret = serdev_device_open(hu->serdev); | |
1557 | if (ret) { | |
1558 | bt_dev_err(hu->hdev, "failed to open port"); | |
1559 | return ret; | |
1560 | } | |
1561 | } | |
1562 | ||
fa9ad876 BG |
1563 | /* Forcefully enable wcn3990 to enter in to boot mode. */ |
1564 | host_set_baudrate(hu, 2400); | |
9836b802 | 1565 | ret = qca_send_power_pulse(hu, false); |
fa9ad876 BG |
1566 | if (ret) |
1567 | return ret; | |
1568 | ||
1569 | qca_set_speed(hu, QCA_INIT_SPEED); | |
9836b802 | 1570 | ret = qca_send_power_pulse(hu, true); |
fa9ad876 BG |
1571 | if (ret) |
1572 | return ret; | |
1573 | ||
fa9ad876 BG |
1574 | /* Now the device is in ready state to communicate with host. |
1575 | * To sync host with device we need to reopen port. | |
1576 | * Without this, we will have RTS and CTS synchronization | |
1577 | * issues. | |
1578 | */ | |
1579 | serdev_device_close(hu->serdev); | |
1580 | ret = serdev_device_open(hu->serdev); | |
1581 | if (ret) { | |
1582 | bt_dev_err(hu->hdev, "failed to open port"); | |
1583 | return ret; | |
1584 | } | |
1585 | ||
1586 | hci_uart_set_flow_control(hu, false); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
5e6d8401 RL |
1591 | static int qca_power_on(struct hci_dev *hdev) |
1592 | { | |
1593 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1594 | enum qca_btsoc_type soc_type = qca_soc_type(hu); | |
1595 | struct qca_serdev *qcadev; | |
1596 | int ret = 0; | |
1597 | ||
1598 | /* Non-serdev device usually is powered by external power | |
1599 | * and don't need additional action in driver for power on | |
1600 | */ | |
1601 | if (!hu->serdev) | |
1602 | return 0; | |
1603 | ||
1604 | if (qca_is_wcn399x(soc_type)) { | |
1605 | ret = qca_wcn3990_init(hu); | |
1606 | } else { | |
1607 | qcadev = serdev_device_get_drvdata(hu->serdev); | |
77131dfe | 1608 | if (qcadev->bt_en) { |
8a208b24 RL |
1609 | gpiod_set_value_cansleep(qcadev->bt_en, 1); |
1610 | /* Controller needs time to bootup. */ | |
1611 | msleep(150); | |
1612 | } | |
5e6d8401 RL |
1613 | } |
1614 | ||
1615 | return ret; | |
1616 | } | |
1617 | ||
0ff252c1 BYTK |
1618 | static int qca_setup(struct hci_uart *hu) |
1619 | { | |
1620 | struct hci_dev *hdev = hu->hdev; | |
1621 | struct qca_data *qca = hu->priv; | |
1622 | unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200; | |
bb2500ab | 1623 | unsigned int retries = 0; |
4fdd5a4f | 1624 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
99c905c6 | 1625 | const char *firmware_name = qca_get_firmware_name(hu); |
0ff252c1 | 1626 | int ret; |
aadebac4 | 1627 | int soc_ver = 0; |
0ff252c1 | 1628 | |
83d9c5e5 BG |
1629 | ret = qca_check_speeds(hu); |
1630 | if (ret) | |
1631 | return ret; | |
1632 | ||
0ff252c1 | 1633 | /* Patch downloading has to be done without IBS mode */ |
62a91990 | 1634 | clear_bit(QCA_IBS_ENABLED, &qca->flags); |
0ff252c1 | 1635 | |
e14c167a RL |
1636 | /* Enable controller to do both LE scan and BR/EDR inquiry |
1637 | * simultaneously. | |
1638 | */ | |
1639 | set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks); | |
1640 | ||
5e6d8401 | 1641 | bt_dev_info(hdev, "setting up %s", |
e5d6468f | 1642 | qca_is_wcn399x(soc_type) ? "wcn399x" : "ROME/QCA6390"); |
3e4be65e | 1643 | |
bb2500ab | 1644 | retry: |
5e6d8401 RL |
1645 | ret = qca_power_on(hdev); |
1646 | if (ret) | |
1647 | return ret; | |
1648 | ||
1649 | if (qca_is_wcn399x(soc_type)) { | |
5971752d | 1650 | set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks); |
fa9ad876 | 1651 | |
7d250a06 | 1652 | ret = qca_read_soc_version(hdev, &soc_ver, soc_type); |
fa9ad876 BG |
1653 | if (ret) |
1654 | return ret; | |
1655 | } else { | |
fa9ad876 BG |
1656 | qca_set_speed(hu, QCA_INIT_SPEED); |
1657 | } | |
0ff252c1 BYTK |
1658 | |
1659 | /* Setup user speed if needed */ | |
83d9c5e5 | 1660 | speed = qca_get_speed(hu, QCA_OPER_SPEED); |
0ff252c1 | 1661 | if (speed) { |
83d9c5e5 BG |
1662 | ret = qca_set_speed(hu, QCA_OPER_SPEED); |
1663 | if (ret) | |
0ff252c1 | 1664 | return ret; |
83d9c5e5 BG |
1665 | |
1666 | qca_baudrate = qca_get_baudrate_value(speed); | |
0ff252c1 BYTK |
1667 | } |
1668 | ||
523760b7 | 1669 | if (!qca_is_wcn399x(soc_type)) { |
fa9ad876 | 1670 | /* Get QCA version information */ |
7d250a06 | 1671 | ret = qca_read_soc_version(hdev, &soc_ver, soc_type); |
fa9ad876 BG |
1672 | if (ret) |
1673 | return ret; | |
1674 | } | |
aadebac4 BG |
1675 | |
1676 | bt_dev_info(hdev, "QCA controller version 0x%08x", soc_ver); | |
0ff252c1 | 1677 | /* Setup patch / NVM configurations */ |
99c905c6 RL |
1678 | ret = qca_uart_setup(hdev, qca_baudrate, soc_type, soc_ver, |
1679 | firmware_name); | |
0ff252c1 | 1680 | if (!ret) { |
62a91990 | 1681 | set_bit(QCA_IBS_ENABLED, &qca->flags); |
0ff252c1 | 1682 | qca_debugfs_init(hdev); |
d841502c BG |
1683 | hu->hdev->hw_error = qca_hw_error; |
1684 | hu->hdev->cmd_timeout = qca_cmd_timeout; | |
ba8f3597 LP |
1685 | } else if (ret == -ENOENT) { |
1686 | /* No patch/nvm-config found, run with original fw/config */ | |
1687 | ret = 0; | |
7dc5fe08 AP |
1688 | } else if (ret == -EAGAIN) { |
1689 | /* | |
1690 | * Userspace firmware loader will return -EAGAIN in case no | |
1691 | * patch/nvm-config is found, so run with original fw/config. | |
1692 | */ | |
1693 | ret = 0; | |
bb2500ab RL |
1694 | } else { |
1695 | if (retries < MAX_INIT_RETRIES) { | |
1696 | qca_power_shutdown(hu); | |
1697 | if (hu->serdev) { | |
1698 | serdev_device_close(hu->serdev); | |
1699 | ret = serdev_device_open(hu->serdev); | |
1700 | if (ret) { | |
1701 | bt_dev_err(hdev, "failed to open port"); | |
1702 | return ret; | |
1703 | } | |
1704 | } | |
1705 | retries++; | |
1706 | goto retry; | |
1707 | } | |
0ff252c1 BYTK |
1708 | } |
1709 | ||
1710 | /* Setup bdaddr */ | |
e5d6468f | 1711 | if (soc_type == QCA_ROME) |
5c0a1001 | 1712 | hu->hdev->set_bdaddr = qca_set_bdaddr_rome; |
e5d6468f RL |
1713 | else |
1714 | hu->hdev->set_bdaddr = qca_set_bdaddr; | |
0ff252c1 BYTK |
1715 | |
1716 | return ret; | |
1717 | } | |
1718 | ||
2edc9c5c | 1719 | static const struct hci_uart_proto qca_proto = { |
0ff252c1 BYTK |
1720 | .id = HCI_UART_QCA, |
1721 | .name = "QCA", | |
aee61f7a | 1722 | .manufacturer = 29, |
0ff252c1 BYTK |
1723 | .init_speed = 115200, |
1724 | .oper_speed = 3000000, | |
1725 | .open = qca_open, | |
1726 | .close = qca_close, | |
1727 | .flush = qca_flush, | |
1728 | .setup = qca_setup, | |
1729 | .recv = qca_recv, | |
1730 | .enqueue = qca_enqueue, | |
1731 | .dequeue = qca_dequeue, | |
1732 | }; | |
1733 | ||
a228f7a4 | 1734 | static const struct qca_device_data qca_soc_data_wcn3990 = { |
fa9ad876 BG |
1735 | .soc_type = QCA_WCN3990, |
1736 | .vregs = (struct qca_vreg []) { | |
f2edd66e BA |
1737 | { "vddio", 15000 }, |
1738 | { "vddxo", 80000 }, | |
1739 | { "vddrf", 300000 }, | |
1740 | { "vddch0", 450000 }, | |
fa9ad876 BG |
1741 | }, |
1742 | .num_vregs = 4, | |
1743 | }; | |
1744 | ||
a228f7a4 | 1745 | static const struct qca_device_data qca_soc_data_wcn3991 = { |
7d250a06 BG |
1746 | .soc_type = QCA_WCN3991, |
1747 | .vregs = (struct qca_vreg []) { | |
1748 | { "vddio", 15000 }, | |
1749 | { "vddxo", 80000 }, | |
1750 | { "vddrf", 300000 }, | |
1751 | { "vddch0", 450000 }, | |
1752 | }, | |
1753 | .num_vregs = 4, | |
a228f7a4 | 1754 | .capabilities = QCA_CAP_WIDEBAND_SPEECH, |
7d250a06 BG |
1755 | }; |
1756 | ||
a228f7a4 | 1757 | static const struct qca_device_data qca_soc_data_wcn3998 = { |
523760b7 HB |
1758 | .soc_type = QCA_WCN3998, |
1759 | .vregs = (struct qca_vreg []) { | |
f2edd66e BA |
1760 | { "vddio", 10000 }, |
1761 | { "vddxo", 80000 }, | |
1762 | { "vddrf", 300000 }, | |
1763 | { "vddch0", 450000 }, | |
523760b7 HB |
1764 | }, |
1765 | .num_vregs = 4, | |
1766 | }; | |
1767 | ||
a228f7a4 | 1768 | static const struct qca_device_data qca_soc_data_qca6390 = { |
e5d6468f RL |
1769 | .soc_type = QCA_QCA6390, |
1770 | .num_vregs = 0, | |
1771 | }; | |
1772 | ||
c2d78273 | 1773 | static void qca_power_shutdown(struct hci_uart *hu) |
fa9ad876 | 1774 | { |
a9314e76 | 1775 | struct qca_serdev *qcadev; |
035a960e BG |
1776 | struct qca_data *qca = hu->priv; |
1777 | unsigned long flags; | |
5559904c | 1778 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
035a960e | 1779 | |
a9314e76 BA |
1780 | qcadev = serdev_device_get_drvdata(hu->serdev); |
1781 | ||
035a960e BG |
1782 | /* From this point we go into power off state. But serial port is |
1783 | * still open, stop queueing the IBS data and flush all the buffered | |
1784 | * data in skb's. | |
1785 | */ | |
1786 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
62a91990 | 1787 | clear_bit(QCA_IBS_ENABLED, &qca->flags); |
035a960e BG |
1788 | qca_flush(hu); |
1789 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
1790 | ||
d841502c BG |
1791 | hu->hdev->hw_error = NULL; |
1792 | hu->hdev->cmd_timeout = NULL; | |
5559904c RL |
1793 | |
1794 | /* Non-serdev device usually is powered by external power | |
1795 | * and don't need additional action in driver for power down | |
1796 | */ | |
1797 | if (!hu->serdev) | |
1798 | return; | |
1799 | ||
1800 | if (qca_is_wcn399x(soc_type)) { | |
1801 | host_set_baudrate(hu, 2400); | |
1802 | qca_send_power_pulse(hu, false); | |
1803 | qca_regulator_disable(qcadev); | |
77131dfe | 1804 | } else if (qcadev->bt_en) { |
5559904c RL |
1805 | gpiod_set_value_cansleep(qcadev->bt_en, 0); |
1806 | } | |
fa9ad876 BG |
1807 | } |
1808 | ||
3e4be65e BG |
1809 | static int qca_power_off(struct hci_dev *hdev) |
1810 | { | |
1811 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
d841502c | 1812 | struct qca_data *qca = hu->priv; |
4f9ed5bd | 1813 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
3e4be65e | 1814 | |
d841502c | 1815 | /* Stop sending shutdown command if soc crashes. */ |
e5d6468f | 1816 | if (soc_type != QCA_ROME |
4f9ed5bd | 1817 | && qca->memdump_state == QCA_MEMDUMP_IDLE) { |
d841502c BG |
1818 | qca_send_pre_shutdown_cmd(hdev); |
1819 | usleep_range(8000, 10000); | |
1820 | } | |
010376ab | 1821 | |
d841502c | 1822 | qca->memdump_state = QCA_MEMDUMP_IDLE; |
3e4be65e BG |
1823 | qca_power_shutdown(hu); |
1824 | return 0; | |
1825 | } | |
1826 | ||
a9314e76 | 1827 | static int qca_regulator_enable(struct qca_serdev *qcadev) |
fa9ad876 | 1828 | { |
a9314e76 BA |
1829 | struct qca_power *power = qcadev->bt_power; |
1830 | int ret; | |
fa9ad876 | 1831 | |
a9314e76 BA |
1832 | /* Already enabled */ |
1833 | if (power->vregs_on) | |
1834 | return 0; | |
fa9ad876 | 1835 | |
a9314e76 | 1836 | BT_DBG("enabling %d regulators)", power->num_vregs); |
fa9ad876 | 1837 | |
a9314e76 BA |
1838 | ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk); |
1839 | if (ret) | |
1840 | return ret; | |
fa9ad876 | 1841 | |
a9314e76 | 1842 | power->vregs_on = true; |
fa9ad876 | 1843 | |
66cb7051 | 1844 | ret = clk_prepare_enable(qcadev->susclk); |
f3d63f50 | 1845 | if (ret) |
66cb7051 | 1846 | qca_regulator_disable(qcadev); |
66cb7051 | 1847 | |
f3d63f50 | 1848 | return ret; |
fa9ad876 BG |
1849 | } |
1850 | ||
a9314e76 BA |
1851 | static void qca_regulator_disable(struct qca_serdev *qcadev) |
1852 | { | |
1853 | struct qca_power *power; | |
1854 | ||
1855 | if (!qcadev) | |
1856 | return; | |
1857 | ||
1858 | power = qcadev->bt_power; | |
1859 | ||
1860 | /* Already disabled? */ | |
1861 | if (!power->vregs_on) | |
1862 | return; | |
1863 | ||
1864 | regulator_bulk_disable(power->num_vregs, power->vreg_bulk); | |
1865 | power->vregs_on = false; | |
66cb7051 | 1866 | |
f3d63f50 | 1867 | clk_disable_unprepare(qcadev->susclk); |
a9314e76 BA |
1868 | } |
1869 | ||
fa9ad876 BG |
1870 | static int qca_init_regulators(struct qca_power *qca, |
1871 | const struct qca_vreg *vregs, size_t num_vregs) | |
1872 | { | |
c29ff107 BA |
1873 | struct regulator_bulk_data *bulk; |
1874 | int ret; | |
fa9ad876 BG |
1875 | int i; |
1876 | ||
c29ff107 BA |
1877 | bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL); |
1878 | if (!bulk) | |
fa9ad876 BG |
1879 | return -ENOMEM; |
1880 | ||
1881 | for (i = 0; i < num_vregs; i++) | |
c29ff107 BA |
1882 | bulk[i].supply = vregs[i].name; |
1883 | ||
1884 | ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk); | |
1885 | if (ret < 0) | |
1886 | return ret; | |
fa9ad876 | 1887 | |
c29ff107 BA |
1888 | for (i = 0; i < num_vregs; i++) { |
1889 | ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA); | |
1890 | if (ret) | |
1891 | return ret; | |
1892 | } | |
1893 | ||
1894 | qca->vreg_bulk = bulk; | |
163d42fa | 1895 | qca->num_vregs = num_vregs; |
c29ff107 BA |
1896 | |
1897 | return 0; | |
fa9ad876 BG |
1898 | } |
1899 | ||
05ba533c TE |
1900 | static int qca_serdev_probe(struct serdev_device *serdev) |
1901 | { | |
1902 | struct qca_serdev *qcadev; | |
ae563183 | 1903 | struct hci_dev *hdev; |
a228f7a4 | 1904 | const struct qca_device_data *data; |
05ba533c | 1905 | int err; |
8a208b24 | 1906 | bool power_ctrl_enabled = true; |
05ba533c TE |
1907 | |
1908 | qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL); | |
1909 | if (!qcadev) | |
1910 | return -ENOMEM; | |
1911 | ||
1912 | qcadev->serdev_hu.serdev = serdev; | |
9f3565b8 | 1913 | data = device_get_match_data(&serdev->dev); |
05ba533c | 1914 | serdev_device_set_drvdata(serdev, qcadev); |
99c905c6 RL |
1915 | device_property_read_string(&serdev->dev, "firmware-name", |
1916 | &qcadev->firmware_name); | |
37aee136 CH |
1917 | device_property_read_u32(&serdev->dev, "max-speed", |
1918 | &qcadev->oper_speed); | |
1919 | if (!qcadev->oper_speed) | |
1920 | BT_DBG("UART will pick default operating speed"); | |
1921 | ||
523760b7 HB |
1922 | if (data && qca_is_wcn399x(data->soc_type)) { |
1923 | qcadev->btsoc_type = data->soc_type; | |
fa9ad876 BG |
1924 | qcadev->bt_power = devm_kzalloc(&serdev->dev, |
1925 | sizeof(struct qca_power), | |
1926 | GFP_KERNEL); | |
1927 | if (!qcadev->bt_power) | |
1928 | return -ENOMEM; | |
1929 | ||
1930 | qcadev->bt_power->dev = &serdev->dev; | |
fa9ad876 BG |
1931 | err = qca_init_regulators(qcadev->bt_power, data->vregs, |
1932 | data->num_vregs); | |
1933 | if (err) { | |
1934 | BT_ERR("Failed to init regulators:%d", err); | |
ae563183 | 1935 | return err; |
fa9ad876 | 1936 | } |
05ba533c | 1937 | |
fa9ad876 | 1938 | qcadev->bt_power->vregs_on = false; |
05ba533c | 1939 | |
66cb7051 VLNG |
1940 | qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL); |
1941 | if (IS_ERR(qcadev->susclk)) { | |
1942 | dev_err(&serdev->dev, "failed to acquire clk\n"); | |
1943 | return PTR_ERR(qcadev->susclk); | |
1944 | } | |
1945 | ||
fa9ad876 BG |
1946 | err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto); |
1947 | if (err) { | |
1948 | BT_ERR("wcn3990 serdev registration failed"); | |
ae563183 | 1949 | return err; |
fa9ad876 BG |
1950 | } |
1951 | } else { | |
e5d6468f RL |
1952 | if (data) |
1953 | qcadev->btsoc_type = data->soc_type; | |
1954 | else | |
1955 | qcadev->btsoc_type = QCA_ROME; | |
1956 | ||
77131dfe | 1957 | qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable", |
fa9ad876 | 1958 | GPIOD_OUT_LOW); |
77131dfe | 1959 | if (!qcadev->bt_en) { |
8a208b24 RL |
1960 | dev_warn(&serdev->dev, "failed to acquire enable gpio\n"); |
1961 | power_ctrl_enabled = false; | |
fa9ad876 | 1962 | } |
05ba533c | 1963 | |
77131dfe RL |
1964 | qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL); |
1965 | if (!qcadev->susclk) { | |
8a208b24 RL |
1966 | dev_warn(&serdev->dev, "failed to acquire clk\n"); |
1967 | } else { | |
1968 | err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ); | |
1969 | if (err) | |
1970 | return err; | |
fa9ad876 | 1971 | |
8a208b24 RL |
1972 | err = clk_prepare_enable(qcadev->susclk); |
1973 | if (err) | |
1974 | return err; | |
1975 | } | |
fa9ad876 BG |
1976 | |
1977 | err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto); | |
ae563183 RL |
1978 | if (err) { |
1979 | BT_ERR("Rome serdev registration failed"); | |
77131dfe | 1980 | if (qcadev->susclk) |
8a208b24 | 1981 | clk_disable_unprepare(qcadev->susclk); |
ae563183 RL |
1982 | return err; |
1983 | } | |
fa9ad876 BG |
1984 | } |
1985 | ||
85e90d93 APS |
1986 | hdev = qcadev->serdev_hu.hdev; |
1987 | ||
8a208b24 | 1988 | if (power_ctrl_enabled) { |
8a208b24 RL |
1989 | set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks); |
1990 | hdev->shutdown = qca_power_off; | |
1991 | } | |
05ba533c | 1992 | |
a228f7a4 APS |
1993 | /* Wideband speech support must be set per driver since it can't be |
1994 | * queried via hci. | |
1995 | */ | |
1996 | if (data && (data->capabilities & QCA_CAP_WIDEBAND_SPEECH)) | |
1997 | set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED, &hdev->quirks); | |
1998 | ||
ae563183 | 1999 | return 0; |
05ba533c TE |
2000 | } |
2001 | ||
2002 | static void qca_serdev_remove(struct serdev_device *serdev) | |
2003 | { | |
2004 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2005 | ||
523760b7 | 2006 | if (qca_is_wcn399x(qcadev->btsoc_type)) |
c2d78273 | 2007 | qca_power_shutdown(&qcadev->serdev_hu); |
77131dfe | 2008 | else if (qcadev->susclk) |
fa9ad876 | 2009 | clk_disable_unprepare(qcadev->susclk); |
05ba533c | 2010 | |
fa9ad876 | 2011 | hci_uart_unregister_device(&qcadev->serdev_hu); |
05ba533c TE |
2012 | } |
2013 | ||
7e7bbddd ZH |
2014 | static void qca_serdev_shutdown(struct device *dev) |
2015 | { | |
2016 | int ret; | |
2017 | int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); | |
2018 | struct serdev_device *serdev = to_serdev_device(dev); | |
2019 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2020 | const u8 ibs_wake_cmd[] = { 0xFD }; | |
2021 | const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 }; | |
2022 | ||
2023 | if (qcadev->btsoc_type == QCA_QCA6390) { | |
2024 | serdev_device_write_flush(serdev); | |
2025 | ret = serdev_device_write_buf(serdev, ibs_wake_cmd, | |
2026 | sizeof(ibs_wake_cmd)); | |
2027 | if (ret < 0) { | |
2028 | BT_ERR("QCA send IBS_WAKE_IND error: %d", ret); | |
2029 | return; | |
2030 | } | |
2031 | serdev_device_wait_until_sent(serdev, timeout); | |
2032 | usleep_range(8000, 10000); | |
2033 | ||
2034 | serdev_device_write_flush(serdev); | |
2035 | ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd, | |
2036 | sizeof(edl_reset_soc_cmd)); | |
2037 | if (ret < 0) { | |
2038 | BT_ERR("QCA send EDL_RESET_REQ error: %d", ret); | |
2039 | return; | |
2040 | } | |
2041 | serdev_device_wait_until_sent(serdev, timeout); | |
2042 | usleep_range(8000, 10000); | |
2043 | } | |
2044 | } | |
2045 | ||
41d5b25f CC |
2046 | static int __maybe_unused qca_suspend(struct device *dev) |
2047 | { | |
feac90d7 ZH |
2048 | struct serdev_device *serdev = to_serdev_device(dev); |
2049 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2050 | struct hci_uart *hu = &qcadev->serdev_hu; | |
41d5b25f CC |
2051 | struct qca_data *qca = hu->priv; |
2052 | unsigned long flags; | |
2053 | int ret = 0; | |
2054 | u8 cmd; | |
2055 | ||
2056 | set_bit(QCA_SUSPENDING, &qca->flags); | |
2057 | ||
2058 | /* Device is downloading patch or doesn't support in-band sleep. */ | |
2059 | if (!test_bit(QCA_IBS_ENABLED, &qca->flags)) | |
2060 | return 0; | |
2061 | ||
2062 | cancel_work_sync(&qca->ws_awake_device); | |
2063 | cancel_work_sync(&qca->ws_awake_rx); | |
2064 | ||
2065 | spin_lock_irqsave_nested(&qca->hci_ibs_lock, | |
2066 | flags, SINGLE_DEPTH_NESTING); | |
2067 | ||
2068 | switch (qca->tx_ibs_state) { | |
2069 | case HCI_IBS_TX_WAKING: | |
2070 | del_timer(&qca->wake_retrans_timer); | |
2071 | /* Fall through */ | |
2072 | case HCI_IBS_TX_AWAKE: | |
2073 | del_timer(&qca->tx_idle_timer); | |
2074 | ||
2075 | serdev_device_write_flush(hu->serdev); | |
2076 | cmd = HCI_IBS_SLEEP_IND; | |
2077 | ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd)); | |
2078 | ||
2079 | if (ret < 0) { | |
2080 | BT_ERR("Failed to send SLEEP to device"); | |
2081 | break; | |
2082 | } | |
2083 | ||
2084 | qca->tx_ibs_state = HCI_IBS_TX_ASLEEP; | |
2085 | qca->ibs_sent_slps++; | |
2086 | ||
2087 | qca_wq_serial_tx_clock_vote_off(&qca->ws_tx_vote_off); | |
2088 | break; | |
2089 | ||
2090 | case HCI_IBS_TX_ASLEEP: | |
2091 | break; | |
2092 | ||
2093 | default: | |
2094 | BT_ERR("Spurious tx state %d", qca->tx_ibs_state); | |
2095 | ret = -EINVAL; | |
2096 | break; | |
2097 | } | |
2098 | ||
2099 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
2100 | ||
2101 | if (ret < 0) | |
2102 | goto error; | |
2103 | ||
2104 | serdev_device_wait_until_sent(hu->serdev, | |
2105 | msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS)); | |
2106 | ||
2107 | /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going | |
2108 | * to sleep, so that the packet does not wake the system later. | |
2109 | */ | |
2110 | ||
2111 | ret = wait_event_interruptible_timeout(qca->suspend_wait_q, | |
2112 | qca->rx_ibs_state == HCI_IBS_RX_ASLEEP, | |
2113 | msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS)); | |
2114 | ||
2115 | if (ret > 0) | |
2116 | return 0; | |
2117 | ||
2118 | if (ret == 0) | |
2119 | ret = -ETIMEDOUT; | |
2120 | ||
2121 | error: | |
2122 | clear_bit(QCA_SUSPENDING, &qca->flags); | |
2123 | ||
2124 | return ret; | |
2125 | } | |
2126 | ||
2127 | static int __maybe_unused qca_resume(struct device *dev) | |
2128 | { | |
feac90d7 ZH |
2129 | struct serdev_device *serdev = to_serdev_device(dev); |
2130 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2131 | struct hci_uart *hu = &qcadev->serdev_hu; | |
41d5b25f CC |
2132 | struct qca_data *qca = hu->priv; |
2133 | ||
2134 | clear_bit(QCA_SUSPENDING, &qca->flags); | |
2135 | ||
2136 | return 0; | |
2137 | } | |
2138 | ||
2139 | static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume); | |
2140 | ||
e5d6468f | 2141 | #ifdef CONFIG_OF |
05ba533c TE |
2142 | static const struct of_device_id qca_bluetooth_of_match[] = { |
2143 | { .compatible = "qcom,qca6174-bt" }, | |
e5d6468f | 2144 | { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390}, |
31d4ab85 | 2145 | { .compatible = "qcom,qca9377-bt" }, |
523760b7 | 2146 | { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990}, |
7d250a06 | 2147 | { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991}, |
523760b7 | 2148 | { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998}, |
05ba533c TE |
2149 | { /* sentinel */ } |
2150 | }; | |
2151 | MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match); | |
e5d6468f RL |
2152 | #endif |
2153 | ||
2154 | #ifdef CONFIG_ACPI | |
2155 | static const struct acpi_device_id qca_bluetooth_acpi_match[] = { | |
2156 | { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2157 | { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2158 | { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2159 | { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2160 | { }, | |
2161 | }; | |
2162 | MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match); | |
2163 | #endif | |
2164 | ||
05ba533c TE |
2165 | |
2166 | static struct serdev_device_driver qca_serdev_driver = { | |
2167 | .probe = qca_serdev_probe, | |
2168 | .remove = qca_serdev_remove, | |
2169 | .driver = { | |
2170 | .name = "hci_uart_qca", | |
e5d6468f RL |
2171 | .of_match_table = of_match_ptr(qca_bluetooth_of_match), |
2172 | .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match), | |
7e7bbddd | 2173 | .shutdown = qca_serdev_shutdown, |
41d5b25f | 2174 | .pm = &qca_pm_ops, |
05ba533c TE |
2175 | }, |
2176 | }; | |
2177 | ||
0ff252c1 BYTK |
2178 | int __init qca_init(void) |
2179 | { | |
05ba533c TE |
2180 | serdev_device_driver_register(&qca_serdev_driver); |
2181 | ||
0ff252c1 BYTK |
2182 | return hci_uart_register_proto(&qca_proto); |
2183 | } | |
2184 | ||
2185 | int __exit qca_deinit(void) | |
2186 | { | |
05ba533c TE |
2187 | serdev_device_driver_unregister(&qca_serdev_driver); |
2188 | ||
0ff252c1 BYTK |
2189 | return hci_uart_unregister_proto(&qca_proto); |
2190 | } |