Bluetooth: Clear suspend tasks on unregister
[linux-2.6-block.git] / drivers / bluetooth / hci_qca.c
CommitLineData
45051539 1// SPDX-License-Identifier: GPL-2.0-only
0ff252c1
BYTK
2/*
3 * Bluetooth Software UART Qualcomm protocol
4 *
5 * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management
6 * protocol extension to H4.
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
fa9ad876 9 * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved.
0ff252c1
BYTK
10 *
11 * Acknowledgements:
12 * This file is based on hci_ll.c, which was...
13 * Written by Ohad Ben-Cohen <ohad@bencohen.org>
14 * which was in turn based on hci_h4.c, which was written
15 * by Maxim Krasnyansky and Marcel Holtmann.
0ff252c1
BYTK
16 */
17
18#include <linux/kernel.h>
05ba533c 19#include <linux/clk.h>
2faa3f15 20#include <linux/completion.h>
0ff252c1 21#include <linux/debugfs.h>
fa9ad876 22#include <linux/delay.h>
d841502c 23#include <linux/devcoredump.h>
fa9ad876 24#include <linux/device.h>
05ba533c
TE
25#include <linux/gpio/consumer.h>
26#include <linux/mod_devicetable.h>
27#include <linux/module.h>
fa9ad876 28#include <linux/of_device.h>
e5d6468f 29#include <linux/acpi.h>
fa9ad876
BG
30#include <linux/platform_device.h>
31#include <linux/regulator/consumer.h>
05ba533c 32#include <linux/serdev.h>
7c2c3e63 33#include <linux/mutex.h>
c614ca3f 34#include <asm/unaligned.h>
0ff252c1
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35
36#include <net/bluetooth/bluetooth.h>
37#include <net/bluetooth/hci_core.h>
38
39#include "hci_uart.h"
40#include "btqca.h"
41
42/* HCI_IBS protocol messages */
43#define HCI_IBS_SLEEP_IND 0xFE
44#define HCI_IBS_WAKE_IND 0xFD
45#define HCI_IBS_WAKE_ACK 0xFC
f81b001a 46#define HCI_MAX_IBS_SIZE 10
0ff252c1 47
f81b001a 48#define IBS_WAKE_RETRANS_TIMEOUT_MS 100
2d68476c 49#define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200
41d5b25f 50#define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000
94d66714 51#define CMD_TRANS_TIMEOUT_MS 100
d841502c 52#define MEMDUMP_TIMEOUT_MS 8000
0ff252c1 53
05ba533c
TE
54/* susclk rate */
55#define SUSCLK_RATE_32KHZ 32768
56
c614ca3f
BG
57/* Controller debug log header */
58#define QCA_DEBUG_HANDLE 0x2EDC
59
bb2500ab
RL
60/* max retry count when init fails */
61#define MAX_INIT_RETRIES 3
62
d841502c
BG
63/* Controller dump header */
64#define QCA_SSR_DUMP_HANDLE 0x0108
65#define QCA_DUMP_PACKET_SIZE 255
66#define QCA_LAST_SEQUENCE_NUM 0xFFFF
67#define QCA_CRASHBYTE_PACKET_LEN 1096
68#define QCA_MEMDUMP_BYTE 0xFB
69
62a91990
MK
70enum qca_flags {
71 QCA_IBS_ENABLED,
2faa3f15 72 QCA_DROP_VENDOR_EVENT,
41d5b25f 73 QCA_SUSPENDING,
7c2c3e63 74 QCA_MEMDUMP_COLLECTION,
3344537f
VLNG
75 QCA_HW_ERROR_EVENT,
76 QCA_SSR_TRIGGERED
62a91990
MK
77};
78
a228f7a4
APS
79enum qca_capabilities {
80 QCA_CAP_WIDEBAND_SPEECH = BIT(0),
81};
d841502c 82
0ff252c1
BYTK
83/* HCI_IBS transmit side sleep protocol states */
84enum tx_ibs_states {
85 HCI_IBS_TX_ASLEEP,
86 HCI_IBS_TX_WAKING,
87 HCI_IBS_TX_AWAKE,
88};
89
90/* HCI_IBS receive side sleep protocol states */
91enum rx_states {
92 HCI_IBS_RX_ASLEEP,
93 HCI_IBS_RX_AWAKE,
94};
95
96/* HCI_IBS transmit and receive side clock state vote */
97enum hci_ibs_clock_state_vote {
98 HCI_IBS_VOTE_STATS_UPDATE,
99 HCI_IBS_TX_VOTE_CLOCK_ON,
100 HCI_IBS_TX_VOTE_CLOCK_OFF,
101 HCI_IBS_RX_VOTE_CLOCK_ON,
102 HCI_IBS_RX_VOTE_CLOCK_OFF,
103};
104
d841502c
BG
105/* Controller memory dump states */
106enum qca_memdump_states {
107 QCA_MEMDUMP_IDLE,
108 QCA_MEMDUMP_COLLECTING,
109 QCA_MEMDUMP_COLLECTED,
110 QCA_MEMDUMP_TIMEOUT,
111};
112
113struct qca_memdump_data {
114 char *memdump_buf_head;
115 char *memdump_buf_tail;
116 u32 current_seq_no;
117 u32 received_dump;
e5aeebdd 118 u32 ram_dump_size;
d841502c
BG
119};
120
121struct qca_memdump_event_hdr {
122 __u8 evt;
123 __u8 plen;
124 __u16 opcode;
125 __u16 seq_no;
126 __u8 reserved;
127} __packed;
128
129
130struct qca_dump_size {
131 u32 dump_size;
132} __packed;
133
0ff252c1
BYTK
134struct qca_data {
135 struct hci_uart *hu;
136 struct sk_buff *rx_skb;
137 struct sk_buff_head txq;
138 struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */
d841502c 139 struct sk_buff_head rx_memdump_q; /* Memdump wait queue */
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140 spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
141 u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
142 u8 rx_ibs_state; /* HCI_IBS receive side power state */
621a5f7a
VK
143 bool tx_vote; /* Clock must be on for TX */
144 bool rx_vote; /* Clock must be on for RX */
0ff252c1
BYTK
145 struct timer_list tx_idle_timer;
146 u32 tx_idle_delay;
147 struct timer_list wake_retrans_timer;
148 u32 wake_retrans;
149 struct workqueue_struct *workqueue;
150 struct work_struct ws_awake_rx;
151 struct work_struct ws_awake_device;
152 struct work_struct ws_rx_vote_off;
153 struct work_struct ws_tx_vote_off;
d841502c 154 struct work_struct ctrl_memdump_evt;
7c2c3e63 155 struct delayed_work ctrl_memdump_timeout;
d841502c 156 struct qca_memdump_data *qca_memdump;
0ff252c1 157 unsigned long flags;
2faa3f15 158 struct completion drop_ev_comp;
41d5b25f 159 wait_queue_head_t suspend_wait_q;
d841502c 160 enum qca_memdump_states memdump_state;
7c2c3e63 161 struct mutex hci_memdump_lock;
0ff252c1
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162
163 /* For debugging purpose */
164 u64 ibs_sent_wacks;
165 u64 ibs_sent_slps;
166 u64 ibs_sent_wakes;
167 u64 ibs_recv_wacks;
168 u64 ibs_recv_slps;
169 u64 ibs_recv_wakes;
170 u64 vote_last_jif;
171 u32 vote_on_ms;
172 u32 vote_off_ms;
173 u64 tx_votes_on;
174 u64 rx_votes_on;
175 u64 tx_votes_off;
176 u64 rx_votes_off;
177 u64 votes_on;
178 u64 votes_off;
179};
180
83d9c5e5
BG
181enum qca_speed_type {
182 QCA_INIT_SPEED = 1,
183 QCA_OPER_SPEED
184};
185
fa9ad876
BG
186/*
187 * Voltage regulator information required for configuring the
188 * QCA Bluetooth chipset
189 */
190struct qca_vreg {
191 const char *name;
fa9ad876
BG
192 unsigned int load_uA;
193};
194
a228f7a4 195struct qca_device_data {
fa9ad876
BG
196 enum qca_btsoc_type soc_type;
197 struct qca_vreg *vregs;
198 size_t num_vregs;
a228f7a4 199 uint32_t capabilities;
fa9ad876
BG
200};
201
202/*
203 * Platform data for the QCA Bluetooth power driver.
204 */
205struct qca_power {
206 struct device *dev;
fa9ad876 207 struct regulator_bulk_data *vreg_bulk;
163d42fa 208 int num_vregs;
fa9ad876
BG
209 bool vregs_on;
210};
211
05ba533c
TE
212struct qca_serdev {
213 struct hci_uart serdev_hu;
214 struct gpio_desc *bt_en;
215 struct clk *susclk;
fa9ad876
BG
216 enum qca_btsoc_type btsoc_type;
217 struct qca_power *bt_power;
218 u32 init_speed;
219 u32 oper_speed;
99c905c6 220 const char *firmware_name;
05ba533c
TE
221};
222
a9314e76
BA
223static int qca_regulator_enable(struct qca_serdev *qcadev);
224static void qca_regulator_disable(struct qca_serdev *qcadev);
c2d78273 225static void qca_power_shutdown(struct hci_uart *hu);
3e4be65e 226static int qca_power_off(struct hci_dev *hdev);
d841502c 227static void qca_controller_memdump(struct work_struct *work);
fa9ad876 228
4fdd5a4f
MK
229static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu)
230{
231 enum qca_btsoc_type soc_type;
232
233 if (hu->serdev) {
234 struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
235
236 soc_type = qsd->btsoc_type;
237 } else {
238 soc_type = QCA_ROME;
239 }
240
241 return soc_type;
242}
243
99c905c6
RL
244static const char *qca_get_firmware_name(struct hci_uart *hu)
245{
246 if (hu->serdev) {
247 struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
248
249 return qsd->firmware_name;
250 } else {
251 return NULL;
252 }
253}
254
0ff252c1
BYTK
255static void __serial_clock_on(struct tty_struct *tty)
256{
257 /* TODO: Some chipset requires to enable UART clock on client
258 * side to save power consumption or manual work is required.
259 * Please put your code to control UART clock here if needed
260 */
261}
262
263static void __serial_clock_off(struct tty_struct *tty)
264{
265 /* TODO: Some chipset requires to disable UART clock on client
266 * side to save power consumption or manual work is required.
267 * Please put your code to control UART clock off here if needed
268 */
269}
270
271/* serial_clock_vote needs to be called with the ibs lock held */
272static void serial_clock_vote(unsigned long vote, struct hci_uart *hu)
273{
274 struct qca_data *qca = hu->priv;
275 unsigned int diff;
276
277 bool old_vote = (qca->tx_vote | qca->rx_vote);
278 bool new_vote;
279
280 switch (vote) {
281 case HCI_IBS_VOTE_STATS_UPDATE:
282 diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
283
284 if (old_vote)
285 qca->vote_off_ms += diff;
286 else
287 qca->vote_on_ms += diff;
288 return;
289
290 case HCI_IBS_TX_VOTE_CLOCK_ON:
291 qca->tx_vote = true;
292 qca->tx_votes_on++;
0ff252c1
BYTK
293 break;
294
295 case HCI_IBS_RX_VOTE_CLOCK_ON:
296 qca->rx_vote = true;
297 qca->rx_votes_on++;
0ff252c1
BYTK
298 break;
299
300 case HCI_IBS_TX_VOTE_CLOCK_OFF:
301 qca->tx_vote = false;
302 qca->tx_votes_off++;
0ff252c1
BYTK
303 break;
304
305 case HCI_IBS_RX_VOTE_CLOCK_OFF:
306 qca->rx_vote = false;
307 qca->rx_votes_off++;
0ff252c1
BYTK
308 break;
309
310 default:
311 BT_ERR("Voting irregularity");
312 return;
313 }
314
7310dd3f
MK
315 new_vote = qca->rx_vote | qca->tx_vote;
316
0ff252c1
BYTK
317 if (new_vote != old_vote) {
318 if (new_vote)
319 __serial_clock_on(hu->tty);
320 else
321 __serial_clock_off(hu->tty);
322
ce26d813
PK
323 BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false",
324 vote ? "true" : "false");
0ff252c1
BYTK
325
326 diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
327
328 if (new_vote) {
329 qca->votes_on++;
330 qca->vote_off_ms += diff;
331 } else {
332 qca->votes_off++;
333 qca->vote_on_ms += diff;
334 }
335 qca->vote_last_jif = jiffies;
336 }
337}
338
339/* Builds and sends an HCI_IBS command packet.
340 * These are very simple packets with only 1 cmd byte.
341 */
342static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu)
343{
344 int err = 0;
345 struct sk_buff *skb = NULL;
346 struct qca_data *qca = hu->priv;
347
348 BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd);
349
350 skb = bt_skb_alloc(1, GFP_ATOMIC);
351 if (!skb) {
352 BT_ERR("Failed to allocate memory for HCI_IBS packet");
353 return -ENOMEM;
354 }
355
356 /* Assign HCI_IBS type */
634fef61 357 skb_put_u8(skb, cmd);
0ff252c1
BYTK
358
359 skb_queue_tail(&qca->txq, skb);
360
361 return err;
362}
363
364static void qca_wq_awake_device(struct work_struct *work)
365{
366 struct qca_data *qca = container_of(work, struct qca_data,
367 ws_awake_device);
368 struct hci_uart *hu = qca->hu;
369 unsigned long retrans_delay;
31fb1bbd 370 unsigned long flags;
0ff252c1
BYTK
371
372 BT_DBG("hu %p wq awake device", hu);
373
374 /* Vote for serial clock */
375 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu);
376
31fb1bbd 377 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
378
379 /* Send wake indication to device */
380 if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0)
381 BT_ERR("Failed to send WAKE to device");
382
383 qca->ibs_sent_wakes++;
384
385 /* Start retransmit timer */
386 retrans_delay = msecs_to_jiffies(qca->wake_retrans);
387 mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
388
31fb1bbd 389 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
390
391 /* Actually send the packets */
392 hci_uart_tx_wakeup(hu);
393}
394
395static void qca_wq_awake_rx(struct work_struct *work)
396{
397 struct qca_data *qca = container_of(work, struct qca_data,
398 ws_awake_rx);
399 struct hci_uart *hu = qca->hu;
31fb1bbd 400 unsigned long flags;
0ff252c1
BYTK
401
402 BT_DBG("hu %p wq awake rx", hu);
403
404 serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu);
405
31fb1bbd 406 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
407 qca->rx_ibs_state = HCI_IBS_RX_AWAKE;
408
409 /* Always acknowledge device wake up,
410 * sending IBS message doesn't count as TX ON.
411 */
412 if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0)
413 BT_ERR("Failed to acknowledge device wake up");
414
415 qca->ibs_sent_wacks++;
416
31fb1bbd 417 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
418
419 /* Actually send the packets */
420 hci_uart_tx_wakeup(hu);
421}
422
423static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work)
424{
425 struct qca_data *qca = container_of(work, struct qca_data,
426 ws_rx_vote_off);
427 struct hci_uart *hu = qca->hu;
428
429 BT_DBG("hu %p rx clock vote off", hu);
430
431 serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu);
432}
433
434static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work)
435{
436 struct qca_data *qca = container_of(work, struct qca_data,
437 ws_tx_vote_off);
438 struct hci_uart *hu = qca->hu;
439
440 BT_DBG("hu %p tx clock vote off", hu);
441
442 /* Run HCI tx handling unlocked */
443 hci_uart_tx_wakeup(hu);
444
445 /* Now that message queued to tty driver, vote for tty clocks off.
446 * It is up to the tty driver to pend the clocks off until tx done.
447 */
448 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
449}
450
04356052 451static void hci_ibs_tx_idle_timeout(struct timer_list *t)
0ff252c1 452{
04356052
KC
453 struct qca_data *qca = from_timer(qca, t, tx_idle_timer);
454 struct hci_uart *hu = qca->hu;
0ff252c1
BYTK
455 unsigned long flags;
456
457 BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
458
459 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
460 flags, SINGLE_DEPTH_NESTING);
461
462 switch (qca->tx_ibs_state) {
463 case HCI_IBS_TX_AWAKE:
464 /* TX_IDLE, go to SLEEP */
465 if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) {
466 BT_ERR("Failed to send SLEEP to device");
467 break;
468 }
469 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
470 qca->ibs_sent_slps++;
471 queue_work(qca->workqueue, &qca->ws_tx_vote_off);
472 break;
473
474 case HCI_IBS_TX_ASLEEP:
475 case HCI_IBS_TX_WAKING:
0ff252c1 476 default:
e059a465 477 BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
0ff252c1
BYTK
478 break;
479 }
480
481 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
482}
483
04356052 484static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
0ff252c1 485{
04356052
KC
486 struct qca_data *qca = from_timer(qca, t, wake_retrans_timer);
487 struct hci_uart *hu = qca->hu;
0ff252c1 488 unsigned long flags, retrans_delay;
a9137188 489 bool retransmit = false;
0ff252c1
BYTK
490
491 BT_DBG("hu %p wake retransmit timeout in %d state",
492 hu, qca->tx_ibs_state);
493
494 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
495 flags, SINGLE_DEPTH_NESTING);
496
41d5b25f
CC
497 /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */
498 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
499 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
500 return;
501 }
502
0ff252c1
BYTK
503 switch (qca->tx_ibs_state) {
504 case HCI_IBS_TX_WAKING:
505 /* No WAKE_ACK, retransmit WAKE */
a9137188 506 retransmit = true;
0ff252c1
BYTK
507 if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) {
508 BT_ERR("Failed to acknowledge device wake up");
509 break;
510 }
511 qca->ibs_sent_wakes++;
512 retrans_delay = msecs_to_jiffies(qca->wake_retrans);
513 mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
514 break;
515
516 case HCI_IBS_TX_ASLEEP:
517 case HCI_IBS_TX_AWAKE:
0ff252c1 518 default:
e059a465 519 BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
0ff252c1
BYTK
520 break;
521 }
522
523 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
524
525 if (retransmit)
526 hci_uart_tx_wakeup(hu);
527}
528
7c2c3e63
VLNG
529
530static void qca_controller_memdump_timeout(struct work_struct *work)
d841502c 531{
7c2c3e63
VLNG
532 struct qca_data *qca = container_of(work, struct qca_data,
533 ctrl_memdump_timeout.work);
d841502c 534 struct hci_uart *hu = qca->hu;
7c2c3e63
VLNG
535
536 mutex_lock(&qca->hci_memdump_lock);
537 if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
538 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
539 if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
540 /* Inject hw error event to reset the device
541 * and driver.
542 */
543 hci_reset_dev(hu->hdev);
544 }
545 }
546
547 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
548}
549
7c2c3e63 550
0ff252c1
BYTK
551/* Initialize protocol */
552static int qca_open(struct hci_uart *hu)
553{
05ba533c 554 struct qca_serdev *qcadev;
0ff252c1
BYTK
555 struct qca_data *qca;
556
557 BT_DBG("hu %p qca_open", hu);
558
b36a1552
VD
559 if (!hci_uart_has_flow_control(hu))
560 return -EOPNOTSUPP;
561
25a13e38 562 qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL);
0ff252c1
BYTK
563 if (!qca)
564 return -ENOMEM;
565
566 skb_queue_head_init(&qca->txq);
567 skb_queue_head_init(&qca->tx_wait_q);
d841502c 568 skb_queue_head_init(&qca->rx_memdump_q);
0ff252c1 569 spin_lock_init(&qca->hci_ibs_lock);
7c2c3e63 570 mutex_init(&qca->hci_memdump_lock);
fac9a602 571 qca->workqueue = alloc_ordered_workqueue("qca_wq", 0);
0ff252c1
BYTK
572 if (!qca->workqueue) {
573 BT_ERR("QCA Workqueue not initialized properly");
574 kfree(qca);
575 return -ENOMEM;
576 }
577
578 INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx);
579 INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device);
580 INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off);
581 INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off);
d841502c 582 INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump);
7c2c3e63
VLNG
583 INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout,
584 qca_controller_memdump_timeout);
41d5b25f
CC
585 init_waitqueue_head(&qca->suspend_wait_q);
586
0ff252c1 587 qca->hu = hu;
2faa3f15 588 init_completion(&qca->drop_ev_comp);
0ff252c1
BYTK
589
590 /* Assume we start with both sides asleep -- extra wakes OK */
591 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
592 qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
593
0ff252c1 594 qca->vote_last_jif = jiffies;
0ff252c1
BYTK
595
596 hu->priv = qca;
597
05ba533c 598 if (hu->serdev) {
05ba533c 599 qcadev = serdev_device_get_drvdata(hu->serdev);
37aee136
CH
600
601 if (qca_is_wcn399x(qcadev->btsoc_type))
fa9ad876 602 hu->init_speed = qcadev->init_speed;
37aee136
CH
603
604 if (qcadev->oper_speed)
fa9ad876 605 hu->oper_speed = qcadev->oper_speed;
05ba533c
TE
606 }
607
fa9ad876
BG
608 timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
609 qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
610
611 timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
41d5b25f 612 qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS;
fa9ad876 613
0ff252c1
BYTK
614 BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u",
615 qca->tx_idle_delay, qca->wake_retrans);
616
617 return 0;
618}
619
620static void qca_debugfs_init(struct hci_dev *hdev)
621{
622 struct hci_uart *hu = hci_get_drvdata(hdev);
623 struct qca_data *qca = hu->priv;
624 struct dentry *ibs_dir;
625 umode_t mode;
626
627 if (!hdev->debugfs)
628 return;
629
630 ibs_dir = debugfs_create_dir("ibs", hdev->debugfs);
631
632 /* read only */
633 mode = S_IRUGO;
634 debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state);
635 debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state);
636 debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir,
637 &qca->ibs_sent_slps);
638 debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir,
639 &qca->ibs_sent_wakes);
640 debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir,
641 &qca->ibs_sent_wacks);
642 debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir,
643 &qca->ibs_recv_slps);
644 debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir,
645 &qca->ibs_recv_wakes);
646 debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir,
647 &qca->ibs_recv_wacks);
10be6c0f 648 debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote);
0ff252c1
BYTK
649 debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on);
650 debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off);
10be6c0f 651 debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote);
0ff252c1
BYTK
652 debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on);
653 debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off);
654 debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on);
655 debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off);
656 debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms);
657 debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms);
658
659 /* read/write */
660 mode = S_IRUGO | S_IWUSR;
661 debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans);
662 debugfs_create_u32("tx_idle_delay", mode, ibs_dir,
663 &qca->tx_idle_delay);
664}
665
666/* Flush protocol data */
667static int qca_flush(struct hci_uart *hu)
668{
669 struct qca_data *qca = hu->priv;
670
671 BT_DBG("hu %p qca flush", hu);
672
673 skb_queue_purge(&qca->tx_wait_q);
674 skb_queue_purge(&qca->txq);
675
676 return 0;
677}
678
679/* Close protocol */
680static int qca_close(struct hci_uart *hu)
681{
682 struct qca_data *qca = hu->priv;
683
684 BT_DBG("hu %p qca close", hu);
685
686 serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu);
687
688 skb_queue_purge(&qca->tx_wait_q);
689 skb_queue_purge(&qca->txq);
d841502c 690 skb_queue_purge(&qca->rx_memdump_q);
0ff252c1
BYTK
691 del_timer(&qca->tx_idle_timer);
692 del_timer(&qca->wake_retrans_timer);
693 destroy_workqueue(qca->workqueue);
694 qca->hu = NULL;
695
5559904c 696 qca_power_shutdown(hu);
05ba533c 697
0ff252c1
BYTK
698 kfree_skb(qca->rx_skb);
699
700 hu->priv = NULL;
701
702 kfree(qca);
703
704 return 0;
705}
706
707/* Called upon a wake-up-indication from the device.
708 */
709static void device_want_to_wakeup(struct hci_uart *hu)
710{
711 unsigned long flags;
712 struct qca_data *qca = hu->priv;
713
714 BT_DBG("hu %p want to wake up", hu);
715
716 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
717
718 qca->ibs_recv_wakes++;
719
41d5b25f
CC
720 /* Don't wake the rx up when suspending. */
721 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
722 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
723 return;
724 }
725
0ff252c1
BYTK
726 switch (qca->rx_ibs_state) {
727 case HCI_IBS_RX_ASLEEP:
728 /* Make sure clock is on - we may have turned clock off since
729 * receiving the wake up indicator awake rx clock.
730 */
731 queue_work(qca->workqueue, &qca->ws_awake_rx);
732 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
733 return;
734
735 case HCI_IBS_RX_AWAKE:
736 /* Always acknowledge device wake up,
737 * sending IBS message doesn't count as TX ON.
738 */
739 if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) {
740 BT_ERR("Failed to acknowledge device wake up");
741 break;
742 }
743 qca->ibs_sent_wacks++;
744 break;
745
746 default:
747 /* Any other state is illegal */
748 BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d",
749 qca->rx_ibs_state);
750 break;
751 }
752
753 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
754
755 /* Actually send the packets */
756 hci_uart_tx_wakeup(hu);
757}
758
759/* Called upon a sleep-indication from the device.
760 */
761static void device_want_to_sleep(struct hci_uart *hu)
762{
763 unsigned long flags;
764 struct qca_data *qca = hu->priv;
765
6600c080 766 BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state);
0ff252c1
BYTK
767
768 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
769
770 qca->ibs_recv_slps++;
771
772 switch (qca->rx_ibs_state) {
773 case HCI_IBS_RX_AWAKE:
774 /* Update state */
775 qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
776 /* Vote off rx clock under workqueue */
777 queue_work(qca->workqueue, &qca->ws_rx_vote_off);
778 break;
779
780 case HCI_IBS_RX_ASLEEP:
6600c080 781 break;
0ff252c1
BYTK
782
783 default:
784 /* Any other state is illegal */
785 BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d",
786 qca->rx_ibs_state);
787 break;
788 }
789
41d5b25f
CC
790 wake_up_interruptible(&qca->suspend_wait_q);
791
0ff252c1
BYTK
792 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
793}
794
795/* Called upon wake-up-acknowledgement from the device
796 */
797static void device_woke_up(struct hci_uart *hu)
798{
799 unsigned long flags, idle_delay;
800 struct qca_data *qca = hu->priv;
801 struct sk_buff *skb = NULL;
802
803 BT_DBG("hu %p woke up", hu);
804
805 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
806
807 qca->ibs_recv_wacks++;
808
41d5b25f
CC
809 /* Don't react to the wake-up-acknowledgment when suspending. */
810 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
811 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
812 return;
813 }
814
0ff252c1
BYTK
815 switch (qca->tx_ibs_state) {
816 case HCI_IBS_TX_AWAKE:
817 /* Expect one if we send 2 WAKEs */
818 BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d",
819 qca->tx_ibs_state);
820 break;
821
822 case HCI_IBS_TX_WAKING:
823 /* Send pending packets */
824 while ((skb = skb_dequeue(&qca->tx_wait_q)))
825 skb_queue_tail(&qca->txq, skb);
826
827 /* Switch timers and change state to HCI_IBS_TX_AWAKE */
828 del_timer(&qca->wake_retrans_timer);
829 idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
830 mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
831 qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
832 break;
833
834 case HCI_IBS_TX_ASLEEP:
0ff252c1
BYTK
835 default:
836 BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d",
837 qca->tx_ibs_state);
838 break;
839 }
840
841 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
842
843 /* Actually send the packets */
844 hci_uart_tx_wakeup(hu);
845}
846
847/* Enqueue frame for transmittion (padding, crc, etc) may be called from
848 * two simultaneous tasklets.
849 */
850static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb)
851{
852 unsigned long flags = 0, idle_delay;
853 struct qca_data *qca = hu->priv;
854
855 BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb,
856 qca->tx_ibs_state);
857
3344537f
VLNG
858 if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
859 /* As SSR is in progress, ignore the packets */
860 bt_dev_dbg(hu->hdev, "SSR is in progress");
861 kfree_skb(skb);
862 return 0;
863 }
864
0ff252c1 865 /* Prepend skb with frame type */
618e8bc2 866 memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
0ff252c1 867
035a960e
BG
868 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
869
0ff252c1
BYTK
870 /* Don't go to sleep in middle of patch download or
871 * Out-Of-Band(GPIOs control) sleep is selected.
41d5b25f 872 * Don't wake the device up when suspending.
0ff252c1 873 */
41d5b25f
CC
874 if (!test_bit(QCA_IBS_ENABLED, &qca->flags) ||
875 test_bit(QCA_SUSPENDING, &qca->flags)) {
0ff252c1 876 skb_queue_tail(&qca->txq, skb);
035a960e 877 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK
878 return 0;
879 }
880
0ff252c1
BYTK
881 /* Act according to current state */
882 switch (qca->tx_ibs_state) {
883 case HCI_IBS_TX_AWAKE:
884 BT_DBG("Device awake, sending normally");
885 skb_queue_tail(&qca->txq, skb);
886 idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
887 mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
888 break;
889
890 case HCI_IBS_TX_ASLEEP:
891 BT_DBG("Device asleep, waking up and queueing packet");
892 /* Save packet for later */
893 skb_queue_tail(&qca->tx_wait_q, skb);
894
895 qca->tx_ibs_state = HCI_IBS_TX_WAKING;
896 /* Schedule a work queue to wake up device */
897 queue_work(qca->workqueue, &qca->ws_awake_device);
898 break;
899
900 case HCI_IBS_TX_WAKING:
901 BT_DBG("Device waking up, queueing packet");
902 /* Transient state; just keep packet for later */
903 skb_queue_tail(&qca->tx_wait_q, skb);
904 break;
905
906 default:
907 BT_ERR("Illegal tx state: %d (losing packet)",
908 qca->tx_ibs_state);
909 kfree_skb(skb);
910 break;
911 }
912
913 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
914
915 return 0;
916}
917
918static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb)
919{
920 struct hci_uart *hu = hci_get_drvdata(hdev);
921
922 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND);
923
924 device_want_to_sleep(hu);
925
926 kfree_skb(skb);
927 return 0;
928}
929
930static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb)
931{
932 struct hci_uart *hu = hci_get_drvdata(hdev);
933
934 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND);
935
936 device_want_to_wakeup(hu);
937
938 kfree_skb(skb);
939 return 0;
940}
941
942static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb)
943{
944 struct hci_uart *hu = hci_get_drvdata(hdev);
945
946 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK);
947
948 device_woke_up(hu);
949
950 kfree_skb(skb);
951 return 0;
952}
953
c614ca3f
BG
954static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb)
955{
956 /* We receive debug logs from chip as an ACL packets.
957 * Instead of sending the data to ACL to decode the
958 * received data, we are pushing them to the above layers
959 * as a diagnostic packet.
960 */
961 if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE)
962 return hci_recv_diag(hdev, skb);
963
964 return hci_recv_frame(hdev, skb);
965}
966
d841502c
BG
967static void qca_controller_memdump(struct work_struct *work)
968{
969 struct qca_data *qca = container_of(work, struct qca_data,
970 ctrl_memdump_evt);
971 struct hci_uart *hu = qca->hu;
972 struct sk_buff *skb;
973 struct qca_memdump_event_hdr *cmd_hdr;
974 struct qca_memdump_data *qca_memdump = qca->qca_memdump;
975 struct qca_dump_size *dump;
976 char *memdump_buf;
977 char nullBuff[QCA_DUMP_PACKET_SIZE] = { 0 };
56b084ed 978 u16 seq_no;
d841502c 979 u32 dump_size;
e5aeebdd
ZH
980 u32 rx_size;
981 enum qca_btsoc_type soc_type = qca_soc_type(hu);
d841502c
BG
982
983 while ((skb = skb_dequeue(&qca->rx_memdump_q))) {
984
7c2c3e63 985 mutex_lock(&qca->hci_memdump_lock);
f98aa80f
VLNG
986 /* Skip processing the received packets if timeout detected
987 * or memdump collection completed.
988 */
989 if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
990 qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
7c2c3e63
VLNG
991 mutex_unlock(&qca->hci_memdump_lock);
992 return;
993 }
994
d841502c
BG
995 if (!qca_memdump) {
996 qca_memdump = kzalloc(sizeof(struct qca_memdump_data),
997 GFP_ATOMIC);
7c2c3e63
VLNG
998 if (!qca_memdump) {
999 mutex_unlock(&qca->hci_memdump_lock);
d841502c 1000 return;
7c2c3e63 1001 }
d841502c
BG
1002
1003 qca->qca_memdump = qca_memdump;
1004 }
1005
1006 qca->memdump_state = QCA_MEMDUMP_COLLECTING;
1007 cmd_hdr = (void *) skb->data;
d841502c
BG
1008 seq_no = __le16_to_cpu(cmd_hdr->seq_no);
1009 skb_pull(skb, sizeof(struct qca_memdump_event_hdr));
1010
1011 if (!seq_no) {
1012
1013 /* This is the first frame of memdump packet from
1014 * the controller, Disable IBS to recevie dump
1015 * with out any interruption, ideally time required for
1016 * the controller to send the dump is 8 seconds. let us
1017 * start timer to handle this asynchronous activity.
1018 */
1019 clear_bit(QCA_IBS_ENABLED, &qca->flags);
1020 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1021 dump = (void *) skb->data;
1022 dump_size = __le32_to_cpu(dump->dump_size);
1023 if (!(dump_size)) {
1024 bt_dev_err(hu->hdev, "Rx invalid memdump size");
1025 kfree_skb(skb);
7c2c3e63 1026 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1027 return;
1028 }
1029
1030 bt_dev_info(hu->hdev, "QCA collecting dump of size:%u",
1031 dump_size);
7c2c3e63
VLNG
1032 queue_delayed_work(qca->workqueue,
1033 &qca->ctrl_memdump_timeout,
e5aeebdd
ZH
1034 msecs_to_jiffies(MEMDUMP_TIMEOUT_MS)
1035 );
d841502c
BG
1036
1037 skb_pull(skb, sizeof(dump_size));
1038 memdump_buf = vmalloc(dump_size);
e5aeebdd 1039 qca_memdump->ram_dump_size = dump_size;
d841502c
BG
1040 qca_memdump->memdump_buf_head = memdump_buf;
1041 qca_memdump->memdump_buf_tail = memdump_buf;
1042 }
1043
1044 memdump_buf = qca_memdump->memdump_buf_tail;
1045
1046 /* If sequence no 0 is missed then there is no point in
1047 * accepting the other sequences.
1048 */
1049 if (!memdump_buf) {
1050 bt_dev_err(hu->hdev, "QCA: Discarding other packets");
1051 kfree(qca_memdump);
1052 kfree_skb(skb);
1053 qca->qca_memdump = NULL;
7c2c3e63 1054 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1055 return;
1056 }
1057
1058 /* There could be chance of missing some packets from
1059 * the controller. In such cases let us store the dummy
1060 * packets in the buffer.
1061 */
e5aeebdd
ZH
1062 /* For QCA6390, controller does not lost packets but
1063 * sequence number field of packat sometimes has error
1064 * bits, so skip this checking for missing packet.
1065 */
d841502c 1066 while ((seq_no > qca_memdump->current_seq_no + 1) &&
e5aeebdd
ZH
1067 (soc_type != QCA_QCA6390) &&
1068 seq_no != QCA_LAST_SEQUENCE_NUM) {
d841502c
BG
1069 bt_dev_err(hu->hdev, "QCA controller missed packet:%d",
1070 qca_memdump->current_seq_no);
e5aeebdd
ZH
1071 rx_size = qca_memdump->received_dump;
1072 rx_size += QCA_DUMP_PACKET_SIZE;
1073 if (rx_size > qca_memdump->ram_dump_size) {
1074 bt_dev_err(hu->hdev,
1075 "QCA memdump received %d, no space for missed packet",
1076 qca_memdump->received_dump);
1077 break;
1078 }
d841502c
BG
1079 memcpy(memdump_buf, nullBuff, QCA_DUMP_PACKET_SIZE);
1080 memdump_buf = memdump_buf + QCA_DUMP_PACKET_SIZE;
1081 qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE;
1082 qca_memdump->current_seq_no++;
1083 }
1084
e5aeebdd
ZH
1085 rx_size = qca_memdump->received_dump + skb->len;
1086 if (rx_size <= qca_memdump->ram_dump_size) {
1087 if ((seq_no != QCA_LAST_SEQUENCE_NUM) &&
1088 (seq_no != qca_memdump->current_seq_no))
1089 bt_dev_err(hu->hdev,
1090 "QCA memdump unexpected packet %d",
1091 seq_no);
1092 bt_dev_dbg(hu->hdev,
1093 "QCA memdump packet %d with length %d",
1094 seq_no, skb->len);
1095 memcpy(memdump_buf, (unsigned char *)skb->data,
1096 skb->len);
1097 memdump_buf = memdump_buf + skb->len;
1098 qca_memdump->memdump_buf_tail = memdump_buf;
1099 qca_memdump->current_seq_no = seq_no + 1;
1100 qca_memdump->received_dump += skb->len;
1101 } else {
1102 bt_dev_err(hu->hdev,
1103 "QCA memdump received %d, no space for packet %d",
1104 qca_memdump->received_dump, seq_no);
1105 }
d841502c
BG
1106 qca->qca_memdump = qca_memdump;
1107 kfree_skb(skb);
1108 if (seq_no == QCA_LAST_SEQUENCE_NUM) {
e5aeebdd
ZH
1109 bt_dev_info(hu->hdev,
1110 "QCA memdump Done, received %d, total %d",
1111 qca_memdump->received_dump,
1112 qca_memdump->ram_dump_size);
d841502c
BG
1113 memdump_buf = qca_memdump->memdump_buf_head;
1114 dev_coredumpv(&hu->serdev->dev, memdump_buf,
1115 qca_memdump->received_dump, GFP_KERNEL);
7c2c3e63 1116 cancel_delayed_work(&qca->ctrl_memdump_timeout);
d841502c
BG
1117 kfree(qca->qca_memdump);
1118 qca->qca_memdump = NULL;
1119 qca->memdump_state = QCA_MEMDUMP_COLLECTED;
7c2c3e63 1120 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c 1121 }
7c2c3e63
VLNG
1122
1123 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1124 }
1125
1126}
1127
7c2c3e63
VLNG
1128static int qca_controller_memdump_event(struct hci_dev *hdev,
1129 struct sk_buff *skb)
d841502c
BG
1130{
1131 struct hci_uart *hu = hci_get_drvdata(hdev);
1132 struct qca_data *qca = hu->priv;
1133
3344537f 1134 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
d841502c
BG
1135 skb_queue_tail(&qca->rx_memdump_q, skb);
1136 queue_work(qca->workqueue, &qca->ctrl_memdump_evt);
1137
1138 return 0;
1139}
1140
2faa3f15
MK
1141static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
1142{
1143 struct hci_uart *hu = hci_get_drvdata(hdev);
1144 struct qca_data *qca = hu->priv;
1145
1146 if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) {
1147 struct hci_event_hdr *hdr = (void *)skb->data;
1148
1149 /* For the WCN3990 the vendor command for a baudrate change
1150 * isn't sent as synchronous HCI command, because the
1151 * controller sends the corresponding vendor event with the
1152 * new baudrate. The event is received and properly decoded
1153 * after changing the baudrate of the host port. It needs to
1154 * be dropped, otherwise it can be misinterpreted as
1155 * response to a later firmware download command (also a
1156 * vendor command).
1157 */
1158
1159 if (hdr->evt == HCI_EV_VENDOR)
1160 complete(&qca->drop_ev_comp);
1161
4974c839 1162 kfree_skb(skb);
2faa3f15
MK
1163
1164 return 0;
1165 }
d841502c
BG
1166 /* We receive chip memory dump as an event packet, With a dedicated
1167 * handler followed by a hardware error event. When this event is
1168 * received we store dump into a file before closing hci. This
1169 * dump will help in triaging the issues.
1170 */
1171 if ((skb->data[0] == HCI_VENDOR_PKT) &&
1172 (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE))
1173 return qca_controller_memdump_event(hdev, skb);
2faa3f15
MK
1174
1175 return hci_recv_frame(hdev, skb);
1176}
1177
0ff252c1
BYTK
1178#define QCA_IBS_SLEEP_IND_EVENT \
1179 .type = HCI_IBS_SLEEP_IND, \
1180 .hlen = 0, \
1181 .loff = 0, \
1182 .lsize = 0, \
1183 .maxlen = HCI_MAX_IBS_SIZE
1184
1185#define QCA_IBS_WAKE_IND_EVENT \
1186 .type = HCI_IBS_WAKE_IND, \
1187 .hlen = 0, \
1188 .loff = 0, \
1189 .lsize = 0, \
1190 .maxlen = HCI_MAX_IBS_SIZE
1191
1192#define QCA_IBS_WAKE_ACK_EVENT \
1193 .type = HCI_IBS_WAKE_ACK, \
1194 .hlen = 0, \
1195 .loff = 0, \
1196 .lsize = 0, \
1197 .maxlen = HCI_MAX_IBS_SIZE
1198
1199static const struct h4_recv_pkt qca_recv_pkts[] = {
c614ca3f 1200 { H4_RECV_ACL, .recv = qca_recv_acl_data },
0ff252c1 1201 { H4_RECV_SCO, .recv = hci_recv_frame },
2faa3f15 1202 { H4_RECV_EVENT, .recv = qca_recv_event },
0ff252c1
BYTK
1203 { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind },
1204 { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack },
1205 { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind },
1206};
1207
1208static int qca_recv(struct hci_uart *hu, const void *data, int count)
1209{
1210 struct qca_data *qca = hu->priv;
1211
1212 if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
1213 return -EUNATCH;
1214
1215 qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count,
1216 qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts));
1217 if (IS_ERR(qca->rx_skb)) {
1218 int err = PTR_ERR(qca->rx_skb);
2064ee33 1219 bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
0ff252c1
BYTK
1220 qca->rx_skb = NULL;
1221 return err;
1222 }
1223
1224 return count;
1225}
1226
1227static struct sk_buff *qca_dequeue(struct hci_uart *hu)
1228{
1229 struct qca_data *qca = hu->priv;
1230
1231 return skb_dequeue(&qca->txq);
1232}
1233
1234static uint8_t qca_get_baudrate_value(int speed)
1235{
ce26d813 1236 switch (speed) {
0ff252c1
BYTK
1237 case 9600:
1238 return QCA_BAUDRATE_9600;
1239 case 19200:
1240 return QCA_BAUDRATE_19200;
1241 case 38400:
1242 return QCA_BAUDRATE_38400;
1243 case 57600:
1244 return QCA_BAUDRATE_57600;
1245 case 115200:
1246 return QCA_BAUDRATE_115200;
1247 case 230400:
1248 return QCA_BAUDRATE_230400;
1249 case 460800:
1250 return QCA_BAUDRATE_460800;
1251 case 500000:
1252 return QCA_BAUDRATE_500000;
1253 case 921600:
1254 return QCA_BAUDRATE_921600;
1255 case 1000000:
1256 return QCA_BAUDRATE_1000000;
1257 case 2000000:
1258 return QCA_BAUDRATE_2000000;
1259 case 3000000:
1260 return QCA_BAUDRATE_3000000;
be93a497
BG
1261 case 3200000:
1262 return QCA_BAUDRATE_3200000;
0ff252c1
BYTK
1263 case 3500000:
1264 return QCA_BAUDRATE_3500000;
1265 default:
1266 return QCA_BAUDRATE_115200;
1267 }
1268}
1269
1270static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)
1271{
1272 struct hci_uart *hu = hci_get_drvdata(hdev);
1273 struct qca_data *qca = hu->priv;
1274 struct sk_buff *skb;
1275 u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 };
1276
be93a497 1277 if (baudrate > QCA_BAUDRATE_3200000)
0ff252c1
BYTK
1278 return -EINVAL;
1279
1280 cmd[4] = baudrate;
1281
25a13e38 1282 skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
0ff252c1 1283 if (!skb) {
2064ee33 1284 bt_dev_err(hdev, "Failed to allocate baudrate packet");
0ff252c1
BYTK
1285 return -ENOMEM;
1286 }
1287
1288 /* Assign commands to change baudrate and packet type. */
59ae1d12 1289 skb_put_data(skb, cmd, sizeof(cmd));
618e8bc2 1290 hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
0ff252c1
BYTK
1291
1292 skb_queue_tail(&qca->txq, skb);
1293 hci_uart_tx_wakeup(hu);
1294
94d66714
MK
1295 /* Wait for the baudrate change request to be sent */
1296
1297 while (!skb_queue_empty(&qca->txq))
1298 usleep_range(100, 200);
1299
ecf2b768
MK
1300 if (hu->serdev)
1301 serdev_device_wait_until_sent(hu->serdev,
94d66714
MK
1302 msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
1303
1304 /* Give the controller time to process the request */
523760b7 1305 if (qca_is_wcn399x(qca_soc_type(hu)))
94d66714
MK
1306 msleep(10);
1307 else
1308 msleep(300);
0ff252c1
BYTK
1309
1310 return 0;
1311}
1312
05ba533c
TE
1313static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed)
1314{
1315 if (hu->serdev)
1316 serdev_device_set_baudrate(hu->serdev, speed);
1317 else
1318 hci_uart_set_baudrate(hu, speed);
1319}
1320
9836b802 1321static int qca_send_power_pulse(struct hci_uart *hu, bool on)
fa9ad876 1322{
f9558270 1323 int ret;
94d66714 1324 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
9836b802 1325 u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE;
fa9ad876
BG
1326
1327 /* These power pulses are single byte command which are sent
1328 * at required baudrate to wcn3990. On wcn3990, we have an external
1329 * circuit at Tx pin which decodes the pulse sent at specific baudrate.
1330 * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT
1331 * and also we use the same power inputs to turn on and off for
1332 * Wi-Fi/BT. Powering up the power sources will not enable BT, until
1333 * we send a power on pulse at 115200 bps. This algorithm will help to
1334 * save power. Disabling hardware flow control is mandatory while
1335 * sending power pulses to SoC.
1336 */
f9558270 1337 bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd);
fa9ad876 1338
f9558270 1339 serdev_device_write_flush(hu->serdev);
fa9ad876 1340 hci_uart_set_flow_control(hu, true);
f9558270
BG
1341 ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
1342 if (ret < 0) {
1343 bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd);
1344 return ret;
1345 }
fa9ad876 1346
f9558270 1347 serdev_device_wait_until_sent(hu->serdev, timeout);
fa9ad876
BG
1348 hci_uart_set_flow_control(hu, false);
1349
0ebcddd8 1350 /* Give to controller time to boot/shutdown */
ad571d72
MK
1351 if (on)
1352 msleep(100);
0ebcddd8
MK
1353 else
1354 msleep(10);
ad571d72 1355
fa9ad876
BG
1356 return 0;
1357}
1358
83d9c5e5
BG
1359static unsigned int qca_get_speed(struct hci_uart *hu,
1360 enum qca_speed_type speed_type)
1361{
1362 unsigned int speed = 0;
1363
1364 if (speed_type == QCA_INIT_SPEED) {
1365 if (hu->init_speed)
1366 speed = hu->init_speed;
1367 else if (hu->proto->init_speed)
1368 speed = hu->proto->init_speed;
1369 } else {
1370 if (hu->oper_speed)
1371 speed = hu->oper_speed;
1372 else if (hu->proto->oper_speed)
1373 speed = hu->proto->oper_speed;
1374 }
1375
1376 return speed;
1377}
1378
1379static int qca_check_speeds(struct hci_uart *hu)
1380{
523760b7 1381 if (qca_is_wcn399x(qca_soc_type(hu))) {
fa9ad876
BG
1382 if (!qca_get_speed(hu, QCA_INIT_SPEED) &&
1383 !qca_get_speed(hu, QCA_OPER_SPEED))
1384 return -EINVAL;
1385 } else {
1386 if (!qca_get_speed(hu, QCA_INIT_SPEED) ||
1387 !qca_get_speed(hu, QCA_OPER_SPEED))
1388 return -EINVAL;
1389 }
83d9c5e5
BG
1390
1391 return 0;
1392}
1393
1394static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type)
1395{
1396 unsigned int speed, qca_baudrate;
2faa3f15 1397 struct qca_data *qca = hu->priv;
78e8fa29 1398 int ret = 0;
83d9c5e5
BG
1399
1400 if (speed_type == QCA_INIT_SPEED) {
1401 speed = qca_get_speed(hu, QCA_INIT_SPEED);
1402 if (speed)
1403 host_set_baudrate(hu, speed);
1404 } else {
4fdd5a4f
MK
1405 enum qca_btsoc_type soc_type = qca_soc_type(hu);
1406
83d9c5e5
BG
1407 speed = qca_get_speed(hu, QCA_OPER_SPEED);
1408 if (!speed)
1409 return 0;
1410
78e8fa29
BG
1411 /* Disable flow control for wcn3990 to deassert RTS while
1412 * changing the baudrate of chip and host.
1413 */
523760b7 1414 if (qca_is_wcn399x(soc_type))
78e8fa29
BG
1415 hci_uart_set_flow_control(hu, true);
1416
2faa3f15
MK
1417 if (soc_type == QCA_WCN3990) {
1418 reinit_completion(&qca->drop_ev_comp);
1419 set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
1420 }
1421
83d9c5e5 1422 qca_baudrate = qca_get_baudrate_value(speed);
fa9ad876 1423 bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed);
83d9c5e5
BG
1424 ret = qca_set_baudrate(hu->hdev, qca_baudrate);
1425 if (ret)
78e8fa29 1426 goto error;
83d9c5e5
BG
1427
1428 host_set_baudrate(hu, speed);
78e8fa29
BG
1429
1430error:
bba79fee 1431 if (qca_is_wcn399x(soc_type))
78e8fa29 1432 hci_uart_set_flow_control(hu, false);
2faa3f15
MK
1433
1434 if (soc_type == QCA_WCN3990) {
1435 /* Wait for the controller to send the vendor event
1436 * for the baudrate change command.
1437 */
1438 if (!wait_for_completion_timeout(&qca->drop_ev_comp,
1439 msecs_to_jiffies(100))) {
1440 bt_dev_err(hu->hdev,
1441 "Failed to change controller baudrate\n");
1442 ret = -ETIMEDOUT;
1443 }
1444
1445 clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
1446 }
83d9c5e5
BG
1447 }
1448
78e8fa29 1449 return ret;
83d9c5e5
BG
1450}
1451
d841502c
BG
1452static int qca_send_crashbuffer(struct hci_uart *hu)
1453{
1454 struct qca_data *qca = hu->priv;
1455 struct sk_buff *skb;
1456
1457 skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL);
1458 if (!skb) {
1459 bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet");
1460 return -ENOMEM;
1461 }
1462
1463 /* We forcefully crash the controller, by sending 0xfb byte for
1464 * 1024 times. We also might have chance of losing data, To be
1465 * on safer side we send 1096 bytes to the SoC.
1466 */
1467 memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE,
1468 QCA_CRASHBYTE_PACKET_LEN);
1469 hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
1470 bt_dev_info(hu->hdev, "crash the soc to collect controller dump");
1471 skb_queue_tail(&qca->txq, skb);
1472 hci_uart_tx_wakeup(hu);
1473
1474 return 0;
1475}
1476
1477static void qca_wait_for_dump_collection(struct hci_dev *hdev)
1478{
1479 struct hci_uart *hu = hci_get_drvdata(hdev);
1480 struct qca_data *qca = hu->priv;
d841502c
BG
1481
1482 wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION,
1483 TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS);
1484
1485 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c
BG
1486}
1487
1488static void qca_hw_error(struct hci_dev *hdev, u8 code)
1489{
1490 struct hci_uart *hu = hci_get_drvdata(hdev);
1491 struct qca_data *qca = hu->priv;
1492
3344537f 1493 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
7c2c3e63 1494 set_bit(QCA_HW_ERROR_EVENT, &qca->flags);
d841502c
BG
1495 bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state);
1496
1497 if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
1498 /* If hardware error event received for other than QCA
1499 * soc memory dump event, then we need to crash the SOC
1500 * and wait here for 8 seconds to get the dump packets.
1501 * This will block main thread to be on hold until we
1502 * collect dump.
1503 */
1504 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1505 qca_send_crashbuffer(hu);
1506 qca_wait_for_dump_collection(hdev);
1507 } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
1508 /* Let us wait here until memory dump collected or
1509 * memory dump timer expired.
1510 */
1511 bt_dev_info(hdev, "waiting for dump to complete");
1512 qca_wait_for_dump_collection(hdev);
1513 }
7c2c3e63 1514
f98aa80f 1515 mutex_lock(&qca->hci_memdump_lock);
7c2c3e63
VLNG
1516 if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
1517 bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout");
f98aa80f
VLNG
1518 if (qca->qca_memdump) {
1519 vfree(qca->qca_memdump->memdump_buf_head);
1520 kfree(qca->qca_memdump);
1521 qca->qca_memdump = NULL;
1522 }
7c2c3e63
VLNG
1523 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
1524 cancel_delayed_work(&qca->ctrl_memdump_timeout);
f98aa80f
VLNG
1525 }
1526 mutex_unlock(&qca->hci_memdump_lock);
1527
1528 if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
1529 qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
7c2c3e63 1530 cancel_work_sync(&qca->ctrl_memdump_evt);
f98aa80f 1531 skb_queue_purge(&qca->rx_memdump_q);
7c2c3e63
VLNG
1532 }
1533
1534 clear_bit(QCA_HW_ERROR_EVENT, &qca->flags);
d841502c
BG
1535}
1536
1537static void qca_cmd_timeout(struct hci_dev *hdev)
1538{
1539 struct hci_uart *hu = hci_get_drvdata(hdev);
1540 struct qca_data *qca = hu->priv;
1541
3344537f
VLNG
1542 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
1543 if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
1544 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c 1545 qca_send_crashbuffer(hu);
3344537f
VLNG
1546 qca_wait_for_dump_collection(hdev);
1547 } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
1548 /* Let us wait here until memory dump collected or
1549 * memory dump timer expired.
1550 */
1551 bt_dev_info(hdev, "waiting for dump to complete");
1552 qca_wait_for_dump_collection(hdev);
1553 }
1554
1555 mutex_lock(&qca->hci_memdump_lock);
1556 if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
1557 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
1558 if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
1559 /* Inject hw error event to reset the device
1560 * and driver.
1561 */
1562 hci_reset_dev(hu->hdev);
1563 }
1564 }
1565 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG
1566}
1567
fa9ad876
BG
1568static int qca_wcn3990_init(struct hci_uart *hu)
1569{
3e4be65e 1570 struct qca_serdev *qcadev;
fa9ad876
BG
1571 int ret;
1572
3e4be65e
BG
1573 /* Check for vregs status, may be hci down has turned
1574 * off the voltage regulator.
1575 */
1576 qcadev = serdev_device_get_drvdata(hu->serdev);
1577 if (!qcadev->bt_power->vregs_on) {
1578 serdev_device_close(hu->serdev);
a9314e76 1579 ret = qca_regulator_enable(qcadev);
3e4be65e
BG
1580 if (ret)
1581 return ret;
1582
1583 ret = serdev_device_open(hu->serdev);
1584 if (ret) {
1585 bt_dev_err(hu->hdev, "failed to open port");
1586 return ret;
1587 }
1588 }
1589
fa9ad876
BG
1590 /* Forcefully enable wcn3990 to enter in to boot mode. */
1591 host_set_baudrate(hu, 2400);
9836b802 1592 ret = qca_send_power_pulse(hu, false);
fa9ad876
BG
1593 if (ret)
1594 return ret;
1595
1596 qca_set_speed(hu, QCA_INIT_SPEED);
9836b802 1597 ret = qca_send_power_pulse(hu, true);
fa9ad876
BG
1598 if (ret)
1599 return ret;
1600
fa9ad876
BG
1601 /* Now the device is in ready state to communicate with host.
1602 * To sync host with device we need to reopen port.
1603 * Without this, we will have RTS and CTS synchronization
1604 * issues.
1605 */
1606 serdev_device_close(hu->serdev);
1607 ret = serdev_device_open(hu->serdev);
1608 if (ret) {
1609 bt_dev_err(hu->hdev, "failed to open port");
1610 return ret;
1611 }
1612
1613 hci_uart_set_flow_control(hu, false);
1614
1615 return 0;
1616}
1617
5e6d8401
RL
1618static int qca_power_on(struct hci_dev *hdev)
1619{
1620 struct hci_uart *hu = hci_get_drvdata(hdev);
1621 enum qca_btsoc_type soc_type = qca_soc_type(hu);
1622 struct qca_serdev *qcadev;
1623 int ret = 0;
1624
1625 /* Non-serdev device usually is powered by external power
1626 * and don't need additional action in driver for power on
1627 */
1628 if (!hu->serdev)
1629 return 0;
1630
1631 if (qca_is_wcn399x(soc_type)) {
1632 ret = qca_wcn3990_init(hu);
1633 } else {
1634 qcadev = serdev_device_get_drvdata(hu->serdev);
77131dfe 1635 if (qcadev->bt_en) {
8a208b24
RL
1636 gpiod_set_value_cansleep(qcadev->bt_en, 1);
1637 /* Controller needs time to bootup. */
1638 msleep(150);
1639 }
5e6d8401
RL
1640 }
1641
1642 return ret;
1643}
1644
0ff252c1
BYTK
1645static int qca_setup(struct hci_uart *hu)
1646{
1647 struct hci_dev *hdev = hu->hdev;
1648 struct qca_data *qca = hu->priv;
1649 unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200;
bb2500ab 1650 unsigned int retries = 0;
4fdd5a4f 1651 enum qca_btsoc_type soc_type = qca_soc_type(hu);
99c905c6 1652 const char *firmware_name = qca_get_firmware_name(hu);
0ff252c1 1653 int ret;
aadebac4 1654 int soc_ver = 0;
0ff252c1 1655
83d9c5e5
BG
1656 ret = qca_check_speeds(hu);
1657 if (ret)
1658 return ret;
1659
0ff252c1 1660 /* Patch downloading has to be done without IBS mode */
62a91990 1661 clear_bit(QCA_IBS_ENABLED, &qca->flags);
0ff252c1 1662
e14c167a
RL
1663 /* Enable controller to do both LE scan and BR/EDR inquiry
1664 * simultaneously.
1665 */
1666 set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks);
1667
5e6d8401 1668 bt_dev_info(hdev, "setting up %s",
e5d6468f 1669 qca_is_wcn399x(soc_type) ? "wcn399x" : "ROME/QCA6390");
3e4be65e 1670
58789a19
VLNG
1671 qca->memdump_state = QCA_MEMDUMP_IDLE;
1672
bb2500ab 1673retry:
5e6d8401
RL
1674 ret = qca_power_on(hdev);
1675 if (ret)
1676 return ret;
1677
3344537f
VLNG
1678 clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
1679
5e6d8401 1680 if (qca_is_wcn399x(soc_type)) {
5971752d 1681 set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks);
fa9ad876 1682
7d250a06 1683 ret = qca_read_soc_version(hdev, &soc_ver, soc_type);
fa9ad876
BG
1684 if (ret)
1685 return ret;
1686 } else {
fa9ad876
BG
1687 qca_set_speed(hu, QCA_INIT_SPEED);
1688 }
0ff252c1
BYTK
1689
1690 /* Setup user speed if needed */
83d9c5e5 1691 speed = qca_get_speed(hu, QCA_OPER_SPEED);
0ff252c1 1692 if (speed) {
83d9c5e5
BG
1693 ret = qca_set_speed(hu, QCA_OPER_SPEED);
1694 if (ret)
0ff252c1 1695 return ret;
83d9c5e5
BG
1696
1697 qca_baudrate = qca_get_baudrate_value(speed);
0ff252c1
BYTK
1698 }
1699
523760b7 1700 if (!qca_is_wcn399x(soc_type)) {
fa9ad876 1701 /* Get QCA version information */
7d250a06 1702 ret = qca_read_soc_version(hdev, &soc_ver, soc_type);
fa9ad876
BG
1703 if (ret)
1704 return ret;
1705 }
aadebac4
BG
1706
1707 bt_dev_info(hdev, "QCA controller version 0x%08x", soc_ver);
0ff252c1 1708 /* Setup patch / NVM configurations */
99c905c6
RL
1709 ret = qca_uart_setup(hdev, qca_baudrate, soc_type, soc_ver,
1710 firmware_name);
0ff252c1 1711 if (!ret) {
62a91990 1712 set_bit(QCA_IBS_ENABLED, &qca->flags);
0ff252c1 1713 qca_debugfs_init(hdev);
d841502c
BG
1714 hu->hdev->hw_error = qca_hw_error;
1715 hu->hdev->cmd_timeout = qca_cmd_timeout;
ba8f3597
LP
1716 } else if (ret == -ENOENT) {
1717 /* No patch/nvm-config found, run with original fw/config */
1718 ret = 0;
7dc5fe08
AP
1719 } else if (ret == -EAGAIN) {
1720 /*
1721 * Userspace firmware loader will return -EAGAIN in case no
1722 * patch/nvm-config is found, so run with original fw/config.
1723 */
1724 ret = 0;
bb2500ab
RL
1725 } else {
1726 if (retries < MAX_INIT_RETRIES) {
1727 qca_power_shutdown(hu);
1728 if (hu->serdev) {
1729 serdev_device_close(hu->serdev);
1730 ret = serdev_device_open(hu->serdev);
1731 if (ret) {
1732 bt_dev_err(hdev, "failed to open port");
1733 return ret;
1734 }
1735 }
1736 retries++;
1737 goto retry;
1738 }
0ff252c1
BYTK
1739 }
1740
1741 /* Setup bdaddr */
e5d6468f 1742 if (soc_type == QCA_ROME)
5c0a1001 1743 hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
e5d6468f
RL
1744 else
1745 hu->hdev->set_bdaddr = qca_set_bdaddr;
0ff252c1
BYTK
1746
1747 return ret;
1748}
1749
2edc9c5c 1750static const struct hci_uart_proto qca_proto = {
0ff252c1
BYTK
1751 .id = HCI_UART_QCA,
1752 .name = "QCA",
aee61f7a 1753 .manufacturer = 29,
0ff252c1
BYTK
1754 .init_speed = 115200,
1755 .oper_speed = 3000000,
1756 .open = qca_open,
1757 .close = qca_close,
1758 .flush = qca_flush,
1759 .setup = qca_setup,
1760 .recv = qca_recv,
1761 .enqueue = qca_enqueue,
1762 .dequeue = qca_dequeue,
1763};
1764
a228f7a4 1765static const struct qca_device_data qca_soc_data_wcn3990 = {
fa9ad876
BG
1766 .soc_type = QCA_WCN3990,
1767 .vregs = (struct qca_vreg []) {
f2edd66e
BA
1768 { "vddio", 15000 },
1769 { "vddxo", 80000 },
1770 { "vddrf", 300000 },
1771 { "vddch0", 450000 },
fa9ad876
BG
1772 },
1773 .num_vregs = 4,
1774};
1775
a228f7a4 1776static const struct qca_device_data qca_soc_data_wcn3991 = {
7d250a06
BG
1777 .soc_type = QCA_WCN3991,
1778 .vregs = (struct qca_vreg []) {
1779 { "vddio", 15000 },
1780 { "vddxo", 80000 },
1781 { "vddrf", 300000 },
1782 { "vddch0", 450000 },
1783 },
1784 .num_vregs = 4,
a228f7a4 1785 .capabilities = QCA_CAP_WIDEBAND_SPEECH,
7d250a06
BG
1786};
1787
a228f7a4 1788static const struct qca_device_data qca_soc_data_wcn3998 = {
523760b7
HB
1789 .soc_type = QCA_WCN3998,
1790 .vregs = (struct qca_vreg []) {
f2edd66e
BA
1791 { "vddio", 10000 },
1792 { "vddxo", 80000 },
1793 { "vddrf", 300000 },
1794 { "vddch0", 450000 },
523760b7
HB
1795 },
1796 .num_vregs = 4,
1797};
1798
a228f7a4 1799static const struct qca_device_data qca_soc_data_qca6390 = {
e5d6468f
RL
1800 .soc_type = QCA_QCA6390,
1801 .num_vregs = 0,
1802};
1803
c2d78273 1804static void qca_power_shutdown(struct hci_uart *hu)
fa9ad876 1805{
a9314e76 1806 struct qca_serdev *qcadev;
035a960e
BG
1807 struct qca_data *qca = hu->priv;
1808 unsigned long flags;
5559904c 1809 enum qca_btsoc_type soc_type = qca_soc_type(hu);
035a960e 1810
a9314e76
BA
1811 qcadev = serdev_device_get_drvdata(hu->serdev);
1812
035a960e
BG
1813 /* From this point we go into power off state. But serial port is
1814 * still open, stop queueing the IBS data and flush all the buffered
1815 * data in skb's.
1816 */
1817 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
62a91990 1818 clear_bit(QCA_IBS_ENABLED, &qca->flags);
035a960e
BG
1819 qca_flush(hu);
1820 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
1821
5559904c
RL
1822 /* Non-serdev device usually is powered by external power
1823 * and don't need additional action in driver for power down
1824 */
1825 if (!hu->serdev)
1826 return;
1827
1828 if (qca_is_wcn399x(soc_type)) {
1829 host_set_baudrate(hu, 2400);
1830 qca_send_power_pulse(hu, false);
1831 qca_regulator_disable(qcadev);
77131dfe 1832 } else if (qcadev->bt_en) {
5559904c
RL
1833 gpiod_set_value_cansleep(qcadev->bt_en, 0);
1834 }
fa9ad876
BG
1835}
1836
3e4be65e
BG
1837static int qca_power_off(struct hci_dev *hdev)
1838{
1839 struct hci_uart *hu = hci_get_drvdata(hdev);
d841502c 1840 struct qca_data *qca = hu->priv;
4f9ed5bd 1841 enum qca_btsoc_type soc_type = qca_soc_type(hu);
3e4be65e 1842
58789a19
VLNG
1843 hu->hdev->hw_error = NULL;
1844 hu->hdev->cmd_timeout = NULL;
1845
d841502c 1846 /* Stop sending shutdown command if soc crashes. */
e5d6468f 1847 if (soc_type != QCA_ROME
4f9ed5bd 1848 && qca->memdump_state == QCA_MEMDUMP_IDLE) {
d841502c
BG
1849 qca_send_pre_shutdown_cmd(hdev);
1850 usleep_range(8000, 10000);
1851 }
010376ab 1852
3e4be65e
BG
1853 qca_power_shutdown(hu);
1854 return 0;
1855}
1856
a9314e76 1857static int qca_regulator_enable(struct qca_serdev *qcadev)
fa9ad876 1858{
a9314e76
BA
1859 struct qca_power *power = qcadev->bt_power;
1860 int ret;
fa9ad876 1861
a9314e76
BA
1862 /* Already enabled */
1863 if (power->vregs_on)
1864 return 0;
fa9ad876 1865
a9314e76 1866 BT_DBG("enabling %d regulators)", power->num_vregs);
fa9ad876 1867
a9314e76
BA
1868 ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk);
1869 if (ret)
1870 return ret;
fa9ad876 1871
a9314e76 1872 power->vregs_on = true;
fa9ad876 1873
66cb7051 1874 ret = clk_prepare_enable(qcadev->susclk);
f3d63f50 1875 if (ret)
66cb7051 1876 qca_regulator_disable(qcadev);
66cb7051 1877
f3d63f50 1878 return ret;
fa9ad876
BG
1879}
1880
a9314e76
BA
1881static void qca_regulator_disable(struct qca_serdev *qcadev)
1882{
1883 struct qca_power *power;
1884
1885 if (!qcadev)
1886 return;
1887
1888 power = qcadev->bt_power;
1889
1890 /* Already disabled? */
1891 if (!power->vregs_on)
1892 return;
1893
1894 regulator_bulk_disable(power->num_vregs, power->vreg_bulk);
1895 power->vregs_on = false;
66cb7051 1896
f3d63f50 1897 clk_disable_unprepare(qcadev->susclk);
a9314e76
BA
1898}
1899
fa9ad876
BG
1900static int qca_init_regulators(struct qca_power *qca,
1901 const struct qca_vreg *vregs, size_t num_vregs)
1902{
c29ff107
BA
1903 struct regulator_bulk_data *bulk;
1904 int ret;
fa9ad876
BG
1905 int i;
1906
c29ff107
BA
1907 bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL);
1908 if (!bulk)
fa9ad876
BG
1909 return -ENOMEM;
1910
1911 for (i = 0; i < num_vregs; i++)
c29ff107
BA
1912 bulk[i].supply = vregs[i].name;
1913
1914 ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk);
1915 if (ret < 0)
1916 return ret;
fa9ad876 1917
c29ff107
BA
1918 for (i = 0; i < num_vregs; i++) {
1919 ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA);
1920 if (ret)
1921 return ret;
1922 }
1923
1924 qca->vreg_bulk = bulk;
163d42fa 1925 qca->num_vregs = num_vregs;
c29ff107
BA
1926
1927 return 0;
fa9ad876
BG
1928}
1929
05ba533c
TE
1930static int qca_serdev_probe(struct serdev_device *serdev)
1931{
1932 struct qca_serdev *qcadev;
ae563183 1933 struct hci_dev *hdev;
a228f7a4 1934 const struct qca_device_data *data;
05ba533c 1935 int err;
8a208b24 1936 bool power_ctrl_enabled = true;
05ba533c
TE
1937
1938 qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL);
1939 if (!qcadev)
1940 return -ENOMEM;
1941
1942 qcadev->serdev_hu.serdev = serdev;
9f3565b8 1943 data = device_get_match_data(&serdev->dev);
05ba533c 1944 serdev_device_set_drvdata(serdev, qcadev);
99c905c6
RL
1945 device_property_read_string(&serdev->dev, "firmware-name",
1946 &qcadev->firmware_name);
37aee136
CH
1947 device_property_read_u32(&serdev->dev, "max-speed",
1948 &qcadev->oper_speed);
1949 if (!qcadev->oper_speed)
1950 BT_DBG("UART will pick default operating speed");
1951
523760b7
HB
1952 if (data && qca_is_wcn399x(data->soc_type)) {
1953 qcadev->btsoc_type = data->soc_type;
fa9ad876
BG
1954 qcadev->bt_power = devm_kzalloc(&serdev->dev,
1955 sizeof(struct qca_power),
1956 GFP_KERNEL);
1957 if (!qcadev->bt_power)
1958 return -ENOMEM;
1959
1960 qcadev->bt_power->dev = &serdev->dev;
fa9ad876
BG
1961 err = qca_init_regulators(qcadev->bt_power, data->vregs,
1962 data->num_vregs);
1963 if (err) {
1964 BT_ERR("Failed to init regulators:%d", err);
ae563183 1965 return err;
fa9ad876 1966 }
05ba533c 1967
fa9ad876 1968 qcadev->bt_power->vregs_on = false;
05ba533c 1969
66cb7051
VLNG
1970 qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
1971 if (IS_ERR(qcadev->susclk)) {
1972 dev_err(&serdev->dev, "failed to acquire clk\n");
1973 return PTR_ERR(qcadev->susclk);
1974 }
1975
fa9ad876
BG
1976 err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
1977 if (err) {
1978 BT_ERR("wcn3990 serdev registration failed");
ae563183 1979 return err;
fa9ad876
BG
1980 }
1981 } else {
e5d6468f
RL
1982 if (data)
1983 qcadev->btsoc_type = data->soc_type;
1984 else
1985 qcadev->btsoc_type = QCA_ROME;
1986
77131dfe 1987 qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
fa9ad876 1988 GPIOD_OUT_LOW);
77131dfe 1989 if (!qcadev->bt_en) {
8a208b24
RL
1990 dev_warn(&serdev->dev, "failed to acquire enable gpio\n");
1991 power_ctrl_enabled = false;
fa9ad876 1992 }
05ba533c 1993
77131dfe 1994 qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
4c07a5d7 1995 if (IS_ERR(qcadev->susclk)) {
8a208b24 1996 dev_warn(&serdev->dev, "failed to acquire clk\n");
4c07a5d7 1997 return PTR_ERR(qcadev->susclk);
8a208b24 1998 }
4c07a5d7
DC
1999 err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ);
2000 if (err)
2001 return err;
2002
2003 err = clk_prepare_enable(qcadev->susclk);
2004 if (err)
2005 return err;
fa9ad876
BG
2006
2007 err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
ae563183
RL
2008 if (err) {
2009 BT_ERR("Rome serdev registration failed");
77131dfe 2010 if (qcadev->susclk)
8a208b24 2011 clk_disable_unprepare(qcadev->susclk);
ae563183
RL
2012 return err;
2013 }
fa9ad876
BG
2014 }
2015
85e90d93
APS
2016 hdev = qcadev->serdev_hu.hdev;
2017
8a208b24 2018 if (power_ctrl_enabled) {
8a208b24
RL
2019 set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks);
2020 hdev->shutdown = qca_power_off;
2021 }
05ba533c 2022
a228f7a4
APS
2023 /* Wideband speech support must be set per driver since it can't be
2024 * queried via hci.
2025 */
2026 if (data && (data->capabilities & QCA_CAP_WIDEBAND_SPEECH))
2027 set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED, &hdev->quirks);
2028
ae563183 2029 return 0;
05ba533c
TE
2030}
2031
2032static void qca_serdev_remove(struct serdev_device *serdev)
2033{
2034 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2035
523760b7 2036 if (qca_is_wcn399x(qcadev->btsoc_type))
c2d78273 2037 qca_power_shutdown(&qcadev->serdev_hu);
77131dfe 2038 else if (qcadev->susclk)
fa9ad876 2039 clk_disable_unprepare(qcadev->susclk);
05ba533c 2040
fa9ad876 2041 hci_uart_unregister_device(&qcadev->serdev_hu);
05ba533c
TE
2042}
2043
7e7bbddd
ZH
2044static void qca_serdev_shutdown(struct device *dev)
2045{
2046 int ret;
2047 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
2048 struct serdev_device *serdev = to_serdev_device(dev);
2049 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2050 const u8 ibs_wake_cmd[] = { 0xFD };
2051 const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 };
2052
2053 if (qcadev->btsoc_type == QCA_QCA6390) {
2054 serdev_device_write_flush(serdev);
2055 ret = serdev_device_write_buf(serdev, ibs_wake_cmd,
2056 sizeof(ibs_wake_cmd));
2057 if (ret < 0) {
2058 BT_ERR("QCA send IBS_WAKE_IND error: %d", ret);
2059 return;
2060 }
2061 serdev_device_wait_until_sent(serdev, timeout);
2062 usleep_range(8000, 10000);
2063
2064 serdev_device_write_flush(serdev);
2065 ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd,
2066 sizeof(edl_reset_soc_cmd));
2067 if (ret < 0) {
2068 BT_ERR("QCA send EDL_RESET_REQ error: %d", ret);
2069 return;
2070 }
2071 serdev_device_wait_until_sent(serdev, timeout);
2072 usleep_range(8000, 10000);
2073 }
2074}
2075
41d5b25f
CC
2076static int __maybe_unused qca_suspend(struct device *dev)
2077{
feac90d7
ZH
2078 struct serdev_device *serdev = to_serdev_device(dev);
2079 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2080 struct hci_uart *hu = &qcadev->serdev_hu;
41d5b25f
CC
2081 struct qca_data *qca = hu->priv;
2082 unsigned long flags;
e2a119cd 2083 bool tx_pending = false;
41d5b25f
CC
2084 int ret = 0;
2085 u8 cmd;
2086
2087 set_bit(QCA_SUSPENDING, &qca->flags);
2088
2089 /* Device is downloading patch or doesn't support in-band sleep. */
2090 if (!test_bit(QCA_IBS_ENABLED, &qca->flags))
2091 return 0;
2092
2093 cancel_work_sync(&qca->ws_awake_device);
2094 cancel_work_sync(&qca->ws_awake_rx);
2095
2096 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
2097 flags, SINGLE_DEPTH_NESTING);
2098
2099 switch (qca->tx_ibs_state) {
2100 case HCI_IBS_TX_WAKING:
2101 del_timer(&qca->wake_retrans_timer);
a3b4cbfc 2102 fallthrough;
41d5b25f
CC
2103 case HCI_IBS_TX_AWAKE:
2104 del_timer(&qca->tx_idle_timer);
2105
2106 serdev_device_write_flush(hu->serdev);
2107 cmd = HCI_IBS_SLEEP_IND;
2108 ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
2109
2110 if (ret < 0) {
2111 BT_ERR("Failed to send SLEEP to device");
2112 break;
2113 }
2114
2115 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
2116 qca->ibs_sent_slps++;
e2a119cd 2117 tx_pending = true;
41d5b25f
CC
2118 break;
2119
2120 case HCI_IBS_TX_ASLEEP:
2121 break;
2122
2123 default:
2124 BT_ERR("Spurious tx state %d", qca->tx_ibs_state);
2125 ret = -EINVAL;
2126 break;
2127 }
2128
2129 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
2130
2131 if (ret < 0)
2132 goto error;
2133
e2a119cd
MK
2134 if (tx_pending) {
2135 serdev_device_wait_until_sent(hu->serdev,
2136 msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
201a1124 2137 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
e2a119cd 2138 }
41d5b25f
CC
2139
2140 /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going
2141 * to sleep, so that the packet does not wake the system later.
2142 */
41d5b25f
CC
2143 ret = wait_event_interruptible_timeout(qca->suspend_wait_q,
2144 qca->rx_ibs_state == HCI_IBS_RX_ASLEEP,
2145 msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS));
4da385f7
MK
2146 if (ret == 0) {
2147 ret = -ETIMEDOUT;
2148 goto error;
eff981f6 2149 }
41d5b25f 2150
4da385f7 2151 return 0;
41d5b25f
CC
2152
2153error:
2154 clear_bit(QCA_SUSPENDING, &qca->flags);
2155
2156 return ret;
2157}
2158
2159static int __maybe_unused qca_resume(struct device *dev)
2160{
feac90d7
ZH
2161 struct serdev_device *serdev = to_serdev_device(dev);
2162 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2163 struct hci_uart *hu = &qcadev->serdev_hu;
41d5b25f
CC
2164 struct qca_data *qca = hu->priv;
2165
2166 clear_bit(QCA_SUSPENDING, &qca->flags);
2167
2168 return 0;
2169}
2170
2171static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume);
2172
e5d6468f 2173#ifdef CONFIG_OF
05ba533c
TE
2174static const struct of_device_id qca_bluetooth_of_match[] = {
2175 { .compatible = "qcom,qca6174-bt" },
e5d6468f 2176 { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390},
31d4ab85 2177 { .compatible = "qcom,qca9377-bt" },
523760b7 2178 { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990},
7d250a06 2179 { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991},
523760b7 2180 { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998},
05ba533c
TE
2181 { /* sentinel */ }
2182};
2183MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match);
e5d6468f
RL
2184#endif
2185
2186#ifdef CONFIG_ACPI
2187static const struct acpi_device_id qca_bluetooth_acpi_match[] = {
2188 { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2189 { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2190 { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2191 { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2192 { },
2193};
2194MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match);
2195#endif
2196
05ba533c
TE
2197
2198static struct serdev_device_driver qca_serdev_driver = {
2199 .probe = qca_serdev_probe,
2200 .remove = qca_serdev_remove,
2201 .driver = {
2202 .name = "hci_uart_qca",
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RL
2203 .of_match_table = of_match_ptr(qca_bluetooth_of_match),
2204 .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match),
7e7bbddd 2205 .shutdown = qca_serdev_shutdown,
41d5b25f 2206 .pm = &qca_pm_ops,
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TE
2207 },
2208};
2209
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BYTK
2210int __init qca_init(void)
2211{
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TE
2212 serdev_device_driver_register(&qca_serdev_driver);
2213
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BYTK
2214 return hci_uart_register_proto(&qca_proto);
2215}
2216
2217int __exit qca_deinit(void)
2218{
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TE
2219 serdev_device_driver_unregister(&qca_serdev_driver);
2220
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BYTK
2221 return hci_uart_unregister_proto(&qca_proto);
2222}