projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'mfd-next-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
[linux-2.6-block.git] / drivers / bluetooth / hci_qca.c
CommitLineData
45051539 1// SPDX-License-Identifier: GPL-2.0-only
0ff252c1
BYTK		 2/*
3 * Bluetooth Software UART Qualcomm protocol
4 *
5 * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management
6 * protocol extension to H4.
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.
fa9ad876 9 * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved.
0ff252c1
BYTK		 10 *
11 * Acknowledgements:
12 * This file is based on hci_ll.c, which was...
13 * Written by Ohad Ben-Cohen <ohad@bencohen.org>
14 * which was in turn based on hci_h4.c, which was written
15 * by Maxim Krasnyansky and Marcel Holtmann.
0ff252c1
BYTK		 16 */
17
18#include <linux/kernel.h>
05ba533c 19#include <linux/clk.h>
2faa3f15 20#include <linux/completion.h>
0ff252c1 21#include <linux/debugfs.h>
fa9ad876 22#include <linux/delay.h>
d841502c 23#include <linux/devcoredump.h>
fa9ad876 24#include <linux/device.h>
05ba533c
TE		 25#include <linux/gpio/consumer.h>
26#include <linux/mod_devicetable.h>
27#include <linux/module.h>
e15f44fb 28#include <linux/of.h>
e5d6468f 29#include <linux/acpi.h>
fa9ad876
BG		 30#include <linux/platform_device.h>
31#include <linux/regulator/consumer.h>
05ba533c 32#include <linux/serdev.h>
7c2c3e63 33#include <linux/mutex.h>
c614ca3f 34#include <asm/unaligned.h>
0ff252c1
BYTK		 35
36#include <net/bluetooth/bluetooth.h>
37#include <net/bluetooth/hci_core.h>
38
39#include "hci_uart.h"
40#include "btqca.h"
41
42/* HCI_IBS protocol messages */
43#define HCI_IBS_SLEEP_IND 0xFE
44#define HCI_IBS_WAKE_IND 0xFD
45#define HCI_IBS_WAKE_ACK 0xFC
f81b001a 46#define HCI_MAX_IBS_SIZE 10
0ff252c1 47
f81b001a 48#define IBS_WAKE_RETRANS_TIMEOUT_MS 100
2d68476c 49#define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200
41d5b25f 50#define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000
94d66714 51#define CMD_TRANS_TIMEOUT_MS 100
d841502c 52#define MEMDUMP_TIMEOUT_MS 8000
ad3a9c0e
VLNG		 53#define IBS_DISABLE_SSR_TIMEOUT_MS \
54 (MEMDUMP_TIMEOUT_MS + FW_DOWNLOAD_TIMEOUT_MS)
2be43aba 55#define FW_DOWNLOAD_TIMEOUT_MS 3000
0ff252c1 56
05ba533c
TE		 57/* susclk rate */
58#define SUSCLK_RATE_32KHZ 32768
59
c614ca3f
BG		 60/* Controller debug log header */
61#define QCA_DEBUG_HANDLE 0x2EDC
62
bb2500ab
RL		 63/* max retry count when init fails */
64#define MAX_INIT_RETRIES 3
65
d841502c
BG		 66/* Controller dump header */
67#define QCA_SSR_DUMP_HANDLE 0x0108
68#define QCA_DUMP_PACKET_SIZE 255
69#define QCA_LAST_SEQUENCE_NUM 0xFFFF
70#define QCA_CRASHBYTE_PACKET_LEN 1096
71#define QCA_MEMDUMP_BYTE 0xFB
72
62a91990 73enum qca_flags {
2be43aba 74 QCA_IBS_DISABLED,
2faa3f15 75 QCA_DROP_VENDOR_EVENT,
41d5b25f 76 QCA_SUSPENDING,
7c2c3e63 77 QCA_MEMDUMP_COLLECTION,
3344537f 78 QCA_HW_ERROR_EVENT,
2be43aba 79 QCA_SSR_TRIGGERED,
55c0bd77 80 QCA_BT_OFF,
47c5d829
JH		 81 QCA_ROM_FW,
82 QCA_DEBUGFS_CREATED,
62a91990
MK		 83};
84
a228f7a4
APS		 85enum qca_capabilities {
86 QCA_CAP_WIDEBAND_SPEECH = BIT(0),
54780138 87 QCA_CAP_VALID_LE_STATES = BIT(1),
a228f7a4 88};
d841502c 89
0ff252c1
BYTK		 90/* HCI_IBS transmit side sleep protocol states */
91enum tx_ibs_states {
92 HCI_IBS_TX_ASLEEP,
93 HCI_IBS_TX_WAKING,
94 HCI_IBS_TX_AWAKE,
95};
96
97/* HCI_IBS receive side sleep protocol states */
98enum rx_states {
99 HCI_IBS_RX_ASLEEP,
100 HCI_IBS_RX_AWAKE,
101};
102
103/* HCI_IBS transmit and receive side clock state vote */
104enum hci_ibs_clock_state_vote {
105 HCI_IBS_VOTE_STATS_UPDATE,
106 HCI_IBS_TX_VOTE_CLOCK_ON,
107 HCI_IBS_TX_VOTE_CLOCK_OFF,
108 HCI_IBS_RX_VOTE_CLOCK_ON,
109 HCI_IBS_RX_VOTE_CLOCK_OFF,
110};
111
d841502c
BG		 112/* Controller memory dump states */
113enum qca_memdump_states {
114 QCA_MEMDUMP_IDLE,
115 QCA_MEMDUMP_COLLECTING,
116 QCA_MEMDUMP_COLLECTED,
117 QCA_MEMDUMP_TIMEOUT,
118};
119
06d3fdfc 120struct qca_memdump_info {
d841502c
BG		 121 u32 current_seq_no;
122 u32 received_dump;
e5aeebdd 123 u32 ram_dump_size;
d841502c
BG		 124};
125
126struct qca_memdump_event_hdr {
127 __u8 evt;
128 __u8 plen;
129 __u16 opcode;
fec2972a 130 __le16 seq_no;
d841502c
BG		 131 __u8 reserved;
132} __packed;
133
134
135struct qca_dump_size {
fec2972a 136 __le32 dump_size;
d841502c
BG		 137} __packed;
138
0ff252c1
BYTK		 139struct qca_data {
140 struct hci_uart *hu;
141 struct sk_buff *rx_skb;
142 struct sk_buff_head txq;
143 struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */
d841502c 144 struct sk_buff_head rx_memdump_q; /* Memdump wait queue */
0ff252c1
BYTK		 145 spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
146 u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
147 u8 rx_ibs_state; /* HCI_IBS receive side power state */
621a5f7a
VK		 148 bool tx_vote; /* Clock must be on for TX */
149 bool rx_vote; /* Clock must be on for RX */
0ff252c1
BYTK		 150 struct timer_list tx_idle_timer;
151 u32 tx_idle_delay;
152 struct timer_list wake_retrans_timer;
153 u32 wake_retrans;
154 struct workqueue_struct *workqueue;
155 struct work_struct ws_awake_rx;
156 struct work_struct ws_awake_device;
157 struct work_struct ws_rx_vote_off;
158 struct work_struct ws_tx_vote_off;
d841502c 159 struct work_struct ctrl_memdump_evt;
7c2c3e63 160 struct delayed_work ctrl_memdump_timeout;
06d3fdfc 161 struct qca_memdump_info *qca_memdump;
0ff252c1 162 unsigned long flags;
2faa3f15 163 struct completion drop_ev_comp;
41d5b25f 164 wait_queue_head_t suspend_wait_q;
d841502c 165 enum qca_memdump_states memdump_state;
7c2c3e63 166 struct mutex hci_memdump_lock;
0ff252c1 167
06d3fdfc
STA		 168 u16 fw_version;
169 u16 controller_id;
0ff252c1
BYTK		 170 /* For debugging purpose */
171 u64 ibs_sent_wacks;
172 u64 ibs_sent_slps;
173 u64 ibs_sent_wakes;
174 u64 ibs_recv_wacks;
175 u64 ibs_recv_slps;
176 u64 ibs_recv_wakes;
177 u64 vote_last_jif;
178 u32 vote_on_ms;
179 u32 vote_off_ms;
180 u64 tx_votes_on;
181 u64 rx_votes_on;
182 u64 tx_votes_off;
183 u64 rx_votes_off;
184 u64 votes_on;
185 u64 votes_off;
186};
187
83d9c5e5
BG		 188enum qca_speed_type {
189 QCA_INIT_SPEED = 1,
190 QCA_OPER_SPEED
191};
192
fa9ad876
BG		 193/*
194 * Voltage regulator information required for configuring the
195 * QCA Bluetooth chipset
196 */
197struct qca_vreg {
198 const char *name;
fa9ad876
BG		 199 unsigned int load_uA;
200};
201
a228f7a4 202struct qca_device_data {
fa9ad876
BG		 203 enum qca_btsoc_type soc_type;
204 struct qca_vreg *vregs;
205 size_t num_vregs;
a228f7a4 206 uint32_t capabilities;
fa9ad876
BG		 207};
208
209/*
210 * Platform data for the QCA Bluetooth power driver.
211 */
212struct qca_power {
213 struct device *dev;
fa9ad876 214 struct regulator_bulk_data *vreg_bulk;
163d42fa 215 int num_vregs;
fa9ad876
BG		 216 bool vregs_on;
217};
218
05ba533c
TE		 219struct qca_serdev {
220 struct hci_uart serdev_hu;
221 struct gpio_desc *bt_en;
d8f97da1 222 struct gpio_desc *sw_ctrl;
05ba533c 223 struct clk *susclk;
fa9ad876
BG		 224 enum qca_btsoc_type btsoc_type;
225 struct qca_power *bt_power;
226 u32 init_speed;
227 u32 oper_speed;
99c905c6 228 const char *firmware_name;
05ba533c
TE		 229};
230
a9314e76
BA		 231static int qca_regulator_enable(struct qca_serdev *qcadev);
232static void qca_regulator_disable(struct qca_serdev *qcadev);
c2d78273 233static void qca_power_shutdown(struct hci_uart *hu);
3e4be65e 234static int qca_power_off(struct hci_dev *hdev);
d841502c 235static void qca_controller_memdump(struct work_struct *work);
06d3fdfc 236static void qca_dmp_hdr(struct hci_dev *hdev, struct sk_buff *skb);
fa9ad876 237
4fdd5a4f
MK		 238static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu)
239{
240 enum qca_btsoc_type soc_type;
241
242 if (hu->serdev) {
243 struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
244
245 soc_type = qsd->btsoc_type;
246 } else {
247 soc_type = QCA_ROME;
248 }
249
250 return soc_type;
251}
252
99c905c6
RL		 253static const char *qca_get_firmware_name(struct hci_uart *hu)
254{
255 if (hu->serdev) {
256 struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
257
258 return qsd->firmware_name;
259 } else {
260 return NULL;
261 }
262}
263
0ff252c1
BYTK		 264static void __serial_clock_on(struct tty_struct *tty)
265{
266 /* TODO: Some chipset requires to enable UART clock on client
267 * side to save power consumption or manual work is required.
268 * Please put your code to control UART clock here if needed
269 */
270}
271
272static void __serial_clock_off(struct tty_struct *tty)
273{
274 /* TODO: Some chipset requires to disable UART clock on client
275 * side to save power consumption or manual work is required.
276 * Please put your code to control UART clock off here if needed
277 */
278}
279
280/* serial_clock_vote needs to be called with the ibs lock held */
281static void serial_clock_vote(unsigned long vote, struct hci_uart *hu)
282{
283 struct qca_data *qca = hu->priv;
284 unsigned int diff;
285
286 bool old_vote = (qca->tx_vote | qca->rx_vote);
287 bool new_vote;
288
289 switch (vote) {
290 case HCI_IBS_VOTE_STATS_UPDATE:
291 diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
292
293 if (old_vote)
294 qca->vote_off_ms += diff;
295 else
296 qca->vote_on_ms += diff;
297 return;
298
299 case HCI_IBS_TX_VOTE_CLOCK_ON:
300 qca->tx_vote = true;
301 qca->tx_votes_on++;
0ff252c1
BYTK		 302 break;
303
304 case HCI_IBS_RX_VOTE_CLOCK_ON:
305 qca->rx_vote = true;
306 qca->rx_votes_on++;
0ff252c1
BYTK		 307 break;
308
309 case HCI_IBS_TX_VOTE_CLOCK_OFF:
310 qca->tx_vote = false;
311 qca->tx_votes_off++;
0ff252c1
BYTK		 312 break;
313
314 case HCI_IBS_RX_VOTE_CLOCK_OFF:
315 qca->rx_vote = false;
316 qca->rx_votes_off++;
0ff252c1
BYTK		 317 break;
318
319 default:
320 BT_ERR("Voting irregularity");
321 return;
322 }
323
7310dd3f
MK		 324 new_vote = qca->rx_vote | qca->tx_vote;
325
0ff252c1
BYTK		 326 if (new_vote != old_vote) {
327 if (new_vote)
328 __serial_clock_on(hu->tty);
329 else
330 __serial_clock_off(hu->tty);
331
ce26d813
PK		 332 BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false",
333 vote ? "true" : "false");
0ff252c1
BYTK		 334
335 diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
336
337 if (new_vote) {
338 qca->votes_on++;
339 qca->vote_off_ms += diff;
340 } else {
341 qca->votes_off++;
342 qca->vote_on_ms += diff;
343 }
344 qca->vote_last_jif = jiffies;
345 }
346}
347
348/* Builds and sends an HCI_IBS command packet.
349 * These are very simple packets with only 1 cmd byte.
350 */
351static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu)
352{
353 int err = 0;
354 struct sk_buff *skb = NULL;
355 struct qca_data *qca = hu->priv;
356
357 BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd);
358
359 skb = bt_skb_alloc(1, GFP_ATOMIC);
360 if (!skb) {
361 BT_ERR("Failed to allocate memory for HCI_IBS packet");
362 return -ENOMEM;
363 }
364
365 /* Assign HCI_IBS type */
634fef61 366 skb_put_u8(skb, cmd);
0ff252c1
BYTK		 367
368 skb_queue_tail(&qca->txq, skb);
369
370 return err;
371}
372
373static void qca_wq_awake_device(struct work_struct *work)
374{
375 struct qca_data *qca = container_of(work, struct qca_data,
376 ws_awake_device);
377 struct hci_uart *hu = qca->hu;
378 unsigned long retrans_delay;
31fb1bbd 379 unsigned long flags;
0ff252c1
BYTK		 380
381 BT_DBG("hu %p wq awake device", hu);
382
383 /* Vote for serial clock */
384 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu);
385
31fb1bbd 386 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK		 387
388 /* Send wake indication to device */
389 if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0)
390 BT_ERR("Failed to send WAKE to device");
391
392 qca->ibs_sent_wakes++;
393
394 /* Start retransmit timer */
395 retrans_delay = msecs_to_jiffies(qca->wake_retrans);
396 mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
397
31fb1bbd 398 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK		 399
400 /* Actually send the packets */
401 hci_uart_tx_wakeup(hu);
402}
403
404static void qca_wq_awake_rx(struct work_struct *work)
405{
406 struct qca_data *qca = container_of(work, struct qca_data,
407 ws_awake_rx);
408 struct hci_uart *hu = qca->hu;
31fb1bbd 409 unsigned long flags;
0ff252c1
BYTK		 410
411 BT_DBG("hu %p wq awake rx", hu);
412
413 serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu);
414
31fb1bbd 415 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK		 416 qca->rx_ibs_state = HCI_IBS_RX_AWAKE;
417
418 /* Always acknowledge device wake up,
419 * sending IBS message doesn't count as TX ON.
420 */
421 if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0)
422 BT_ERR("Failed to acknowledge device wake up");
423
424 qca->ibs_sent_wacks++;
425
31fb1bbd 426 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK		 427
428 /* Actually send the packets */
429 hci_uart_tx_wakeup(hu);
430}
431
432static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work)
433{
434 struct qca_data *qca = container_of(work, struct qca_data,
435 ws_rx_vote_off);
436 struct hci_uart *hu = qca->hu;
437
438 BT_DBG("hu %p rx clock vote off", hu);
439
440 serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu);
441}
442
443static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work)
444{
445 struct qca_data *qca = container_of(work, struct qca_data,
446 ws_tx_vote_off);
447 struct hci_uart *hu = qca->hu;
448
449 BT_DBG("hu %p tx clock vote off", hu);
450
451 /* Run HCI tx handling unlocked */
452 hci_uart_tx_wakeup(hu);
453
454 /* Now that message queued to tty driver, vote for tty clocks off.
455 * It is up to the tty driver to pend the clocks off until tx done.
456 */
457 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
458}
459
04356052 460static void hci_ibs_tx_idle_timeout(struct timer_list *t)
0ff252c1 461{
04356052
KC		 462 struct qca_data *qca = from_timer(qca, t, tx_idle_timer);
463 struct hci_uart *hu = qca->hu;
0ff252c1
BYTK		 464 unsigned long flags;
465
466 BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
467
468 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
469 flags, SINGLE_DEPTH_NESTING);
470
471 switch (qca->tx_ibs_state) {
472 case HCI_IBS_TX_AWAKE:
473 /* TX_IDLE, go to SLEEP */
474 if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) {
475 BT_ERR("Failed to send SLEEP to device");
476 break;
477 }
478 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
479 qca->ibs_sent_slps++;
480 queue_work(qca->workqueue, &qca->ws_tx_vote_off);
481 break;
482
483 case HCI_IBS_TX_ASLEEP:
484 case HCI_IBS_TX_WAKING:
0ff252c1 485 default:
e059a465 486 BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
0ff252c1
BYTK		 487 break;
488 }
489
490 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
491}
492
04356052 493static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
0ff252c1 494{
04356052
KC		 495 struct qca_data *qca = from_timer(qca, t, wake_retrans_timer);
496 struct hci_uart *hu = qca->hu;
0ff252c1 497 unsigned long flags, retrans_delay;
a9137188 498 bool retransmit = false;
0ff252c1
BYTK		 499
500 BT_DBG("hu %p wake retransmit timeout in %d state",
501 hu, qca->tx_ibs_state);
502
503 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
504 flags, SINGLE_DEPTH_NESTING);
505
41d5b25f
CC		 506 /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */
507 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
508 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
509 return;
510 }
511
0ff252c1
BYTK		 512 switch (qca->tx_ibs_state) {
513 case HCI_IBS_TX_WAKING:
514 /* No WAKE_ACK, retransmit WAKE */
a9137188 515 retransmit = true;
0ff252c1
BYTK		 516 if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) {
517 BT_ERR("Failed to acknowledge device wake up");
518 break;
519 }
520 qca->ibs_sent_wakes++;
521 retrans_delay = msecs_to_jiffies(qca->wake_retrans);
522 mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
523 break;
524
525 case HCI_IBS_TX_ASLEEP:
526 case HCI_IBS_TX_AWAKE:
0ff252c1 527 default:
e059a465 528 BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
0ff252c1
BYTK		 529 break;
530 }
531
532 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
533
534 if (retransmit)
535 hci_uart_tx_wakeup(hu);
536}
537
7c2c3e63
VLNG		 538
539static void qca_controller_memdump_timeout(struct work_struct *work)
d841502c 540{
7c2c3e63
VLNG		 541 struct qca_data *qca = container_of(work, struct qca_data,
542 ctrl_memdump_timeout.work);
d841502c 543 struct hci_uart *hu = qca->hu;
7c2c3e63
VLNG		 544
545 mutex_lock(&qca->hci_memdump_lock);
546 if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
547 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
548 if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
549 /* Inject hw error event to reset the device
550 * and driver.
551 */
552 hci_reset_dev(hu->hdev);
553 }
554 }
555
556 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG		 557}
558
7c2c3e63 559
0ff252c1
BYTK		 560/* Initialize protocol */
561static int qca_open(struct hci_uart *hu)
562{
05ba533c 563 struct qca_serdev *qcadev;
0ff252c1
BYTK		 564 struct qca_data *qca;
565
566 BT_DBG("hu %p qca_open", hu);
567
b36a1552
VD		 568 if (!hci_uart_has_flow_control(hu))
569 return -EOPNOTSUPP;
570
25a13e38 571 qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL);
0ff252c1
BYTK		 572 if (!qca)
573 return -ENOMEM;
574
575 skb_queue_head_init(&qca->txq);
576 skb_queue_head_init(&qca->tx_wait_q);
d841502c 577 skb_queue_head_init(&qca->rx_memdump_q);
0ff252c1 578 spin_lock_init(&qca->hci_ibs_lock);
7c2c3e63 579 mutex_init(&qca->hci_memdump_lock);
fac9a602 580 qca->workqueue = alloc_ordered_workqueue("qca_wq", 0);
0ff252c1
BYTK		 581 if (!qca->workqueue) {
582 BT_ERR("QCA Workqueue not initialized properly");
583 kfree(qca);
584 return -ENOMEM;
585 }
586
587 INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx);
588 INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device);
589 INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off);
590 INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off);
d841502c 591 INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump);
7c2c3e63
VLNG		 592 INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout,
593 qca_controller_memdump_timeout);
41d5b25f
CC		 594 init_waitqueue_head(&qca->suspend_wait_q);
595
0ff252c1 596 qca->hu = hu;
2faa3f15 597 init_completion(&qca->drop_ev_comp);
0ff252c1
BYTK		 598
599 /* Assume we start with both sides asleep -- extra wakes OK */
600 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
601 qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
602
0ff252c1 603 qca->vote_last_jif = jiffies;
0ff252c1
BYTK		 604
605 hu->priv = qca;
606
05ba533c 607 if (hu->serdev) {
05ba533c 608 qcadev = serdev_device_get_drvdata(hu->serdev);
37aee136 609
691d54d0
NA		 610 switch (qcadev->btsoc_type) {
611 case QCA_WCN3988:
612 case QCA_WCN3990:
613 case QCA_WCN3991:
614 case QCA_WCN3998:
615 case QCA_WCN6750:
fa9ad876 616 hu->init_speed = qcadev->init_speed;
691d54d0
NA		 617 break;
618
619 default:
620 break;
621 }
37aee136
CH		 622
623 if (qcadev->oper_speed)
fa9ad876 624 hu->oper_speed = qcadev->oper_speed;
05ba533c
TE		 625 }
626
fa9ad876
BG		 627 timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
628 qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
629
630 timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
41d5b25f 631 qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS;
fa9ad876 632
0ff252c1
BYTK		 633 BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u",
634 qca->tx_idle_delay, qca->wake_retrans);
635
636 return 0;
637}
638
639static void qca_debugfs_init(struct hci_dev *hdev)
640{
641 struct hci_uart *hu = hci_get_drvdata(hdev);
642 struct qca_data *qca = hu->priv;
643 struct dentry *ibs_dir;
644 umode_t mode;
645
646 if (!hdev->debugfs)
647 return;
648
47c5d829
JH		 649 if (test_and_set_bit(QCA_DEBUGFS_CREATED, &qca->flags))
650 return;
651
0ff252c1
BYTK		 652 ibs_dir = debugfs_create_dir("ibs", hdev->debugfs);
653
654 /* read only */
99719449 655 mode = 0444;
0ff252c1
BYTK		 656 debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state);
657 debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state);
658 debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir,
659 &qca->ibs_sent_slps);
660 debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir,
661 &qca->ibs_sent_wakes);
662 debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir,
663 &qca->ibs_sent_wacks);
664 debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir,
665 &qca->ibs_recv_slps);
666 debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir,
667 &qca->ibs_recv_wakes);
668 debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir,
669 &qca->ibs_recv_wacks);
10be6c0f 670 debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote);
0ff252c1
BYTK		 671 debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on);
672 debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off);
10be6c0f 673 debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote);
0ff252c1
BYTK		 674 debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on);
675 debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off);
676 debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on);
677 debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off);
678 debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms);
679 debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms);
680
681 /* read/write */
99719449 682 mode = 0644;
0ff252c1
BYTK		 683 debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans);
684 debugfs_create_u32("tx_idle_delay", mode, ibs_dir,
685 &qca->tx_idle_delay);
686}
687
688/* Flush protocol data */
689static int qca_flush(struct hci_uart *hu)
690{
691 struct qca_data *qca = hu->priv;
692
693 BT_DBG("hu %p qca flush", hu);
694
695 skb_queue_purge(&qca->tx_wait_q);
696 skb_queue_purge(&qca->txq);
697
698 return 0;
699}
700
701/* Close protocol */
702static int qca_close(struct hci_uart *hu)
703{
704 struct qca_data *qca = hu->priv;
705
706 BT_DBG("hu %p qca close", hu);
707
708 serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu);
709
710 skb_queue_purge(&qca->tx_wait_q);
711 skb_queue_purge(&qca->txq);
d841502c 712 skb_queue_purge(&qca->rx_memdump_q);
e0d3da98
TG		 713 /*
714 * Shut the timers down so they can't be rearmed when
715 * destroy_workqueue() drains pending work which in turn might try
716 * to arm a timer. After shutdown rearm attempts are silently
717 * ignored by the timer core code.
718 */
719 timer_shutdown_sync(&qca->tx_idle_timer);
720 timer_shutdown_sync(&qca->wake_retrans_timer);
0ff252c1
BYTK		 721 destroy_workqueue(qca->workqueue);
722 qca->hu = NULL;
723
724 kfree_skb(qca->rx_skb);
725
726 hu->priv = NULL;
727
728 kfree(qca);
729
730 return 0;
731}
732
733/* Called upon a wake-up-indication from the device.
734 */
735static void device_want_to_wakeup(struct hci_uart *hu)
736{
737 unsigned long flags;
738 struct qca_data *qca = hu->priv;
739
740 BT_DBG("hu %p want to wake up", hu);
741
742 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
743
744 qca->ibs_recv_wakes++;
745
41d5b25f
CC		 746 /* Don't wake the rx up when suspending. */
747 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
748 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
749 return;
750 }
751
0ff252c1
BYTK		 752 switch (qca->rx_ibs_state) {
753 case HCI_IBS_RX_ASLEEP:
754 /* Make sure clock is on - we may have turned clock off since
755 * receiving the wake up indicator awake rx clock.
756 */
757 queue_work(qca->workqueue, &qca->ws_awake_rx);
758 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
759 return;
760
761 case HCI_IBS_RX_AWAKE:
762 /* Always acknowledge device wake up,
763 * sending IBS message doesn't count as TX ON.
764 */
765 if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) {
766 BT_ERR("Failed to acknowledge device wake up");
767 break;
768 }
769 qca->ibs_sent_wacks++;
770 break;
771
772 default:
773 /* Any other state is illegal */
774 BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d",
775 qca->rx_ibs_state);
776 break;
777 }
778
779 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
780
781 /* Actually send the packets */
782 hci_uart_tx_wakeup(hu);
783}
784
785/* Called upon a sleep-indication from the device.
786 */
787static void device_want_to_sleep(struct hci_uart *hu)
788{
789 unsigned long flags;
790 struct qca_data *qca = hu->priv;
791
6600c080 792 BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state);
0ff252c1
BYTK		 793
794 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
795
796 qca->ibs_recv_slps++;
797
798 switch (qca->rx_ibs_state) {
799 case HCI_IBS_RX_AWAKE:
800 /* Update state */
801 qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
802 /* Vote off rx clock under workqueue */
803 queue_work(qca->workqueue, &qca->ws_rx_vote_off);
804 break;
805
806 case HCI_IBS_RX_ASLEEP:
6600c080 807 break;
0ff252c1
BYTK		 808
809 default:
810 /* Any other state is illegal */
811 BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d",
812 qca->rx_ibs_state);
813 break;
814 }
815
41d5b25f
CC		 816 wake_up_interruptible(&qca->suspend_wait_q);
817
0ff252c1
BYTK		 818 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
819}
820
821/* Called upon wake-up-acknowledgement from the device
822 */
823static void device_woke_up(struct hci_uart *hu)
824{
825 unsigned long flags, idle_delay;
826 struct qca_data *qca = hu->priv;
827 struct sk_buff *skb = NULL;
828
829 BT_DBG("hu %p woke up", hu);
830
831 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
832
833 qca->ibs_recv_wacks++;
834
41d5b25f
CC		 835 /* Don't react to the wake-up-acknowledgment when suspending. */
836 if (test_bit(QCA_SUSPENDING, &qca->flags)) {
837 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
838 return;
839 }
840
0ff252c1
BYTK		 841 switch (qca->tx_ibs_state) {
842 case HCI_IBS_TX_AWAKE:
843 /* Expect one if we send 2 WAKEs */
844 BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d",
845 qca->tx_ibs_state);
846 break;
847
848 case HCI_IBS_TX_WAKING:
849 /* Send pending packets */
850 while ((skb = skb_dequeue(&qca->tx_wait_q)))
851 skb_queue_tail(&qca->txq, skb);
852
853 /* Switch timers and change state to HCI_IBS_TX_AWAKE */
854 del_timer(&qca->wake_retrans_timer);
855 idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
856 mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
857 qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
858 break;
859
860 case HCI_IBS_TX_ASLEEP:
0ff252c1
BYTK		 861 default:
862 BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d",
863 qca->tx_ibs_state);
864 break;
865 }
866
867 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
868
869 /* Actually send the packets */
870 hci_uart_tx_wakeup(hu);
871}
872
873/* Enqueue frame for transmittion (padding, crc, etc) may be called from
874 * two simultaneous tasklets.
875 */
876static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb)
877{
878 unsigned long flags = 0, idle_delay;
879 struct qca_data *qca = hu->priv;
880
881 BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb,
882 qca->tx_ibs_state);
883
3344537f
VLNG		 884 if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
885 /* As SSR is in progress, ignore the packets */
886 bt_dev_dbg(hu->hdev, "SSR is in progress");
887 kfree_skb(skb);
888 return 0;
889 }
890
0ff252c1 891 /* Prepend skb with frame type */
618e8bc2 892 memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
0ff252c1 893
035a960e
BG		 894 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
895
0ff252c1
BYTK		 896 /* Don't go to sleep in middle of patch download or
897 * Out-Of-Band(GPIOs control) sleep is selected.
41d5b25f 898 * Don't wake the device up when suspending.
0ff252c1 899 */
2be43aba 900 if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
41d5b25f 901 test_bit(QCA_SUSPENDING, &qca->flags)) {
0ff252c1 902 skb_queue_tail(&qca->txq, skb);
035a960e 903 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
0ff252c1
BYTK		 904 return 0;
905 }
906
0ff252c1
BYTK		 907 /* Act according to current state */
908 switch (qca->tx_ibs_state) {
909 case HCI_IBS_TX_AWAKE:
910 BT_DBG("Device awake, sending normally");
911 skb_queue_tail(&qca->txq, skb);
912 idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
913 mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
914 break;
915
916 case HCI_IBS_TX_ASLEEP:
917 BT_DBG("Device asleep, waking up and queueing packet");
918 /* Save packet for later */
919 skb_queue_tail(&qca->tx_wait_q, skb);
920
921 qca->tx_ibs_state = HCI_IBS_TX_WAKING;
922 /* Schedule a work queue to wake up device */
923 queue_work(qca->workqueue, &qca->ws_awake_device);
924 break;
925
926 case HCI_IBS_TX_WAKING:
927 BT_DBG("Device waking up, queueing packet");
928 /* Transient state; just keep packet for later */
929 skb_queue_tail(&qca->tx_wait_q, skb);
930 break;
931
932 default:
933 BT_ERR("Illegal tx state: %d (losing packet)",
934 qca->tx_ibs_state);
df4cfc91 935 dev_kfree_skb_irq(skb);
0ff252c1
BYTK		 936 break;
937 }
938
939 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
940
941 return 0;
942}
943
944static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb)
945{
946 struct hci_uart *hu = hci_get_drvdata(hdev);
947
948 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND);
949
950 device_want_to_sleep(hu);
951
952 kfree_skb(skb);
953 return 0;
954}
955
956static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb)
957{
958 struct hci_uart *hu = hci_get_drvdata(hdev);
959
960 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND);
961
962 device_want_to_wakeup(hu);
963
964 kfree_skb(skb);
965 return 0;
966}
967
968static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb)
969{
970 struct hci_uart *hu = hci_get_drvdata(hdev);
971
972 BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK);
973
974 device_woke_up(hu);
975
976 kfree_skb(skb);
977 return 0;
978}
979
c614ca3f
BG		 980static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb)
981{
982 /* We receive debug logs from chip as an ACL packets.
983 * Instead of sending the data to ACL to decode the
984 * received data, we are pushing them to the above layers
985 * as a diagnostic packet.
986 */
987 if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE)
988 return hci_recv_diag(hdev, skb);
989
990 return hci_recv_frame(hdev, skb);
991}
992
06d3fdfc
STA		 993static void qca_dmp_hdr(struct hci_dev *hdev, struct sk_buff *skb)
994{
995 struct hci_uart *hu = hci_get_drvdata(hdev);
996 struct qca_data *qca = hu->priv;
997 char buf[80];
998
999 snprintf(buf, sizeof(buf), "Controller Name: 0x%x\n",
1000 qca->controller_id);
1001 skb_put_data(skb, buf, strlen(buf));
1002
1003 snprintf(buf, sizeof(buf), "Firmware Version: 0x%x\n",
1004 qca->fw_version);
1005 skb_put_data(skb, buf, strlen(buf));
1006
1007 snprintf(buf, sizeof(buf), "Vendor:Qualcomm\n");
1008 skb_put_data(skb, buf, strlen(buf));
1009
1010 snprintf(buf, sizeof(buf), "Driver: %s\n",
1011 hu->serdev->dev.driver->name);
1012 skb_put_data(skb, buf, strlen(buf));
1013}
1014
d841502c
BG		 1015static void qca_controller_memdump(struct work_struct *work)
1016{
1017 struct qca_data *qca = container_of(work, struct qca_data,
1018 ctrl_memdump_evt);
1019 struct hci_uart *hu = qca->hu;
1020 struct sk_buff *skb;
1021 struct qca_memdump_event_hdr *cmd_hdr;
06d3fdfc 1022 struct qca_memdump_info *qca_memdump = qca->qca_memdump;
d841502c 1023 struct qca_dump_size *dump;
56b084ed 1024 u16 seq_no;
e5aeebdd 1025 u32 rx_size;
06d3fdfc 1026 int ret = 0;
e5aeebdd 1027 enum qca_btsoc_type soc_type = qca_soc_type(hu);
d841502c
BG		 1028
1029 while ((skb = skb_dequeue(&qca->rx_memdump_q))) {
1030
7c2c3e63 1031 mutex_lock(&qca->hci_memdump_lock);
f98aa80f
VLNG		 1032 /* Skip processing the received packets if timeout detected
1033 * or memdump collection completed.
1034 */
1035 if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
1036 qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
7c2c3e63
VLNG		 1037 mutex_unlock(&qca->hci_memdump_lock);
1038 return;
1039 }
1040
d841502c 1041 if (!qca_memdump) {
06d3fdfc 1042 qca_memdump = kzalloc(sizeof(struct qca_memdump_info),
d841502c 1043 GFP_ATOMIC);
7c2c3e63
VLNG		 1044 if (!qca_memdump) {
1045 mutex_unlock(&qca->hci_memdump_lock);
d841502c 1046 return;
7c2c3e63 1047 }
d841502c
BG		 1048
1049 qca->qca_memdump = qca_memdump;
1050 }
1051
1052 qca->memdump_state = QCA_MEMDUMP_COLLECTING;
1053 cmd_hdr = (void *) skb->data;
d841502c
BG		 1054 seq_no = __le16_to_cpu(cmd_hdr->seq_no);
1055 skb_pull(skb, sizeof(struct qca_memdump_event_hdr));
1056
1057 if (!seq_no) {
1058
1059 /* This is the first frame of memdump packet from
1060 * the controller, Disable IBS to recevie dump
1061 * with out any interruption, ideally time required for
1062 * the controller to send the dump is 8 seconds. let us
1063 * start timer to handle this asynchronous activity.
1064 */
2be43aba 1065 set_bit(QCA_IBS_DISABLED, &qca->flags);
d841502c
BG		 1066 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1067 dump = (void *) skb->data;
06d3fdfc
STA		 1068 qca_memdump->ram_dump_size = __le32_to_cpu(dump->dump_size);
1069 if (!(qca_memdump->ram_dump_size)) {
d841502c 1070 bt_dev_err(hu->hdev, "Rx invalid memdump size");
71f8e707 1071 kfree(qca_memdump);
d841502c 1072 kfree_skb(skb);
7c2c3e63 1073 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG		 1074 return;
1075 }
1076
7c2c3e63
VLNG		 1077 queue_delayed_work(qca->workqueue,
1078 &qca->ctrl_memdump_timeout,
06d3fdfc
STA		 1079 msecs_to_jiffies(MEMDUMP_TIMEOUT_MS));
1080 skb_pull(skb, sizeof(qca_memdump->ram_dump_size));
1081 qca_memdump->current_seq_no = 0;
1082 qca_memdump->received_dump = 0;
1083 ret = hci_devcd_init(hu->hdev, qca_memdump->ram_dump_size);
1084 bt_dev_info(hu->hdev, "hci_devcd_init Return:%d",
1085 ret);
1086 if (ret < 0) {
1087 kfree(qca->qca_memdump);
1088 qca->qca_memdump = NULL;
1089 qca->memdump_state = QCA_MEMDUMP_COLLECTED;
1090 cancel_delayed_work(&qca->ctrl_memdump_timeout);
1091 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1092 mutex_unlock(&qca->hci_memdump_lock);
1093 return;
1094 }
d841502c 1095
06d3fdfc
STA		 1096 bt_dev_info(hu->hdev, "QCA collecting dump of size:%u",
1097 qca_memdump->ram_dump_size);
1098
1099 }
d841502c
BG		 1100
1101 /* If sequence no 0 is missed then there is no point in
1102 * accepting the other sequences.
1103 */
06d3fdfc 1104 if (!test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
d841502c
BG		 1105 bt_dev_err(hu->hdev, "QCA: Discarding other packets");
1106 kfree(qca_memdump);
1107 kfree_skb(skb);
7c2c3e63 1108 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG		 1109 return;
1110 }
d841502c
BG		 1111 /* There could be chance of missing some packets from
1112 * the controller. In such cases let us store the dummy
1113 * packets in the buffer.
1114 */
e5aeebdd 1115 /* For QCA6390, controller does not lost packets but
07528783 1116 * sequence number field of packet sometimes has error
e5aeebdd
ZH		 1117 * bits, so skip this checking for missing packet.
1118 */
d841502c 1119 while ((seq_no > qca_memdump->current_seq_no + 1) &&
06d3fdfc
STA		 1120 (soc_type != QCA_QCA6390) &&
1121 seq_no != QCA_LAST_SEQUENCE_NUM) {
d841502c
BG		 1122 bt_dev_err(hu->hdev, "QCA controller missed packet:%d",
1123 qca_memdump->current_seq_no);
e5aeebdd
ZH		 1124 rx_size = qca_memdump->received_dump;
1125 rx_size += QCA_DUMP_PACKET_SIZE;
1126 if (rx_size > qca_memdump->ram_dump_size) {
1127 bt_dev_err(hu->hdev,
1128 "QCA memdump received %d, no space for missed packet",
1129 qca_memdump->received_dump);
1130 break;
1131 }
06d3fdfc
STA		 1132 hci_devcd_append_pattern(hu->hdev, 0x00,
1133 QCA_DUMP_PACKET_SIZE);
d841502c
BG		 1134 qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE;
1135 qca_memdump->current_seq_no++;
1136 }
1137
06d3fdfc 1138 rx_size = qca_memdump->received_dump + skb->len;
e5aeebdd
ZH		 1139 if (rx_size <= qca_memdump->ram_dump_size) {
1140 if ((seq_no != QCA_LAST_SEQUENCE_NUM) &&
06d3fdfc 1141 (seq_no != qca_memdump->current_seq_no)) {
e5aeebdd
ZH		 1142 bt_dev_err(hu->hdev,
1143 "QCA memdump unexpected packet %d",
1144 seq_no);
06d3fdfc 1145 }
e5aeebdd
ZH		 1146 bt_dev_dbg(hu->hdev,
1147 "QCA memdump packet %d with length %d",
1148 seq_no, skb->len);
06d3fdfc
STA		 1149 hci_devcd_append(hu->hdev, skb);
1150 qca_memdump->current_seq_no += 1;
1151 qca_memdump->received_dump = rx_size;
e5aeebdd
ZH		 1152 } else {
1153 bt_dev_err(hu->hdev,
06d3fdfc
STA		 1154 "QCA memdump received no space for packet %d",
1155 qca_memdump->current_seq_no);
e5aeebdd 1156 }
06d3fdfc 1157
d841502c 1158 if (seq_no == QCA_LAST_SEQUENCE_NUM) {
e5aeebdd 1159 bt_dev_info(hu->hdev,
06d3fdfc
STA		 1160 "QCA memdump Done, received %d, total %d",
1161 qca_memdump->received_dump,
1162 qca_memdump->ram_dump_size);
1163 hci_devcd_complete(hu->hdev);
7c2c3e63 1164 cancel_delayed_work(&qca->ctrl_memdump_timeout);
d841502c
BG		 1165 kfree(qca->qca_memdump);
1166 qca->qca_memdump = NULL;
1167 qca->memdump_state = QCA_MEMDUMP_COLLECTED;
7c2c3e63 1168 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c 1169 }
7c2c3e63
VLNG		 1170
1171 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG		 1172 }
1173
1174}
1175
7c2c3e63
VLNG		 1176static int qca_controller_memdump_event(struct hci_dev *hdev,
1177 struct sk_buff *skb)
d841502c
BG		 1178{
1179 struct hci_uart *hu = hci_get_drvdata(hdev);
1180 struct qca_data *qca = hu->priv;
1181
3344537f 1182 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
d841502c
BG		 1183 skb_queue_tail(&qca->rx_memdump_q, skb);
1184 queue_work(qca->workqueue, &qca->ctrl_memdump_evt);
1185
1186 return 0;
1187}
1188
2faa3f15
MK		 1189static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
1190{
1191 struct hci_uart *hu = hci_get_drvdata(hdev);
1192 struct qca_data *qca = hu->priv;
1193
1194 if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) {
1195 struct hci_event_hdr *hdr = (void *)skb->data;
1196
1197 /* For the WCN3990 the vendor command for a baudrate change
1198 * isn't sent as synchronous HCI command, because the
1199 * controller sends the corresponding vendor event with the
1200 * new baudrate. The event is received and properly decoded
1201 * after changing the baudrate of the host port. It needs to
1202 * be dropped, otherwise it can be misinterpreted as
1203 * response to a later firmware download command (also a
1204 * vendor command).
1205 */
1206
1207 if (hdr->evt == HCI_EV_VENDOR)
1208 complete(&qca->drop_ev_comp);
1209
4974c839 1210 kfree_skb(skb);
2faa3f15
MK		 1211
1212 return 0;
1213 }
d841502c
BG		 1214 /* We receive chip memory dump as an event packet, With a dedicated
1215 * handler followed by a hardware error event. When this event is
1216 * received we store dump into a file before closing hci. This
1217 * dump will help in triaging the issues.
1218 */
1219 if ((skb->data[0] == HCI_VENDOR_PKT) &&
1220 (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE))
1221 return qca_controller_memdump_event(hdev, skb);
2faa3f15
MK		 1222
1223 return hci_recv_frame(hdev, skb);
1224}
1225
0ff252c1
BYTK		 1226#define QCA_IBS_SLEEP_IND_EVENT \
1227 .type = HCI_IBS_SLEEP_IND, \
1228 .hlen = 0, \
1229 .loff = 0, \
1230 .lsize = 0, \
1231 .maxlen = HCI_MAX_IBS_SIZE
1232
1233#define QCA_IBS_WAKE_IND_EVENT \
1234 .type = HCI_IBS_WAKE_IND, \
1235 .hlen = 0, \
1236 .loff = 0, \
1237 .lsize = 0, \
1238 .maxlen = HCI_MAX_IBS_SIZE
1239
1240#define QCA_IBS_WAKE_ACK_EVENT \
1241 .type = HCI_IBS_WAKE_ACK, \
1242 .hlen = 0, \
1243 .loff = 0, \
1244 .lsize = 0, \
1245 .maxlen = HCI_MAX_IBS_SIZE
1246
1247static const struct h4_recv_pkt qca_recv_pkts[] = {
c614ca3f 1248 { H4_RECV_ACL, .recv = qca_recv_acl_data },
0ff252c1 1249 { H4_RECV_SCO, .recv = hci_recv_frame },
2faa3f15 1250 { H4_RECV_EVENT, .recv = qca_recv_event },
0ff252c1
BYTK		 1251 { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind },
1252 { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack },
1253 { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind },
1254};
1255
1256static int qca_recv(struct hci_uart *hu, const void *data, int count)
1257{
1258 struct qca_data *qca = hu->priv;
1259
1260 if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
1261 return -EUNATCH;
1262
1263 qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count,
1264 qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts));
1265 if (IS_ERR(qca->rx_skb)) {
1266 int err = PTR_ERR(qca->rx_skb);
2064ee33 1267 bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
0ff252c1
BYTK		 1268 qca->rx_skb = NULL;
1269 return err;
1270 }
1271
1272 return count;
1273}
1274
1275static struct sk_buff *qca_dequeue(struct hci_uart *hu)
1276{
1277 struct qca_data *qca = hu->priv;
1278
1279 return skb_dequeue(&qca->txq);
1280}
1281
1282static uint8_t qca_get_baudrate_value(int speed)
1283{
ce26d813 1284 switch (speed) {
0ff252c1
BYTK		 1285 case 9600:
1286 return QCA_BAUDRATE_9600;
1287 case 19200:
1288 return QCA_BAUDRATE_19200;
1289 case 38400:
1290 return QCA_BAUDRATE_38400;
1291 case 57600:
1292 return QCA_BAUDRATE_57600;
1293 case 115200:
1294 return QCA_BAUDRATE_115200;
1295 case 230400:
1296 return QCA_BAUDRATE_230400;
1297 case 460800:
1298 return QCA_BAUDRATE_460800;
1299 case 500000:
1300 return QCA_BAUDRATE_500000;
1301 case 921600:
1302 return QCA_BAUDRATE_921600;
1303 case 1000000:
1304 return QCA_BAUDRATE_1000000;
1305 case 2000000:
1306 return QCA_BAUDRATE_2000000;
1307 case 3000000:
1308 return QCA_BAUDRATE_3000000;
be93a497
BG		 1309 case 3200000:
1310 return QCA_BAUDRATE_3200000;
0ff252c1
BYTK		 1311 case 3500000:
1312 return QCA_BAUDRATE_3500000;
1313 default:
1314 return QCA_BAUDRATE_115200;
1315 }
1316}
1317
1318static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)
1319{
1320 struct hci_uart *hu = hci_get_drvdata(hdev);
1321 struct qca_data *qca = hu->priv;
1322 struct sk_buff *skb;
1323 u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 };
1324
be93a497 1325 if (baudrate > QCA_BAUDRATE_3200000)
0ff252c1
BYTK		 1326 return -EINVAL;
1327
1328 cmd[4] = baudrate;
1329
25a13e38 1330 skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
0ff252c1 1331 if (!skb) {
2064ee33 1332 bt_dev_err(hdev, "Failed to allocate baudrate packet");
0ff252c1
BYTK		 1333 return -ENOMEM;
1334 }
1335
1336 /* Assign commands to change baudrate and packet type. */
59ae1d12 1337 skb_put_data(skb, cmd, sizeof(cmd));
618e8bc2 1338 hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
0ff252c1
BYTK		 1339
1340 skb_queue_tail(&qca->txq, skb);
1341 hci_uart_tx_wakeup(hu);
1342
94d66714
MK		 1343 /* Wait for the baudrate change request to be sent */
1344
1345 while (!skb_queue_empty(&qca->txq))
1346 usleep_range(100, 200);
1347
ecf2b768
MK		 1348 if (hu->serdev)
1349 serdev_device_wait_until_sent(hu->serdev,
94d66714
MK		 1350 msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
1351
1352 /* Give the controller time to process the request */
691d54d0
NA		 1353 switch (qca_soc_type(hu)) {
1354 case QCA_WCN3988:
1355 case QCA_WCN3990:
1356 case QCA_WCN3991:
1357 case QCA_WCN3998:
1358 case QCA_WCN6750:
1359 case QCA_WCN6855:
e0c1278a 1360 case QCA_WCN7850:
99719449 1361 usleep_range(1000, 10000);
691d54d0
NA		 1362 break;
1363
1364 default:
94d66714 1365 msleep(300);
691d54d0 1366 }
0ff252c1
BYTK		 1367
1368 return 0;
1369}
1370
05ba533c
TE		 1371static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed)
1372{
1373 if (hu->serdev)
1374 serdev_device_set_baudrate(hu->serdev, speed);
1375 else
1376 hci_uart_set_baudrate(hu, speed);
1377}
1378
9836b802 1379static int qca_send_power_pulse(struct hci_uart *hu, bool on)
fa9ad876 1380{
f9558270 1381 int ret;
94d66714 1382 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
9836b802 1383 u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE;
fa9ad876
BG		 1384
1385 /* These power pulses are single byte command which are sent
1386 * at required baudrate to wcn3990. On wcn3990, we have an external
1387 * circuit at Tx pin which decodes the pulse sent at specific baudrate.
1388 * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT
1389 * and also we use the same power inputs to turn on and off for
1390 * Wi-Fi/BT. Powering up the power sources will not enable BT, until
1391 * we send a power on pulse at 115200 bps. This algorithm will help to
1392 * save power. Disabling hardware flow control is mandatory while
1393 * sending power pulses to SoC.
1394 */
f9558270 1395 bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd);
fa9ad876 1396
f9558270 1397 serdev_device_write_flush(hu->serdev);
fa9ad876 1398 hci_uart_set_flow_control(hu, true);
f9558270
BG		 1399 ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
1400 if (ret < 0) {
1401 bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd);
1402 return ret;
1403 }
fa9ad876 1404
f9558270 1405 serdev_device_wait_until_sent(hu->serdev, timeout);
fa9ad876
BG		 1406 hci_uart_set_flow_control(hu, false);
1407
0ebcddd8 1408 /* Give to controller time to boot/shutdown */
ad571d72
MK		 1409 if (on)
1410 msleep(100);
0ebcddd8 1411 else
99719449 1412 usleep_range(1000, 10000);
ad571d72 1413
fa9ad876
BG		 1414 return 0;
1415}
1416
83d9c5e5
BG		 1417static unsigned int qca_get_speed(struct hci_uart *hu,
1418 enum qca_speed_type speed_type)
1419{
1420 unsigned int speed = 0;
1421
1422 if (speed_type == QCA_INIT_SPEED) {
1423 if (hu->init_speed)
1424 speed = hu->init_speed;
1425 else if (hu->proto->init_speed)
1426 speed = hu->proto->init_speed;
1427 } else {
1428 if (hu->oper_speed)
1429 speed = hu->oper_speed;
1430 else if (hu->proto->oper_speed)
1431 speed = hu->proto->oper_speed;
1432 }
1433
1434 return speed;
1435}
1436
1437static int qca_check_speeds(struct hci_uart *hu)
1438{
691d54d0
NA		 1439 switch (qca_soc_type(hu)) {
1440 case QCA_WCN3988:
1441 case QCA_WCN3990:
1442 case QCA_WCN3991:
1443 case QCA_WCN3998:
1444 case QCA_WCN6750:
1445 case QCA_WCN6855:
e0c1278a 1446 case QCA_WCN7850:
fa9ad876
BG		 1447 if (!qca_get_speed(hu, QCA_INIT_SPEED) &&
1448 !qca_get_speed(hu, QCA_OPER_SPEED))
1449 return -EINVAL;
691d54d0
NA		 1450 break;
1451
1452 default:
fa9ad876
BG		 1453 if (!qca_get_speed(hu, QCA_INIT_SPEED) ||
1454 !qca_get_speed(hu, QCA_OPER_SPEED))
1455 return -EINVAL;
1456 }
83d9c5e5
BG		 1457
1458 return 0;
1459}
1460
1461static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type)
1462{
1463 unsigned int speed, qca_baudrate;
2faa3f15 1464 struct qca_data *qca = hu->priv;
78e8fa29 1465 int ret = 0;
83d9c5e5
BG		 1466
1467 if (speed_type == QCA_INIT_SPEED) {
1468 speed = qca_get_speed(hu, QCA_INIT_SPEED);
1469 if (speed)
1470 host_set_baudrate(hu, speed);
1471 } else {
4fdd5a4f
MK		 1472 enum qca_btsoc_type soc_type = qca_soc_type(hu);
1473
83d9c5e5
BG		 1474 speed = qca_get_speed(hu, QCA_OPER_SPEED);
1475 if (!speed)
1476 return 0;
1477
78e8fa29
BG		 1478 /* Disable flow control for wcn3990 to deassert RTS while
1479 * changing the baudrate of chip and host.
1480 */
691d54d0
NA		 1481 switch (soc_type) {
1482 case QCA_WCN3988:
1483 case QCA_WCN3990:
1484 case QCA_WCN3991:
1485 case QCA_WCN3998:
1486 case QCA_WCN6750:
1487 case QCA_WCN6855:
e0c1278a 1488 case QCA_WCN7850:
78e8fa29 1489 hci_uart_set_flow_control(hu, true);
691d54d0 1490 break;
78e8fa29 1491
691d54d0
NA		 1492 default:
1493 break;
1494 }
1495
1496 switch (soc_type) {
1497 case QCA_WCN3990:
2faa3f15
MK		 1498 reinit_completion(&qca->drop_ev_comp);
1499 set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
691d54d0
NA		 1500 break;
1501
1502 default:
1503 break;
2faa3f15
MK		 1504 }
1505
83d9c5e5 1506 qca_baudrate = qca_get_baudrate_value(speed);
fa9ad876 1507 bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed);
83d9c5e5
BG		 1508 ret = qca_set_baudrate(hu->hdev, qca_baudrate);
1509 if (ret)
78e8fa29 1510 goto error;
83d9c5e5
BG		 1511
1512 host_set_baudrate(hu, speed);
78e8fa29
BG		 1513
1514error:
691d54d0
NA		 1515 switch (soc_type) {
1516 case QCA_WCN3988:
1517 case QCA_WCN3990:
1518 case QCA_WCN3991:
1519 case QCA_WCN3998:
1520 case QCA_WCN6750:
1521 case QCA_WCN6855:
e0c1278a 1522 case QCA_WCN7850:
78e8fa29 1523 hci_uart_set_flow_control(hu, false);
691d54d0 1524 break;
2faa3f15 1525
691d54d0
NA		 1526 default:
1527 break;
1528 }
1529
1530 switch (soc_type) {
1531 case QCA_WCN3990:
2faa3f15
MK		 1532 /* Wait for the controller to send the vendor event
1533 * for the baudrate change command.
1534 */
1535 if (!wait_for_completion_timeout(&qca->drop_ev_comp,
1536 msecs_to_jiffies(100))) {
1537 bt_dev_err(hu->hdev,
1538 "Failed to change controller baudrate\n");
1539 ret = -ETIMEDOUT;
1540 }
1541
1542 clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
691d54d0
NA		 1543 break;
1544
1545 default:
1546 break;
2faa3f15 1547 }
83d9c5e5
BG		 1548 }
1549
78e8fa29 1550 return ret;
83d9c5e5
BG		 1551}
1552
d841502c
BG		 1553static int qca_send_crashbuffer(struct hci_uart *hu)
1554{
1555 struct qca_data *qca = hu->priv;
1556 struct sk_buff *skb;
1557
1558 skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL);
1559 if (!skb) {
1560 bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet");
1561 return -ENOMEM;
1562 }
1563
1564 /* We forcefully crash the controller, by sending 0xfb byte for
1565 * 1024 times. We also might have chance of losing data, To be
1566 * on safer side we send 1096 bytes to the SoC.
1567 */
1568 memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE,
1569 QCA_CRASHBYTE_PACKET_LEN);
1570 hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
1571 bt_dev_info(hu->hdev, "crash the soc to collect controller dump");
1572 skb_queue_tail(&qca->txq, skb);
1573 hci_uart_tx_wakeup(hu);
1574
1575 return 0;
1576}
1577
1578static void qca_wait_for_dump_collection(struct hci_dev *hdev)
1579{
1580 struct hci_uart *hu = hci_get_drvdata(hdev);
1581 struct qca_data *qca = hu->priv;
d841502c
BG		 1582
1583 wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION,
1584 TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS);
1585
1586 clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c
BG		 1587}
1588
1589static void qca_hw_error(struct hci_dev *hdev, u8 code)
1590{
1591 struct hci_uart *hu = hci_get_drvdata(hdev);
1592 struct qca_data *qca = hu->priv;
1593
3344537f 1594 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
7c2c3e63 1595 set_bit(QCA_HW_ERROR_EVENT, &qca->flags);
d841502c
BG		 1596 bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state);
1597
1598 if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
1599 /* If hardware error event received for other than QCA
1600 * soc memory dump event, then we need to crash the SOC
1601 * and wait here for 8 seconds to get the dump packets.
1602 * This will block main thread to be on hold until we
1603 * collect dump.
1604 */
1605 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
1606 qca_send_crashbuffer(hu);
1607 qca_wait_for_dump_collection(hdev);
1608 } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
1609 /* Let us wait here until memory dump collected or
1610 * memory dump timer expired.
1611 */
1612 bt_dev_info(hdev, "waiting for dump to complete");
1613 qca_wait_for_dump_collection(hdev);
1614 }
7c2c3e63 1615
f98aa80f 1616 mutex_lock(&qca->hci_memdump_lock);
7c2c3e63
VLNG		 1617 if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
1618 bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout");
06d3fdfc 1619 hci_devcd_abort(hu->hdev);
f98aa80f 1620 if (qca->qca_memdump) {
f98aa80f
VLNG		 1621 kfree(qca->qca_memdump);
1622 qca->qca_memdump = NULL;
1623 }
7c2c3e63
VLNG		 1624 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
1625 cancel_delayed_work(&qca->ctrl_memdump_timeout);
f98aa80f
VLNG		 1626 }
1627 mutex_unlock(&qca->hci_memdump_lock);
1628
1629 if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
1630 qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
7c2c3e63 1631 cancel_work_sync(&qca->ctrl_memdump_evt);
f98aa80f 1632 skb_queue_purge(&qca->rx_memdump_q);
7c2c3e63
VLNG		 1633 }
1634
1635 clear_bit(QCA_HW_ERROR_EVENT, &qca->flags);
d841502c
BG		 1636}
1637
1638static void qca_cmd_timeout(struct hci_dev *hdev)
1639{
1640 struct hci_uart *hu = hci_get_drvdata(hdev);
1641 struct qca_data *qca = hu->priv;
1642
3344537f
VLNG		 1643 set_bit(QCA_SSR_TRIGGERED, &qca->flags);
1644 if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
1645 set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
d841502c 1646 qca_send_crashbuffer(hu);
3344537f
VLNG		 1647 qca_wait_for_dump_collection(hdev);
1648 } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
1649 /* Let us wait here until memory dump collected or
1650 * memory dump timer expired.
1651 */
1652 bt_dev_info(hdev, "waiting for dump to complete");
1653 qca_wait_for_dump_collection(hdev);
1654 }
1655
1656 mutex_lock(&qca->hci_memdump_lock);
1657 if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
1658 qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
1659 if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
1660 /* Inject hw error event to reset the device
1661 * and driver.
1662 */
1663 hci_reset_dev(hu->hdev);
1664 }
1665 }
1666 mutex_unlock(&qca->hci_memdump_lock);
d841502c
BG		 1667}
1668
4539ca67 1669static bool qca_wakeup(struct hci_dev *hdev)
c1a74160
VLNG		 1670{
1671 struct hci_uart *hu = hci_get_drvdata(hdev);
1672 bool wakeup;
1673
03b0093f
ZJ		 1674 /* BT SoC attached through the serial bus is handled by the serdev driver.
1675 * So we need to use the device handle of the serdev driver to get the
1676 * status of device may wakeup.
c1a74160 1677 */
03b0093f 1678 wakeup = device_may_wakeup(&hu->serdev->ctrl->dev);
c1a74160
VLNG		 1679 bt_dev_dbg(hu->hdev, "wakeup status : %d", wakeup);
1680
bde63e9e 1681 return wakeup;
c1a74160
VLNG		 1682}
1683
d8f97da1 1684static int qca_regulator_init(struct hci_uart *hu)
fa9ad876 1685{
d8f97da1 1686 enum qca_btsoc_type soc_type = qca_soc_type(hu);
3e4be65e 1687 struct qca_serdev *qcadev;
fa9ad876 1688 int ret;
d8f97da1 1689 bool sw_ctrl_state;
fa9ad876 1690
3e4be65e
BG		 1691 /* Check for vregs status, may be hci down has turned
1692 * off the voltage regulator.
1693 */
1694 qcadev = serdev_device_get_drvdata(hu->serdev);
1695 if (!qcadev->bt_power->vregs_on) {
1696 serdev_device_close(hu->serdev);
a9314e76 1697 ret = qca_regulator_enable(qcadev);
3e4be65e
BG		 1698 if (ret)
1699 return ret;
1700
1701 ret = serdev_device_open(hu->serdev);
1702 if (ret) {
1703 bt_dev_err(hu->hdev, "failed to open port");
1704 return ret;
1705 }
1706 }
1707
691d54d0
NA		 1708 switch (soc_type) {
1709 case QCA_WCN3988:
1710 case QCA_WCN3990:
1711 case QCA_WCN3991:
1712 case QCA_WCN3998:
d8f97da1
VLNG		 1713 /* Forcefully enable wcn399x to enter in to boot mode. */
1714 host_set_baudrate(hu, 2400);
1715 ret = qca_send_power_pulse(hu, false);
1716 if (ret)
1717 return ret;
691d54d0
NA		 1718 break;
1719
1720 default:
1721 break;
d8f97da1
VLNG		 1722 }
1723
1724 /* For wcn6750 need to enable gpio bt_en */
1725 if (qcadev->bt_en) {
1726 gpiod_set_value_cansleep(qcadev->bt_en, 0);
1727 msleep(50);
1728 gpiod_set_value_cansleep(qcadev->bt_en, 1);
1729 msleep(50);
1730 if (qcadev->sw_ctrl) {
1731 sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
1732 bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
1733 }
1734 }
fa9ad876
BG		 1735
1736 qca_set_speed(hu, QCA_INIT_SPEED);
d8f97da1 1737
691d54d0
NA		 1738 switch (soc_type) {
1739 case QCA_WCN3988:
1740 case QCA_WCN3990:
1741 case QCA_WCN3991:
1742 case QCA_WCN3998:
d8f97da1
VLNG		 1743 ret = qca_send_power_pulse(hu, true);
1744 if (ret)
1745 return ret;
691d54d0
NA		 1746 break;
1747
1748 default:
1749 break;
d8f97da1 1750 }
fa9ad876 1751
fa9ad876
BG		 1752 /* Now the device is in ready state to communicate with host.
1753 * To sync host with device we need to reopen port.
1754 * Without this, we will have RTS and CTS synchronization
1755 * issues.
1756 */
1757 serdev_device_close(hu->serdev);
1758 ret = serdev_device_open(hu->serdev);
1759 if (ret) {
1760 bt_dev_err(hu->hdev, "failed to open port");
1761 return ret;
1762 }
1763
1764 hci_uart_set_flow_control(hu, false);
1765
1766 return 0;
1767}
1768
5e6d8401
RL		 1769static int qca_power_on(struct hci_dev *hdev)
1770{
1771 struct hci_uart *hu = hci_get_drvdata(hdev);
1772 enum qca_btsoc_type soc_type = qca_soc_type(hu);
1773 struct qca_serdev *qcadev;
2be43aba 1774 struct qca_data *qca = hu->priv;
5e6d8401
RL		 1775 int ret = 0;
1776
1777 /* Non-serdev device usually is powered by external power
1778 * and don't need additional action in driver for power on
1779 */
1780 if (!hu->serdev)
1781 return 0;
1782
691d54d0
NA		 1783 switch (soc_type) {
1784 case QCA_WCN3988:
1785 case QCA_WCN3990:
1786 case QCA_WCN3991:
1787 case QCA_WCN3998:
1788 case QCA_WCN6750:
1789 case QCA_WCN6855:
e0c1278a 1790 case QCA_WCN7850:
d8f97da1 1791 ret = qca_regulator_init(hu);
691d54d0
NA		 1792 break;
1793
1794 default:
5e6d8401 1795 qcadev = serdev_device_get_drvdata(hu->serdev);
77131dfe 1796 if (qcadev->bt_en) {
8a208b24
RL		 1797 gpiod_set_value_cansleep(qcadev->bt_en, 1);
1798 /* Controller needs time to bootup. */
1799 msleep(150);
1800 }
5e6d8401
RL		 1801 }
1802
2be43aba 1803 clear_bit(QCA_BT_OFF, &qca->flags);
5e6d8401
RL		 1804 return ret;
1805}
1806
06d3fdfc
STA		 1807static void hci_coredump_qca(struct hci_dev *hdev)
1808{
1809 static const u8 param[] = { 0x26 };
1810 struct sk_buff *skb;
1811
1812 skb = __hci_cmd_sync(hdev, 0xfc0c, 1, param, HCI_CMD_TIMEOUT);
1813 if (IS_ERR(skb))
1814 bt_dev_err(hdev, "%s: trigger crash failed (%ld)", __func__, PTR_ERR(skb));
1815 kfree_skb(skb);
1816}
1817
0ff252c1
BYTK		 1818static int qca_setup(struct hci_uart *hu)
1819{
1820 struct hci_dev *hdev = hu->hdev;
1821 struct qca_data *qca = hu->priv;
1822 unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200;
bb2500ab 1823 unsigned int retries = 0;
4fdd5a4f 1824 enum qca_btsoc_type soc_type = qca_soc_type(hu);
99c905c6 1825 const char *firmware_name = qca_get_firmware_name(hu);
0ff252c1 1826 int ret;
059924fd 1827 struct qca_btsoc_version ver;
691d54d0 1828 const char *soc_name;
0ff252c1 1829
83d9c5e5
BG		 1830 ret = qca_check_speeds(hu);
1831 if (ret)
1832 return ret;
1833
55c0bd77 1834 clear_bit(QCA_ROM_FW, &qca->flags);
0ff252c1 1835 /* Patch downloading has to be done without IBS mode */
2be43aba 1836 set_bit(QCA_IBS_DISABLED, &qca->flags);
0ff252c1 1837
e14c167a
RL		 1838 /* Enable controller to do both LE scan and BR/EDR inquiry
1839 * simultaneously.
1840 */
1841 set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks);
1842
691d54d0
NA		 1843 switch (soc_type) {
1844 case QCA_WCN3988:
1845 case QCA_WCN3990:
1846 case QCA_WCN3991:
1847 case QCA_WCN3998:
1848 soc_name = "wcn399x";
1849 break;
1850
1851 case QCA_WCN6750:
1852 soc_name = "wcn6750";
1853 break;
1854
1855 case QCA_WCN6855:
1856 soc_name = "wcn6855";
1857 break;
1858
e0c1278a
NA		 1859 case QCA_WCN7850:
1860 soc_name = "wcn7850";
1861 break;
1862
691d54d0
NA		 1863 default:
1864 soc_name = "ROME/QCA6390";
1865 }
1866 bt_dev_info(hdev, "setting up %s", soc_name);
3e4be65e 1867
58789a19
VLNG		 1868 qca->memdump_state = QCA_MEMDUMP_IDLE;
1869
bb2500ab 1870retry:
5e6d8401
RL		 1871 ret = qca_power_on(hdev);
1872 if (ret)
9e80587a 1873 goto out;
5e6d8401 1874
3344537f
VLNG		 1875 clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
1876
691d54d0
NA		 1877 switch (soc_type) {
1878 case QCA_WCN3988:
1879 case QCA_WCN3990:
1880 case QCA_WCN3991:
1881 case QCA_WCN3998:
1882 case QCA_WCN6750:
1883 case QCA_WCN6855:
e0c1278a 1884 case QCA_WCN7850:
5971752d 1885 set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks);
34af56e8 1886 hci_set_aosp_capable(hdev);
fa9ad876 1887
059924fd 1888 ret = qca_read_soc_version(hdev, &ver, soc_type);
fa9ad876 1889 if (ret)
9e80587a 1890 goto out;
691d54d0
NA		 1891 break;
1892
1893 default:
fa9ad876
BG		 1894 qca_set_speed(hu, QCA_INIT_SPEED);
1895 }
0ff252c1
BYTK		 1896
1897 /* Setup user speed if needed */
83d9c5e5 1898 speed = qca_get_speed(hu, QCA_OPER_SPEED);
0ff252c1 1899 if (speed) {
83d9c5e5
BG		 1900 ret = qca_set_speed(hu, QCA_OPER_SPEED);
1901 if (ret)
9e80587a 1902 goto out;
83d9c5e5
BG		 1903
1904 qca_baudrate = qca_get_baudrate_value(speed);
0ff252c1
BYTK		 1905 }
1906
691d54d0
NA		 1907 switch (soc_type) {
1908 case QCA_WCN3988:
1909 case QCA_WCN3990:
1910 case QCA_WCN3991:
1911 case QCA_WCN3998:
1912 case QCA_WCN6750:
1913 case QCA_WCN6855:
e0c1278a 1914 case QCA_WCN7850:
691d54d0
NA		 1915 break;
1916
1917 default:
fa9ad876 1918 /* Get QCA version information */
059924fd 1919 ret = qca_read_soc_version(hdev, &ver, soc_type);
fa9ad876 1920 if (ret)
9e80587a 1921 goto out;
fa9ad876 1922 }
aadebac4 1923
0ff252c1 1924 /* Setup patch / NVM configurations */
059924fd 1925 ret = qca_uart_setup(hdev, qca_baudrate, soc_type, ver,
99c905c6 1926 firmware_name);
0ff252c1 1927 if (!ret) {
2be43aba 1928 clear_bit(QCA_IBS_DISABLED, &qca->flags);
0ff252c1 1929 qca_debugfs_init(hdev);
d841502c
BG		 1930 hu->hdev->hw_error = qca_hw_error;
1931 hu->hdev->cmd_timeout = qca_cmd_timeout;
e9b3e5b8
ZJ		 1932 if (device_can_wakeup(hu->serdev->ctrl->dev.parent))
1933 hu->hdev->wakeup = qca_wakeup;
ba8f3597
LP		 1934 } else if (ret == -ENOENT) {
1935 /* No patch/nvm-config found, run with original fw/config */
55c0bd77 1936 set_bit(QCA_ROM_FW, &qca->flags);
ba8f3597 1937 ret = 0;
7dc5fe08
AP		 1938 } else if (ret == -EAGAIN) {
1939 /*
1940 * Userspace firmware loader will return -EAGAIN in case no
1941 * patch/nvm-config is found, so run with original fw/config.
1942 */
55c0bd77 1943 set_bit(QCA_ROM_FW, &qca->flags);
7dc5fe08 1944 ret = 0;
9e80587a
BG		 1945 }
1946
1947out:
1948 if (ret && retries < MAX_INIT_RETRIES) {
1949 bt_dev_warn(hdev, "Retry BT power ON:%d", retries);
1950 qca_power_shutdown(hu);
1951 if (hu->serdev) {
1952 serdev_device_close(hu->serdev);
1953 ret = serdev_device_open(hu->serdev);
1954 if (ret) {
1955 bt_dev_err(hdev, "failed to open port");
1956 return ret;
bb2500ab 1957 }
bb2500ab 1958 }
9e80587a
BG		 1959 retries++;
1960 goto retry;
0ff252c1
BYTK		 1961 }
1962
1963 /* Setup bdaddr */
e5d6468f 1964 if (soc_type == QCA_ROME)
5c0a1001 1965 hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
e5d6468f
RL		 1966 else
1967 hu->hdev->set_bdaddr = qca_set_bdaddr;
06d3fdfc
STA		 1968 qca->fw_version = le16_to_cpu(ver.patch_ver);
1969 qca->controller_id = le16_to_cpu(ver.rom_ver);
1970 hci_devcd_register(hdev, hci_coredump_qca, qca_dmp_hdr, NULL);
0ff252c1
BYTK		 1971
1972 return ret;
1973}
1974
2edc9c5c 1975static const struct hci_uart_proto qca_proto = {
0ff252c1
BYTK		 1976 .id = HCI_UART_QCA,
1977 .name = "QCA",
aee61f7a 1978 .manufacturer = 29,
0ff252c1
BYTK		 1979 .init_speed = 115200,
1980 .oper_speed = 3000000,
1981 .open = qca_open,
1982 .close = qca_close,
1983 .flush = qca_flush,
1984 .setup = qca_setup,
1985 .recv = qca_recv,
1986 .enqueue = qca_enqueue,
1987 .dequeue = qca_dequeue,
1988};
1989
f904feef
LW		 1990static const struct qca_device_data qca_soc_data_wcn3988 __maybe_unused = {
1991 .soc_type = QCA_WCN3988,
1992 .vregs = (struct qca_vreg []) {
1993 { "vddio", 15000 },
1994 { "vddxo", 80000 },
1995 { "vddrf", 300000 },
1996 { "vddch0", 450000 },
1997 },
1998 .num_vregs = 4,
1999};
2000
44fac8a2 2001static const struct qca_device_data qca_soc_data_wcn3990 __maybe_unused = {
fa9ad876
BG		 2002 .soc_type = QCA_WCN3990,
2003 .vregs = (struct qca_vreg []) {
f2edd66e
BA		 2004 { "vddio", 15000 },
2005 { "vddxo", 80000 },
2006 { "vddrf", 300000 },
2007 { "vddch0", 450000 },
fa9ad876
BG		 2008 },
2009 .num_vregs = 4,
2010};
2011
44fac8a2 2012static const struct qca_device_data qca_soc_data_wcn3991 __maybe_unused = {
7d250a06
BG		 2013 .soc_type = QCA_WCN3991,
2014 .vregs = (struct qca_vreg []) {
2015 { "vddio", 15000 },
2016 { "vddxo", 80000 },
2017 { "vddrf", 300000 },
2018 { "vddch0", 450000 },
2019 },
2020 .num_vregs = 4,
54780138 2021 .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
7d250a06
BG		 2022};
2023
44fac8a2 2024static const struct qca_device_data qca_soc_data_wcn3998 __maybe_unused = {
523760b7
HB		 2025 .soc_type = QCA_WCN3998,
2026 .vregs = (struct qca_vreg []) {
f2edd66e
BA		 2027 { "vddio", 10000 },
2028 { "vddxo", 80000 },
2029 { "vddrf", 300000 },
2030 { "vddch0", 450000 },
523760b7
HB		 2031 },
2032 .num_vregs = 4,
2033};
2034
44fac8a2 2035static const struct qca_device_data qca_soc_data_qca6390 __maybe_unused = {
e5d6468f
RL		 2036 .soc_type = QCA_QCA6390,
2037 .num_vregs = 0,
2038};
2039
44fac8a2 2040static const struct qca_device_data qca_soc_data_wcn6750 __maybe_unused = {
d8f97da1
VLNG		 2041 .soc_type = QCA_WCN6750,
2042 .vregs = (struct qca_vreg []) {
2043 { "vddio", 5000 },
2044 { "vddaon", 26000 },
2045 { "vddbtcxmx", 126000 },
2046 { "vddrfacmn", 12500 },
2047 { "vddrfa0p8", 102000 },
2048 { "vddrfa1p7", 302000 },
2049 { "vddrfa1p2", 257000 },
2050 { "vddrfa2p2", 1700000 },
2051 { "vddasd", 200 },
2052 },
2053 .num_vregs = 9,
2054 .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
2055};
2056
0811ff48 2057static const struct qca_device_data qca_soc_data_wcn6855 __maybe_unused = {
095327fe
SK		 2058 .soc_type = QCA_WCN6855,
2059 .vregs = (struct qca_vreg []) {
2060 { "vddio", 5000 },
2061 { "vddbtcxmx", 126000 },
2062 { "vddrfacmn", 12500 },
2063 { "vddrfa0p8", 102000 },
2064 { "vddrfa1p7", 302000 },
2065 { "vddrfa1p2", 257000 },
2066 },
2067 .num_vregs = 6,
2068 .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
2069};
2070
e0c1278a
NA		 2071static const struct qca_device_data qca_soc_data_wcn7850 __maybe_unused = {
2072 .soc_type = QCA_WCN7850,
2073 .vregs = (struct qca_vreg []) {
2074 { "vddio", 5000 },
2075 { "vddaon", 26000 },
2076 { "vdddig", 126000 },
2077 { "vddrfa0p8", 102000 },
2078 { "vddrfa1p2", 257000 },
2079 { "vddrfa1p9", 302000 },
2080 },
2081 .num_vregs = 6,
2082 .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
2083};
2084
c2d78273 2085static void qca_power_shutdown(struct hci_uart *hu)
fa9ad876 2086{
a9314e76 2087 struct qca_serdev *qcadev;
035a960e
BG		 2088 struct qca_data *qca = hu->priv;
2089 unsigned long flags;
5559904c 2090 enum qca_btsoc_type soc_type = qca_soc_type(hu);
d8f97da1 2091 bool sw_ctrl_state;
035a960e
BG		 2092
2093 /* From this point we go into power off state. But serial port is
2094 * still open, stop queueing the IBS data and flush all the buffered
2095 * data in skb's.
2096 */
2097 spin_lock_irqsave(&qca->hci_ibs_lock, flags);
2be43aba 2098 set_bit(QCA_IBS_DISABLED, &qca->flags);
035a960e
BG		 2099 qca_flush(hu);
2100 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
2101
5559904c
RL		 2102 /* Non-serdev device usually is powered by external power
2103 * and don't need additional action in driver for power down
2104 */
2105 if (!hu->serdev)
2106 return;
2107
59f90f13
PS		 2108 qcadev = serdev_device_get_drvdata(hu->serdev);
2109
691d54d0
NA		 2110 switch (soc_type) {
2111 case QCA_WCN3988:
2112 case QCA_WCN3990:
2113 case QCA_WCN3991:
2114 case QCA_WCN3998:
5559904c
RL		 2115 host_set_baudrate(hu, 2400);
2116 qca_send_power_pulse(hu, false);
2117 qca_regulator_disable(qcadev);
691d54d0
NA		 2118 break;
2119
2120 case QCA_WCN6750:
2121 case QCA_WCN6855:
d8f97da1
VLNG		 2122 gpiod_set_value_cansleep(qcadev->bt_en, 0);
2123 msleep(100);
2124 qca_regulator_disable(qcadev);
2125 if (qcadev->sw_ctrl) {
2126 sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
2127 bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
2128 }
691d54d0
NA		 2129 break;
2130
2131 default:
5559904c
RL		 2132 gpiod_set_value_cansleep(qcadev->bt_en, 0);
2133 }
2be43aba
VLNG		 2134
2135 set_bit(QCA_BT_OFF, &qca->flags);
fa9ad876
BG		 2136}
2137
3e4be65e
BG		 2138static int qca_power_off(struct hci_dev *hdev)
2139{
2140 struct hci_uart *hu = hci_get_drvdata(hdev);
d841502c 2141 struct qca_data *qca = hu->priv;
4f9ed5bd 2142 enum qca_btsoc_type soc_type = qca_soc_type(hu);
3e4be65e 2143
58789a19
VLNG		 2144 hu->hdev->hw_error = NULL;
2145 hu->hdev->cmd_timeout = NULL;
2146
df1e5c51
PH		 2147 del_timer_sync(&qca->wake_retrans_timer);
2148 del_timer_sync(&qca->tx_idle_timer);
2149
d841502c 2150 /* Stop sending shutdown command if soc crashes. */
e5d6468f 2151 if (soc_type != QCA_ROME
4f9ed5bd 2152 && qca->memdump_state == QCA_MEMDUMP_IDLE) {
d841502c
BG		 2153 qca_send_pre_shutdown_cmd(hdev);
2154 usleep_range(8000, 10000);
2155 }
010376ab 2156
3e4be65e
BG		 2157 qca_power_shutdown(hu);
2158 return 0;
2159}
2160
a9314e76 2161static int qca_regulator_enable(struct qca_serdev *qcadev)
fa9ad876 2162{
a9314e76
BA		 2163 struct qca_power *power = qcadev->bt_power;
2164 int ret;
fa9ad876 2165
a9314e76
BA		 2166 /* Already enabled */
2167 if (power->vregs_on)
2168 return 0;
fa9ad876 2169
a9314e76 2170 BT_DBG("enabling %d regulators)", power->num_vregs);
fa9ad876 2171
a9314e76
BA		 2172 ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk);
2173 if (ret)
2174 return ret;
fa9ad876 2175
a9314e76 2176 power->vregs_on = true;
fa9ad876 2177
66cb7051 2178 ret = clk_prepare_enable(qcadev->susclk);
f3d63f50 2179 if (ret)
66cb7051 2180 qca_regulator_disable(qcadev);
66cb7051 2181
f3d63f50 2182 return ret;
fa9ad876
BG		 2183}
2184
a9314e76
BA		 2185static void qca_regulator_disable(struct qca_serdev *qcadev)
2186{
2187 struct qca_power *power;
2188
2189 if (!qcadev)
2190 return;
2191
2192 power = qcadev->bt_power;
2193
2194 /* Already disabled? */
2195 if (!power->vregs_on)
2196 return;
2197
2198 regulator_bulk_disable(power->num_vregs, power->vreg_bulk);
2199 power->vregs_on = false;
66cb7051 2200
f3d63f50 2201 clk_disable_unprepare(qcadev->susclk);
a9314e76
BA		 2202}
2203
fa9ad876
BG		 2204static int qca_init_regulators(struct qca_power *qca,
2205 const struct qca_vreg *vregs, size_t num_vregs)
2206{
c29ff107
BA		 2207 struct regulator_bulk_data *bulk;
2208 int ret;
fa9ad876
BG		 2209 int i;
2210
c29ff107
BA		 2211 bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL);
2212 if (!bulk)
fa9ad876
BG		 2213 return -ENOMEM;
2214
2215 for (i = 0; i < num_vregs; i++)
c29ff107
BA		 2216 bulk[i].supply = vregs[i].name;
2217
2218 ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk);
2219 if (ret < 0)
2220 return ret;
fa9ad876 2221
c29ff107
BA		 2222 for (i = 0; i < num_vregs; i++) {
2223 ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA);
2224 if (ret)
2225 return ret;
2226 }
2227
2228 qca->vreg_bulk = bulk;
163d42fa 2229 qca->num_vregs = num_vregs;
c29ff107
BA		 2230
2231 return 0;
fa9ad876
BG		 2232}
2233
05ba533c
TE		 2234static int qca_serdev_probe(struct serdev_device *serdev)
2235{
2236 struct qca_serdev *qcadev;
ae563183 2237 struct hci_dev *hdev;
a228f7a4 2238 const struct qca_device_data *data;
05ba533c 2239 int err;
8a208b24 2240 bool power_ctrl_enabled = true;
05ba533c
TE		 2241
2242 qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL);
2243 if (!qcadev)
2244 return -ENOMEM;
2245
2246 qcadev->serdev_hu.serdev = serdev;
9f3565b8 2247 data = device_get_match_data(&serdev->dev);
05ba533c 2248 serdev_device_set_drvdata(serdev, qcadev);
99c905c6
RL		 2249 device_property_read_string(&serdev->dev, "firmware-name",
2250 &qcadev->firmware_name);
37aee136
CH		 2251 device_property_read_u32(&serdev->dev, "max-speed",
2252 &qcadev->oper_speed);
2253 if (!qcadev->oper_speed)
2254 BT_DBG("UART will pick default operating speed");
2255
691d54d0 2256 if (data)
523760b7 2257 qcadev->btsoc_type = data->soc_type;
691d54d0
NA		 2258 else
2259 qcadev->btsoc_type = QCA_ROME;
2260
2261 switch (qcadev->btsoc_type) {
2262 case QCA_WCN3988:
2263 case QCA_WCN3990:
2264 case QCA_WCN3991:
2265 case QCA_WCN3998:
2266 case QCA_WCN6750:
2267 case QCA_WCN6855:
e0c1278a 2268 case QCA_WCN7850:
fa9ad876
BG		 2269 qcadev->bt_power = devm_kzalloc(&serdev->dev,
2270 sizeof(struct qca_power),
2271 GFP_KERNEL);
2272 if (!qcadev->bt_power)
2273 return -ENOMEM;
2274
2275 qcadev->bt_power->dev = &serdev->dev;
fa9ad876
BG		 2276 err = qca_init_regulators(qcadev->bt_power, data->vregs,
2277 data->num_vregs);
2278 if (err) {
2279 BT_ERR("Failed to init regulators:%d", err);
ae563183 2280 return err;
fa9ad876 2281 }
05ba533c 2282
fa9ad876 2283 qcadev->bt_power->vregs_on = false;
05ba533c 2284
d8f97da1
VLNG		 2285 qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
2286 GPIOD_OUT_LOW);
095327fe
SK		 2287 if (IS_ERR_OR_NULL(qcadev->bt_en) &&
2288 (data->soc_type == QCA_WCN6750 ||
2289 data->soc_type == QCA_WCN6855)) {
d8f97da1
VLNG		 2290 dev_err(&serdev->dev, "failed to acquire BT_EN gpio\n");
2291 power_ctrl_enabled = false;
2292 }
2293
2294 qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl",
2295 GPIOD_IN);
095327fe
SK		 2296 if (IS_ERR_OR_NULL(qcadev->sw_ctrl) &&
2297 (data->soc_type == QCA_WCN6750 ||
e0c1278a
NA		 2298 data->soc_type == QCA_WCN6855 ||
2299 data->soc_type == QCA_WCN7850))
d8f97da1
VLNG		 2300 dev_warn(&serdev->dev, "failed to acquire SW_CTRL gpio\n");
2301
66cb7051
VLNG		 2302 qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
2303 if (IS_ERR(qcadev->susclk)) {
2304 dev_err(&serdev->dev, "failed to acquire clk\n");
2305 return PTR_ERR(qcadev->susclk);
2306 }
2307
fa9ad876
BG		 2308 err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
2309 if (err) {
2310 BT_ERR("wcn3990 serdev registration failed");
ae563183 2311 return err;
fa9ad876 2312 }
691d54d0 2313 break;
e5d6468f 2314
691d54d0 2315 default:
77131dfe 2316 qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
fa9ad876 2317 GPIOD_OUT_LOW);
68456671 2318 if (IS_ERR_OR_NULL(qcadev->bt_en)) {
8a208b24
RL		 2319 dev_warn(&serdev->dev, "failed to acquire enable gpio\n");
2320 power_ctrl_enabled = false;
fa9ad876 2321 }
05ba533c 2322
77131dfe 2323 qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
4c07a5d7 2324 if (IS_ERR(qcadev->susclk)) {
8a208b24 2325 dev_warn(&serdev->dev, "failed to acquire clk\n");
4c07a5d7 2326 return PTR_ERR(qcadev->susclk);
8a208b24 2327 }
4c07a5d7
DC		 2328 err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ);
2329 if (err)
2330 return err;
2331
2332 err = clk_prepare_enable(qcadev->susclk);
2333 if (err)
2334 return err;
fa9ad876
BG		 2335
2336 err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
ae563183
RL		 2337 if (err) {
2338 BT_ERR("Rome serdev registration failed");
65a24d4c 2339 clk_disable_unprepare(qcadev->susclk);
ae563183
RL		 2340 return err;
2341 }
fa9ad876
BG		 2342 }
2343
85e90d93
APS		 2344 hdev = qcadev->serdev_hu.hdev;
2345
8a208b24 2346 if (power_ctrl_enabled) {
8a208b24
RL		 2347 set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks);
2348 hdev->shutdown = qca_power_off;
2349 }
05ba533c 2350
54780138
APS		 2351 if (data) {
2352 /* Wideband speech support must be set per driver since it can't
2353 * be queried via hci. Same with the valid le states quirk.
2354 */
2355 if (data->capabilities & QCA_CAP_WIDEBAND_SPEECH)
2356 set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED,
2357 &hdev->quirks);
2358
2359 if (data->capabilities & QCA_CAP_VALID_LE_STATES)
2360 set_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks);
2361 }
a228f7a4 2362
ae563183 2363 return 0;
05ba533c
TE		 2364}
2365
2366static void qca_serdev_remove(struct serdev_device *serdev)
2367{
2368 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
054ec5e9 2369 struct qca_power *power = qcadev->bt_power;
05ba533c 2370
691d54d0
NA		 2371 switch (qcadev->btsoc_type) {
2372 case QCA_WCN3988:
2373 case QCA_WCN3990:
2374 case QCA_WCN3991:
2375 case QCA_WCN3998:
2376 case QCA_WCN6750:
2377 case QCA_WCN6855:
e0c1278a 2378 case QCA_WCN7850:
691d54d0
NA		 2379 if (power->vregs_on) {
2380 qca_power_shutdown(&qcadev->serdev_hu);
2381 break;
2382 }
2383 fallthrough;
2384
2385 default:
2386 if (qcadev->susclk)
2387 clk_disable_unprepare(qcadev->susclk);
2388 }
05ba533c 2389
fa9ad876 2390 hci_uart_unregister_device(&qcadev->serdev_hu);
05ba533c
TE		 2391}
2392
7e7bbddd
ZH		 2393static void qca_serdev_shutdown(struct device *dev)
2394{
2395 int ret;
2396 int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
2397 struct serdev_device *serdev = to_serdev_device(dev);
2398 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
272970be
KK		 2399 struct hci_uart *hu = &qcadev->serdev_hu;
2400 struct hci_dev *hdev = hu->hdev;
2401 struct qca_data *qca = hu->priv;
7e7bbddd
ZH		 2402 const u8 ibs_wake_cmd[] = { 0xFD };
2403 const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 };
2404
2405 if (qcadev->btsoc_type == QCA_QCA6390) {
272970be
KK		 2406 if (test_bit(QCA_BT_OFF, &qca->flags) ||
2407 !test_bit(HCI_RUNNING, &hdev->flags))
2408 return;
2409
7e7bbddd
ZH		 2410 serdev_device_write_flush(serdev);
2411 ret = serdev_device_write_buf(serdev, ibs_wake_cmd,
2412 sizeof(ibs_wake_cmd));
2413 if (ret < 0) {
2414 BT_ERR("QCA send IBS_WAKE_IND error: %d", ret);
2415 return;
2416 }
2417 serdev_device_wait_until_sent(serdev, timeout);
2418 usleep_range(8000, 10000);
2419
2420 serdev_device_write_flush(serdev);
2421 ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd,
2422 sizeof(edl_reset_soc_cmd));
2423 if (ret < 0) {
2424 BT_ERR("QCA send EDL_RESET_REQ error: %d", ret);
2425 return;
2426 }
2427 serdev_device_wait_until_sent(serdev, timeout);
2428 usleep_range(8000, 10000);
2429 }
2430}
2431
41d5b25f
CC		 2432static int __maybe_unused qca_suspend(struct device *dev)
2433{
feac90d7
ZH		 2434 struct serdev_device *serdev = to_serdev_device(dev);
2435 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2436 struct hci_uart *hu = &qcadev->serdev_hu;
41d5b25f
CC		 2437 struct qca_data *qca = hu->priv;
2438 unsigned long flags;
e2a119cd 2439 bool tx_pending = false;
41d5b25f
CC		 2440 int ret = 0;
2441 u8 cmd;
2be43aba 2442 u32 wait_timeout = 0;
41d5b25f
CC		 2443
2444 set_bit(QCA_SUSPENDING, &qca->flags);
2445
55c0bd77
VLNG		 2446 /* if BT SoC is running with default firmware then it does not
2447 * support in-band sleep
2448 */
2449 if (test_bit(QCA_ROM_FW, &qca->flags))
2450 return 0;
2451
ad3a9c0e
VLNG		 2452 /* During SSR after memory dump collection, controller will be
2453 * powered off and then powered on.If controller is powered off
2454 * during SSR then we should wait until SSR is completed.
2455 */
2456 if (test_bit(QCA_BT_OFF, &qca->flags) &&
2457 !test_bit(QCA_SSR_TRIGGERED, &qca->flags))
2be43aba
VLNG		 2458 return 0;
2459
1bb0c663
VLNG		 2460 if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
2461 test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
2be43aba
VLNG		 2462 wait_timeout = test_bit(QCA_SSR_TRIGGERED, &qca->flags) ?
2463 IBS_DISABLE_SSR_TIMEOUT_MS :
2464 FW_DOWNLOAD_TIMEOUT_MS;
2465
2466 /* QCA_IBS_DISABLED flag is set to true, During FW download
2467 * and during memory dump collection. It is reset to false,
ad3a9c0e 2468 * After FW download complete.
2be43aba
VLNG		 2469 */
2470 wait_on_bit_timeout(&qca->flags, QCA_IBS_DISABLED,
2471 TASK_UNINTERRUPTIBLE, msecs_to_jiffies(wait_timeout));
2472
2473 if (test_bit(QCA_IBS_DISABLED, &qca->flags)) {
2474 bt_dev_err(hu->hdev, "SSR or FW download time out");
2475 ret = -ETIMEDOUT;
2476 goto error;
2477 }
2478 }
2479
41d5b25f
CC		 2480 cancel_work_sync(&qca->ws_awake_device);
2481 cancel_work_sync(&qca->ws_awake_rx);
2482
2483 spin_lock_irqsave_nested(&qca->hci_ibs_lock,
2484 flags, SINGLE_DEPTH_NESTING);
2485
2486 switch (qca->tx_ibs_state) {
2487 case HCI_IBS_TX_WAKING:
2488 del_timer(&qca->wake_retrans_timer);
a3b4cbfc 2489 fallthrough;
41d5b25f
CC		 2490 case HCI_IBS_TX_AWAKE:
2491 del_timer(&qca->tx_idle_timer);
2492
2493 serdev_device_write_flush(hu->serdev);
2494 cmd = HCI_IBS_SLEEP_IND;
2495 ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
2496
2497 if (ret < 0) {
2498 BT_ERR("Failed to send SLEEP to device");
2499 break;
2500 }
2501
2502 qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
2503 qca->ibs_sent_slps++;
e2a119cd 2504 tx_pending = true;
41d5b25f
CC		 2505 break;
2506
2507 case HCI_IBS_TX_ASLEEP:
2508 break;
2509
2510 default:
2511 BT_ERR("Spurious tx state %d", qca->tx_ibs_state);
2512 ret = -EINVAL;
2513 break;
2514 }
2515
2516 spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
2517
2518 if (ret < 0)
2519 goto error;
2520
e2a119cd
MK		 2521 if (tx_pending) {
2522 serdev_device_wait_until_sent(hu->serdev,
2523 msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
201a1124 2524 serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
e2a119cd 2525 }
41d5b25f
CC		 2526
2527 /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going
2528 * to sleep, so that the packet does not wake the system later.
2529 */
41d5b25f
CC		 2530 ret = wait_event_interruptible_timeout(qca->suspend_wait_q,
2531 qca->rx_ibs_state == HCI_IBS_RX_ASLEEP,
2532 msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS));
4da385f7
MK		 2533 if (ret == 0) {
2534 ret = -ETIMEDOUT;
2535 goto error;
eff981f6 2536 }
41d5b25f 2537
4da385f7 2538 return 0;
41d5b25f
CC		 2539
2540error:
2541 clear_bit(QCA_SUSPENDING, &qca->flags);
2542
2543 return ret;
2544}
2545
2546static int __maybe_unused qca_resume(struct device *dev)
2547{
feac90d7
ZH		 2548 struct serdev_device *serdev = to_serdev_device(dev);
2549 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2550 struct hci_uart *hu = &qcadev->serdev_hu;
41d5b25f
CC		 2551 struct qca_data *qca = hu->priv;
2552
2553 clear_bit(QCA_SUSPENDING, &qca->flags);
2554
2555 return 0;
2556}
2557
2558static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume);
2559
e5d6468f 2560#ifdef CONFIG_OF
05ba533c
TE		 2561static const struct of_device_id qca_bluetooth_of_match[] = {
2562 { .compatible = "qcom,qca6174-bt" },
e5d6468f 2563 { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390},
31d4ab85 2564 { .compatible = "qcom,qca9377-bt" },
f904feef 2565 { .compatible = "qcom,wcn3988-bt", .data = &qca_soc_data_wcn3988},
523760b7 2566 { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990},
7d250a06 2567 { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991},
523760b7 2568 { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998},
d8f97da1 2569 { .compatible = "qcom,wcn6750-bt", .data = &qca_soc_data_wcn6750},
095327fe 2570 { .compatible = "qcom,wcn6855-bt", .data = &qca_soc_data_wcn6855},
e0c1278a 2571 { .compatible = "qcom,wcn7850-bt", .data = &qca_soc_data_wcn7850},
05ba533c
TE		 2572 { /* sentinel */ }
2573};
2574MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match);
e5d6468f
RL		 2575#endif
2576
2577#ifdef CONFIG_ACPI
2578static const struct acpi_device_id qca_bluetooth_acpi_match[] = {
2579 { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2580 { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2581 { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2582 { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 },
2583 { },
2584};
2585MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match);
2586#endif
2587
6ce95a30
STA		 2588#ifdef CONFIG_DEV_COREDUMP
2589static void hciqca_coredump(struct device *dev)
2590{
2591 struct serdev_device *serdev = to_serdev_device(dev);
2592 struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
2593 struct hci_uart *hu = &qcadev->serdev_hu;
2594 struct hci_dev *hdev = hu->hdev;
2595
2596 if (hdev->dump.coredump)
2597 hdev->dump.coredump(hdev);
2598}
2599#endif
05ba533c
TE		 2600
2601static struct serdev_device_driver qca_serdev_driver = {
2602 .probe = qca_serdev_probe,
2603 .remove = qca_serdev_remove,
2604 .driver = {
2605 .name = "hci_uart_qca",
e5d6468f
RL		 2606 .of_match_table = of_match_ptr(qca_bluetooth_of_match),
2607 .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match),
7e7bbddd 2608 .shutdown = qca_serdev_shutdown,
41d5b25f 2609 .pm = &qca_pm_ops,
6ce95a30
STA		 2610#ifdef CONFIG_DEV_COREDUMP
2611 .coredump = hciqca_coredump,
2612#endif
05ba533c
TE		 2613 },
2614};
2615
0ff252c1
BYTK		 2616int __init qca_init(void)
2617{
05ba533c
TE		 2618 serdev_device_driver_register(&qca_serdev_driver);
2619
0ff252c1
BYTK		 2620 return hci_uart_register_proto(&qca_proto);
2621}
2622
2623int __exit qca_deinit(void)
2624{
05ba533c
TE		 2625 serdev_device_driver_unregister(&qca_serdev_driver);
2626
0ff252c1
BYTK		 2627 return hci_uart_unregister_proto(&qca_proto);
2628}
Linux 6.x block layer and io_uring tree(s)