Commit | Line | Data |
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45051539 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
0ff252c1 BYTK |
2 | /* |
3 | * Bluetooth Software UART Qualcomm protocol | |
4 | * | |
5 | * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management | |
6 | * protocol extension to H4. | |
7 | * | |
8 | * Copyright (C) 2007 Texas Instruments, Inc. | |
fa9ad876 | 9 | * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved. |
0ff252c1 BYTK |
10 | * |
11 | * Acknowledgements: | |
12 | * This file is based on hci_ll.c, which was... | |
13 | * Written by Ohad Ben-Cohen <ohad@bencohen.org> | |
14 | * which was in turn based on hci_h4.c, which was written | |
15 | * by Maxim Krasnyansky and Marcel Holtmann. | |
0ff252c1 BYTK |
16 | */ |
17 | ||
18 | #include <linux/kernel.h> | |
05ba533c | 19 | #include <linux/clk.h> |
2faa3f15 | 20 | #include <linux/completion.h> |
0ff252c1 | 21 | #include <linux/debugfs.h> |
fa9ad876 | 22 | #include <linux/delay.h> |
d841502c | 23 | #include <linux/devcoredump.h> |
fa9ad876 | 24 | #include <linux/device.h> |
05ba533c TE |
25 | #include <linux/gpio/consumer.h> |
26 | #include <linux/mod_devicetable.h> | |
27 | #include <linux/module.h> | |
fa9ad876 | 28 | #include <linux/of_device.h> |
e5d6468f | 29 | #include <linux/acpi.h> |
fa9ad876 BG |
30 | #include <linux/platform_device.h> |
31 | #include <linux/regulator/consumer.h> | |
05ba533c | 32 | #include <linux/serdev.h> |
7c2c3e63 | 33 | #include <linux/mutex.h> |
c614ca3f | 34 | #include <asm/unaligned.h> |
0ff252c1 BYTK |
35 | |
36 | #include <net/bluetooth/bluetooth.h> | |
37 | #include <net/bluetooth/hci_core.h> | |
38 | ||
39 | #include "hci_uart.h" | |
40 | #include "btqca.h" | |
41 | ||
42 | /* HCI_IBS protocol messages */ | |
43 | #define HCI_IBS_SLEEP_IND 0xFE | |
44 | #define HCI_IBS_WAKE_IND 0xFD | |
45 | #define HCI_IBS_WAKE_ACK 0xFC | |
f81b001a | 46 | #define HCI_MAX_IBS_SIZE 10 |
0ff252c1 | 47 | |
f81b001a | 48 | #define IBS_WAKE_RETRANS_TIMEOUT_MS 100 |
2d68476c | 49 | #define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200 |
41d5b25f | 50 | #define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000 |
94d66714 | 51 | #define CMD_TRANS_TIMEOUT_MS 100 |
d841502c | 52 | #define MEMDUMP_TIMEOUT_MS 8000 |
2be43aba VLNG |
53 | #define IBS_DISABLE_SSR_TIMEOUT_MS (MEMDUMP_TIMEOUT_MS + 1000) |
54 | #define FW_DOWNLOAD_TIMEOUT_MS 3000 | |
0ff252c1 | 55 | |
05ba533c TE |
56 | /* susclk rate */ |
57 | #define SUSCLK_RATE_32KHZ 32768 | |
58 | ||
c614ca3f BG |
59 | /* Controller debug log header */ |
60 | #define QCA_DEBUG_HANDLE 0x2EDC | |
61 | ||
bb2500ab RL |
62 | /* max retry count when init fails */ |
63 | #define MAX_INIT_RETRIES 3 | |
64 | ||
d841502c BG |
65 | /* Controller dump header */ |
66 | #define QCA_SSR_DUMP_HANDLE 0x0108 | |
67 | #define QCA_DUMP_PACKET_SIZE 255 | |
68 | #define QCA_LAST_SEQUENCE_NUM 0xFFFF | |
69 | #define QCA_CRASHBYTE_PACKET_LEN 1096 | |
70 | #define QCA_MEMDUMP_BYTE 0xFB | |
71 | ||
62a91990 | 72 | enum qca_flags { |
2be43aba | 73 | QCA_IBS_DISABLED, |
2faa3f15 | 74 | QCA_DROP_VENDOR_EVENT, |
41d5b25f | 75 | QCA_SUSPENDING, |
7c2c3e63 | 76 | QCA_MEMDUMP_COLLECTION, |
3344537f | 77 | QCA_HW_ERROR_EVENT, |
2be43aba VLNG |
78 | QCA_SSR_TRIGGERED, |
79 | QCA_BT_OFF | |
62a91990 MK |
80 | }; |
81 | ||
a228f7a4 APS |
82 | enum qca_capabilities { |
83 | QCA_CAP_WIDEBAND_SPEECH = BIT(0), | |
54780138 | 84 | QCA_CAP_VALID_LE_STATES = BIT(1), |
a228f7a4 | 85 | }; |
d841502c | 86 | |
0ff252c1 BYTK |
87 | /* HCI_IBS transmit side sleep protocol states */ |
88 | enum tx_ibs_states { | |
89 | HCI_IBS_TX_ASLEEP, | |
90 | HCI_IBS_TX_WAKING, | |
91 | HCI_IBS_TX_AWAKE, | |
92 | }; | |
93 | ||
94 | /* HCI_IBS receive side sleep protocol states */ | |
95 | enum rx_states { | |
96 | HCI_IBS_RX_ASLEEP, | |
97 | HCI_IBS_RX_AWAKE, | |
98 | }; | |
99 | ||
100 | /* HCI_IBS transmit and receive side clock state vote */ | |
101 | enum hci_ibs_clock_state_vote { | |
102 | HCI_IBS_VOTE_STATS_UPDATE, | |
103 | HCI_IBS_TX_VOTE_CLOCK_ON, | |
104 | HCI_IBS_TX_VOTE_CLOCK_OFF, | |
105 | HCI_IBS_RX_VOTE_CLOCK_ON, | |
106 | HCI_IBS_RX_VOTE_CLOCK_OFF, | |
107 | }; | |
108 | ||
d841502c BG |
109 | /* Controller memory dump states */ |
110 | enum qca_memdump_states { | |
111 | QCA_MEMDUMP_IDLE, | |
112 | QCA_MEMDUMP_COLLECTING, | |
113 | QCA_MEMDUMP_COLLECTED, | |
114 | QCA_MEMDUMP_TIMEOUT, | |
115 | }; | |
116 | ||
117 | struct qca_memdump_data { | |
118 | char *memdump_buf_head; | |
119 | char *memdump_buf_tail; | |
120 | u32 current_seq_no; | |
121 | u32 received_dump; | |
e5aeebdd | 122 | u32 ram_dump_size; |
d841502c BG |
123 | }; |
124 | ||
125 | struct qca_memdump_event_hdr { | |
126 | __u8 evt; | |
127 | __u8 plen; | |
128 | __u16 opcode; | |
129 | __u16 seq_no; | |
130 | __u8 reserved; | |
131 | } __packed; | |
132 | ||
133 | ||
134 | struct qca_dump_size { | |
135 | u32 dump_size; | |
136 | } __packed; | |
137 | ||
0ff252c1 BYTK |
138 | struct qca_data { |
139 | struct hci_uart *hu; | |
140 | struct sk_buff *rx_skb; | |
141 | struct sk_buff_head txq; | |
142 | struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */ | |
d841502c | 143 | struct sk_buff_head rx_memdump_q; /* Memdump wait queue */ |
0ff252c1 BYTK |
144 | spinlock_t hci_ibs_lock; /* HCI_IBS state lock */ |
145 | u8 tx_ibs_state; /* HCI_IBS transmit side power state*/ | |
146 | u8 rx_ibs_state; /* HCI_IBS receive side power state */ | |
621a5f7a VK |
147 | bool tx_vote; /* Clock must be on for TX */ |
148 | bool rx_vote; /* Clock must be on for RX */ | |
0ff252c1 BYTK |
149 | struct timer_list tx_idle_timer; |
150 | u32 tx_idle_delay; | |
151 | struct timer_list wake_retrans_timer; | |
152 | u32 wake_retrans; | |
153 | struct workqueue_struct *workqueue; | |
154 | struct work_struct ws_awake_rx; | |
155 | struct work_struct ws_awake_device; | |
156 | struct work_struct ws_rx_vote_off; | |
157 | struct work_struct ws_tx_vote_off; | |
d841502c | 158 | struct work_struct ctrl_memdump_evt; |
7c2c3e63 | 159 | struct delayed_work ctrl_memdump_timeout; |
d841502c | 160 | struct qca_memdump_data *qca_memdump; |
0ff252c1 | 161 | unsigned long flags; |
2faa3f15 | 162 | struct completion drop_ev_comp; |
41d5b25f | 163 | wait_queue_head_t suspend_wait_q; |
d841502c | 164 | enum qca_memdump_states memdump_state; |
7c2c3e63 | 165 | struct mutex hci_memdump_lock; |
0ff252c1 BYTK |
166 | |
167 | /* For debugging purpose */ | |
168 | u64 ibs_sent_wacks; | |
169 | u64 ibs_sent_slps; | |
170 | u64 ibs_sent_wakes; | |
171 | u64 ibs_recv_wacks; | |
172 | u64 ibs_recv_slps; | |
173 | u64 ibs_recv_wakes; | |
174 | u64 vote_last_jif; | |
175 | u32 vote_on_ms; | |
176 | u32 vote_off_ms; | |
177 | u64 tx_votes_on; | |
178 | u64 rx_votes_on; | |
179 | u64 tx_votes_off; | |
180 | u64 rx_votes_off; | |
181 | u64 votes_on; | |
182 | u64 votes_off; | |
183 | }; | |
184 | ||
83d9c5e5 BG |
185 | enum qca_speed_type { |
186 | QCA_INIT_SPEED = 1, | |
187 | QCA_OPER_SPEED | |
188 | }; | |
189 | ||
fa9ad876 BG |
190 | /* |
191 | * Voltage regulator information required for configuring the | |
192 | * QCA Bluetooth chipset | |
193 | */ | |
194 | struct qca_vreg { | |
195 | const char *name; | |
fa9ad876 BG |
196 | unsigned int load_uA; |
197 | }; | |
198 | ||
a228f7a4 | 199 | struct qca_device_data { |
fa9ad876 BG |
200 | enum qca_btsoc_type soc_type; |
201 | struct qca_vreg *vregs; | |
202 | size_t num_vregs; | |
a228f7a4 | 203 | uint32_t capabilities; |
fa9ad876 BG |
204 | }; |
205 | ||
206 | /* | |
207 | * Platform data for the QCA Bluetooth power driver. | |
208 | */ | |
209 | struct qca_power { | |
210 | struct device *dev; | |
fa9ad876 | 211 | struct regulator_bulk_data *vreg_bulk; |
163d42fa | 212 | int num_vregs; |
fa9ad876 BG |
213 | bool vregs_on; |
214 | }; | |
215 | ||
05ba533c TE |
216 | struct qca_serdev { |
217 | struct hci_uart serdev_hu; | |
218 | struct gpio_desc *bt_en; | |
219 | struct clk *susclk; | |
fa9ad876 BG |
220 | enum qca_btsoc_type btsoc_type; |
221 | struct qca_power *bt_power; | |
222 | u32 init_speed; | |
223 | u32 oper_speed; | |
99c905c6 | 224 | const char *firmware_name; |
05ba533c TE |
225 | }; |
226 | ||
a9314e76 BA |
227 | static int qca_regulator_enable(struct qca_serdev *qcadev); |
228 | static void qca_regulator_disable(struct qca_serdev *qcadev); | |
c2d78273 | 229 | static void qca_power_shutdown(struct hci_uart *hu); |
3e4be65e | 230 | static int qca_power_off(struct hci_dev *hdev); |
d841502c | 231 | static void qca_controller_memdump(struct work_struct *work); |
fa9ad876 | 232 | |
4fdd5a4f MK |
233 | static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu) |
234 | { | |
235 | enum qca_btsoc_type soc_type; | |
236 | ||
237 | if (hu->serdev) { | |
238 | struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev); | |
239 | ||
240 | soc_type = qsd->btsoc_type; | |
241 | } else { | |
242 | soc_type = QCA_ROME; | |
243 | } | |
244 | ||
245 | return soc_type; | |
246 | } | |
247 | ||
99c905c6 RL |
248 | static const char *qca_get_firmware_name(struct hci_uart *hu) |
249 | { | |
250 | if (hu->serdev) { | |
251 | struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev); | |
252 | ||
253 | return qsd->firmware_name; | |
254 | } else { | |
255 | return NULL; | |
256 | } | |
257 | } | |
258 | ||
0ff252c1 BYTK |
259 | static void __serial_clock_on(struct tty_struct *tty) |
260 | { | |
261 | /* TODO: Some chipset requires to enable UART clock on client | |
262 | * side to save power consumption or manual work is required. | |
263 | * Please put your code to control UART clock here if needed | |
264 | */ | |
265 | } | |
266 | ||
267 | static void __serial_clock_off(struct tty_struct *tty) | |
268 | { | |
269 | /* TODO: Some chipset requires to disable UART clock on client | |
270 | * side to save power consumption or manual work is required. | |
271 | * Please put your code to control UART clock off here if needed | |
272 | */ | |
273 | } | |
274 | ||
275 | /* serial_clock_vote needs to be called with the ibs lock held */ | |
276 | static void serial_clock_vote(unsigned long vote, struct hci_uart *hu) | |
277 | { | |
278 | struct qca_data *qca = hu->priv; | |
279 | unsigned int diff; | |
280 | ||
281 | bool old_vote = (qca->tx_vote | qca->rx_vote); | |
282 | bool new_vote; | |
283 | ||
284 | switch (vote) { | |
285 | case HCI_IBS_VOTE_STATS_UPDATE: | |
286 | diff = jiffies_to_msecs(jiffies - qca->vote_last_jif); | |
287 | ||
288 | if (old_vote) | |
289 | qca->vote_off_ms += diff; | |
290 | else | |
291 | qca->vote_on_ms += diff; | |
292 | return; | |
293 | ||
294 | case HCI_IBS_TX_VOTE_CLOCK_ON: | |
295 | qca->tx_vote = true; | |
296 | qca->tx_votes_on++; | |
0ff252c1 BYTK |
297 | break; |
298 | ||
299 | case HCI_IBS_RX_VOTE_CLOCK_ON: | |
300 | qca->rx_vote = true; | |
301 | qca->rx_votes_on++; | |
0ff252c1 BYTK |
302 | break; |
303 | ||
304 | case HCI_IBS_TX_VOTE_CLOCK_OFF: | |
305 | qca->tx_vote = false; | |
306 | qca->tx_votes_off++; | |
0ff252c1 BYTK |
307 | break; |
308 | ||
309 | case HCI_IBS_RX_VOTE_CLOCK_OFF: | |
310 | qca->rx_vote = false; | |
311 | qca->rx_votes_off++; | |
0ff252c1 BYTK |
312 | break; |
313 | ||
314 | default: | |
315 | BT_ERR("Voting irregularity"); | |
316 | return; | |
317 | } | |
318 | ||
7310dd3f MK |
319 | new_vote = qca->rx_vote | qca->tx_vote; |
320 | ||
0ff252c1 BYTK |
321 | if (new_vote != old_vote) { |
322 | if (new_vote) | |
323 | __serial_clock_on(hu->tty); | |
324 | else | |
325 | __serial_clock_off(hu->tty); | |
326 | ||
ce26d813 PK |
327 | BT_DBG("Vote serial clock %s(%s)", new_vote ? "true" : "false", |
328 | vote ? "true" : "false"); | |
0ff252c1 BYTK |
329 | |
330 | diff = jiffies_to_msecs(jiffies - qca->vote_last_jif); | |
331 | ||
332 | if (new_vote) { | |
333 | qca->votes_on++; | |
334 | qca->vote_off_ms += diff; | |
335 | } else { | |
336 | qca->votes_off++; | |
337 | qca->vote_on_ms += diff; | |
338 | } | |
339 | qca->vote_last_jif = jiffies; | |
340 | } | |
341 | } | |
342 | ||
343 | /* Builds and sends an HCI_IBS command packet. | |
344 | * These are very simple packets with only 1 cmd byte. | |
345 | */ | |
346 | static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu) | |
347 | { | |
348 | int err = 0; | |
349 | struct sk_buff *skb = NULL; | |
350 | struct qca_data *qca = hu->priv; | |
351 | ||
352 | BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd); | |
353 | ||
354 | skb = bt_skb_alloc(1, GFP_ATOMIC); | |
355 | if (!skb) { | |
356 | BT_ERR("Failed to allocate memory for HCI_IBS packet"); | |
357 | return -ENOMEM; | |
358 | } | |
359 | ||
360 | /* Assign HCI_IBS type */ | |
634fef61 | 361 | skb_put_u8(skb, cmd); |
0ff252c1 BYTK |
362 | |
363 | skb_queue_tail(&qca->txq, skb); | |
364 | ||
365 | return err; | |
366 | } | |
367 | ||
368 | static void qca_wq_awake_device(struct work_struct *work) | |
369 | { | |
370 | struct qca_data *qca = container_of(work, struct qca_data, | |
371 | ws_awake_device); | |
372 | struct hci_uart *hu = qca->hu; | |
373 | unsigned long retrans_delay; | |
31fb1bbd | 374 | unsigned long flags; |
0ff252c1 BYTK |
375 | |
376 | BT_DBG("hu %p wq awake device", hu); | |
377 | ||
378 | /* Vote for serial clock */ | |
379 | serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu); | |
380 | ||
31fb1bbd | 381 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
382 | |
383 | /* Send wake indication to device */ | |
384 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) | |
385 | BT_ERR("Failed to send WAKE to device"); | |
386 | ||
387 | qca->ibs_sent_wakes++; | |
388 | ||
389 | /* Start retransmit timer */ | |
390 | retrans_delay = msecs_to_jiffies(qca->wake_retrans); | |
391 | mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay); | |
392 | ||
31fb1bbd | 393 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
394 | |
395 | /* Actually send the packets */ | |
396 | hci_uart_tx_wakeup(hu); | |
397 | } | |
398 | ||
399 | static void qca_wq_awake_rx(struct work_struct *work) | |
400 | { | |
401 | struct qca_data *qca = container_of(work, struct qca_data, | |
402 | ws_awake_rx); | |
403 | struct hci_uart *hu = qca->hu; | |
31fb1bbd | 404 | unsigned long flags; |
0ff252c1 BYTK |
405 | |
406 | BT_DBG("hu %p wq awake rx", hu); | |
407 | ||
408 | serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu); | |
409 | ||
31fb1bbd | 410 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
411 | qca->rx_ibs_state = HCI_IBS_RX_AWAKE; |
412 | ||
413 | /* Always acknowledge device wake up, | |
414 | * sending IBS message doesn't count as TX ON. | |
415 | */ | |
416 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) | |
417 | BT_ERR("Failed to acknowledge device wake up"); | |
418 | ||
419 | qca->ibs_sent_wacks++; | |
420 | ||
31fb1bbd | 421 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
422 | |
423 | /* Actually send the packets */ | |
424 | hci_uart_tx_wakeup(hu); | |
425 | } | |
426 | ||
427 | static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work) | |
428 | { | |
429 | struct qca_data *qca = container_of(work, struct qca_data, | |
430 | ws_rx_vote_off); | |
431 | struct hci_uart *hu = qca->hu; | |
432 | ||
433 | BT_DBG("hu %p rx clock vote off", hu); | |
434 | ||
435 | serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu); | |
436 | } | |
437 | ||
438 | static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work) | |
439 | { | |
440 | struct qca_data *qca = container_of(work, struct qca_data, | |
441 | ws_tx_vote_off); | |
442 | struct hci_uart *hu = qca->hu; | |
443 | ||
444 | BT_DBG("hu %p tx clock vote off", hu); | |
445 | ||
446 | /* Run HCI tx handling unlocked */ | |
447 | hci_uart_tx_wakeup(hu); | |
448 | ||
449 | /* Now that message queued to tty driver, vote for tty clocks off. | |
450 | * It is up to the tty driver to pend the clocks off until tx done. | |
451 | */ | |
452 | serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu); | |
453 | } | |
454 | ||
04356052 | 455 | static void hci_ibs_tx_idle_timeout(struct timer_list *t) |
0ff252c1 | 456 | { |
04356052 KC |
457 | struct qca_data *qca = from_timer(qca, t, tx_idle_timer); |
458 | struct hci_uart *hu = qca->hu; | |
0ff252c1 BYTK |
459 | unsigned long flags; |
460 | ||
461 | BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state); | |
462 | ||
463 | spin_lock_irqsave_nested(&qca->hci_ibs_lock, | |
464 | flags, SINGLE_DEPTH_NESTING); | |
465 | ||
466 | switch (qca->tx_ibs_state) { | |
467 | case HCI_IBS_TX_AWAKE: | |
468 | /* TX_IDLE, go to SLEEP */ | |
469 | if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) { | |
470 | BT_ERR("Failed to send SLEEP to device"); | |
471 | break; | |
472 | } | |
473 | qca->tx_ibs_state = HCI_IBS_TX_ASLEEP; | |
474 | qca->ibs_sent_slps++; | |
475 | queue_work(qca->workqueue, &qca->ws_tx_vote_off); | |
476 | break; | |
477 | ||
478 | case HCI_IBS_TX_ASLEEP: | |
479 | case HCI_IBS_TX_WAKING: | |
0ff252c1 | 480 | default: |
e059a465 | 481 | BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state); |
0ff252c1 BYTK |
482 | break; |
483 | } | |
484 | ||
485 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
486 | } | |
487 | ||
04356052 | 488 | static void hci_ibs_wake_retrans_timeout(struct timer_list *t) |
0ff252c1 | 489 | { |
04356052 KC |
490 | struct qca_data *qca = from_timer(qca, t, wake_retrans_timer); |
491 | struct hci_uart *hu = qca->hu; | |
0ff252c1 | 492 | unsigned long flags, retrans_delay; |
a9137188 | 493 | bool retransmit = false; |
0ff252c1 BYTK |
494 | |
495 | BT_DBG("hu %p wake retransmit timeout in %d state", | |
496 | hu, qca->tx_ibs_state); | |
497 | ||
498 | spin_lock_irqsave_nested(&qca->hci_ibs_lock, | |
499 | flags, SINGLE_DEPTH_NESTING); | |
500 | ||
41d5b25f CC |
501 | /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */ |
502 | if (test_bit(QCA_SUSPENDING, &qca->flags)) { | |
503 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
504 | return; | |
505 | } | |
506 | ||
0ff252c1 BYTK |
507 | switch (qca->tx_ibs_state) { |
508 | case HCI_IBS_TX_WAKING: | |
509 | /* No WAKE_ACK, retransmit WAKE */ | |
a9137188 | 510 | retransmit = true; |
0ff252c1 BYTK |
511 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) { |
512 | BT_ERR("Failed to acknowledge device wake up"); | |
513 | break; | |
514 | } | |
515 | qca->ibs_sent_wakes++; | |
516 | retrans_delay = msecs_to_jiffies(qca->wake_retrans); | |
517 | mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay); | |
518 | break; | |
519 | ||
520 | case HCI_IBS_TX_ASLEEP: | |
521 | case HCI_IBS_TX_AWAKE: | |
0ff252c1 | 522 | default: |
e059a465 | 523 | BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state); |
0ff252c1 BYTK |
524 | break; |
525 | } | |
526 | ||
527 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
528 | ||
529 | if (retransmit) | |
530 | hci_uart_tx_wakeup(hu); | |
531 | } | |
532 | ||
7c2c3e63 VLNG |
533 | |
534 | static void qca_controller_memdump_timeout(struct work_struct *work) | |
d841502c | 535 | { |
7c2c3e63 VLNG |
536 | struct qca_data *qca = container_of(work, struct qca_data, |
537 | ctrl_memdump_timeout.work); | |
d841502c | 538 | struct hci_uart *hu = qca->hu; |
7c2c3e63 VLNG |
539 | |
540 | mutex_lock(&qca->hci_memdump_lock); | |
541 | if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) { | |
542 | qca->memdump_state = QCA_MEMDUMP_TIMEOUT; | |
543 | if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) { | |
544 | /* Inject hw error event to reset the device | |
545 | * and driver. | |
546 | */ | |
547 | hci_reset_dev(hu->hdev); | |
548 | } | |
549 | } | |
550 | ||
551 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c BG |
552 | } |
553 | ||
7c2c3e63 | 554 | |
0ff252c1 BYTK |
555 | /* Initialize protocol */ |
556 | static int qca_open(struct hci_uart *hu) | |
557 | { | |
05ba533c | 558 | struct qca_serdev *qcadev; |
0ff252c1 BYTK |
559 | struct qca_data *qca; |
560 | ||
561 | BT_DBG("hu %p qca_open", hu); | |
562 | ||
b36a1552 VD |
563 | if (!hci_uart_has_flow_control(hu)) |
564 | return -EOPNOTSUPP; | |
565 | ||
25a13e38 | 566 | qca = kzalloc(sizeof(struct qca_data), GFP_KERNEL); |
0ff252c1 BYTK |
567 | if (!qca) |
568 | return -ENOMEM; | |
569 | ||
570 | skb_queue_head_init(&qca->txq); | |
571 | skb_queue_head_init(&qca->tx_wait_q); | |
d841502c | 572 | skb_queue_head_init(&qca->rx_memdump_q); |
0ff252c1 | 573 | spin_lock_init(&qca->hci_ibs_lock); |
7c2c3e63 | 574 | mutex_init(&qca->hci_memdump_lock); |
fac9a602 | 575 | qca->workqueue = alloc_ordered_workqueue("qca_wq", 0); |
0ff252c1 BYTK |
576 | if (!qca->workqueue) { |
577 | BT_ERR("QCA Workqueue not initialized properly"); | |
578 | kfree(qca); | |
579 | return -ENOMEM; | |
580 | } | |
581 | ||
582 | INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx); | |
583 | INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device); | |
584 | INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off); | |
585 | INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off); | |
d841502c | 586 | INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump); |
7c2c3e63 VLNG |
587 | INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout, |
588 | qca_controller_memdump_timeout); | |
41d5b25f CC |
589 | init_waitqueue_head(&qca->suspend_wait_q); |
590 | ||
0ff252c1 | 591 | qca->hu = hu; |
2faa3f15 | 592 | init_completion(&qca->drop_ev_comp); |
0ff252c1 BYTK |
593 | |
594 | /* Assume we start with both sides asleep -- extra wakes OK */ | |
595 | qca->tx_ibs_state = HCI_IBS_TX_ASLEEP; | |
596 | qca->rx_ibs_state = HCI_IBS_RX_ASLEEP; | |
597 | ||
0ff252c1 | 598 | qca->vote_last_jif = jiffies; |
0ff252c1 BYTK |
599 | |
600 | hu->priv = qca; | |
601 | ||
05ba533c | 602 | if (hu->serdev) { |
05ba533c | 603 | qcadev = serdev_device_get_drvdata(hu->serdev); |
37aee136 CH |
604 | |
605 | if (qca_is_wcn399x(qcadev->btsoc_type)) | |
fa9ad876 | 606 | hu->init_speed = qcadev->init_speed; |
37aee136 CH |
607 | |
608 | if (qcadev->oper_speed) | |
fa9ad876 | 609 | hu->oper_speed = qcadev->oper_speed; |
05ba533c TE |
610 | } |
611 | ||
fa9ad876 BG |
612 | timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0); |
613 | qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS; | |
614 | ||
615 | timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0); | |
41d5b25f | 616 | qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS; |
fa9ad876 | 617 | |
0ff252c1 BYTK |
618 | BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u", |
619 | qca->tx_idle_delay, qca->wake_retrans); | |
620 | ||
621 | return 0; | |
622 | } | |
623 | ||
624 | static void qca_debugfs_init(struct hci_dev *hdev) | |
625 | { | |
626 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
627 | struct qca_data *qca = hu->priv; | |
628 | struct dentry *ibs_dir; | |
629 | umode_t mode; | |
630 | ||
631 | if (!hdev->debugfs) | |
632 | return; | |
633 | ||
634 | ibs_dir = debugfs_create_dir("ibs", hdev->debugfs); | |
635 | ||
636 | /* read only */ | |
99719449 | 637 | mode = 0444; |
0ff252c1 BYTK |
638 | debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state); |
639 | debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state); | |
640 | debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir, | |
641 | &qca->ibs_sent_slps); | |
642 | debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir, | |
643 | &qca->ibs_sent_wakes); | |
644 | debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir, | |
645 | &qca->ibs_sent_wacks); | |
646 | debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir, | |
647 | &qca->ibs_recv_slps); | |
648 | debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir, | |
649 | &qca->ibs_recv_wakes); | |
650 | debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir, | |
651 | &qca->ibs_recv_wacks); | |
10be6c0f | 652 | debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote); |
0ff252c1 BYTK |
653 | debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on); |
654 | debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off); | |
10be6c0f | 655 | debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote); |
0ff252c1 BYTK |
656 | debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on); |
657 | debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off); | |
658 | debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on); | |
659 | debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off); | |
660 | debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms); | |
661 | debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms); | |
662 | ||
663 | /* read/write */ | |
99719449 | 664 | mode = 0644; |
0ff252c1 BYTK |
665 | debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans); |
666 | debugfs_create_u32("tx_idle_delay", mode, ibs_dir, | |
667 | &qca->tx_idle_delay); | |
668 | } | |
669 | ||
670 | /* Flush protocol data */ | |
671 | static int qca_flush(struct hci_uart *hu) | |
672 | { | |
673 | struct qca_data *qca = hu->priv; | |
674 | ||
675 | BT_DBG("hu %p qca flush", hu); | |
676 | ||
677 | skb_queue_purge(&qca->tx_wait_q); | |
678 | skb_queue_purge(&qca->txq); | |
679 | ||
680 | return 0; | |
681 | } | |
682 | ||
683 | /* Close protocol */ | |
684 | static int qca_close(struct hci_uart *hu) | |
685 | { | |
686 | struct qca_data *qca = hu->priv; | |
687 | ||
688 | BT_DBG("hu %p qca close", hu); | |
689 | ||
690 | serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu); | |
691 | ||
692 | skb_queue_purge(&qca->tx_wait_q); | |
693 | skb_queue_purge(&qca->txq); | |
d841502c | 694 | skb_queue_purge(&qca->rx_memdump_q); |
0ff252c1 BYTK |
695 | del_timer(&qca->tx_idle_timer); |
696 | del_timer(&qca->wake_retrans_timer); | |
697 | destroy_workqueue(qca->workqueue); | |
698 | qca->hu = NULL; | |
699 | ||
700 | kfree_skb(qca->rx_skb); | |
701 | ||
702 | hu->priv = NULL; | |
703 | ||
704 | kfree(qca); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | /* Called upon a wake-up-indication from the device. | |
710 | */ | |
711 | static void device_want_to_wakeup(struct hci_uart *hu) | |
712 | { | |
713 | unsigned long flags; | |
714 | struct qca_data *qca = hu->priv; | |
715 | ||
716 | BT_DBG("hu %p want to wake up", hu); | |
717 | ||
718 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
719 | ||
720 | qca->ibs_recv_wakes++; | |
721 | ||
41d5b25f CC |
722 | /* Don't wake the rx up when suspending. */ |
723 | if (test_bit(QCA_SUSPENDING, &qca->flags)) { | |
724 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
725 | return; | |
726 | } | |
727 | ||
0ff252c1 BYTK |
728 | switch (qca->rx_ibs_state) { |
729 | case HCI_IBS_RX_ASLEEP: | |
730 | /* Make sure clock is on - we may have turned clock off since | |
731 | * receiving the wake up indicator awake rx clock. | |
732 | */ | |
733 | queue_work(qca->workqueue, &qca->ws_awake_rx); | |
734 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
735 | return; | |
736 | ||
737 | case HCI_IBS_RX_AWAKE: | |
738 | /* Always acknowledge device wake up, | |
739 | * sending IBS message doesn't count as TX ON. | |
740 | */ | |
741 | if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) { | |
742 | BT_ERR("Failed to acknowledge device wake up"); | |
743 | break; | |
744 | } | |
745 | qca->ibs_sent_wacks++; | |
746 | break; | |
747 | ||
748 | default: | |
749 | /* Any other state is illegal */ | |
750 | BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d", | |
751 | qca->rx_ibs_state); | |
752 | break; | |
753 | } | |
754 | ||
755 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
756 | ||
757 | /* Actually send the packets */ | |
758 | hci_uart_tx_wakeup(hu); | |
759 | } | |
760 | ||
761 | /* Called upon a sleep-indication from the device. | |
762 | */ | |
763 | static void device_want_to_sleep(struct hci_uart *hu) | |
764 | { | |
765 | unsigned long flags; | |
766 | struct qca_data *qca = hu->priv; | |
767 | ||
6600c080 | 768 | BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state); |
0ff252c1 BYTK |
769 | |
770 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
771 | ||
772 | qca->ibs_recv_slps++; | |
773 | ||
774 | switch (qca->rx_ibs_state) { | |
775 | case HCI_IBS_RX_AWAKE: | |
776 | /* Update state */ | |
777 | qca->rx_ibs_state = HCI_IBS_RX_ASLEEP; | |
778 | /* Vote off rx clock under workqueue */ | |
779 | queue_work(qca->workqueue, &qca->ws_rx_vote_off); | |
780 | break; | |
781 | ||
782 | case HCI_IBS_RX_ASLEEP: | |
6600c080 | 783 | break; |
0ff252c1 BYTK |
784 | |
785 | default: | |
786 | /* Any other state is illegal */ | |
787 | BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d", | |
788 | qca->rx_ibs_state); | |
789 | break; | |
790 | } | |
791 | ||
41d5b25f CC |
792 | wake_up_interruptible(&qca->suspend_wait_q); |
793 | ||
0ff252c1 BYTK |
794 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
795 | } | |
796 | ||
797 | /* Called upon wake-up-acknowledgement from the device | |
798 | */ | |
799 | static void device_woke_up(struct hci_uart *hu) | |
800 | { | |
801 | unsigned long flags, idle_delay; | |
802 | struct qca_data *qca = hu->priv; | |
803 | struct sk_buff *skb = NULL; | |
804 | ||
805 | BT_DBG("hu %p woke up", hu); | |
806 | ||
807 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
808 | ||
809 | qca->ibs_recv_wacks++; | |
810 | ||
41d5b25f CC |
811 | /* Don't react to the wake-up-acknowledgment when suspending. */ |
812 | if (test_bit(QCA_SUSPENDING, &qca->flags)) { | |
813 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
814 | return; | |
815 | } | |
816 | ||
0ff252c1 BYTK |
817 | switch (qca->tx_ibs_state) { |
818 | case HCI_IBS_TX_AWAKE: | |
819 | /* Expect one if we send 2 WAKEs */ | |
820 | BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d", | |
821 | qca->tx_ibs_state); | |
822 | break; | |
823 | ||
824 | case HCI_IBS_TX_WAKING: | |
825 | /* Send pending packets */ | |
826 | while ((skb = skb_dequeue(&qca->tx_wait_q))) | |
827 | skb_queue_tail(&qca->txq, skb); | |
828 | ||
829 | /* Switch timers and change state to HCI_IBS_TX_AWAKE */ | |
830 | del_timer(&qca->wake_retrans_timer); | |
831 | idle_delay = msecs_to_jiffies(qca->tx_idle_delay); | |
832 | mod_timer(&qca->tx_idle_timer, jiffies + idle_delay); | |
833 | qca->tx_ibs_state = HCI_IBS_TX_AWAKE; | |
834 | break; | |
835 | ||
836 | case HCI_IBS_TX_ASLEEP: | |
0ff252c1 BYTK |
837 | default: |
838 | BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d", | |
839 | qca->tx_ibs_state); | |
840 | break; | |
841 | } | |
842 | ||
843 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
844 | ||
845 | /* Actually send the packets */ | |
846 | hci_uart_tx_wakeup(hu); | |
847 | } | |
848 | ||
849 | /* Enqueue frame for transmittion (padding, crc, etc) may be called from | |
850 | * two simultaneous tasklets. | |
851 | */ | |
852 | static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb) | |
853 | { | |
854 | unsigned long flags = 0, idle_delay; | |
855 | struct qca_data *qca = hu->priv; | |
856 | ||
857 | BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb, | |
858 | qca->tx_ibs_state); | |
859 | ||
3344537f VLNG |
860 | if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) { |
861 | /* As SSR is in progress, ignore the packets */ | |
862 | bt_dev_dbg(hu->hdev, "SSR is in progress"); | |
863 | kfree_skb(skb); | |
864 | return 0; | |
865 | } | |
866 | ||
0ff252c1 | 867 | /* Prepend skb with frame type */ |
618e8bc2 | 868 | memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); |
0ff252c1 | 869 | |
035a960e BG |
870 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); |
871 | ||
0ff252c1 BYTK |
872 | /* Don't go to sleep in middle of patch download or |
873 | * Out-Of-Band(GPIOs control) sleep is selected. | |
41d5b25f | 874 | * Don't wake the device up when suspending. |
0ff252c1 | 875 | */ |
2be43aba | 876 | if (test_bit(QCA_IBS_DISABLED, &qca->flags) || |
41d5b25f | 877 | test_bit(QCA_SUSPENDING, &qca->flags)) { |
0ff252c1 | 878 | skb_queue_tail(&qca->txq, skb); |
035a960e | 879 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); |
0ff252c1 BYTK |
880 | return 0; |
881 | } | |
882 | ||
0ff252c1 BYTK |
883 | /* Act according to current state */ |
884 | switch (qca->tx_ibs_state) { | |
885 | case HCI_IBS_TX_AWAKE: | |
886 | BT_DBG("Device awake, sending normally"); | |
887 | skb_queue_tail(&qca->txq, skb); | |
888 | idle_delay = msecs_to_jiffies(qca->tx_idle_delay); | |
889 | mod_timer(&qca->tx_idle_timer, jiffies + idle_delay); | |
890 | break; | |
891 | ||
892 | case HCI_IBS_TX_ASLEEP: | |
893 | BT_DBG("Device asleep, waking up and queueing packet"); | |
894 | /* Save packet for later */ | |
895 | skb_queue_tail(&qca->tx_wait_q, skb); | |
896 | ||
897 | qca->tx_ibs_state = HCI_IBS_TX_WAKING; | |
898 | /* Schedule a work queue to wake up device */ | |
899 | queue_work(qca->workqueue, &qca->ws_awake_device); | |
900 | break; | |
901 | ||
902 | case HCI_IBS_TX_WAKING: | |
903 | BT_DBG("Device waking up, queueing packet"); | |
904 | /* Transient state; just keep packet for later */ | |
905 | skb_queue_tail(&qca->tx_wait_q, skb); | |
906 | break; | |
907 | ||
908 | default: | |
909 | BT_ERR("Illegal tx state: %d (losing packet)", | |
910 | qca->tx_ibs_state); | |
911 | kfree_skb(skb); | |
912 | break; | |
913 | } | |
914 | ||
915 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
916 | ||
917 | return 0; | |
918 | } | |
919 | ||
920 | static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb) | |
921 | { | |
922 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
923 | ||
924 | BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND); | |
925 | ||
926 | device_want_to_sleep(hu); | |
927 | ||
928 | kfree_skb(skb); | |
929 | return 0; | |
930 | } | |
931 | ||
932 | static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb) | |
933 | { | |
934 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
935 | ||
936 | BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND); | |
937 | ||
938 | device_want_to_wakeup(hu); | |
939 | ||
940 | kfree_skb(skb); | |
941 | return 0; | |
942 | } | |
943 | ||
944 | static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb) | |
945 | { | |
946 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
947 | ||
948 | BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK); | |
949 | ||
950 | device_woke_up(hu); | |
951 | ||
952 | kfree_skb(skb); | |
953 | return 0; | |
954 | } | |
955 | ||
c614ca3f BG |
956 | static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb) |
957 | { | |
958 | /* We receive debug logs from chip as an ACL packets. | |
959 | * Instead of sending the data to ACL to decode the | |
960 | * received data, we are pushing them to the above layers | |
961 | * as a diagnostic packet. | |
962 | */ | |
963 | if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE) | |
964 | return hci_recv_diag(hdev, skb); | |
965 | ||
966 | return hci_recv_frame(hdev, skb); | |
967 | } | |
968 | ||
d841502c BG |
969 | static void qca_controller_memdump(struct work_struct *work) |
970 | { | |
971 | struct qca_data *qca = container_of(work, struct qca_data, | |
972 | ctrl_memdump_evt); | |
973 | struct hci_uart *hu = qca->hu; | |
974 | struct sk_buff *skb; | |
975 | struct qca_memdump_event_hdr *cmd_hdr; | |
976 | struct qca_memdump_data *qca_memdump = qca->qca_memdump; | |
977 | struct qca_dump_size *dump; | |
978 | char *memdump_buf; | |
979 | char nullBuff[QCA_DUMP_PACKET_SIZE] = { 0 }; | |
56b084ed | 980 | u16 seq_no; |
d841502c | 981 | u32 dump_size; |
e5aeebdd ZH |
982 | u32 rx_size; |
983 | enum qca_btsoc_type soc_type = qca_soc_type(hu); | |
d841502c BG |
984 | |
985 | while ((skb = skb_dequeue(&qca->rx_memdump_q))) { | |
986 | ||
7c2c3e63 | 987 | mutex_lock(&qca->hci_memdump_lock); |
f98aa80f VLNG |
988 | /* Skip processing the received packets if timeout detected |
989 | * or memdump collection completed. | |
990 | */ | |
991 | if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT || | |
992 | qca->memdump_state == QCA_MEMDUMP_COLLECTED) { | |
7c2c3e63 VLNG |
993 | mutex_unlock(&qca->hci_memdump_lock); |
994 | return; | |
995 | } | |
996 | ||
d841502c BG |
997 | if (!qca_memdump) { |
998 | qca_memdump = kzalloc(sizeof(struct qca_memdump_data), | |
999 | GFP_ATOMIC); | |
7c2c3e63 VLNG |
1000 | if (!qca_memdump) { |
1001 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c | 1002 | return; |
7c2c3e63 | 1003 | } |
d841502c BG |
1004 | |
1005 | qca->qca_memdump = qca_memdump; | |
1006 | } | |
1007 | ||
1008 | qca->memdump_state = QCA_MEMDUMP_COLLECTING; | |
1009 | cmd_hdr = (void *) skb->data; | |
d841502c BG |
1010 | seq_no = __le16_to_cpu(cmd_hdr->seq_no); |
1011 | skb_pull(skb, sizeof(struct qca_memdump_event_hdr)); | |
1012 | ||
1013 | if (!seq_no) { | |
1014 | ||
1015 | /* This is the first frame of memdump packet from | |
1016 | * the controller, Disable IBS to recevie dump | |
1017 | * with out any interruption, ideally time required for | |
1018 | * the controller to send the dump is 8 seconds. let us | |
1019 | * start timer to handle this asynchronous activity. | |
1020 | */ | |
2be43aba | 1021 | set_bit(QCA_IBS_DISABLED, &qca->flags); |
d841502c BG |
1022 | set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); |
1023 | dump = (void *) skb->data; | |
1024 | dump_size = __le32_to_cpu(dump->dump_size); | |
1025 | if (!(dump_size)) { | |
1026 | bt_dev_err(hu->hdev, "Rx invalid memdump size"); | |
1027 | kfree_skb(skb); | |
7c2c3e63 | 1028 | mutex_unlock(&qca->hci_memdump_lock); |
d841502c BG |
1029 | return; |
1030 | } | |
1031 | ||
1032 | bt_dev_info(hu->hdev, "QCA collecting dump of size:%u", | |
1033 | dump_size); | |
7c2c3e63 VLNG |
1034 | queue_delayed_work(qca->workqueue, |
1035 | &qca->ctrl_memdump_timeout, | |
e5aeebdd ZH |
1036 | msecs_to_jiffies(MEMDUMP_TIMEOUT_MS) |
1037 | ); | |
d841502c BG |
1038 | |
1039 | skb_pull(skb, sizeof(dump_size)); | |
1040 | memdump_buf = vmalloc(dump_size); | |
e5aeebdd | 1041 | qca_memdump->ram_dump_size = dump_size; |
d841502c BG |
1042 | qca_memdump->memdump_buf_head = memdump_buf; |
1043 | qca_memdump->memdump_buf_tail = memdump_buf; | |
1044 | } | |
1045 | ||
1046 | memdump_buf = qca_memdump->memdump_buf_tail; | |
1047 | ||
1048 | /* If sequence no 0 is missed then there is no point in | |
1049 | * accepting the other sequences. | |
1050 | */ | |
1051 | if (!memdump_buf) { | |
1052 | bt_dev_err(hu->hdev, "QCA: Discarding other packets"); | |
1053 | kfree(qca_memdump); | |
1054 | kfree_skb(skb); | |
1055 | qca->qca_memdump = NULL; | |
7c2c3e63 | 1056 | mutex_unlock(&qca->hci_memdump_lock); |
d841502c BG |
1057 | return; |
1058 | } | |
1059 | ||
1060 | /* There could be chance of missing some packets from | |
1061 | * the controller. In such cases let us store the dummy | |
1062 | * packets in the buffer. | |
1063 | */ | |
e5aeebdd ZH |
1064 | /* For QCA6390, controller does not lost packets but |
1065 | * sequence number field of packat sometimes has error | |
1066 | * bits, so skip this checking for missing packet. | |
1067 | */ | |
d841502c | 1068 | while ((seq_no > qca_memdump->current_seq_no + 1) && |
e5aeebdd ZH |
1069 | (soc_type != QCA_QCA6390) && |
1070 | seq_no != QCA_LAST_SEQUENCE_NUM) { | |
d841502c BG |
1071 | bt_dev_err(hu->hdev, "QCA controller missed packet:%d", |
1072 | qca_memdump->current_seq_no); | |
e5aeebdd ZH |
1073 | rx_size = qca_memdump->received_dump; |
1074 | rx_size += QCA_DUMP_PACKET_SIZE; | |
1075 | if (rx_size > qca_memdump->ram_dump_size) { | |
1076 | bt_dev_err(hu->hdev, | |
1077 | "QCA memdump received %d, no space for missed packet", | |
1078 | qca_memdump->received_dump); | |
1079 | break; | |
1080 | } | |
d841502c BG |
1081 | memcpy(memdump_buf, nullBuff, QCA_DUMP_PACKET_SIZE); |
1082 | memdump_buf = memdump_buf + QCA_DUMP_PACKET_SIZE; | |
1083 | qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE; | |
1084 | qca_memdump->current_seq_no++; | |
1085 | } | |
1086 | ||
e5aeebdd ZH |
1087 | rx_size = qca_memdump->received_dump + skb->len; |
1088 | if (rx_size <= qca_memdump->ram_dump_size) { | |
1089 | if ((seq_no != QCA_LAST_SEQUENCE_NUM) && | |
1090 | (seq_no != qca_memdump->current_seq_no)) | |
1091 | bt_dev_err(hu->hdev, | |
1092 | "QCA memdump unexpected packet %d", | |
1093 | seq_no); | |
1094 | bt_dev_dbg(hu->hdev, | |
1095 | "QCA memdump packet %d with length %d", | |
1096 | seq_no, skb->len); | |
1097 | memcpy(memdump_buf, (unsigned char *)skb->data, | |
1098 | skb->len); | |
1099 | memdump_buf = memdump_buf + skb->len; | |
1100 | qca_memdump->memdump_buf_tail = memdump_buf; | |
1101 | qca_memdump->current_seq_no = seq_no + 1; | |
1102 | qca_memdump->received_dump += skb->len; | |
1103 | } else { | |
1104 | bt_dev_err(hu->hdev, | |
1105 | "QCA memdump received %d, no space for packet %d", | |
1106 | qca_memdump->received_dump, seq_no); | |
1107 | } | |
d841502c BG |
1108 | qca->qca_memdump = qca_memdump; |
1109 | kfree_skb(skb); | |
1110 | if (seq_no == QCA_LAST_SEQUENCE_NUM) { | |
e5aeebdd ZH |
1111 | bt_dev_info(hu->hdev, |
1112 | "QCA memdump Done, received %d, total %d", | |
1113 | qca_memdump->received_dump, | |
1114 | qca_memdump->ram_dump_size); | |
d841502c BG |
1115 | memdump_buf = qca_memdump->memdump_buf_head; |
1116 | dev_coredumpv(&hu->serdev->dev, memdump_buf, | |
1117 | qca_memdump->received_dump, GFP_KERNEL); | |
7c2c3e63 | 1118 | cancel_delayed_work(&qca->ctrl_memdump_timeout); |
d841502c BG |
1119 | kfree(qca->qca_memdump); |
1120 | qca->qca_memdump = NULL; | |
1121 | qca->memdump_state = QCA_MEMDUMP_COLLECTED; | |
7c2c3e63 | 1122 | clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); |
d841502c | 1123 | } |
7c2c3e63 VLNG |
1124 | |
1125 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c BG |
1126 | } |
1127 | ||
1128 | } | |
1129 | ||
7c2c3e63 VLNG |
1130 | static int qca_controller_memdump_event(struct hci_dev *hdev, |
1131 | struct sk_buff *skb) | |
d841502c BG |
1132 | { |
1133 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1134 | struct qca_data *qca = hu->priv; | |
1135 | ||
3344537f | 1136 | set_bit(QCA_SSR_TRIGGERED, &qca->flags); |
d841502c BG |
1137 | skb_queue_tail(&qca->rx_memdump_q, skb); |
1138 | queue_work(qca->workqueue, &qca->ctrl_memdump_evt); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
2faa3f15 MK |
1143 | static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb) |
1144 | { | |
1145 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1146 | struct qca_data *qca = hu->priv; | |
1147 | ||
1148 | if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) { | |
1149 | struct hci_event_hdr *hdr = (void *)skb->data; | |
1150 | ||
1151 | /* For the WCN3990 the vendor command for a baudrate change | |
1152 | * isn't sent as synchronous HCI command, because the | |
1153 | * controller sends the corresponding vendor event with the | |
1154 | * new baudrate. The event is received and properly decoded | |
1155 | * after changing the baudrate of the host port. It needs to | |
1156 | * be dropped, otherwise it can be misinterpreted as | |
1157 | * response to a later firmware download command (also a | |
1158 | * vendor command). | |
1159 | */ | |
1160 | ||
1161 | if (hdr->evt == HCI_EV_VENDOR) | |
1162 | complete(&qca->drop_ev_comp); | |
1163 | ||
4974c839 | 1164 | kfree_skb(skb); |
2faa3f15 MK |
1165 | |
1166 | return 0; | |
1167 | } | |
d841502c BG |
1168 | /* We receive chip memory dump as an event packet, With a dedicated |
1169 | * handler followed by a hardware error event. When this event is | |
1170 | * received we store dump into a file before closing hci. This | |
1171 | * dump will help in triaging the issues. | |
1172 | */ | |
1173 | if ((skb->data[0] == HCI_VENDOR_PKT) && | |
1174 | (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE)) | |
1175 | return qca_controller_memdump_event(hdev, skb); | |
2faa3f15 MK |
1176 | |
1177 | return hci_recv_frame(hdev, skb); | |
1178 | } | |
1179 | ||
0ff252c1 BYTK |
1180 | #define QCA_IBS_SLEEP_IND_EVENT \ |
1181 | .type = HCI_IBS_SLEEP_IND, \ | |
1182 | .hlen = 0, \ | |
1183 | .loff = 0, \ | |
1184 | .lsize = 0, \ | |
1185 | .maxlen = HCI_MAX_IBS_SIZE | |
1186 | ||
1187 | #define QCA_IBS_WAKE_IND_EVENT \ | |
1188 | .type = HCI_IBS_WAKE_IND, \ | |
1189 | .hlen = 0, \ | |
1190 | .loff = 0, \ | |
1191 | .lsize = 0, \ | |
1192 | .maxlen = HCI_MAX_IBS_SIZE | |
1193 | ||
1194 | #define QCA_IBS_WAKE_ACK_EVENT \ | |
1195 | .type = HCI_IBS_WAKE_ACK, \ | |
1196 | .hlen = 0, \ | |
1197 | .loff = 0, \ | |
1198 | .lsize = 0, \ | |
1199 | .maxlen = HCI_MAX_IBS_SIZE | |
1200 | ||
1201 | static const struct h4_recv_pkt qca_recv_pkts[] = { | |
c614ca3f | 1202 | { H4_RECV_ACL, .recv = qca_recv_acl_data }, |
0ff252c1 | 1203 | { H4_RECV_SCO, .recv = hci_recv_frame }, |
2faa3f15 | 1204 | { H4_RECV_EVENT, .recv = qca_recv_event }, |
0ff252c1 BYTK |
1205 | { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind }, |
1206 | { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack }, | |
1207 | { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind }, | |
1208 | }; | |
1209 | ||
1210 | static int qca_recv(struct hci_uart *hu, const void *data, int count) | |
1211 | { | |
1212 | struct qca_data *qca = hu->priv; | |
1213 | ||
1214 | if (!test_bit(HCI_UART_REGISTERED, &hu->flags)) | |
1215 | return -EUNATCH; | |
1216 | ||
1217 | qca->rx_skb = h4_recv_buf(hu->hdev, qca->rx_skb, data, count, | |
1218 | qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts)); | |
1219 | if (IS_ERR(qca->rx_skb)) { | |
1220 | int err = PTR_ERR(qca->rx_skb); | |
2064ee33 | 1221 | bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err); |
0ff252c1 BYTK |
1222 | qca->rx_skb = NULL; |
1223 | return err; | |
1224 | } | |
1225 | ||
1226 | return count; | |
1227 | } | |
1228 | ||
1229 | static struct sk_buff *qca_dequeue(struct hci_uart *hu) | |
1230 | { | |
1231 | struct qca_data *qca = hu->priv; | |
1232 | ||
1233 | return skb_dequeue(&qca->txq); | |
1234 | } | |
1235 | ||
1236 | static uint8_t qca_get_baudrate_value(int speed) | |
1237 | { | |
ce26d813 | 1238 | switch (speed) { |
0ff252c1 BYTK |
1239 | case 9600: |
1240 | return QCA_BAUDRATE_9600; | |
1241 | case 19200: | |
1242 | return QCA_BAUDRATE_19200; | |
1243 | case 38400: | |
1244 | return QCA_BAUDRATE_38400; | |
1245 | case 57600: | |
1246 | return QCA_BAUDRATE_57600; | |
1247 | case 115200: | |
1248 | return QCA_BAUDRATE_115200; | |
1249 | case 230400: | |
1250 | return QCA_BAUDRATE_230400; | |
1251 | case 460800: | |
1252 | return QCA_BAUDRATE_460800; | |
1253 | case 500000: | |
1254 | return QCA_BAUDRATE_500000; | |
1255 | case 921600: | |
1256 | return QCA_BAUDRATE_921600; | |
1257 | case 1000000: | |
1258 | return QCA_BAUDRATE_1000000; | |
1259 | case 2000000: | |
1260 | return QCA_BAUDRATE_2000000; | |
1261 | case 3000000: | |
1262 | return QCA_BAUDRATE_3000000; | |
be93a497 BG |
1263 | case 3200000: |
1264 | return QCA_BAUDRATE_3200000; | |
0ff252c1 BYTK |
1265 | case 3500000: |
1266 | return QCA_BAUDRATE_3500000; | |
1267 | default: | |
1268 | return QCA_BAUDRATE_115200; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate) | |
1273 | { | |
1274 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1275 | struct qca_data *qca = hu->priv; | |
1276 | struct sk_buff *skb; | |
1277 | u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 }; | |
1278 | ||
be93a497 | 1279 | if (baudrate > QCA_BAUDRATE_3200000) |
0ff252c1 BYTK |
1280 | return -EINVAL; |
1281 | ||
1282 | cmd[4] = baudrate; | |
1283 | ||
25a13e38 | 1284 | skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL); |
0ff252c1 | 1285 | if (!skb) { |
2064ee33 | 1286 | bt_dev_err(hdev, "Failed to allocate baudrate packet"); |
0ff252c1 BYTK |
1287 | return -ENOMEM; |
1288 | } | |
1289 | ||
1290 | /* Assign commands to change baudrate and packet type. */ | |
59ae1d12 | 1291 | skb_put_data(skb, cmd, sizeof(cmd)); |
618e8bc2 | 1292 | hci_skb_pkt_type(skb) = HCI_COMMAND_PKT; |
0ff252c1 BYTK |
1293 | |
1294 | skb_queue_tail(&qca->txq, skb); | |
1295 | hci_uart_tx_wakeup(hu); | |
1296 | ||
94d66714 MK |
1297 | /* Wait for the baudrate change request to be sent */ |
1298 | ||
1299 | while (!skb_queue_empty(&qca->txq)) | |
1300 | usleep_range(100, 200); | |
1301 | ||
ecf2b768 MK |
1302 | if (hu->serdev) |
1303 | serdev_device_wait_until_sent(hu->serdev, | |
94d66714 MK |
1304 | msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS)); |
1305 | ||
1306 | /* Give the controller time to process the request */ | |
523760b7 | 1307 | if (qca_is_wcn399x(qca_soc_type(hu))) |
99719449 | 1308 | usleep_range(1000, 10000); |
94d66714 MK |
1309 | else |
1310 | msleep(300); | |
0ff252c1 BYTK |
1311 | |
1312 | return 0; | |
1313 | } | |
1314 | ||
05ba533c TE |
1315 | static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed) |
1316 | { | |
1317 | if (hu->serdev) | |
1318 | serdev_device_set_baudrate(hu->serdev, speed); | |
1319 | else | |
1320 | hci_uart_set_baudrate(hu, speed); | |
1321 | } | |
1322 | ||
9836b802 | 1323 | static int qca_send_power_pulse(struct hci_uart *hu, bool on) |
fa9ad876 | 1324 | { |
f9558270 | 1325 | int ret; |
94d66714 | 1326 | int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); |
9836b802 | 1327 | u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE; |
fa9ad876 BG |
1328 | |
1329 | /* These power pulses are single byte command which are sent | |
1330 | * at required baudrate to wcn3990. On wcn3990, we have an external | |
1331 | * circuit at Tx pin which decodes the pulse sent at specific baudrate. | |
1332 | * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT | |
1333 | * and also we use the same power inputs to turn on and off for | |
1334 | * Wi-Fi/BT. Powering up the power sources will not enable BT, until | |
1335 | * we send a power on pulse at 115200 bps. This algorithm will help to | |
1336 | * save power. Disabling hardware flow control is mandatory while | |
1337 | * sending power pulses to SoC. | |
1338 | */ | |
f9558270 | 1339 | bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd); |
fa9ad876 | 1340 | |
f9558270 | 1341 | serdev_device_write_flush(hu->serdev); |
fa9ad876 | 1342 | hci_uart_set_flow_control(hu, true); |
f9558270 BG |
1343 | ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd)); |
1344 | if (ret < 0) { | |
1345 | bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd); | |
1346 | return ret; | |
1347 | } | |
fa9ad876 | 1348 | |
f9558270 | 1349 | serdev_device_wait_until_sent(hu->serdev, timeout); |
fa9ad876 BG |
1350 | hci_uart_set_flow_control(hu, false); |
1351 | ||
0ebcddd8 | 1352 | /* Give to controller time to boot/shutdown */ |
ad571d72 MK |
1353 | if (on) |
1354 | msleep(100); | |
0ebcddd8 | 1355 | else |
99719449 | 1356 | usleep_range(1000, 10000); |
ad571d72 | 1357 | |
fa9ad876 BG |
1358 | return 0; |
1359 | } | |
1360 | ||
83d9c5e5 BG |
1361 | static unsigned int qca_get_speed(struct hci_uart *hu, |
1362 | enum qca_speed_type speed_type) | |
1363 | { | |
1364 | unsigned int speed = 0; | |
1365 | ||
1366 | if (speed_type == QCA_INIT_SPEED) { | |
1367 | if (hu->init_speed) | |
1368 | speed = hu->init_speed; | |
1369 | else if (hu->proto->init_speed) | |
1370 | speed = hu->proto->init_speed; | |
1371 | } else { | |
1372 | if (hu->oper_speed) | |
1373 | speed = hu->oper_speed; | |
1374 | else if (hu->proto->oper_speed) | |
1375 | speed = hu->proto->oper_speed; | |
1376 | } | |
1377 | ||
1378 | return speed; | |
1379 | } | |
1380 | ||
1381 | static int qca_check_speeds(struct hci_uart *hu) | |
1382 | { | |
523760b7 | 1383 | if (qca_is_wcn399x(qca_soc_type(hu))) { |
fa9ad876 BG |
1384 | if (!qca_get_speed(hu, QCA_INIT_SPEED) && |
1385 | !qca_get_speed(hu, QCA_OPER_SPEED)) | |
1386 | return -EINVAL; | |
1387 | } else { | |
1388 | if (!qca_get_speed(hu, QCA_INIT_SPEED) || | |
1389 | !qca_get_speed(hu, QCA_OPER_SPEED)) | |
1390 | return -EINVAL; | |
1391 | } | |
83d9c5e5 BG |
1392 | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type) | |
1397 | { | |
1398 | unsigned int speed, qca_baudrate; | |
2faa3f15 | 1399 | struct qca_data *qca = hu->priv; |
78e8fa29 | 1400 | int ret = 0; |
83d9c5e5 BG |
1401 | |
1402 | if (speed_type == QCA_INIT_SPEED) { | |
1403 | speed = qca_get_speed(hu, QCA_INIT_SPEED); | |
1404 | if (speed) | |
1405 | host_set_baudrate(hu, speed); | |
1406 | } else { | |
4fdd5a4f MK |
1407 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
1408 | ||
83d9c5e5 BG |
1409 | speed = qca_get_speed(hu, QCA_OPER_SPEED); |
1410 | if (!speed) | |
1411 | return 0; | |
1412 | ||
78e8fa29 BG |
1413 | /* Disable flow control for wcn3990 to deassert RTS while |
1414 | * changing the baudrate of chip and host. | |
1415 | */ | |
523760b7 | 1416 | if (qca_is_wcn399x(soc_type)) |
78e8fa29 BG |
1417 | hci_uart_set_flow_control(hu, true); |
1418 | ||
2faa3f15 MK |
1419 | if (soc_type == QCA_WCN3990) { |
1420 | reinit_completion(&qca->drop_ev_comp); | |
1421 | set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags); | |
1422 | } | |
1423 | ||
83d9c5e5 | 1424 | qca_baudrate = qca_get_baudrate_value(speed); |
fa9ad876 | 1425 | bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed); |
83d9c5e5 BG |
1426 | ret = qca_set_baudrate(hu->hdev, qca_baudrate); |
1427 | if (ret) | |
78e8fa29 | 1428 | goto error; |
83d9c5e5 BG |
1429 | |
1430 | host_set_baudrate(hu, speed); | |
78e8fa29 BG |
1431 | |
1432 | error: | |
bba79fee | 1433 | if (qca_is_wcn399x(soc_type)) |
78e8fa29 | 1434 | hci_uart_set_flow_control(hu, false); |
2faa3f15 MK |
1435 | |
1436 | if (soc_type == QCA_WCN3990) { | |
1437 | /* Wait for the controller to send the vendor event | |
1438 | * for the baudrate change command. | |
1439 | */ | |
1440 | if (!wait_for_completion_timeout(&qca->drop_ev_comp, | |
1441 | msecs_to_jiffies(100))) { | |
1442 | bt_dev_err(hu->hdev, | |
1443 | "Failed to change controller baudrate\n"); | |
1444 | ret = -ETIMEDOUT; | |
1445 | } | |
1446 | ||
1447 | clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags); | |
1448 | } | |
83d9c5e5 BG |
1449 | } |
1450 | ||
78e8fa29 | 1451 | return ret; |
83d9c5e5 BG |
1452 | } |
1453 | ||
d841502c BG |
1454 | static int qca_send_crashbuffer(struct hci_uart *hu) |
1455 | { | |
1456 | struct qca_data *qca = hu->priv; | |
1457 | struct sk_buff *skb; | |
1458 | ||
1459 | skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL); | |
1460 | if (!skb) { | |
1461 | bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet"); | |
1462 | return -ENOMEM; | |
1463 | } | |
1464 | ||
1465 | /* We forcefully crash the controller, by sending 0xfb byte for | |
1466 | * 1024 times. We also might have chance of losing data, To be | |
1467 | * on safer side we send 1096 bytes to the SoC. | |
1468 | */ | |
1469 | memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE, | |
1470 | QCA_CRASHBYTE_PACKET_LEN); | |
1471 | hci_skb_pkt_type(skb) = HCI_COMMAND_PKT; | |
1472 | bt_dev_info(hu->hdev, "crash the soc to collect controller dump"); | |
1473 | skb_queue_tail(&qca->txq, skb); | |
1474 | hci_uart_tx_wakeup(hu); | |
1475 | ||
1476 | return 0; | |
1477 | } | |
1478 | ||
1479 | static void qca_wait_for_dump_collection(struct hci_dev *hdev) | |
1480 | { | |
1481 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1482 | struct qca_data *qca = hu->priv; | |
d841502c BG |
1483 | |
1484 | wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION, | |
1485 | TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS); | |
1486 | ||
1487 | clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); | |
d841502c BG |
1488 | } |
1489 | ||
1490 | static void qca_hw_error(struct hci_dev *hdev, u8 code) | |
1491 | { | |
1492 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1493 | struct qca_data *qca = hu->priv; | |
1494 | ||
3344537f | 1495 | set_bit(QCA_SSR_TRIGGERED, &qca->flags); |
7c2c3e63 | 1496 | set_bit(QCA_HW_ERROR_EVENT, &qca->flags); |
d841502c BG |
1497 | bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state); |
1498 | ||
1499 | if (qca->memdump_state == QCA_MEMDUMP_IDLE) { | |
1500 | /* If hardware error event received for other than QCA | |
1501 | * soc memory dump event, then we need to crash the SOC | |
1502 | * and wait here for 8 seconds to get the dump packets. | |
1503 | * This will block main thread to be on hold until we | |
1504 | * collect dump. | |
1505 | */ | |
1506 | set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); | |
1507 | qca_send_crashbuffer(hu); | |
1508 | qca_wait_for_dump_collection(hdev); | |
1509 | } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) { | |
1510 | /* Let us wait here until memory dump collected or | |
1511 | * memory dump timer expired. | |
1512 | */ | |
1513 | bt_dev_info(hdev, "waiting for dump to complete"); | |
1514 | qca_wait_for_dump_collection(hdev); | |
1515 | } | |
7c2c3e63 | 1516 | |
f98aa80f | 1517 | mutex_lock(&qca->hci_memdump_lock); |
7c2c3e63 VLNG |
1518 | if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) { |
1519 | bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout"); | |
f98aa80f VLNG |
1520 | if (qca->qca_memdump) { |
1521 | vfree(qca->qca_memdump->memdump_buf_head); | |
1522 | kfree(qca->qca_memdump); | |
1523 | qca->qca_memdump = NULL; | |
1524 | } | |
7c2c3e63 VLNG |
1525 | qca->memdump_state = QCA_MEMDUMP_TIMEOUT; |
1526 | cancel_delayed_work(&qca->ctrl_memdump_timeout); | |
f98aa80f VLNG |
1527 | } |
1528 | mutex_unlock(&qca->hci_memdump_lock); | |
1529 | ||
1530 | if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT || | |
1531 | qca->memdump_state == QCA_MEMDUMP_COLLECTED) { | |
7c2c3e63 | 1532 | cancel_work_sync(&qca->ctrl_memdump_evt); |
f98aa80f | 1533 | skb_queue_purge(&qca->rx_memdump_q); |
7c2c3e63 VLNG |
1534 | } |
1535 | ||
1536 | clear_bit(QCA_HW_ERROR_EVENT, &qca->flags); | |
d841502c BG |
1537 | } |
1538 | ||
1539 | static void qca_cmd_timeout(struct hci_dev *hdev) | |
1540 | { | |
1541 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1542 | struct qca_data *qca = hu->priv; | |
1543 | ||
3344537f VLNG |
1544 | set_bit(QCA_SSR_TRIGGERED, &qca->flags); |
1545 | if (qca->memdump_state == QCA_MEMDUMP_IDLE) { | |
1546 | set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags); | |
d841502c | 1547 | qca_send_crashbuffer(hu); |
3344537f VLNG |
1548 | qca_wait_for_dump_collection(hdev); |
1549 | } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) { | |
1550 | /* Let us wait here until memory dump collected or | |
1551 | * memory dump timer expired. | |
1552 | */ | |
1553 | bt_dev_info(hdev, "waiting for dump to complete"); | |
1554 | qca_wait_for_dump_collection(hdev); | |
1555 | } | |
1556 | ||
1557 | mutex_lock(&qca->hci_memdump_lock); | |
1558 | if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) { | |
1559 | qca->memdump_state = QCA_MEMDUMP_TIMEOUT; | |
1560 | if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) { | |
1561 | /* Inject hw error event to reset the device | |
1562 | * and driver. | |
1563 | */ | |
1564 | hci_reset_dev(hu->hdev); | |
1565 | } | |
1566 | } | |
1567 | mutex_unlock(&qca->hci_memdump_lock); | |
d841502c BG |
1568 | } |
1569 | ||
fa9ad876 BG |
1570 | static int qca_wcn3990_init(struct hci_uart *hu) |
1571 | { | |
3e4be65e | 1572 | struct qca_serdev *qcadev; |
fa9ad876 BG |
1573 | int ret; |
1574 | ||
3e4be65e BG |
1575 | /* Check for vregs status, may be hci down has turned |
1576 | * off the voltage regulator. | |
1577 | */ | |
1578 | qcadev = serdev_device_get_drvdata(hu->serdev); | |
1579 | if (!qcadev->bt_power->vregs_on) { | |
1580 | serdev_device_close(hu->serdev); | |
a9314e76 | 1581 | ret = qca_regulator_enable(qcadev); |
3e4be65e BG |
1582 | if (ret) |
1583 | return ret; | |
1584 | ||
1585 | ret = serdev_device_open(hu->serdev); | |
1586 | if (ret) { | |
1587 | bt_dev_err(hu->hdev, "failed to open port"); | |
1588 | return ret; | |
1589 | } | |
1590 | } | |
1591 | ||
fa9ad876 BG |
1592 | /* Forcefully enable wcn3990 to enter in to boot mode. */ |
1593 | host_set_baudrate(hu, 2400); | |
9836b802 | 1594 | ret = qca_send_power_pulse(hu, false); |
fa9ad876 BG |
1595 | if (ret) |
1596 | return ret; | |
1597 | ||
1598 | qca_set_speed(hu, QCA_INIT_SPEED); | |
9836b802 | 1599 | ret = qca_send_power_pulse(hu, true); |
fa9ad876 BG |
1600 | if (ret) |
1601 | return ret; | |
1602 | ||
fa9ad876 BG |
1603 | /* Now the device is in ready state to communicate with host. |
1604 | * To sync host with device we need to reopen port. | |
1605 | * Without this, we will have RTS and CTS synchronization | |
1606 | * issues. | |
1607 | */ | |
1608 | serdev_device_close(hu->serdev); | |
1609 | ret = serdev_device_open(hu->serdev); | |
1610 | if (ret) { | |
1611 | bt_dev_err(hu->hdev, "failed to open port"); | |
1612 | return ret; | |
1613 | } | |
1614 | ||
1615 | hci_uart_set_flow_control(hu, false); | |
1616 | ||
1617 | return 0; | |
1618 | } | |
1619 | ||
5e6d8401 RL |
1620 | static int qca_power_on(struct hci_dev *hdev) |
1621 | { | |
1622 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
1623 | enum qca_btsoc_type soc_type = qca_soc_type(hu); | |
1624 | struct qca_serdev *qcadev; | |
2be43aba | 1625 | struct qca_data *qca = hu->priv; |
5e6d8401 RL |
1626 | int ret = 0; |
1627 | ||
1628 | /* Non-serdev device usually is powered by external power | |
1629 | * and don't need additional action in driver for power on | |
1630 | */ | |
1631 | if (!hu->serdev) | |
1632 | return 0; | |
1633 | ||
1634 | if (qca_is_wcn399x(soc_type)) { | |
1635 | ret = qca_wcn3990_init(hu); | |
1636 | } else { | |
1637 | qcadev = serdev_device_get_drvdata(hu->serdev); | |
77131dfe | 1638 | if (qcadev->bt_en) { |
8a208b24 RL |
1639 | gpiod_set_value_cansleep(qcadev->bt_en, 1); |
1640 | /* Controller needs time to bootup. */ | |
1641 | msleep(150); | |
1642 | } | |
5e6d8401 RL |
1643 | } |
1644 | ||
2be43aba | 1645 | clear_bit(QCA_BT_OFF, &qca->flags); |
5e6d8401 RL |
1646 | return ret; |
1647 | } | |
1648 | ||
0ff252c1 BYTK |
1649 | static int qca_setup(struct hci_uart *hu) |
1650 | { | |
1651 | struct hci_dev *hdev = hu->hdev; | |
1652 | struct qca_data *qca = hu->priv; | |
1653 | unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200; | |
bb2500ab | 1654 | unsigned int retries = 0; |
4fdd5a4f | 1655 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
99c905c6 | 1656 | const char *firmware_name = qca_get_firmware_name(hu); |
0ff252c1 | 1657 | int ret; |
059924fd | 1658 | struct qca_btsoc_version ver; |
0ff252c1 | 1659 | |
83d9c5e5 BG |
1660 | ret = qca_check_speeds(hu); |
1661 | if (ret) | |
1662 | return ret; | |
1663 | ||
0ff252c1 | 1664 | /* Patch downloading has to be done without IBS mode */ |
2be43aba | 1665 | set_bit(QCA_IBS_DISABLED, &qca->flags); |
0ff252c1 | 1666 | |
e14c167a RL |
1667 | /* Enable controller to do both LE scan and BR/EDR inquiry |
1668 | * simultaneously. | |
1669 | */ | |
1670 | set_bit(HCI_QUIRK_SIMULTANEOUS_DISCOVERY, &hdev->quirks); | |
1671 | ||
5e6d8401 | 1672 | bt_dev_info(hdev, "setting up %s", |
e5d6468f | 1673 | qca_is_wcn399x(soc_type) ? "wcn399x" : "ROME/QCA6390"); |
3e4be65e | 1674 | |
58789a19 VLNG |
1675 | qca->memdump_state = QCA_MEMDUMP_IDLE; |
1676 | ||
bb2500ab | 1677 | retry: |
5e6d8401 RL |
1678 | ret = qca_power_on(hdev); |
1679 | if (ret) | |
9e80587a | 1680 | goto out; |
5e6d8401 | 1681 | |
3344537f VLNG |
1682 | clear_bit(QCA_SSR_TRIGGERED, &qca->flags); |
1683 | ||
5e6d8401 | 1684 | if (qca_is_wcn399x(soc_type)) { |
5971752d | 1685 | set_bit(HCI_QUIRK_USE_BDADDR_PROPERTY, &hdev->quirks); |
fa9ad876 | 1686 | |
059924fd | 1687 | ret = qca_read_soc_version(hdev, &ver, soc_type); |
fa9ad876 | 1688 | if (ret) |
9e80587a | 1689 | goto out; |
fa9ad876 | 1690 | } else { |
fa9ad876 BG |
1691 | qca_set_speed(hu, QCA_INIT_SPEED); |
1692 | } | |
0ff252c1 BYTK |
1693 | |
1694 | /* Setup user speed if needed */ | |
83d9c5e5 | 1695 | speed = qca_get_speed(hu, QCA_OPER_SPEED); |
0ff252c1 | 1696 | if (speed) { |
83d9c5e5 BG |
1697 | ret = qca_set_speed(hu, QCA_OPER_SPEED); |
1698 | if (ret) | |
9e80587a | 1699 | goto out; |
83d9c5e5 BG |
1700 | |
1701 | qca_baudrate = qca_get_baudrate_value(speed); | |
0ff252c1 BYTK |
1702 | } |
1703 | ||
523760b7 | 1704 | if (!qca_is_wcn399x(soc_type)) { |
fa9ad876 | 1705 | /* Get QCA version information */ |
059924fd | 1706 | ret = qca_read_soc_version(hdev, &ver, soc_type); |
fa9ad876 | 1707 | if (ret) |
9e80587a | 1708 | goto out; |
fa9ad876 | 1709 | } |
aadebac4 | 1710 | |
0ff252c1 | 1711 | /* Setup patch / NVM configurations */ |
059924fd | 1712 | ret = qca_uart_setup(hdev, qca_baudrate, soc_type, ver, |
99c905c6 | 1713 | firmware_name); |
0ff252c1 | 1714 | if (!ret) { |
2be43aba | 1715 | clear_bit(QCA_IBS_DISABLED, &qca->flags); |
0ff252c1 | 1716 | qca_debugfs_init(hdev); |
d841502c BG |
1717 | hu->hdev->hw_error = qca_hw_error; |
1718 | hu->hdev->cmd_timeout = qca_cmd_timeout; | |
ba8f3597 LP |
1719 | } else if (ret == -ENOENT) { |
1720 | /* No patch/nvm-config found, run with original fw/config */ | |
1721 | ret = 0; | |
7dc5fe08 AP |
1722 | } else if (ret == -EAGAIN) { |
1723 | /* | |
1724 | * Userspace firmware loader will return -EAGAIN in case no | |
1725 | * patch/nvm-config is found, so run with original fw/config. | |
1726 | */ | |
1727 | ret = 0; | |
9e80587a BG |
1728 | } |
1729 | ||
1730 | out: | |
1731 | if (ret && retries < MAX_INIT_RETRIES) { | |
1732 | bt_dev_warn(hdev, "Retry BT power ON:%d", retries); | |
1733 | qca_power_shutdown(hu); | |
1734 | if (hu->serdev) { | |
1735 | serdev_device_close(hu->serdev); | |
1736 | ret = serdev_device_open(hu->serdev); | |
1737 | if (ret) { | |
1738 | bt_dev_err(hdev, "failed to open port"); | |
1739 | return ret; | |
bb2500ab | 1740 | } |
bb2500ab | 1741 | } |
9e80587a BG |
1742 | retries++; |
1743 | goto retry; | |
0ff252c1 BYTK |
1744 | } |
1745 | ||
1746 | /* Setup bdaddr */ | |
e5d6468f | 1747 | if (soc_type == QCA_ROME) |
5c0a1001 | 1748 | hu->hdev->set_bdaddr = qca_set_bdaddr_rome; |
e5d6468f RL |
1749 | else |
1750 | hu->hdev->set_bdaddr = qca_set_bdaddr; | |
0ff252c1 BYTK |
1751 | |
1752 | return ret; | |
1753 | } | |
1754 | ||
2edc9c5c | 1755 | static const struct hci_uart_proto qca_proto = { |
0ff252c1 BYTK |
1756 | .id = HCI_UART_QCA, |
1757 | .name = "QCA", | |
aee61f7a | 1758 | .manufacturer = 29, |
0ff252c1 BYTK |
1759 | .init_speed = 115200, |
1760 | .oper_speed = 3000000, | |
1761 | .open = qca_open, | |
1762 | .close = qca_close, | |
1763 | .flush = qca_flush, | |
1764 | .setup = qca_setup, | |
1765 | .recv = qca_recv, | |
1766 | .enqueue = qca_enqueue, | |
1767 | .dequeue = qca_dequeue, | |
1768 | }; | |
1769 | ||
a228f7a4 | 1770 | static const struct qca_device_data qca_soc_data_wcn3990 = { |
fa9ad876 BG |
1771 | .soc_type = QCA_WCN3990, |
1772 | .vregs = (struct qca_vreg []) { | |
f2edd66e BA |
1773 | { "vddio", 15000 }, |
1774 | { "vddxo", 80000 }, | |
1775 | { "vddrf", 300000 }, | |
1776 | { "vddch0", 450000 }, | |
fa9ad876 BG |
1777 | }, |
1778 | .num_vregs = 4, | |
1779 | }; | |
1780 | ||
a228f7a4 | 1781 | static const struct qca_device_data qca_soc_data_wcn3991 = { |
7d250a06 BG |
1782 | .soc_type = QCA_WCN3991, |
1783 | .vregs = (struct qca_vreg []) { | |
1784 | { "vddio", 15000 }, | |
1785 | { "vddxo", 80000 }, | |
1786 | { "vddrf", 300000 }, | |
1787 | { "vddch0", 450000 }, | |
1788 | }, | |
1789 | .num_vregs = 4, | |
54780138 | 1790 | .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES, |
7d250a06 BG |
1791 | }; |
1792 | ||
a228f7a4 | 1793 | static const struct qca_device_data qca_soc_data_wcn3998 = { |
523760b7 HB |
1794 | .soc_type = QCA_WCN3998, |
1795 | .vregs = (struct qca_vreg []) { | |
f2edd66e BA |
1796 | { "vddio", 10000 }, |
1797 | { "vddxo", 80000 }, | |
1798 | { "vddrf", 300000 }, | |
1799 | { "vddch0", 450000 }, | |
523760b7 HB |
1800 | }, |
1801 | .num_vregs = 4, | |
1802 | }; | |
1803 | ||
a228f7a4 | 1804 | static const struct qca_device_data qca_soc_data_qca6390 = { |
e5d6468f RL |
1805 | .soc_type = QCA_QCA6390, |
1806 | .num_vregs = 0, | |
1807 | }; | |
1808 | ||
c2d78273 | 1809 | static void qca_power_shutdown(struct hci_uart *hu) |
fa9ad876 | 1810 | { |
a9314e76 | 1811 | struct qca_serdev *qcadev; |
035a960e BG |
1812 | struct qca_data *qca = hu->priv; |
1813 | unsigned long flags; | |
5559904c | 1814 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
035a960e | 1815 | |
a9314e76 BA |
1816 | qcadev = serdev_device_get_drvdata(hu->serdev); |
1817 | ||
035a960e BG |
1818 | /* From this point we go into power off state. But serial port is |
1819 | * still open, stop queueing the IBS data and flush all the buffered | |
1820 | * data in skb's. | |
1821 | */ | |
1822 | spin_lock_irqsave(&qca->hci_ibs_lock, flags); | |
2be43aba | 1823 | set_bit(QCA_IBS_DISABLED, &qca->flags); |
035a960e BG |
1824 | qca_flush(hu); |
1825 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
1826 | ||
5559904c RL |
1827 | /* Non-serdev device usually is powered by external power |
1828 | * and don't need additional action in driver for power down | |
1829 | */ | |
1830 | if (!hu->serdev) | |
1831 | return; | |
1832 | ||
1833 | if (qca_is_wcn399x(soc_type)) { | |
1834 | host_set_baudrate(hu, 2400); | |
1835 | qca_send_power_pulse(hu, false); | |
1836 | qca_regulator_disable(qcadev); | |
77131dfe | 1837 | } else if (qcadev->bt_en) { |
5559904c RL |
1838 | gpiod_set_value_cansleep(qcadev->bt_en, 0); |
1839 | } | |
2be43aba VLNG |
1840 | |
1841 | set_bit(QCA_BT_OFF, &qca->flags); | |
fa9ad876 BG |
1842 | } |
1843 | ||
3e4be65e BG |
1844 | static int qca_power_off(struct hci_dev *hdev) |
1845 | { | |
1846 | struct hci_uart *hu = hci_get_drvdata(hdev); | |
d841502c | 1847 | struct qca_data *qca = hu->priv; |
4f9ed5bd | 1848 | enum qca_btsoc_type soc_type = qca_soc_type(hu); |
3e4be65e | 1849 | |
58789a19 VLNG |
1850 | hu->hdev->hw_error = NULL; |
1851 | hu->hdev->cmd_timeout = NULL; | |
1852 | ||
d841502c | 1853 | /* Stop sending shutdown command if soc crashes. */ |
e5d6468f | 1854 | if (soc_type != QCA_ROME |
4f9ed5bd | 1855 | && qca->memdump_state == QCA_MEMDUMP_IDLE) { |
d841502c BG |
1856 | qca_send_pre_shutdown_cmd(hdev); |
1857 | usleep_range(8000, 10000); | |
1858 | } | |
010376ab | 1859 | |
3e4be65e BG |
1860 | qca_power_shutdown(hu); |
1861 | return 0; | |
1862 | } | |
1863 | ||
a9314e76 | 1864 | static int qca_regulator_enable(struct qca_serdev *qcadev) |
fa9ad876 | 1865 | { |
a9314e76 BA |
1866 | struct qca_power *power = qcadev->bt_power; |
1867 | int ret; | |
fa9ad876 | 1868 | |
a9314e76 BA |
1869 | /* Already enabled */ |
1870 | if (power->vregs_on) | |
1871 | return 0; | |
fa9ad876 | 1872 | |
a9314e76 | 1873 | BT_DBG("enabling %d regulators)", power->num_vregs); |
fa9ad876 | 1874 | |
a9314e76 BA |
1875 | ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk); |
1876 | if (ret) | |
1877 | return ret; | |
fa9ad876 | 1878 | |
a9314e76 | 1879 | power->vregs_on = true; |
fa9ad876 | 1880 | |
66cb7051 | 1881 | ret = clk_prepare_enable(qcadev->susclk); |
f3d63f50 | 1882 | if (ret) |
66cb7051 | 1883 | qca_regulator_disable(qcadev); |
66cb7051 | 1884 | |
f3d63f50 | 1885 | return ret; |
fa9ad876 BG |
1886 | } |
1887 | ||
a9314e76 BA |
1888 | static void qca_regulator_disable(struct qca_serdev *qcadev) |
1889 | { | |
1890 | struct qca_power *power; | |
1891 | ||
1892 | if (!qcadev) | |
1893 | return; | |
1894 | ||
1895 | power = qcadev->bt_power; | |
1896 | ||
1897 | /* Already disabled? */ | |
1898 | if (!power->vregs_on) | |
1899 | return; | |
1900 | ||
1901 | regulator_bulk_disable(power->num_vregs, power->vreg_bulk); | |
1902 | power->vregs_on = false; | |
66cb7051 | 1903 | |
f3d63f50 | 1904 | clk_disable_unprepare(qcadev->susclk); |
a9314e76 BA |
1905 | } |
1906 | ||
fa9ad876 BG |
1907 | static int qca_init_regulators(struct qca_power *qca, |
1908 | const struct qca_vreg *vregs, size_t num_vregs) | |
1909 | { | |
c29ff107 BA |
1910 | struct regulator_bulk_data *bulk; |
1911 | int ret; | |
fa9ad876 BG |
1912 | int i; |
1913 | ||
c29ff107 BA |
1914 | bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL); |
1915 | if (!bulk) | |
fa9ad876 BG |
1916 | return -ENOMEM; |
1917 | ||
1918 | for (i = 0; i < num_vregs; i++) | |
c29ff107 BA |
1919 | bulk[i].supply = vregs[i].name; |
1920 | ||
1921 | ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk); | |
1922 | if (ret < 0) | |
1923 | return ret; | |
fa9ad876 | 1924 | |
c29ff107 BA |
1925 | for (i = 0; i < num_vregs; i++) { |
1926 | ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA); | |
1927 | if (ret) | |
1928 | return ret; | |
1929 | } | |
1930 | ||
1931 | qca->vreg_bulk = bulk; | |
163d42fa | 1932 | qca->num_vregs = num_vregs; |
c29ff107 BA |
1933 | |
1934 | return 0; | |
fa9ad876 BG |
1935 | } |
1936 | ||
05ba533c TE |
1937 | static int qca_serdev_probe(struct serdev_device *serdev) |
1938 | { | |
1939 | struct qca_serdev *qcadev; | |
ae563183 | 1940 | struct hci_dev *hdev; |
a228f7a4 | 1941 | const struct qca_device_data *data; |
05ba533c | 1942 | int err; |
8a208b24 | 1943 | bool power_ctrl_enabled = true; |
05ba533c TE |
1944 | |
1945 | qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL); | |
1946 | if (!qcadev) | |
1947 | return -ENOMEM; | |
1948 | ||
1949 | qcadev->serdev_hu.serdev = serdev; | |
9f3565b8 | 1950 | data = device_get_match_data(&serdev->dev); |
05ba533c | 1951 | serdev_device_set_drvdata(serdev, qcadev); |
99c905c6 RL |
1952 | device_property_read_string(&serdev->dev, "firmware-name", |
1953 | &qcadev->firmware_name); | |
37aee136 CH |
1954 | device_property_read_u32(&serdev->dev, "max-speed", |
1955 | &qcadev->oper_speed); | |
1956 | if (!qcadev->oper_speed) | |
1957 | BT_DBG("UART will pick default operating speed"); | |
1958 | ||
523760b7 HB |
1959 | if (data && qca_is_wcn399x(data->soc_type)) { |
1960 | qcadev->btsoc_type = data->soc_type; | |
fa9ad876 BG |
1961 | qcadev->bt_power = devm_kzalloc(&serdev->dev, |
1962 | sizeof(struct qca_power), | |
1963 | GFP_KERNEL); | |
1964 | if (!qcadev->bt_power) | |
1965 | return -ENOMEM; | |
1966 | ||
1967 | qcadev->bt_power->dev = &serdev->dev; | |
fa9ad876 BG |
1968 | err = qca_init_regulators(qcadev->bt_power, data->vregs, |
1969 | data->num_vregs); | |
1970 | if (err) { | |
1971 | BT_ERR("Failed to init regulators:%d", err); | |
ae563183 | 1972 | return err; |
fa9ad876 | 1973 | } |
05ba533c | 1974 | |
fa9ad876 | 1975 | qcadev->bt_power->vregs_on = false; |
05ba533c | 1976 | |
66cb7051 VLNG |
1977 | qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL); |
1978 | if (IS_ERR(qcadev->susclk)) { | |
1979 | dev_err(&serdev->dev, "failed to acquire clk\n"); | |
1980 | return PTR_ERR(qcadev->susclk); | |
1981 | } | |
1982 | ||
fa9ad876 BG |
1983 | err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto); |
1984 | if (err) { | |
1985 | BT_ERR("wcn3990 serdev registration failed"); | |
ae563183 | 1986 | return err; |
fa9ad876 BG |
1987 | } |
1988 | } else { | |
e5d6468f RL |
1989 | if (data) |
1990 | qcadev->btsoc_type = data->soc_type; | |
1991 | else | |
1992 | qcadev->btsoc_type = QCA_ROME; | |
1993 | ||
77131dfe | 1994 | qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable", |
fa9ad876 | 1995 | GPIOD_OUT_LOW); |
77131dfe | 1996 | if (!qcadev->bt_en) { |
8a208b24 RL |
1997 | dev_warn(&serdev->dev, "failed to acquire enable gpio\n"); |
1998 | power_ctrl_enabled = false; | |
fa9ad876 | 1999 | } |
05ba533c | 2000 | |
77131dfe | 2001 | qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL); |
4c07a5d7 | 2002 | if (IS_ERR(qcadev->susclk)) { |
8a208b24 | 2003 | dev_warn(&serdev->dev, "failed to acquire clk\n"); |
4c07a5d7 | 2004 | return PTR_ERR(qcadev->susclk); |
8a208b24 | 2005 | } |
4c07a5d7 DC |
2006 | err = clk_set_rate(qcadev->susclk, SUSCLK_RATE_32KHZ); |
2007 | if (err) | |
2008 | return err; | |
2009 | ||
2010 | err = clk_prepare_enable(qcadev->susclk); | |
2011 | if (err) | |
2012 | return err; | |
fa9ad876 BG |
2013 | |
2014 | err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto); | |
ae563183 RL |
2015 | if (err) { |
2016 | BT_ERR("Rome serdev registration failed"); | |
65a24d4c | 2017 | clk_disable_unprepare(qcadev->susclk); |
ae563183 RL |
2018 | return err; |
2019 | } | |
fa9ad876 BG |
2020 | } |
2021 | ||
85e90d93 APS |
2022 | hdev = qcadev->serdev_hu.hdev; |
2023 | ||
8a208b24 | 2024 | if (power_ctrl_enabled) { |
8a208b24 RL |
2025 | set_bit(HCI_QUIRK_NON_PERSISTENT_SETUP, &hdev->quirks); |
2026 | hdev->shutdown = qca_power_off; | |
2027 | } | |
05ba533c | 2028 | |
54780138 APS |
2029 | if (data) { |
2030 | /* Wideband speech support must be set per driver since it can't | |
2031 | * be queried via hci. Same with the valid le states quirk. | |
2032 | */ | |
2033 | if (data->capabilities & QCA_CAP_WIDEBAND_SPEECH) | |
2034 | set_bit(HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED, | |
2035 | &hdev->quirks); | |
2036 | ||
2037 | if (data->capabilities & QCA_CAP_VALID_LE_STATES) | |
2038 | set_bit(HCI_QUIRK_VALID_LE_STATES, &hdev->quirks); | |
2039 | } | |
a228f7a4 | 2040 | |
ae563183 | 2041 | return 0; |
05ba533c TE |
2042 | } |
2043 | ||
2044 | static void qca_serdev_remove(struct serdev_device *serdev) | |
2045 | { | |
2046 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
054ec5e9 | 2047 | struct qca_power *power = qcadev->bt_power; |
05ba533c | 2048 | |
054ec5e9 | 2049 | if (qca_is_wcn399x(qcadev->btsoc_type) && power->vregs_on) |
c2d78273 | 2050 | qca_power_shutdown(&qcadev->serdev_hu); |
77131dfe | 2051 | else if (qcadev->susclk) |
fa9ad876 | 2052 | clk_disable_unprepare(qcadev->susclk); |
05ba533c | 2053 | |
fa9ad876 | 2054 | hci_uart_unregister_device(&qcadev->serdev_hu); |
05ba533c TE |
2055 | } |
2056 | ||
7e7bbddd ZH |
2057 | static void qca_serdev_shutdown(struct device *dev) |
2058 | { | |
2059 | int ret; | |
2060 | int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS); | |
2061 | struct serdev_device *serdev = to_serdev_device(dev); | |
2062 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2063 | const u8 ibs_wake_cmd[] = { 0xFD }; | |
2064 | const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 }; | |
2065 | ||
2066 | if (qcadev->btsoc_type == QCA_QCA6390) { | |
2067 | serdev_device_write_flush(serdev); | |
2068 | ret = serdev_device_write_buf(serdev, ibs_wake_cmd, | |
2069 | sizeof(ibs_wake_cmd)); | |
2070 | if (ret < 0) { | |
2071 | BT_ERR("QCA send IBS_WAKE_IND error: %d", ret); | |
2072 | return; | |
2073 | } | |
2074 | serdev_device_wait_until_sent(serdev, timeout); | |
2075 | usleep_range(8000, 10000); | |
2076 | ||
2077 | serdev_device_write_flush(serdev); | |
2078 | ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd, | |
2079 | sizeof(edl_reset_soc_cmd)); | |
2080 | if (ret < 0) { | |
2081 | BT_ERR("QCA send EDL_RESET_REQ error: %d", ret); | |
2082 | return; | |
2083 | } | |
2084 | serdev_device_wait_until_sent(serdev, timeout); | |
2085 | usleep_range(8000, 10000); | |
2086 | } | |
2087 | } | |
2088 | ||
41d5b25f CC |
2089 | static int __maybe_unused qca_suspend(struct device *dev) |
2090 | { | |
feac90d7 ZH |
2091 | struct serdev_device *serdev = to_serdev_device(dev); |
2092 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2093 | struct hci_uart *hu = &qcadev->serdev_hu; | |
41d5b25f CC |
2094 | struct qca_data *qca = hu->priv; |
2095 | unsigned long flags; | |
e2a119cd | 2096 | bool tx_pending = false; |
41d5b25f CC |
2097 | int ret = 0; |
2098 | u8 cmd; | |
2be43aba | 2099 | u32 wait_timeout = 0; |
41d5b25f CC |
2100 | |
2101 | set_bit(QCA_SUSPENDING, &qca->flags); | |
2102 | ||
2be43aba VLNG |
2103 | if (test_bit(QCA_BT_OFF, &qca->flags)) |
2104 | return 0; | |
2105 | ||
2106 | if (test_bit(QCA_IBS_DISABLED, &qca->flags)) { | |
2107 | wait_timeout = test_bit(QCA_SSR_TRIGGERED, &qca->flags) ? | |
2108 | IBS_DISABLE_SSR_TIMEOUT_MS : | |
2109 | FW_DOWNLOAD_TIMEOUT_MS; | |
2110 | ||
2111 | /* QCA_IBS_DISABLED flag is set to true, During FW download | |
2112 | * and during memory dump collection. It is reset to false, | |
2113 | * After FW download complete and after memory dump collections. | |
2114 | */ | |
2115 | wait_on_bit_timeout(&qca->flags, QCA_IBS_DISABLED, | |
2116 | TASK_UNINTERRUPTIBLE, msecs_to_jiffies(wait_timeout)); | |
2117 | ||
2118 | if (test_bit(QCA_IBS_DISABLED, &qca->flags)) { | |
2119 | bt_dev_err(hu->hdev, "SSR or FW download time out"); | |
2120 | ret = -ETIMEDOUT; | |
2121 | goto error; | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | /* After memory dump collection, Controller is powered off.*/ | |
2126 | if (test_bit(QCA_BT_OFF, &qca->flags)) | |
41d5b25f CC |
2127 | return 0; |
2128 | ||
2129 | cancel_work_sync(&qca->ws_awake_device); | |
2130 | cancel_work_sync(&qca->ws_awake_rx); | |
2131 | ||
2132 | spin_lock_irqsave_nested(&qca->hci_ibs_lock, | |
2133 | flags, SINGLE_DEPTH_NESTING); | |
2134 | ||
2135 | switch (qca->tx_ibs_state) { | |
2136 | case HCI_IBS_TX_WAKING: | |
2137 | del_timer(&qca->wake_retrans_timer); | |
a3b4cbfc | 2138 | fallthrough; |
41d5b25f CC |
2139 | case HCI_IBS_TX_AWAKE: |
2140 | del_timer(&qca->tx_idle_timer); | |
2141 | ||
2142 | serdev_device_write_flush(hu->serdev); | |
2143 | cmd = HCI_IBS_SLEEP_IND; | |
2144 | ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd)); | |
2145 | ||
2146 | if (ret < 0) { | |
2147 | BT_ERR("Failed to send SLEEP to device"); | |
2148 | break; | |
2149 | } | |
2150 | ||
2151 | qca->tx_ibs_state = HCI_IBS_TX_ASLEEP; | |
2152 | qca->ibs_sent_slps++; | |
e2a119cd | 2153 | tx_pending = true; |
41d5b25f CC |
2154 | break; |
2155 | ||
2156 | case HCI_IBS_TX_ASLEEP: | |
2157 | break; | |
2158 | ||
2159 | default: | |
2160 | BT_ERR("Spurious tx state %d", qca->tx_ibs_state); | |
2161 | ret = -EINVAL; | |
2162 | break; | |
2163 | } | |
2164 | ||
2165 | spin_unlock_irqrestore(&qca->hci_ibs_lock, flags); | |
2166 | ||
2167 | if (ret < 0) | |
2168 | goto error; | |
2169 | ||
e2a119cd MK |
2170 | if (tx_pending) { |
2171 | serdev_device_wait_until_sent(hu->serdev, | |
2172 | msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS)); | |
201a1124 | 2173 | serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu); |
e2a119cd | 2174 | } |
41d5b25f CC |
2175 | |
2176 | /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going | |
2177 | * to sleep, so that the packet does not wake the system later. | |
2178 | */ | |
41d5b25f CC |
2179 | ret = wait_event_interruptible_timeout(qca->suspend_wait_q, |
2180 | qca->rx_ibs_state == HCI_IBS_RX_ASLEEP, | |
2181 | msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS)); | |
4da385f7 MK |
2182 | if (ret == 0) { |
2183 | ret = -ETIMEDOUT; | |
2184 | goto error; | |
eff981f6 | 2185 | } |
41d5b25f | 2186 | |
4da385f7 | 2187 | return 0; |
41d5b25f CC |
2188 | |
2189 | error: | |
2190 | clear_bit(QCA_SUSPENDING, &qca->flags); | |
2191 | ||
2192 | return ret; | |
2193 | } | |
2194 | ||
2195 | static int __maybe_unused qca_resume(struct device *dev) | |
2196 | { | |
feac90d7 ZH |
2197 | struct serdev_device *serdev = to_serdev_device(dev); |
2198 | struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev); | |
2199 | struct hci_uart *hu = &qcadev->serdev_hu; | |
41d5b25f CC |
2200 | struct qca_data *qca = hu->priv; |
2201 | ||
2202 | clear_bit(QCA_SUSPENDING, &qca->flags); | |
2203 | ||
2204 | return 0; | |
2205 | } | |
2206 | ||
2207 | static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume); | |
2208 | ||
e5d6468f | 2209 | #ifdef CONFIG_OF |
05ba533c TE |
2210 | static const struct of_device_id qca_bluetooth_of_match[] = { |
2211 | { .compatible = "qcom,qca6174-bt" }, | |
e5d6468f | 2212 | { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390}, |
31d4ab85 | 2213 | { .compatible = "qcom,qca9377-bt" }, |
523760b7 | 2214 | { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990}, |
7d250a06 | 2215 | { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991}, |
523760b7 | 2216 | { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998}, |
05ba533c TE |
2217 | { /* sentinel */ } |
2218 | }; | |
2219 | MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match); | |
e5d6468f RL |
2220 | #endif |
2221 | ||
2222 | #ifdef CONFIG_ACPI | |
2223 | static const struct acpi_device_id qca_bluetooth_acpi_match[] = { | |
2224 | { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2225 | { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2226 | { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2227 | { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 }, | |
2228 | { }, | |
2229 | }; | |
2230 | MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match); | |
2231 | #endif | |
2232 | ||
05ba533c TE |
2233 | |
2234 | static struct serdev_device_driver qca_serdev_driver = { | |
2235 | .probe = qca_serdev_probe, | |
2236 | .remove = qca_serdev_remove, | |
2237 | .driver = { | |
2238 | .name = "hci_uart_qca", | |
e5d6468f RL |
2239 | .of_match_table = of_match_ptr(qca_bluetooth_of_match), |
2240 | .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match), | |
7e7bbddd | 2241 | .shutdown = qca_serdev_shutdown, |
41d5b25f | 2242 | .pm = &qca_pm_ops, |
05ba533c TE |
2243 | }, |
2244 | }; | |
2245 | ||
0ff252c1 BYTK |
2246 | int __init qca_init(void) |
2247 | { | |
05ba533c TE |
2248 | serdev_device_driver_register(&qca_serdev_driver); |
2249 | ||
0ff252c1 BYTK |
2250 | return hci_uart_register_proto(&qca_proto); |
2251 | } | |
2252 | ||
2253 | int __exit qca_deinit(void) | |
2254 | { | |
05ba533c TE |
2255 | serdev_device_driver_unregister(&qca_serdev_driver); |
2256 | ||
0ff252c1 BYTK |
2257 | return hci_uart_unregister_proto(&qca_proto); |
2258 | } |