[linux-block.git] / drivers / bluetooth / btqca.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  Bluetooth supports for Qualcomm Atheros ROME chips
 *
 *  Copyright (c) 2015 The Linux Foundation. All rights reserved.
 */

#define EDL_PATCH_CMD_OPCODE		(0xFC00)
#define EDL_NVM_ACCESS_OPCODE		(0xFC0B)
#define EDL_WRITE_BD_ADDR_OPCODE	(0xFC14)
#define EDL_PATCH_CMD_LEN		(1)
#define EDL_PATCH_VER_REQ_CMD		(0x19)
#define EDL_PATCH_TLV_REQ_CMD		(0x1E)
#define EDL_GET_BUILD_INFO_CMD		(0x20)
#define EDL_NVM_ACCESS_SET_REQ_CMD	(0x01)
#define EDL_PATCH_CONFIG_CMD		(0x28)
#define MAX_SIZE_PER_TLV_SEGMENT	(243)
#define QCA_PRE_SHUTDOWN_CMD		(0xFC08)
#define QCA_DISABLE_LOGGING		(0xFC17)

#define EDL_CMD_REQ_RES_EVT		(0x00)
#define EDL_PATCH_VER_RES_EVT		(0x19)
#define EDL_APP_VER_RES_EVT		(0x02)
#define EDL_TVL_DNLD_RES_EVT		(0x04)
#define EDL_CMD_EXE_STATUS_EVT		(0x00)
#define EDL_SET_BAUDRATE_RSP_EVT	(0x92)
#define EDL_NVM_ACCESS_CODE_EVT		(0x0B)
#define EDL_PATCH_CONFIG_RES_EVT	(0x00)
#define QCA_DISABLE_LOGGING_SUB_OP	(0x14)

#define EDL_TAG_ID_HCI			(17)
#define EDL_TAG_ID_DEEP_SLEEP		(27)

#define QCA_WCN3990_POWERON_PULSE	0xFC
#define QCA_WCN3990_POWEROFF_PULSE	0xC0

#define QCA_HCI_CC_OPCODE		0xFC00
#define QCA_HCI_CC_SUCCESS		0x00

#define QCA_WCN3991_SOC_ID		(0x40014320)

/* QCA chipset version can be decided by patch and SoC
 * version, combination with upper 2 bytes from SoC
 * and lower 2 bytes from patch will be used.
 */
#define get_soc_ver(soc_id, rom_ver)	\
	((le32_to_cpu(soc_id) << 16) | (le16_to_cpu(rom_ver)))

#define QCA_FW_BUILD_VER_LEN		255


enum qca_baudrate {
	QCA_BAUDRATE_115200 	= 0,
	QCA_BAUDRATE_57600,
	QCA_BAUDRATE_38400,
	QCA_BAUDRATE_19200,
	QCA_BAUDRATE_9600,
	QCA_BAUDRATE_230400,
	QCA_BAUDRATE_250000,
	QCA_BAUDRATE_460800,
	QCA_BAUDRATE_500000,
	QCA_BAUDRATE_720000,
	QCA_BAUDRATE_921600,
	QCA_BAUDRATE_1000000,
	QCA_BAUDRATE_1250000,
	QCA_BAUDRATE_2000000,
	QCA_BAUDRATE_3000000,
	QCA_BAUDRATE_4000000,
	QCA_BAUDRATE_1600000,
	QCA_BAUDRATE_3200000,
	QCA_BAUDRATE_3500000,
	QCA_BAUDRATE_AUTO 	= 0xFE,
	QCA_BAUDRATE_RESERVED
};

enum qca_tlv_dnld_mode {
	QCA_SKIP_EVT_NONE,
	QCA_SKIP_EVT_VSE,
	QCA_SKIP_EVT_CC,
	QCA_SKIP_EVT_VSE_CC
};

enum qca_tlv_type {
	TLV_TYPE_PATCH = 1,
	TLV_TYPE_NVM,
	ELF_TYPE_PATCH,
};

struct qca_fw_config {
	u8 type;
	char fwname[64];
	uint8_t user_baud_rate;
	enum qca_tlv_dnld_mode dnld_mode;
	enum qca_tlv_dnld_mode dnld_type;
};

struct edl_event_hdr {
	__u8 cresp;
	__u8 rtype;
	__u8 data[];
} __packed;

struct qca_btsoc_version {
	__le32 product_id;
	__le16 patch_ver;
	__le16 rom_ver;
	__le32 soc_id;
} __packed;

struct tlv_seg_resp {
	__u8 result;
} __packed;

struct tlv_type_patch {
	__le32 total_size;
	__le32 data_length;
	__u8   format_version;
	__u8   signature;
	__u8   download_mode;
	__u8   reserved1;
	__le16 product_id;
	__le16 rom_build;
	__le16 patch_version;
	__le16 reserved2;
	__le32 entry;
} __packed;

struct tlv_type_nvm {
	__le16 tag_id;
	__le16 tag_len;
	__le32 reserve1;
	__le32 reserve2;
	__u8   data[];
} __packed;

struct tlv_type_hdr {
	__le32 type_len;
	__u8   data[];
} __packed;

enum qca_btsoc_type {
	QCA_INVALID = -1,
	QCA_AR3002,
	QCA_ROME,
	QCA_WCN3990,
	QCA_WCN3998,
	QCA_WCN3991,
	QCA_QCA6390,
	QCA_WCN6750,
};

#if IS_ENABLED(CONFIG_BT_QCA)

int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr);
int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
		   enum qca_btsoc_type soc_type, struct qca_btsoc_version ver,
		   const char *firmware_name);
int qca_read_soc_version(struct hci_dev *hdev, struct qca_btsoc_version *ver,
			 enum qca_btsoc_type);
int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
int qca_send_pre_shutdown_cmd(struct hci_dev *hdev);
static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
{
	return soc_type == QCA_WCN3990 || soc_type == QCA_WCN3991 ||
	       soc_type == QCA_WCN3998;
}
static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
{
	return soc_type == QCA_WCN6750;
}

#else

static inline int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
{
	return -EOPNOTSUPP;
}

static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
				 enum qca_btsoc_type soc_type,
				 struct qca_btsoc_version ver,
				 const char *firmware_name)
{
	return -EOPNOTSUPP;
}

static inline int qca_read_soc_version(struct hci_dev *hdev,
				       struct qca_btsoc_version *ver,
				       enum qca_btsoc_type)
{
	return -EOPNOTSUPP;
}

static inline int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
{
	return -EOPNOTSUPP;
}

static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
{
	return false;
}

static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
{
	return false;
}

static inline int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
{
	return -EOPNOTSUPP;
}
#endif
Commit	Line	Data
45051539	1	/* SPDX-License-Identifier: GPL-2.0-only */
83e81961 BYTK	2	/*
	3	* Bluetooth supports for Qualcomm Atheros ROME chips
	4	*
	5	* Copyright (c) 2015 The Linux Foundation. All rights reserved.
83e81961 BYTK	6	*/
	7
	8	#define EDL_PATCH_CMD_OPCODE (0xFC00)
	9	#define EDL_NVM_ACCESS_OPCODE (0xFC0B)
5c0a1001	10	#define EDL_WRITE_BD_ADDR_OPCODE (0xFC14)
83e81961 BYTK	11	#define EDL_PATCH_CMD_LEN (1)
	12	#define EDL_PATCH_VER_REQ_CMD (0x19)
	13	#define EDL_PATCH_TLV_REQ_CMD (0x1E)
c0187b0b	14	#define EDL_GET_BUILD_INFO_CMD (0x20)
83e81961	15	#define EDL_NVM_ACCESS_SET_REQ_CMD (0x01)
4fac8a7a	16	#define EDL_PATCH_CONFIG_CMD (0x28)
83e81961	17	#define MAX_SIZE_PER_TLV_SEGMENT (243)
a2780889	18	#define QCA_PRE_SHUTDOWN_CMD (0xFC08)
590deccf	19	#define QCA_DISABLE_LOGGING (0xFC17)
83e81961 BYTK	20
	21	#define EDL_CMD_REQ_RES_EVT (0x00)
	22	#define EDL_PATCH_VER_RES_EVT (0x19)
	23	#define EDL_APP_VER_RES_EVT (0x02)
	24	#define EDL_TVL_DNLD_RES_EVT (0x04)
	25	#define EDL_CMD_EXE_STATUS_EVT (0x00)
	26	#define EDL_SET_BAUDRATE_RSP_EVT (0x92)
	27	#define EDL_NVM_ACCESS_CODE_EVT (0x0B)
4fac8a7a	28	#define EDL_PATCH_CONFIG_RES_EVT (0x00)
590deccf	29	#define QCA_DISABLE_LOGGING_SUB_OP (0x14)
83e81961 BYTK	30
	31	#define EDL_TAG_ID_HCI (17)
	32	#define EDL_TAG_ID_DEEP_SLEEP (27)
	33
fa9ad876 BG	34	#define QCA_WCN3990_POWERON_PULSE 0xFC
	35	#define QCA_WCN3990_POWEROFF_PULSE 0xC0
	36
32646db8 BG	37	#define QCA_HCI_CC_OPCODE 0xFC00
	38	#define QCA_HCI_CC_SUCCESS 0x00
	39
059924fd VLNG	40	#define QCA_WCN3991_SOC_ID (0x40014320)
	41
	42	/* QCA chipset version can be decided by patch and SoC
	43	* version, combination with upper 2 bytes from SoC
	44	* and lower 2 bytes from patch will be used.
	45	*/
	46	#define get_soc_ver(soc_id, rom_ver) \
	47	((le32_to_cpu(soc_id) << 16) \| (le16_to_cpu(rom_ver)))
	48
	49	#define QCA_FW_BUILD_VER_LEN 255
	50
	51
75c98a97	52	enum qca_baudrate {
83e81961 BYTK	53	QCA_BAUDRATE_115200 = 0,
	54	QCA_BAUDRATE_57600,
	55	QCA_BAUDRATE_38400,
	56	QCA_BAUDRATE_19200,
	57	QCA_BAUDRATE_9600,
	58	QCA_BAUDRATE_230400,
	59	QCA_BAUDRATE_250000,
	60	QCA_BAUDRATE_460800,
	61	QCA_BAUDRATE_500000,
	62	QCA_BAUDRATE_720000,
	63	QCA_BAUDRATE_921600,
	64	QCA_BAUDRATE_1000000,
	65	QCA_BAUDRATE_1250000,
	66	QCA_BAUDRATE_2000000,
	67	QCA_BAUDRATE_3000000,
	68	QCA_BAUDRATE_4000000,
	69	QCA_BAUDRATE_1600000,
	70	QCA_BAUDRATE_3200000,
	71	QCA_BAUDRATE_3500000,
	72	QCA_BAUDRATE_AUTO = 0xFE,
	73	QCA_BAUDRATE_RESERVED
	74	};
	75
e303d124 BG	76	enum qca_tlv_dnld_mode {
	77	QCA_SKIP_EVT_NONE,
	78	QCA_SKIP_EVT_VSE,
	79	QCA_SKIP_EVT_CC,
	80	QCA_SKIP_EVT_VSE_CC
6e03126a LP	81	};
6e03126a LP	82
e303d124	83	enum qca_tlv_type {
83e81961	84	TLV_TYPE_PATCH = 1,
ecf6b2d9 VLNG	85	TLV_TYPE_NVM,
ecf6b2d9 VLNG	86	ELF_TYPE_PATCH,
83e81961 BYTK	87	};
83e81961 BYTK	88
e303d124	89	struct qca_fw_config {
83e81961 BYTK	90	u8 type;
	91	char fwname[64];
	92	uint8_t user_baud_rate;
e303d124 BG	93	enum qca_tlv_dnld_mode dnld_mode;
e303d124 BG	94	enum qca_tlv_dnld_mode dnld_type;
83e81961 BYTK	95	};
	96
	97	struct edl_event_hdr {
	98	__u8 cresp;
	99	__u8 rtype;
a7e45454	100	__u8 data[];
83e81961 BYTK	101	} __packed;
83e81961 BYTK	102
e303d124	103	struct qca_btsoc_version {
83e81961 BYTK	104	__le32 product_id;
83e81961 BYTK	105	__le16 patch_ver;
e303d124	106	__le16 rom_ver;
83e81961 BYTK	107	__le32 soc_id;
	108	} __packed;
	109
	110	struct tlv_seg_resp {
	111	__u8 result;
	112	} __packed;
	113
	114	struct tlv_type_patch {
	115	__le32 total_size;
	116	__le32 data_length;
	117	__u8 format_version;
	118	__u8 signature;
6e03126a LP	119	__u8 download_mode;
6e03126a LP	120	__u8 reserved1;
83e81961 BYTK	121	__le16 product_id;
	122	__le16 rom_build;
	123	__le16 patch_version;
	124	__le16 reserved2;
	125	__le32 entry;
	126	} __packed;
	127
	128	struct tlv_type_nvm {
	129	__le16 tag_id;
	130	__le16 tag_len;
	131	__le32 reserve1;
	132	__le32 reserve2;
a7e45454	133	__u8 data[];
83e81961 BYTK	134	} __packed;
	135
	136	struct tlv_type_hdr {
	137	__le32 type_len;
a7e45454	138	__u8 data[];
83e81961 BYTK	139	} __packed;
83e81961 BYTK	140
aadebac4 BG	141	enum qca_btsoc_type {
	142	QCA_INVALID = -1,
	143	QCA_AR3002,
	144	QCA_ROME,
523760b7 HB	145	QCA_WCN3990,
523760b7 HB	146	QCA_WCN3998,
e5d6468f RL	147	QCA_WCN3991,
e5d6468f RL	148	QCA_QCA6390,
d8f97da1	149	QCA_WCN6750,
aadebac4 BG	150	};
aadebac4 BG	151
83e81961 BYTK	152	#if IS_ENABLED(CONFIG_BT_QCA)
	153
	154	int qca_set_bdaddr_rome(struct hci_dev hdev, const bdaddr_t bdaddr);
aadebac4	155	int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
059924fd	156	enum qca_btsoc_type soc_type, struct qca_btsoc_version ver,
99c905c6	157	const char *firmware_name);
059924fd	158	int qca_read_soc_version(struct hci_dev hdev, struct qca_btsoc_version ver,
7d250a06	159	enum qca_btsoc_type);
5c0a1001	160	int qca_set_bdaddr(struct hci_dev hdev, const bdaddr_t bdaddr);
a2780889	161	int qca_send_pre_shutdown_cmd(struct hci_dev *hdev);
523760b7 HB	162	static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
523760b7 HB	163	{
7d250a06 BG	164	return soc_type == QCA_WCN3990 \|\| soc_type == QCA_WCN3991 \|\|
7d250a06 BG	165	soc_type == QCA_WCN3998;
523760b7	166	}
d8f97da1 VLNG	167	static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
	168	{
	169	return soc_type == QCA_WCN6750;
	170	}
	171
83e81961 BYTK	172	#else
	173
	174	static inline int qca_set_bdaddr_rome(struct hci_dev hdev, const bdaddr_t bdaddr)
	175	{
	176	return -EOPNOTSUPP;
	177	}
	178
aadebac4	179	static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
059924fd VLNG	180	enum qca_btsoc_type soc_type,
059924fd VLNG	181	struct qca_btsoc_version ver,
99c905c6	182	const char *firmware_name)
ba493d4f BG	183	{
	184	return -EOPNOTSUPP;
	185	}
	186
059924fd VLNG	187	static inline int qca_read_soc_version(struct hci_dev *hdev,
059924fd VLNG	188	struct qca_btsoc_version *ver,
7d250a06	189	enum qca_btsoc_type)
83e81961 BYTK	190	{
	191	return -EOPNOTSUPP;
	192	}
	193
5c0a1001 BG	194	static inline int qca_set_bdaddr(struct hci_dev hdev, const bdaddr_t bdaddr)
	195	{
	196	return -EOPNOTSUPP;
	197	}
	198
523760b7 HB	199	static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
	200	{
	201	return false;
	202	}
a2780889	203
d8f97da1 VLNG	204	static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
	205	{
	206	return false;
	207	}
	208
a2780889 HB	209	static inline int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
	210	{
	211	return -EOPNOTSUPP;
	212	}
83e81961	213	#endif