[linux-block.git] / drivers / bluetooth / btmrvl_sdio.h

/* SPDX-License-Identifier: GPL-2.0-only */
/**
 * Marvell BT-over-SDIO driver: SDIO interface related definitions
 *
 * Copyright (C) 2009, Marvell International Ltd.
 **/

#define SDIO_HEADER_LEN			4

/* SD block size can not bigger than 64 due to buf size limit in firmware */
/* define SD block size for data Tx/Rx */
#define SDIO_BLOCK_SIZE			64

/* Number of blocks for firmware transfer */
#define FIRMWARE_TRANSFER_NBLOCK	2

/* This is for firmware specific length */
#define FW_EXTRA_LEN			36

#define MRVDRV_SIZE_OF_CMD_BUFFER       (2 * 1024)

#define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
	(HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)

#define ALLOC_BUF_SIZE	(((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
			MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
			+ SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
			* SDIO_BLOCK_SIZE)

/* The number of times to try when polling for status */
#define MAX_POLL_TRIES			100

/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY		2

/* register bitmasks */
#define HOST_POWER_UP				BIT(1)
#define HOST_CMD53_FIN				BIT(2)

#define HIM_DISABLE				0xff
#define HIM_ENABLE				(BIT(0) | BIT(1))

#define UP_LD_HOST_INT_STATUS			BIT(0)
#define DN_LD_HOST_INT_STATUS			BIT(1)

#define DN_LD_CARD_RDY				BIT(0)
#define CARD_IO_READY				BIT(3)

#define FIRMWARE_READY				0xfedc

struct btmrvl_plt_wake_cfg {
	int irq_bt;
	bool wake_by_bt;
};

struct btmrvl_sdio_card_reg {
	u8 cfg;
	u8 host_int_mask;
	u8 host_intstatus;
	u8 card_status;
	u8 sq_read_base_addr_a0;
	u8 sq_read_base_addr_a1;
	u8 card_revision;
	u8 card_fw_status0;
	u8 card_fw_status1;
	u8 card_rx_len;
	u8 card_rx_unit;
	u8 io_port_0;
	u8 io_port_1;
	u8 io_port_2;
	bool int_read_to_clear;
	u8 host_int_rsr;
	u8 card_misc_cfg;
	u8 fw_dump_ctrl;
	u8 fw_dump_start;
	u8 fw_dump_end;
};

struct btmrvl_sdio_card {
	struct sdio_func *func;
	u32 ioport;
	const char *helper;
	const char *firmware;
	const struct btmrvl_sdio_card_reg *reg;
	bool support_pscan_win_report;
	bool supports_fw_dump;
	u16 sd_blksz_fw_dl;
	u8 rx_unit;
	struct btmrvl_private *priv;
	struct device_node *plt_of_node;
	struct btmrvl_plt_wake_cfg *plt_wake_cfg;
};

struct btmrvl_sdio_device {
	const char *helper;
	const char *firmware;
	const struct btmrvl_sdio_card_reg *reg;
	const bool support_pscan_win_report;
	u16 sd_blksz_fw_dl;
	bool supports_fw_dump;
};


/* Platform specific DMA alignment */
#define BTSDIO_DMA_ALIGN		8

/* Macros for Data Alignment : size */
#define ALIGN_SZ(p, a)	\
	(((p) + ((a) - 1)) & ~((a) - 1))

/* Macros for Data Alignment : address */
#define ALIGN_ADDR(p, a)	\
	((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \
					~(((unsigned long)(a)) - 1))
Commit	Line	Data
99c926ce	1	/* SPDX-License-Identifier: GPL-2.0-only */
789221ec BZ	2	/**
	3	* Marvell BT-over-SDIO driver: SDIO interface related definitions
	4	*
	5	* Copyright (C) 2009, Marvell International Ltd.
789221ec BZ	6	**/
789221ec BZ	7
789221ec BZ	8	#define SDIO_HEADER_LEN 4
	9
	10	/* SD block size can not bigger than 64 due to buf size limit in firmware */
	11	/* define SD block size for data Tx/Rx */
	12	#define SDIO_BLOCK_SIZE 64
	13
	14	/* Number of blocks for firmware transfer */
	15	#define FIRMWARE_TRANSFER_NBLOCK 2
	16
	17	/* This is for firmware specific length */
	18	#define FW_EXTRA_LEN 36
	19
	20	#define MRVDRV_SIZE_OF_CMD_BUFFER (2 * 1024)
	21
	22	#define MRVDRV_BT_RX_PACKET_BUFFER_SIZE \
	23	(HCI_MAX_FRAME_SIZE + FW_EXTRA_LEN)
	24
	25	#define ALLOC_BUF_SIZE (((max_t (int, MRVDRV_BT_RX_PACKET_BUFFER_SIZE, \
	26	MRVDRV_SIZE_OF_CMD_BUFFER) + SDIO_HEADER_LEN \
	27	+ SDIO_BLOCK_SIZE - 1) / SDIO_BLOCK_SIZE) \
	28	* SDIO_BLOCK_SIZE)
	29
	30	/* The number of times to try when polling for status */
	31	#define MAX_POLL_TRIES 100
	32
	33	/* Max retry number of CMD53 write */
	34	#define MAX_WRITE_IOMEM_RETRY 2
	35
9f72c1d9 KG	36	/* register bitmasks */
	37	#define HOST_POWER_UP BIT(1)
	38	#define HOST_CMD53_FIN BIT(2)
	39
	40	#define HIM_DISABLE 0xff
	41	#define HIM_ENABLE (BIT(0) \| BIT(1))
	42
	43	#define UP_LD_HOST_INT_STATUS BIT(0)
	44	#define DN_LD_HOST_INT_STATUS BIT(1)
	45
	46	#define DN_LD_CARD_RDY BIT(0)
	47	#define CARD_IO_READY BIT(3)
	48
	49	#define FIRMWARE_READY 0xfedc
	50
bb7f4f0b XH	51	struct btmrvl_plt_wake_cfg {
	52	int irq_bt;
	53	bool wake_by_bt;
	54	};
9f72c1d9 KG	55
	56	struct btmrvl_sdio_card_reg {
	57	u8 cfg;
	58	u8 host_int_mask;
	59	u8 host_intstatus;
	60	u8 card_status;
	61	u8 sq_read_base_addr_a0;
	62	u8 sq_read_base_addr_a1;
	63	u8 card_revision;
	64	u8 card_fw_status0;
	65	u8 card_fw_status1;
	66	u8 card_rx_len;
	67	u8 card_rx_unit;
	68	u8 io_port_0;
	69	u8 io_port_1;
	70	u8 io_port_2;
0d367408 BZ	71	bool int_read_to_clear;
	72	u8 host_int_rsr;
	73	u8 card_misc_cfg;
dc759613 XH	74	u8 fw_dump_ctrl;
	75	u8 fw_dump_start;
	76	u8 fw_dump_end;
9f72c1d9	77	};
789221ec BZ	78
	79	struct btmrvl_sdio_card {
	80	struct sdio_func *func;
	81	u32 ioport;
	82	const char *helper;
	83	const char *firmware;
9f72c1d9	84	const struct btmrvl_sdio_card_reg *reg;
4df82b59	85	bool support_pscan_win_report;
dc759613	86	bool supports_fw_dump;
9f72c1d9	87	u16 sd_blksz_fw_dl;
789221ec BZ	88	u8 rx_unit;
789221ec BZ	89	struct btmrvl_private *priv;
bb7f4f0b XH	90	struct device_node *plt_of_node;
bb7f4f0b XH	91	struct btmrvl_plt_wake_cfg *plt_wake_cfg;
789221ec BZ	92	};
	93
	94	struct btmrvl_sdio_device {
789221ec BZ	95	const char *helper;
789221ec BZ	96	const char *firmware;
9f72c1d9	97	const struct btmrvl_sdio_card_reg *reg;
4df82b59	98	const bool support_pscan_win_report;
9f72c1d9	99	u16 sd_blksz_fw_dl;
dc759613	100	bool supports_fw_dump;
789221ec BZ	101	};
	102
	103
	104	/* Platform specific DMA alignment */
	105	#define BTSDIO_DMA_ALIGN 8
	106
	107	/* Macros for Data Alignment : size */
	108	#define ALIGN_SZ(p, a) \
	109	(((p) + ((a) - 1)) & ~((a) - 1))
	110
	111	/* Macros for Data Alignment : address */
	112	#define ALIGN_ADDR(p, a) \
3318b236 BZ	113	((((unsigned long)(p)) + (((unsigned long)(a)) - 1)) & \
3318b236 BZ	114	~(((unsigned long)(a)) - 1))