Commit | Line | Data |
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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
48f0ed1b MH |
2 | /* |
3 | * | |
4 | * Bluetooth support for Intel devices | |
5 | * | |
6 | * Copyright (C) 2015 Intel Corporation | |
48f0ed1b MH |
7 | */ |
8 | ||
57375bee K |
9 | /* List of tlv type */ |
10 | enum { | |
11 | INTEL_TLV_CNVI_TOP = 0x10, | |
12 | INTEL_TLV_CNVR_TOP, | |
13 | INTEL_TLV_CNVI_BT, | |
14 | INTEL_TLV_CNVR_BT, | |
15 | INTEL_TLV_CNVI_OTP, | |
16 | INTEL_TLV_CNVR_OTP, | |
17 | INTEL_TLV_DEV_REV_ID, | |
18 | INTEL_TLV_USB_VENDOR_ID, | |
19 | INTEL_TLV_USB_PRODUCT_ID, | |
20 | INTEL_TLV_PCIE_VENDOR_ID, | |
21 | INTEL_TLV_PCIE_DEVICE_ID, | |
22 | INTEL_TLV_PCIE_SUBSYSTEM_ID, | |
23 | INTEL_TLV_IMAGE_TYPE, | |
24 | INTEL_TLV_TIME_STAMP, | |
25 | INTEL_TLV_BUILD_TYPE, | |
26 | INTEL_TLV_BUILD_NUM, | |
27 | INTEL_TLV_FW_BUILD_PRODUCT, | |
28 | INTEL_TLV_FW_BUILD_HW, | |
29 | INTEL_TLV_FW_STEP, | |
30 | INTEL_TLV_BT_SPEC, | |
31 | INTEL_TLV_MFG_NAME, | |
32 | INTEL_TLV_HCI_REV, | |
33 | INTEL_TLV_LMP_SUBVER, | |
34 | INTEL_TLV_OTP_PATCH_VER, | |
35 | INTEL_TLV_SECURE_BOOT, | |
36 | INTEL_TLV_KEY_FROM_HDR, | |
37 | INTEL_TLV_OTP_LOCK, | |
38 | INTEL_TLV_API_LOCK, | |
39 | INTEL_TLV_DEBUG_LOCK, | |
40 | INTEL_TLV_MIN_FW, | |
41 | INTEL_TLV_LIMITED_CCE, | |
42 | INTEL_TLV_SBE_TYPE, | |
43 | INTEL_TLV_OTP_BDADDR, | |
44 | INTEL_TLV_UNLOCKED_STATE | |
45 | }; | |
46 | ||
47 | struct intel_tlv { | |
48 | u8 type; | |
49 | u8 len; | |
4acbf554 | 50 | u8 val[]; |
57375bee K |
51 | } __packed; |
52 | ||
53 | struct intel_version_tlv { | |
54 | u32 cnvi_top; | |
55 | u32 cnvr_top; | |
56 | u32 cnvi_bt; | |
57 | u32 cnvr_bt; | |
58 | u16 dev_rev_id; | |
59 | u8 img_type; | |
60 | u16 timestamp; | |
61 | u8 build_type; | |
62 | u32 build_num; | |
63 | u8 secure_boot; | |
64 | u8 otp_lock; | |
65 | u8 api_lock; | |
66 | u8 debug_lock; | |
67 | u8 min_fw_build_nn; | |
68 | u8 min_fw_build_cw; | |
69 | u8 min_fw_build_yy; | |
70 | u8 limited_cce; | |
71 | u8 sbe_type; | |
72 | bdaddr_t otp_bd_addr; | |
73 | }; | |
74 | ||
59a077c4 MH |
75 | struct intel_version { |
76 | u8 status; | |
77 | u8 hw_platform; | |
78 | u8 hw_variant; | |
79 | u8 hw_revision; | |
80 | u8 fw_variant; | |
81 | u8 fw_revision; | |
82 | u8 fw_build_num; | |
83 | u8 fw_build_ww; | |
84 | u8 fw_build_yy; | |
85 | u8 fw_patch_num; | |
86 | } __packed; | |
87 | ||
88 | struct intel_boot_params { | |
89 | __u8 status; | |
90 | __u8 otp_format; | |
91 | __u8 otp_content; | |
92 | __u8 otp_patch; | |
93 | __le16 dev_revid; | |
94 | __u8 secure_boot; | |
95 | __u8 key_from_hdr; | |
96 | __u8 key_type; | |
97 | __u8 otp_lock; | |
98 | __u8 api_lock; | |
99 | __u8 debug_lock; | |
100 | bdaddr_t otp_bdaddr; | |
101 | __u8 min_fw_build_nn; | |
102 | __u8 min_fw_build_cw; | |
103 | __u8 min_fw_build_yy; | |
104 | __u8 limited_cce; | |
105 | __u8 unlocked_state; | |
106 | } __packed; | |
107 | ||
ccd6da2a MH |
108 | struct intel_bootup { |
109 | __u8 zero; | |
110 | __u8 num_cmds; | |
111 | __u8 source; | |
112 | __u8 reset_type; | |
113 | __u8 reset_reason; | |
114 | __u8 ddc_status; | |
115 | } __packed; | |
116 | ||
117 | struct intel_secure_send_result { | |
118 | __u8 result; | |
119 | __le16 opcode; | |
120 | __u8 status; | |
121 | } __packed; | |
122 | ||
e5889af6 THJA |
123 | struct intel_reset { |
124 | __u8 reset_type; | |
125 | __u8 patch_enable; | |
126 | __u8 ddc_reload; | |
127 | __u8 boot_option; | |
128 | __le32 boot_param; | |
129 | } __packed; | |
130 | ||
d74abe21 C |
131 | struct intel_debug_features { |
132 | __u8 page1[16]; | |
133 | } __packed; | |
134 | ||
48f0ed1b MH |
135 | #if IS_ENABLED(CONFIG_BT_INTEL) |
136 | ||
137 | int btintel_check_bdaddr(struct hci_dev *hdev); | |
28dc4b92 LP |
138 | int btintel_enter_mfg(struct hci_dev *hdev); |
139 | int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched); | |
48f0ed1b | 140 | int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); |
6d2e50d2 | 141 | int btintel_set_diag(struct hci_dev *hdev, bool enable); |
3e24767b | 142 | int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable); |
973bb97e | 143 | void btintel_hw_error(struct hci_dev *hdev, u8 code); |
48f0ed1b | 144 | |
7feb99e1 | 145 | void btintel_version_info(struct hci_dev *hdev, struct intel_version *ver); |
57375bee | 146 | void btintel_version_info_tlv(struct hci_dev *hdev, struct intel_version_tlv *version); |
09df123d MH |
147 | int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen, |
148 | const void *param); | |
145f2368 | 149 | int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name); |
213445b2 MH |
150 | int btintel_set_event_mask(struct hci_dev *hdev, bool debug); |
151 | int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug); | |
6c483de1 | 152 | int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver); |
57375bee | 153 | int btintel_read_version_tlv(struct hci_dev *hdev, struct intel_version_tlv *ver); |
09df123d | 154 | |
d06f107b LP |
155 | struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, |
156 | u16 opcode_write); | |
e5889af6 | 157 | int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param); |
faf174d2 THJA |
158 | int btintel_read_boot_params(struct hci_dev *hdev, |
159 | struct intel_boot_params *params); | |
fbbe83c5 THJA |
160 | int btintel_download_firmware(struct hci_dev *dev, const struct firmware *fw, |
161 | u32 *boot_param); | |
81ebea53 K |
162 | int btintel_download_firmware_newgen(struct hci_dev *hdev, |
163 | const struct firmware *fw, | |
164 | u32 *boot_param, u8 hw_variant, | |
165 | u8 sbe_type); | |
b9a2562f | 166 | void btintel_reset_to_bootloader(struct hci_dev *hdev); |
d74abe21 C |
167 | int btintel_read_debug_features(struct hci_dev *hdev, |
168 | struct intel_debug_features *features); | |
c453b10c C |
169 | int btintel_set_debug_features(struct hci_dev *hdev, |
170 | const struct intel_debug_features *features); | |
48f0ed1b MH |
171 | #else |
172 | ||
173 | static inline int btintel_check_bdaddr(struct hci_dev *hdev) | |
174 | { | |
175 | return -EOPNOTSUPP; | |
176 | } | |
177 | ||
28dc4b92 LP |
178 | static inline int btintel_enter_mfg(struct hci_dev *hdev) |
179 | { | |
180 | return -EOPNOTSUPP; | |
181 | } | |
182 | ||
183 | static inline int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) | |
184 | { | |
185 | return -EOPNOTSUPP; | |
186 | } | |
187 | ||
48f0ed1b MH |
188 | static inline int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) |
189 | { | |
190 | return -EOPNOTSUPP; | |
191 | } | |
192 | ||
6d2e50d2 MH |
193 | static inline int btintel_set_diag(struct hci_dev *hdev, bool enable) |
194 | { | |
195 | return -EOPNOTSUPP; | |
196 | } | |
197 | ||
3e24767b MH |
198 | static inline int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable) |
199 | { | |
200 | return -EOPNOTSUPP; | |
201 | } | |
202 | ||
973bb97e MH |
203 | static inline void btintel_hw_error(struct hci_dev *hdev, u8 code) |
204 | { | |
205 | } | |
206 | ||
0eee53cd VS |
207 | static inline void btintel_version_info(struct hci_dev *hdev, |
208 | struct intel_version *ver) | |
7feb99e1 MH |
209 | { |
210 | } | |
211 | ||
57375bee K |
212 | static inline void btintel_version_info_tlv(struct hci_dev *hdev, |
213 | struct intel_version_tlv *version) | |
214 | { | |
215 | } | |
216 | ||
09df123d MH |
217 | static inline int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, |
218 | u32 plen, const void *param) | |
219 | { | |
220 | return -EOPNOTSUPP; | |
221 | } | |
222 | ||
145f2368 LP |
223 | static inline int btintel_load_ddc_config(struct hci_dev *hdev, |
224 | const char *ddc_name) | |
225 | { | |
226 | return -EOPNOTSUPP; | |
227 | } | |
228 | ||
213445b2 MH |
229 | static inline int btintel_set_event_mask(struct hci_dev *hdev, bool debug) |
230 | { | |
231 | return -EOPNOTSUPP; | |
232 | } | |
233 | ||
234 | static inline int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) | |
235 | { | |
236 | return -EOPNOTSUPP; | |
237 | } | |
238 | ||
6c483de1 LP |
239 | static inline int btintel_read_version(struct hci_dev *hdev, |
240 | struct intel_version *ver) | |
241 | { | |
242 | return -EOPNOTSUPP; | |
243 | } | |
244 | ||
57375bee K |
245 | static inline int btintel_read_version_tlv(struct hci_dev *hdev, |
246 | struct intel_version_tlv *ver) | |
247 | { | |
248 | return -EOPNOTSUPP; | |
249 | } | |
250 | ||
d06f107b LP |
251 | static inline struct regmap *btintel_regmap_init(struct hci_dev *hdev, |
252 | u16 opcode_read, | |
253 | u16 opcode_write) | |
254 | { | |
255 | return ERR_PTR(-EINVAL); | |
256 | } | |
e5889af6 THJA |
257 | |
258 | static inline int btintel_send_intel_reset(struct hci_dev *hdev, | |
259 | u32 reset_param) | |
260 | { | |
261 | return -EOPNOTSUPP; | |
262 | } | |
faf174d2 THJA |
263 | |
264 | static inline int btintel_read_boot_params(struct hci_dev *hdev, | |
265 | struct intel_boot_params *params) | |
266 | { | |
267 | return -EOPNOTSUPP; | |
268 | } | |
fbbe83c5 THJA |
269 | |
270 | static inline int btintel_download_firmware(struct hci_dev *dev, | |
271 | const struct firmware *fw, | |
272 | u32 *boot_param) | |
273 | { | |
274 | return -EOPNOTSUPP; | |
275 | } | |
b9a2562f | 276 | |
81ebea53 K |
277 | static inline int btintel_download_firmware_newgen(struct hci_dev *hdev, |
278 | const struct firmware *fw, | |
279 | u32 *boot_param, | |
280 | u8 hw_variant, u8 sbe_type) | |
281 | { | |
282 | return -EOPNOTSUPP; | |
283 | } | |
284 | ||
b9a2562f AB |
285 | static inline void btintel_reset_to_bootloader(struct hci_dev *hdev) |
286 | { | |
b9a2562f | 287 | } |
d74abe21 C |
288 | |
289 | static inline int btintel_read_debug_features(struct hci_dev *hdev, | |
290 | struct intel_debug_features *features) | |
291 | { | |
292 | return -EOPNOTSUPP; | |
293 | } | |
294 | ||
c453b10c C |
295 | static inline int btintel_set_debug_features(struct hci_dev *hdev, |
296 | const struct intel_debug_features *features) | |
297 | { | |
298 | return -EOPNOTSUPP; | |
299 | } | |
300 | ||
48f0ed1b | 301 | #endif |