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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
48f0ed1b MH |
2 | /* |
3 | * | |
4 | * Bluetooth support for Intel devices | |
5 | * | |
6 | * Copyright (C) 2015 Intel Corporation | |
48f0ed1b MH |
7 | */ |
8 | ||
57375bee K |
9 | /* List of tlv type */ |
10 | enum { | |
11 | INTEL_TLV_CNVI_TOP = 0x10, | |
12 | INTEL_TLV_CNVR_TOP, | |
13 | INTEL_TLV_CNVI_BT, | |
14 | INTEL_TLV_CNVR_BT, | |
15 | INTEL_TLV_CNVI_OTP, | |
16 | INTEL_TLV_CNVR_OTP, | |
17 | INTEL_TLV_DEV_REV_ID, | |
18 | INTEL_TLV_USB_VENDOR_ID, | |
19 | INTEL_TLV_USB_PRODUCT_ID, | |
20 | INTEL_TLV_PCIE_VENDOR_ID, | |
21 | INTEL_TLV_PCIE_DEVICE_ID, | |
22 | INTEL_TLV_PCIE_SUBSYSTEM_ID, | |
23 | INTEL_TLV_IMAGE_TYPE, | |
24 | INTEL_TLV_TIME_STAMP, | |
25 | INTEL_TLV_BUILD_TYPE, | |
26 | INTEL_TLV_BUILD_NUM, | |
27 | INTEL_TLV_FW_BUILD_PRODUCT, | |
28 | INTEL_TLV_FW_BUILD_HW, | |
29 | INTEL_TLV_FW_STEP, | |
30 | INTEL_TLV_BT_SPEC, | |
31 | INTEL_TLV_MFG_NAME, | |
32 | INTEL_TLV_HCI_REV, | |
33 | INTEL_TLV_LMP_SUBVER, | |
34 | INTEL_TLV_OTP_PATCH_VER, | |
35 | INTEL_TLV_SECURE_BOOT, | |
36 | INTEL_TLV_KEY_FROM_HDR, | |
37 | INTEL_TLV_OTP_LOCK, | |
38 | INTEL_TLV_API_LOCK, | |
39 | INTEL_TLV_DEBUG_LOCK, | |
40 | INTEL_TLV_MIN_FW, | |
41 | INTEL_TLV_LIMITED_CCE, | |
42 | INTEL_TLV_SBE_TYPE, | |
43 | INTEL_TLV_OTP_BDADDR, | |
a2e7707b K |
44 | INTEL_TLV_UNLOCKED_STATE, |
45 | INTEL_TLV_GIT_SHA1 | |
57375bee K |
46 | }; |
47 | ||
48 | struct intel_tlv { | |
49 | u8 type; | |
50 | u8 len; | |
4acbf554 | 51 | u8 val[]; |
57375bee K |
52 | } __packed; |
53 | ||
54 | struct intel_version_tlv { | |
55 | u32 cnvi_top; | |
56 | u32 cnvr_top; | |
57 | u32 cnvi_bt; | |
58 | u32 cnvr_bt; | |
59 | u16 dev_rev_id; | |
60 | u8 img_type; | |
61 | u16 timestamp; | |
62 | u8 build_type; | |
63 | u32 build_num; | |
64 | u8 secure_boot; | |
65 | u8 otp_lock; | |
66 | u8 api_lock; | |
67 | u8 debug_lock; | |
68 | u8 min_fw_build_nn; | |
69 | u8 min_fw_build_cw; | |
70 | u8 min_fw_build_yy; | |
71 | u8 limited_cce; | |
72 | u8 sbe_type; | |
a2e7707b | 73 | u32 git_sha1; |
57375bee K |
74 | bdaddr_t otp_bd_addr; |
75 | }; | |
76 | ||
59a077c4 MH |
77 | struct intel_version { |
78 | u8 status; | |
79 | u8 hw_platform; | |
80 | u8 hw_variant; | |
81 | u8 hw_revision; | |
82 | u8 fw_variant; | |
83 | u8 fw_revision; | |
84 | u8 fw_build_num; | |
85 | u8 fw_build_ww; | |
86 | u8 fw_build_yy; | |
87 | u8 fw_patch_num; | |
88 | } __packed; | |
89 | ||
90 | struct intel_boot_params { | |
91 | __u8 status; | |
92 | __u8 otp_format; | |
93 | __u8 otp_content; | |
94 | __u8 otp_patch; | |
95 | __le16 dev_revid; | |
96 | __u8 secure_boot; | |
97 | __u8 key_from_hdr; | |
98 | __u8 key_type; | |
99 | __u8 otp_lock; | |
100 | __u8 api_lock; | |
101 | __u8 debug_lock; | |
102 | bdaddr_t otp_bdaddr; | |
103 | __u8 min_fw_build_nn; | |
104 | __u8 min_fw_build_cw; | |
105 | __u8 min_fw_build_yy; | |
106 | __u8 limited_cce; | |
107 | __u8 unlocked_state; | |
108 | } __packed; | |
109 | ||
ccd6da2a MH |
110 | struct intel_bootup { |
111 | __u8 zero; | |
112 | __u8 num_cmds; | |
113 | __u8 source; | |
114 | __u8 reset_type; | |
115 | __u8 reset_reason; | |
116 | __u8 ddc_status; | |
117 | } __packed; | |
118 | ||
119 | struct intel_secure_send_result { | |
120 | __u8 result; | |
121 | __le16 opcode; | |
122 | __u8 status; | |
123 | } __packed; | |
124 | ||
e5889af6 THJA |
125 | struct intel_reset { |
126 | __u8 reset_type; | |
127 | __u8 patch_enable; | |
128 | __u8 ddc_reload; | |
129 | __u8 boot_option; | |
130 | __le32 boot_param; | |
131 | } __packed; | |
132 | ||
d74abe21 C |
133 | struct intel_debug_features { |
134 | __u8 page1[16]; | |
135 | } __packed; | |
136 | ||
a358ef86 K |
137 | struct intel_offload_use_cases { |
138 | __u8 status; | |
139 | __u8 preset[8]; | |
140 | } __packed; | |
141 | ||
7866b9fa LS |
142 | #define INTEL_OP_PPAG_CMD 0xFE0B |
143 | struct hci_ppag_enable_cmd { | |
144 | __le32 ppag_enable_flags; | |
c585a92b SS |
145 | } __packed; |
146 | ||
af395330 APS |
147 | #define INTEL_TLV_TYPE_ID 0x01 |
148 | ||
149 | #define INTEL_TLV_SYSTEM_EXCEPTION 0x00 | |
150 | #define INTEL_TLV_FATAL_EXCEPTION 0x01 | |
151 | #define INTEL_TLV_DEBUG_EXCEPTION 0x02 | |
152 | #define INTEL_TLV_TEST_EXCEPTION 0xDE | |
153 | ||
9a93b8b8 K |
154 | #define INTEL_HW_PLATFORM(cnvx_bt) ((u8)(((cnvx_bt) & 0x0000ff00) >> 8)) |
155 | #define INTEL_HW_VARIANT(cnvx_bt) ((u8)(((cnvx_bt) & 0x003f0000) >> 16)) | |
156 | #define INTEL_CNVX_TOP_TYPE(cnvx_top) ((cnvx_top) & 0x00000fff) | |
157 | #define INTEL_CNVX_TOP_STEP(cnvx_top) (((cnvx_top) & 0x0f000000) >> 24) | |
158 | #define INTEL_CNVX_TOP_PACK_SWAB(t, s) __swab16(((__u16)(((t) << 4) | (s)))) | |
159 | ||
53492a66 THJA |
160 | enum { |
161 | INTEL_BOOTLOADER, | |
162 | INTEL_DOWNLOADING, | |
163 | INTEL_FIRMWARE_LOADED, | |
164 | INTEL_FIRMWARE_FAILED, | |
165 | INTEL_BOOTING, | |
ea7c4c0e | 166 | INTEL_BROKEN_INITIAL_NCMD, |
95655456 | 167 | INTEL_BROKEN_SHUTDOWN_LED, |
55380714 | 168 | INTEL_ROM_LEGACY, |
55235304 | 169 | INTEL_ROM_LEGACY_NO_WBS_SUPPORT, |
8f0a3786 | 170 | INTEL_ACPI_RESET_ACTIVE, |
53492a66 THJA |
171 | |
172 | __INTEL_NUM_FLAGS, | |
173 | }; | |
174 | ||
175 | struct btintel_data { | |
176 | DECLARE_BITMAP(flags, __INTEL_NUM_FLAGS); | |
8f0a3786 | 177 | int (*acpi_reset_method)(struct hci_dev *hdev); |
53492a66 THJA |
178 | }; |
179 | ||
180 | #define btintel_set_flag(hdev, nr) \ | |
181 | do { \ | |
182 | struct btintel_data *intel = hci_get_priv((hdev)); \ | |
183 | set_bit((nr), intel->flags); \ | |
184 | } while (0) | |
185 | ||
186 | #define btintel_clear_flag(hdev, nr) \ | |
187 | do { \ | |
188 | struct btintel_data *intel = hci_get_priv((hdev)); \ | |
189 | clear_bit((nr), intel->flags); \ | |
190 | } while (0) | |
191 | ||
192 | #define btintel_wake_up_flag(hdev, nr) \ | |
193 | do { \ | |
194 | struct btintel_data *intel = hci_get_priv((hdev)); \ | |
195 | wake_up_bit(intel->flags, (nr)); \ | |
196 | } while (0) | |
197 | ||
198 | #define btintel_get_flag(hdev) \ | |
199 | (((struct btintel_data *)hci_get_priv(hdev))->flags) | |
200 | ||
201 | #define btintel_test_flag(hdev, nr) test_bit((nr), btintel_get_flag(hdev)) | |
202 | #define btintel_test_and_clear_flag(hdev, nr) test_and_clear_bit((nr), btintel_get_flag(hdev)) | |
203 | #define btintel_wait_on_flag_timeout(hdev, nr, m, to) \ | |
204 | wait_on_bit_timeout(btintel_get_flag(hdev), (nr), m, to) | |
205 | ||
48f0ed1b MH |
206 | #if IS_ENABLED(CONFIG_BT_INTEL) |
207 | ||
208 | int btintel_check_bdaddr(struct hci_dev *hdev); | |
28dc4b92 LP |
209 | int btintel_enter_mfg(struct hci_dev *hdev); |
210 | int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched); | |
48f0ed1b | 211 | int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); |
6d2e50d2 | 212 | int btintel_set_diag(struct hci_dev *hdev, bool enable); |
48f0ed1b | 213 | |
d68903da | 214 | int btintel_version_info(struct hci_dev *hdev, struct intel_version *ver); |
145f2368 | 215 | int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name); |
213445b2 | 216 | int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug); |
6c483de1 | 217 | int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver); |
d06f107b LP |
218 | struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, |
219 | u16 opcode_write); | |
e5889af6 | 220 | int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param); |
faf174d2 THJA |
221 | int btintel_read_boot_params(struct hci_dev *hdev, |
222 | struct intel_boot_params *params); | |
ac056546 LAD |
223 | int btintel_download_firmware(struct hci_dev *dev, struct intel_version *ver, |
224 | const struct firmware *fw, u32 *boot_param); | |
af395330 | 225 | int btintel_configure_setup(struct hci_dev *hdev, const char *driver_name); |
123c2631 | 226 | int btintel_recv_event(struct hci_dev *hdev, struct sk_buff *skb); |
019a1caa THJA |
227 | void btintel_bootup(struct hci_dev *hdev, const void *ptr, unsigned int len); |
228 | void btintel_secure_send_result(struct hci_dev *hdev, | |
229 | const void *ptr, unsigned int len); | |
927ac8da | 230 | int btintel_set_quality_report(struct hci_dev *hdev, bool enable); |
48f0ed1b MH |
231 | #else |
232 | ||
233 | static inline int btintel_check_bdaddr(struct hci_dev *hdev) | |
234 | { | |
235 | return -EOPNOTSUPP; | |
236 | } | |
237 | ||
28dc4b92 LP |
238 | static inline int btintel_enter_mfg(struct hci_dev *hdev) |
239 | { | |
240 | return -EOPNOTSUPP; | |
241 | } | |
242 | ||
243 | static inline int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) | |
244 | { | |
245 | return -EOPNOTSUPP; | |
246 | } | |
247 | ||
48f0ed1b MH |
248 | static inline int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) |
249 | { | |
250 | return -EOPNOTSUPP; | |
251 | } | |
252 | ||
6d2e50d2 MH |
253 | static inline int btintel_set_diag(struct hci_dev *hdev, bool enable) |
254 | { | |
255 | return -EOPNOTSUPP; | |
256 | } | |
257 | ||
d68903da LAD |
258 | static inline int btintel_version_info(struct hci_dev *hdev, |
259 | struct intel_version *ver) | |
7feb99e1 | 260 | { |
d68903da | 261 | return -EOPNOTSUPP; |
7feb99e1 MH |
262 | } |
263 | ||
145f2368 LP |
264 | static inline int btintel_load_ddc_config(struct hci_dev *hdev, |
265 | const char *ddc_name) | |
266 | { | |
267 | return -EOPNOTSUPP; | |
268 | } | |
269 | ||
213445b2 MH |
270 | static inline int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) |
271 | { | |
272 | return -EOPNOTSUPP; | |
273 | } | |
274 | ||
6c483de1 LP |
275 | static inline int btintel_read_version(struct hci_dev *hdev, |
276 | struct intel_version *ver) | |
277 | { | |
278 | return -EOPNOTSUPP; | |
279 | } | |
280 | ||
d06f107b LP |
281 | static inline struct regmap *btintel_regmap_init(struct hci_dev *hdev, |
282 | u16 opcode_read, | |
283 | u16 opcode_write) | |
284 | { | |
285 | return ERR_PTR(-EINVAL); | |
286 | } | |
e5889af6 THJA |
287 | |
288 | static inline int btintel_send_intel_reset(struct hci_dev *hdev, | |
289 | u32 reset_param) | |
290 | { | |
291 | return -EOPNOTSUPP; | |
292 | } | |
faf174d2 THJA |
293 | |
294 | static inline int btintel_read_boot_params(struct hci_dev *hdev, | |
295 | struct intel_boot_params *params) | |
296 | { | |
297 | return -EOPNOTSUPP; | |
298 | } | |
fbbe83c5 THJA |
299 | |
300 | static inline int btintel_download_firmware(struct hci_dev *dev, | |
301 | const struct firmware *fw, | |
302 | u32 *boot_param) | |
303 | { | |
304 | return -EOPNOTSUPP; | |
305 | } | |
b9a2562f | 306 | |
af395330 APS |
307 | static inline int btintel_configure_setup(struct hci_dev *hdev, |
308 | const char *driver_name) | |
ca5425e1 THJA |
309 | { |
310 | return -ENODEV; | |
311 | } | |
312 | ||
019a1caa THJA |
313 | static inline void btintel_bootup(struct hci_dev *hdev, |
314 | const void *ptr, unsigned int len) | |
315 | { | |
316 | } | |
317 | ||
318 | static inline void btintel_secure_send_result(struct hci_dev *hdev, | |
319 | const void *ptr, unsigned int len) | |
320 | { | |
321 | } | |
927ac8da JH |
322 | |
323 | static inline int btintel_set_quality_report(struct hci_dev *hdev, bool enable) | |
324 | { | |
325 | return -ENODEV; | |
326 | } | |
48f0ed1b | 327 | #endif |