Commit | Line | Data |
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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
48f0ed1b MH |
2 | /* |
3 | * | |
4 | * Bluetooth support for Intel devices | |
5 | * | |
6 | * Copyright (C) 2015 Intel Corporation | |
48f0ed1b MH |
7 | */ |
8 | ||
9 | #include <linux/module.h> | |
145f2368 | 10 | #include <linux/firmware.h> |
d06f107b | 11 | #include <linux/regmap.h> |
fbbe83c5 | 12 | #include <asm/unaligned.h> |
48f0ed1b MH |
13 | |
14 | #include <net/bluetooth/bluetooth.h> | |
15 | #include <net/bluetooth/hci_core.h> | |
16 | ||
17 | #include "btintel.h" | |
18 | ||
19 | #define VERSION "0.1" | |
20 | ||
81ebea53 K |
21 | #define BDADDR_INTEL (&(bdaddr_t){{0x00, 0x8b, 0x9e, 0x19, 0x03, 0x00}}) |
22 | #define RSA_HEADER_LEN 644 | |
23 | #define CSS_HEADER_OFFSET 8 | |
24 | #define ECDSA_OFFSET 644 | |
25 | #define ECDSA_HEADER_LEN 320 | |
48f0ed1b | 26 | |
ac056546 LAD |
27 | #define CMD_WRITE_BOOT_PARAMS 0xfc0e |
28 | struct cmd_write_boot_params { | |
29 | u32 boot_addr; | |
30 | u8 fw_build_num; | |
31 | u8 fw_build_ww; | |
32 | u8 fw_build_yy; | |
33 | } __packed; | |
34 | ||
48f0ed1b MH |
35 | int btintel_check_bdaddr(struct hci_dev *hdev) |
36 | { | |
37 | struct hci_rp_read_bd_addr *bda; | |
38 | struct sk_buff *skb; | |
39 | ||
40 | skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL, | |
41 | HCI_INIT_TIMEOUT); | |
42 | if (IS_ERR(skb)) { | |
43 | int err = PTR_ERR(skb); | |
2064ee33 MH |
44 | bt_dev_err(hdev, "Reading Intel device address failed (%d)", |
45 | err); | |
48f0ed1b MH |
46 | return err; |
47 | } | |
48 | ||
49 | if (skb->len != sizeof(*bda)) { | |
2064ee33 | 50 | bt_dev_err(hdev, "Intel device address length mismatch"); |
48f0ed1b MH |
51 | kfree_skb(skb); |
52 | return -EIO; | |
53 | } | |
54 | ||
55 | bda = (struct hci_rp_read_bd_addr *)skb->data; | |
48f0ed1b MH |
56 | |
57 | /* For some Intel based controllers, the default Bluetooth device | |
58 | * address 00:03:19:9E:8B:00 can be found. These controllers are | |
59 | * fully operational, but have the danger of duplicate addresses | |
60 | * and that in turn can cause problems with Bluetooth operation. | |
61 | */ | |
62 | if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) { | |
2064ee33 MH |
63 | bt_dev_err(hdev, "Found Intel default device address (%pMR)", |
64 | &bda->bdaddr); | |
48f0ed1b MH |
65 | set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks); |
66 | } | |
67 | ||
68 | kfree_skb(skb); | |
69 | ||
70 | return 0; | |
71 | } | |
72 | EXPORT_SYMBOL_GPL(btintel_check_bdaddr); | |
73 | ||
28dc4b92 LP |
74 | int btintel_enter_mfg(struct hci_dev *hdev) |
75 | { | |
948c7ca0 | 76 | static const u8 param[] = { 0x01, 0x00 }; |
28dc4b92 LP |
77 | struct sk_buff *skb; |
78 | ||
79 | skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT); | |
80 | if (IS_ERR(skb)) { | |
81 | bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)", | |
82 | PTR_ERR(skb)); | |
83 | return PTR_ERR(skb); | |
84 | } | |
85 | kfree_skb(skb); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | EXPORT_SYMBOL_GPL(btintel_enter_mfg); | |
90 | ||
91 | int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) | |
92 | { | |
93 | u8 param[] = { 0x00, 0x00 }; | |
94 | struct sk_buff *skb; | |
95 | ||
96 | /* The 2nd command parameter specifies the manufacturing exit method: | |
97 | * 0x00: Just disable the manufacturing mode (0x00). | |
98 | * 0x01: Disable manufacturing mode and reset with patches deactivated. | |
99 | * 0x02: Disable manufacturing mode and reset with patches activated. | |
100 | */ | |
101 | if (reset) | |
102 | param[1] |= patched ? 0x02 : 0x01; | |
103 | ||
104 | skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT); | |
105 | if (IS_ERR(skb)) { | |
106 | bt_dev_err(hdev, "Exiting manufacturer mode failed (%ld)", | |
107 | PTR_ERR(skb)); | |
108 | return PTR_ERR(skb); | |
109 | } | |
110 | kfree_skb(skb); | |
111 | ||
112 | return 0; | |
113 | } | |
114 | EXPORT_SYMBOL_GPL(btintel_exit_mfg); | |
115 | ||
48f0ed1b MH |
116 | int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) |
117 | { | |
118 | struct sk_buff *skb; | |
119 | int err; | |
120 | ||
121 | skb = __hci_cmd_sync(hdev, 0xfc31, 6, bdaddr, HCI_INIT_TIMEOUT); | |
122 | if (IS_ERR(skb)) { | |
123 | err = PTR_ERR(skb); | |
2064ee33 MH |
124 | bt_dev_err(hdev, "Changing Intel device address failed (%d)", |
125 | err); | |
48f0ed1b MH |
126 | return err; |
127 | } | |
128 | kfree_skb(skb); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | EXPORT_SYMBOL_GPL(btintel_set_bdaddr); | |
133 | ||
6d2e50d2 MH |
134 | int btintel_set_diag(struct hci_dev *hdev, bool enable) |
135 | { | |
136 | struct sk_buff *skb; | |
137 | u8 param[3]; | |
138 | int err; | |
139 | ||
6d2e50d2 MH |
140 | if (enable) { |
141 | param[0] = 0x03; | |
142 | param[1] = 0x03; | |
143 | param[2] = 0x03; | |
144 | } else { | |
145 | param[0] = 0x00; | |
146 | param[1] = 0x00; | |
147 | param[2] = 0x00; | |
148 | } | |
149 | ||
150 | skb = __hci_cmd_sync(hdev, 0xfc43, 3, param, HCI_INIT_TIMEOUT); | |
151 | if (IS_ERR(skb)) { | |
152 | err = PTR_ERR(skb); | |
d8270fbb | 153 | if (err == -ENODATA) |
213445b2 | 154 | goto done; |
2064ee33 MH |
155 | bt_dev_err(hdev, "Changing Intel diagnostic mode failed (%d)", |
156 | err); | |
6d2e50d2 MH |
157 | return err; |
158 | } | |
159 | kfree_skb(skb); | |
160 | ||
213445b2 MH |
161 | done: |
162 | btintel_set_event_mask(hdev, enable); | |
6d2e50d2 MH |
163 | return 0; |
164 | } | |
165 | EXPORT_SYMBOL_GPL(btintel_set_diag); | |
166 | ||
3e24767b MH |
167 | int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable) |
168 | { | |
28dc4b92 | 169 | int err, ret; |
3e24767b | 170 | |
28dc4b92 LP |
171 | err = btintel_enter_mfg(hdev); |
172 | if (err) | |
173 | return err; | |
3e24767b | 174 | |
28dc4b92 | 175 | ret = btintel_set_diag(hdev, enable); |
3e24767b | 176 | |
28dc4b92 LP |
177 | err = btintel_exit_mfg(hdev, false, false); |
178 | if (err) | |
179 | return err; | |
3e24767b | 180 | |
28dc4b92 | 181 | return ret; |
3e24767b MH |
182 | } |
183 | EXPORT_SYMBOL_GPL(btintel_set_diag_mfg); | |
184 | ||
973bb97e MH |
185 | void btintel_hw_error(struct hci_dev *hdev, u8 code) |
186 | { | |
187 | struct sk_buff *skb; | |
188 | u8 type = 0x00; | |
189 | ||
2064ee33 | 190 | bt_dev_err(hdev, "Hardware error 0x%2.2x", code); |
973bb97e MH |
191 | |
192 | skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT); | |
193 | if (IS_ERR(skb)) { | |
2064ee33 MH |
194 | bt_dev_err(hdev, "Reset after hardware error failed (%ld)", |
195 | PTR_ERR(skb)); | |
973bb97e MH |
196 | return; |
197 | } | |
198 | kfree_skb(skb); | |
199 | ||
200 | skb = __hci_cmd_sync(hdev, 0xfc22, 1, &type, HCI_INIT_TIMEOUT); | |
201 | if (IS_ERR(skb)) { | |
2064ee33 MH |
202 | bt_dev_err(hdev, "Retrieving Intel exception info failed (%ld)", |
203 | PTR_ERR(skb)); | |
973bb97e MH |
204 | return; |
205 | } | |
206 | ||
207 | if (skb->len != 13) { | |
2064ee33 | 208 | bt_dev_err(hdev, "Exception info size mismatch"); |
973bb97e MH |
209 | kfree_skb(skb); |
210 | return; | |
211 | } | |
212 | ||
2064ee33 | 213 | bt_dev_err(hdev, "Exception info %s", (char *)(skb->data + 1)); |
973bb97e MH |
214 | |
215 | kfree_skb(skb); | |
216 | } | |
217 | EXPORT_SYMBOL_GPL(btintel_hw_error); | |
218 | ||
7feb99e1 MH |
219 | void btintel_version_info(struct hci_dev *hdev, struct intel_version *ver) |
220 | { | |
221 | const char *variant; | |
222 | ||
223 | switch (ver->fw_variant) { | |
224 | case 0x06: | |
225 | variant = "Bootloader"; | |
226 | break; | |
227 | case 0x23: | |
228 | variant = "Firmware"; | |
229 | break; | |
230 | default: | |
231 | return; | |
232 | } | |
233 | ||
2064ee33 MH |
234 | bt_dev_info(hdev, "%s revision %u.%u build %u week %u %u", |
235 | variant, ver->fw_revision >> 4, ver->fw_revision & 0x0f, | |
236 | ver->fw_build_num, ver->fw_build_ww, | |
237 | 2000 + ver->fw_build_yy); | |
7feb99e1 MH |
238 | } |
239 | EXPORT_SYMBOL_GPL(btintel_version_info); | |
240 | ||
09df123d MH |
241 | int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen, |
242 | const void *param) | |
243 | { | |
244 | while (plen > 0) { | |
245 | struct sk_buff *skb; | |
246 | u8 cmd_param[253], fragment_len = (plen > 252) ? 252 : plen; | |
247 | ||
248 | cmd_param[0] = fragment_type; | |
249 | memcpy(cmd_param + 1, param, fragment_len); | |
250 | ||
251 | skb = __hci_cmd_sync(hdev, 0xfc09, fragment_len + 1, | |
252 | cmd_param, HCI_INIT_TIMEOUT); | |
253 | if (IS_ERR(skb)) | |
254 | return PTR_ERR(skb); | |
255 | ||
256 | kfree_skb(skb); | |
257 | ||
258 | plen -= fragment_len; | |
259 | param += fragment_len; | |
260 | } | |
261 | ||
262 | return 0; | |
263 | } | |
264 | EXPORT_SYMBOL_GPL(btintel_secure_send); | |
265 | ||
145f2368 LP |
266 | int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name) |
267 | { | |
268 | const struct firmware *fw; | |
269 | struct sk_buff *skb; | |
270 | const u8 *fw_ptr; | |
271 | int err; | |
272 | ||
273 | err = request_firmware_direct(&fw, ddc_name, &hdev->dev); | |
274 | if (err < 0) { | |
275 | bt_dev_err(hdev, "Failed to load Intel DDC file %s (%d)", | |
276 | ddc_name, err); | |
277 | return err; | |
278 | } | |
279 | ||
280 | bt_dev_info(hdev, "Found Intel DDC parameters: %s", ddc_name); | |
281 | ||
282 | fw_ptr = fw->data; | |
283 | ||
284 | /* DDC file contains one or more DDC structure which has | |
285 | * Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2). | |
286 | */ | |
287 | while (fw->size > fw_ptr - fw->data) { | |
288 | u8 cmd_plen = fw_ptr[0] + sizeof(u8); | |
289 | ||
290 | skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr, | |
291 | HCI_INIT_TIMEOUT); | |
292 | if (IS_ERR(skb)) { | |
293 | bt_dev_err(hdev, "Failed to send Intel_Write_DDC (%ld)", | |
294 | PTR_ERR(skb)); | |
295 | release_firmware(fw); | |
296 | return PTR_ERR(skb); | |
297 | } | |
298 | ||
299 | fw_ptr += cmd_plen; | |
300 | kfree_skb(skb); | |
301 | } | |
302 | ||
303 | release_firmware(fw); | |
304 | ||
305 | bt_dev_info(hdev, "Applying Intel DDC parameters completed"); | |
306 | ||
307 | return 0; | |
308 | } | |
309 | EXPORT_SYMBOL_GPL(btintel_load_ddc_config); | |
310 | ||
213445b2 MH |
311 | int btintel_set_event_mask(struct hci_dev *hdev, bool debug) |
312 | { | |
313 | u8 mask[8] = { 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; | |
314 | struct sk_buff *skb; | |
315 | int err; | |
316 | ||
317 | if (debug) | |
318 | mask[1] |= 0x62; | |
319 | ||
320 | skb = __hci_cmd_sync(hdev, 0xfc52, 8, mask, HCI_INIT_TIMEOUT); | |
321 | if (IS_ERR(skb)) { | |
322 | err = PTR_ERR(skb); | |
2064ee33 | 323 | bt_dev_err(hdev, "Setting Intel event mask failed (%d)", err); |
213445b2 MH |
324 | return err; |
325 | } | |
326 | kfree_skb(skb); | |
327 | ||
328 | return 0; | |
329 | } | |
330 | EXPORT_SYMBOL_GPL(btintel_set_event_mask); | |
331 | ||
332 | int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) | |
333 | { | |
28dc4b92 | 334 | int err, ret; |
213445b2 | 335 | |
28dc4b92 LP |
336 | err = btintel_enter_mfg(hdev); |
337 | if (err) | |
338 | return err; | |
213445b2 | 339 | |
28dc4b92 | 340 | ret = btintel_set_event_mask(hdev, debug); |
213445b2 | 341 | |
28dc4b92 LP |
342 | err = btintel_exit_mfg(hdev, false, false); |
343 | if (err) | |
344 | return err; | |
213445b2 | 345 | |
28dc4b92 | 346 | return ret; |
213445b2 MH |
347 | } |
348 | EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg); | |
349 | ||
6c483de1 LP |
350 | int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver) |
351 | { | |
352 | struct sk_buff *skb; | |
353 | ||
354 | skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT); | |
355 | if (IS_ERR(skb)) { | |
356 | bt_dev_err(hdev, "Reading Intel version information failed (%ld)", | |
357 | PTR_ERR(skb)); | |
358 | return PTR_ERR(skb); | |
359 | } | |
360 | ||
361 | if (skb->len != sizeof(*ver)) { | |
362 | bt_dev_err(hdev, "Intel version event size mismatch"); | |
363 | kfree_skb(skb); | |
364 | return -EILSEQ; | |
365 | } | |
366 | ||
367 | memcpy(ver, skb->data, sizeof(*ver)); | |
368 | ||
369 | kfree_skb(skb); | |
370 | ||
371 | return 0; | |
372 | } | |
373 | EXPORT_SYMBOL_GPL(btintel_read_version); | |
374 | ||
57375bee K |
375 | void btintel_version_info_tlv(struct hci_dev *hdev, struct intel_version_tlv *version) |
376 | { | |
377 | const char *variant; | |
378 | ||
379 | switch (version->img_type) { | |
380 | case 0x01: | |
381 | variant = "Bootloader"; | |
382 | bt_dev_info(hdev, "Device revision is %u", version->dev_rev_id); | |
383 | bt_dev_info(hdev, "Secure boot is %s", | |
384 | version->secure_boot ? "enabled" : "disabled"); | |
385 | bt_dev_info(hdev, "OTP lock is %s", | |
386 | version->otp_lock ? "enabled" : "disabled"); | |
387 | bt_dev_info(hdev, "API lock is %s", | |
388 | version->api_lock ? "enabled" : "disabled"); | |
389 | bt_dev_info(hdev, "Debug lock is %s", | |
390 | version->debug_lock ? "enabled" : "disabled"); | |
391 | bt_dev_info(hdev, "Minimum firmware build %u week %u %u", | |
392 | version->min_fw_build_nn, version->min_fw_build_cw, | |
393 | 2000 + version->min_fw_build_yy); | |
394 | break; | |
395 | case 0x03: | |
396 | variant = "Firmware"; | |
397 | break; | |
398 | default: | |
399 | bt_dev_err(hdev, "Unsupported image type(%02x)", version->img_type); | |
400 | goto done; | |
401 | } | |
402 | ||
403 | bt_dev_info(hdev, "%s timestamp %u.%u buildtype %u build %u", variant, | |
404 | 2000 + (version->timestamp >> 8), version->timestamp & 0xff, | |
405 | version->build_type, version->build_num); | |
406 | ||
407 | done: | |
408 | return; | |
409 | } | |
410 | EXPORT_SYMBOL_GPL(btintel_version_info_tlv); | |
411 | ||
412 | int btintel_read_version_tlv(struct hci_dev *hdev, struct intel_version_tlv *version) | |
413 | { | |
414 | struct sk_buff *skb; | |
415 | const u8 param[1] = { 0xFF }; | |
416 | ||
417 | if (!version) | |
418 | return -EINVAL; | |
419 | ||
420 | skb = __hci_cmd_sync(hdev, 0xfc05, 1, param, HCI_CMD_TIMEOUT); | |
421 | if (IS_ERR(skb)) { | |
422 | bt_dev_err(hdev, "Reading Intel version information failed (%ld)", | |
423 | PTR_ERR(skb)); | |
424 | return PTR_ERR(skb); | |
425 | } | |
426 | ||
427 | if (skb->data[0]) { | |
428 | bt_dev_err(hdev, "Intel Read Version command failed (%02x)", | |
429 | skb->data[0]); | |
430 | kfree_skb(skb); | |
431 | return -EIO; | |
432 | } | |
433 | ||
434 | /* Consume Command Complete Status field */ | |
435 | skb_pull(skb, 1); | |
436 | ||
437 | /* Event parameters contatin multiple TLVs. Read each of them | |
438 | * and only keep the required data. Also, it use existing legacy | |
439 | * version field like hw_platform, hw_variant, and fw_variant | |
440 | * to keep the existing setup flow | |
441 | */ | |
442 | while (skb->len) { | |
443 | struct intel_tlv *tlv; | |
444 | ||
445 | tlv = (struct intel_tlv *)skb->data; | |
446 | switch (tlv->type) { | |
447 | case INTEL_TLV_CNVI_TOP: | |
ac406791 | 448 | version->cnvi_top = get_unaligned_le32(tlv->val); |
57375bee K |
449 | break; |
450 | case INTEL_TLV_CNVR_TOP: | |
ac406791 | 451 | version->cnvr_top = get_unaligned_le32(tlv->val); |
57375bee K |
452 | break; |
453 | case INTEL_TLV_CNVI_BT: | |
ac406791 | 454 | version->cnvi_bt = get_unaligned_le32(tlv->val); |
57375bee K |
455 | break; |
456 | case INTEL_TLV_CNVR_BT: | |
ac406791 | 457 | version->cnvr_bt = get_unaligned_le32(tlv->val); |
57375bee K |
458 | break; |
459 | case INTEL_TLV_DEV_REV_ID: | |
ac406791 | 460 | version->dev_rev_id = get_unaligned_le16(tlv->val); |
57375bee K |
461 | break; |
462 | case INTEL_TLV_IMAGE_TYPE: | |
463 | version->img_type = tlv->val[0]; | |
464 | break; | |
465 | case INTEL_TLV_TIME_STAMP: | |
ac406791 | 466 | version->timestamp = get_unaligned_le16(tlv->val); |
57375bee K |
467 | break; |
468 | case INTEL_TLV_BUILD_TYPE: | |
469 | version->build_type = tlv->val[0]; | |
470 | break; | |
471 | case INTEL_TLV_BUILD_NUM: | |
ac406791 | 472 | version->build_num = get_unaligned_le32(tlv->val); |
57375bee K |
473 | break; |
474 | case INTEL_TLV_SECURE_BOOT: | |
475 | version->secure_boot = tlv->val[0]; | |
476 | break; | |
477 | case INTEL_TLV_OTP_LOCK: | |
478 | version->otp_lock = tlv->val[0]; | |
479 | break; | |
480 | case INTEL_TLV_API_LOCK: | |
481 | version->api_lock = tlv->val[0]; | |
482 | break; | |
483 | case INTEL_TLV_DEBUG_LOCK: | |
484 | version->debug_lock = tlv->val[0]; | |
485 | break; | |
486 | case INTEL_TLV_MIN_FW: | |
487 | version->min_fw_build_nn = tlv->val[0]; | |
488 | version->min_fw_build_cw = tlv->val[1]; | |
489 | version->min_fw_build_yy = tlv->val[2]; | |
490 | break; | |
491 | case INTEL_TLV_LIMITED_CCE: | |
492 | version->limited_cce = tlv->val[0]; | |
493 | break; | |
494 | case INTEL_TLV_SBE_TYPE: | |
495 | version->sbe_type = tlv->val[0]; | |
496 | break; | |
497 | case INTEL_TLV_OTP_BDADDR: | |
498 | memcpy(&version->otp_bd_addr, tlv->val, tlv->len); | |
499 | break; | |
500 | default: | |
501 | /* Ignore rest of information */ | |
502 | break; | |
503 | } | |
504 | /* consume the current tlv and move to next*/ | |
505 | skb_pull(skb, tlv->len + sizeof(*tlv)); | |
506 | } | |
507 | ||
508 | kfree_skb(skb); | |
509 | return 0; | |
510 | } | |
511 | EXPORT_SYMBOL_GPL(btintel_read_version_tlv); | |
512 | ||
d06f107b LP |
513 | /* ------- REGMAP IBT SUPPORT ------- */ |
514 | ||
515 | #define IBT_REG_MODE_8BIT 0x00 | |
516 | #define IBT_REG_MODE_16BIT 0x01 | |
517 | #define IBT_REG_MODE_32BIT 0x02 | |
518 | ||
519 | struct regmap_ibt_context { | |
520 | struct hci_dev *hdev; | |
521 | __u16 op_write; | |
522 | __u16 op_read; | |
523 | }; | |
524 | ||
525 | struct ibt_cp_reg_access { | |
526 | __le32 addr; | |
527 | __u8 mode; | |
528 | __u8 len; | |
683cc86d | 529 | __u8 data[]; |
d06f107b LP |
530 | } __packed; |
531 | ||
532 | struct ibt_rp_reg_access { | |
533 | __u8 status; | |
534 | __le32 addr; | |
683cc86d | 535 | __u8 data[]; |
d06f107b LP |
536 | } __packed; |
537 | ||
538 | static int regmap_ibt_read(void *context, const void *addr, size_t reg_size, | |
539 | void *val, size_t val_size) | |
540 | { | |
541 | struct regmap_ibt_context *ctx = context; | |
542 | struct ibt_cp_reg_access cp; | |
543 | struct ibt_rp_reg_access *rp; | |
544 | struct sk_buff *skb; | |
545 | int err = 0; | |
546 | ||
547 | if (reg_size != sizeof(__le32)) | |
548 | return -EINVAL; | |
549 | ||
550 | switch (val_size) { | |
551 | case 1: | |
552 | cp.mode = IBT_REG_MODE_8BIT; | |
553 | break; | |
554 | case 2: | |
555 | cp.mode = IBT_REG_MODE_16BIT; | |
556 | break; | |
557 | case 4: | |
558 | cp.mode = IBT_REG_MODE_32BIT; | |
559 | break; | |
560 | default: | |
561 | return -EINVAL; | |
562 | } | |
563 | ||
564 | /* regmap provides a little-endian formatted addr */ | |
565 | cp.addr = *(__le32 *)addr; | |
566 | cp.len = val_size; | |
567 | ||
568 | bt_dev_dbg(ctx->hdev, "Register (0x%x) read", le32_to_cpu(cp.addr)); | |
569 | ||
570 | skb = hci_cmd_sync(ctx->hdev, ctx->op_read, sizeof(cp), &cp, | |
571 | HCI_CMD_TIMEOUT); | |
572 | if (IS_ERR(skb)) { | |
573 | err = PTR_ERR(skb); | |
574 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error (%d)", | |
575 | le32_to_cpu(cp.addr), err); | |
576 | return err; | |
577 | } | |
578 | ||
579 | if (skb->len != sizeof(*rp) + val_size) { | |
580 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad len", | |
581 | le32_to_cpu(cp.addr)); | |
582 | err = -EINVAL; | |
583 | goto done; | |
584 | } | |
585 | ||
586 | rp = (struct ibt_rp_reg_access *)skb->data; | |
587 | ||
588 | if (rp->addr != cp.addr) { | |
589 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad addr", | |
590 | le32_to_cpu(rp->addr)); | |
591 | err = -EINVAL; | |
592 | goto done; | |
593 | } | |
594 | ||
595 | memcpy(val, rp->data, val_size); | |
596 | ||
597 | done: | |
598 | kfree_skb(skb); | |
599 | return err; | |
600 | } | |
601 | ||
602 | static int regmap_ibt_gather_write(void *context, | |
603 | const void *addr, size_t reg_size, | |
604 | const void *val, size_t val_size) | |
605 | { | |
606 | struct regmap_ibt_context *ctx = context; | |
607 | struct ibt_cp_reg_access *cp; | |
608 | struct sk_buff *skb; | |
609 | int plen = sizeof(*cp) + val_size; | |
610 | u8 mode; | |
611 | int err = 0; | |
612 | ||
613 | if (reg_size != sizeof(__le32)) | |
614 | return -EINVAL; | |
615 | ||
616 | switch (val_size) { | |
617 | case 1: | |
618 | mode = IBT_REG_MODE_8BIT; | |
619 | break; | |
620 | case 2: | |
621 | mode = IBT_REG_MODE_16BIT; | |
622 | break; | |
623 | case 4: | |
624 | mode = IBT_REG_MODE_32BIT; | |
625 | break; | |
626 | default: | |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | cp = kmalloc(plen, GFP_KERNEL); | |
631 | if (!cp) | |
632 | return -ENOMEM; | |
633 | ||
634 | /* regmap provides a little-endian formatted addr/value */ | |
635 | cp->addr = *(__le32 *)addr; | |
636 | cp->mode = mode; | |
637 | cp->len = val_size; | |
638 | memcpy(&cp->data, val, val_size); | |
639 | ||
640 | bt_dev_dbg(ctx->hdev, "Register (0x%x) write", le32_to_cpu(cp->addr)); | |
641 | ||
642 | skb = hci_cmd_sync(ctx->hdev, ctx->op_write, plen, cp, HCI_CMD_TIMEOUT); | |
643 | if (IS_ERR(skb)) { | |
644 | err = PTR_ERR(skb); | |
645 | bt_dev_err(ctx->hdev, "regmap: Register (0x%x) write error (%d)", | |
646 | le32_to_cpu(cp->addr), err); | |
647 | goto done; | |
648 | } | |
649 | kfree_skb(skb); | |
650 | ||
651 | done: | |
652 | kfree(cp); | |
653 | return err; | |
654 | } | |
655 | ||
656 | static int regmap_ibt_write(void *context, const void *data, size_t count) | |
657 | { | |
658 | /* data contains register+value, since we only support 32bit addr, | |
659 | * minimum data size is 4 bytes. | |
660 | */ | |
661 | if (WARN_ONCE(count < 4, "Invalid register access")) | |
662 | return -EINVAL; | |
663 | ||
664 | return regmap_ibt_gather_write(context, data, 4, data + 4, count - 4); | |
665 | } | |
666 | ||
667 | static void regmap_ibt_free_context(void *context) | |
668 | { | |
669 | kfree(context); | |
670 | } | |
671 | ||
672 | static struct regmap_bus regmap_ibt = { | |
673 | .read = regmap_ibt_read, | |
674 | .write = regmap_ibt_write, | |
675 | .gather_write = regmap_ibt_gather_write, | |
676 | .free_context = regmap_ibt_free_context, | |
677 | .reg_format_endian_default = REGMAP_ENDIAN_LITTLE, | |
678 | .val_format_endian_default = REGMAP_ENDIAN_LITTLE, | |
679 | }; | |
680 | ||
681 | /* Config is the same for all register regions */ | |
682 | static const struct regmap_config regmap_ibt_cfg = { | |
683 | .name = "btintel_regmap", | |
684 | .reg_bits = 32, | |
685 | .val_bits = 32, | |
686 | }; | |
687 | ||
688 | struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, | |
689 | u16 opcode_write) | |
690 | { | |
691 | struct regmap_ibt_context *ctx; | |
692 | ||
693 | bt_dev_info(hdev, "regmap: Init R%x-W%x region", opcode_read, | |
694 | opcode_write); | |
695 | ||
696 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
697 | if (!ctx) | |
698 | return ERR_PTR(-ENOMEM); | |
699 | ||
700 | ctx->op_read = opcode_read; | |
701 | ctx->op_write = opcode_write; | |
702 | ctx->hdev = hdev; | |
703 | ||
704 | return regmap_init(&hdev->dev, ®map_ibt, ctx, ®map_ibt_cfg); | |
705 | } | |
706 | EXPORT_SYMBOL_GPL(btintel_regmap_init); | |
707 | ||
e5889af6 THJA |
708 | int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param) |
709 | { | |
710 | struct intel_reset params = { 0x00, 0x01, 0x00, 0x01, 0x00000000 }; | |
711 | struct sk_buff *skb; | |
712 | ||
713 | params.boot_param = cpu_to_le32(boot_param); | |
714 | ||
715 | skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params), ¶ms, | |
716 | HCI_INIT_TIMEOUT); | |
717 | if (IS_ERR(skb)) { | |
718 | bt_dev_err(hdev, "Failed to send Intel Reset command"); | |
719 | return PTR_ERR(skb); | |
720 | } | |
721 | ||
722 | kfree_skb(skb); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | EXPORT_SYMBOL_GPL(btintel_send_intel_reset); | |
727 | ||
faf174d2 THJA |
728 | int btintel_read_boot_params(struct hci_dev *hdev, |
729 | struct intel_boot_params *params) | |
730 | { | |
731 | struct sk_buff *skb; | |
732 | ||
733 | skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_INIT_TIMEOUT); | |
734 | if (IS_ERR(skb)) { | |
735 | bt_dev_err(hdev, "Reading Intel boot parameters failed (%ld)", | |
736 | PTR_ERR(skb)); | |
737 | return PTR_ERR(skb); | |
738 | } | |
739 | ||
740 | if (skb->len != sizeof(*params)) { | |
741 | bt_dev_err(hdev, "Intel boot parameters size mismatch"); | |
742 | kfree_skb(skb); | |
743 | return -EILSEQ; | |
744 | } | |
745 | ||
746 | memcpy(params, skb->data, sizeof(*params)); | |
747 | ||
748 | kfree_skb(skb); | |
749 | ||
750 | if (params->status) { | |
751 | bt_dev_err(hdev, "Intel boot parameters command failed (%02x)", | |
752 | params->status); | |
753 | return -bt_to_errno(params->status); | |
754 | } | |
755 | ||
756 | bt_dev_info(hdev, "Device revision is %u", | |
757 | le16_to_cpu(params->dev_revid)); | |
758 | ||
759 | bt_dev_info(hdev, "Secure boot is %s", | |
760 | params->secure_boot ? "enabled" : "disabled"); | |
761 | ||
762 | bt_dev_info(hdev, "OTP lock is %s", | |
763 | params->otp_lock ? "enabled" : "disabled"); | |
764 | ||
765 | bt_dev_info(hdev, "API lock is %s", | |
766 | params->api_lock ? "enabled" : "disabled"); | |
767 | ||
768 | bt_dev_info(hdev, "Debug lock is %s", | |
769 | params->debug_lock ? "enabled" : "disabled"); | |
770 | ||
771 | bt_dev_info(hdev, "Minimum firmware build %u week %u %u", | |
772 | params->min_fw_build_nn, params->min_fw_build_cw, | |
773 | 2000 + params->min_fw_build_yy); | |
774 | ||
775 | return 0; | |
776 | } | |
777 | EXPORT_SYMBOL_GPL(btintel_read_boot_params); | |
778 | ||
e9117215 K |
779 | static int btintel_sfi_rsa_header_secure_send(struct hci_dev *hdev, |
780 | const struct firmware *fw) | |
fbbe83c5 THJA |
781 | { |
782 | int err; | |
fbbe83c5 THJA |
783 | |
784 | /* Start the firmware download transaction with the Init fragment | |
785 | * represented by the 128 bytes of CSS header. | |
786 | */ | |
787 | err = btintel_secure_send(hdev, 0x00, 128, fw->data); | |
788 | if (err < 0) { | |
789 | bt_dev_err(hdev, "Failed to send firmware header (%d)", err); | |
790 | goto done; | |
791 | } | |
792 | ||
793 | /* Send the 256 bytes of public key information from the firmware | |
794 | * as the PKey fragment. | |
795 | */ | |
796 | err = btintel_secure_send(hdev, 0x03, 256, fw->data + 128); | |
797 | if (err < 0) { | |
798 | bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err); | |
799 | goto done; | |
800 | } | |
801 | ||
802 | /* Send the 256 bytes of signature information from the firmware | |
803 | * as the Sign fragment. | |
804 | */ | |
805 | err = btintel_secure_send(hdev, 0x02, 256, fw->data + 388); | |
806 | if (err < 0) { | |
807 | bt_dev_err(hdev, "Failed to send firmware signature (%d)", err); | |
808 | goto done; | |
809 | } | |
810 | ||
e9117215 K |
811 | done: |
812 | return err; | |
813 | } | |
814 | ||
81ebea53 K |
815 | static int btintel_sfi_ecdsa_header_secure_send(struct hci_dev *hdev, |
816 | const struct firmware *fw) | |
817 | { | |
818 | int err; | |
819 | ||
820 | /* Start the firmware download transaction with the Init fragment | |
821 | * represented by the 128 bytes of CSS header. | |
822 | */ | |
823 | err = btintel_secure_send(hdev, 0x00, 128, fw->data + 644); | |
824 | if (err < 0) { | |
825 | bt_dev_err(hdev, "Failed to send firmware header (%d)", err); | |
826 | return err; | |
827 | } | |
828 | ||
829 | /* Send the 96 bytes of public key information from the firmware | |
830 | * as the PKey fragment. | |
831 | */ | |
832 | err = btintel_secure_send(hdev, 0x03, 96, fw->data + 644 + 128); | |
833 | if (err < 0) { | |
834 | bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err); | |
835 | return err; | |
836 | } | |
837 | ||
838 | /* Send the 96 bytes of signature information from the firmware | |
839 | * as the Sign fragment | |
840 | */ | |
841 | err = btintel_secure_send(hdev, 0x02, 96, fw->data + 644 + 224); | |
842 | if (err < 0) { | |
843 | bt_dev_err(hdev, "Failed to send firmware signature (%d)", | |
844 | err); | |
845 | return err; | |
846 | } | |
847 | return 0; | |
848 | } | |
849 | ||
e9117215 K |
850 | static int btintel_download_firmware_payload(struct hci_dev *hdev, |
851 | const struct firmware *fw, | |
ac056546 | 852 | size_t offset) |
e9117215 K |
853 | { |
854 | int err; | |
855 | const u8 *fw_ptr; | |
856 | u32 frag_len; | |
857 | ||
858 | fw_ptr = fw->data + offset; | |
fbbe83c5 | 859 | frag_len = 0; |
e9117215 | 860 | err = -EINVAL; |
fbbe83c5 THJA |
861 | |
862 | while (fw_ptr - fw->data < fw->size) { | |
863 | struct hci_command_hdr *cmd = (void *)(fw_ptr + frag_len); | |
864 | ||
fbbe83c5 THJA |
865 | frag_len += sizeof(*cmd) + cmd->plen; |
866 | ||
867 | /* The parameter length of the secure send command requires | |
868 | * a 4 byte alignment. It happens so that the firmware file | |
869 | * contains proper Intel_NOP commands to align the fragments | |
870 | * as needed. | |
871 | * | |
872 | * Send set of commands with 4 byte alignment from the | |
873 | * firmware data buffer as a single Data fragement. | |
874 | */ | |
875 | if (!(frag_len % 4)) { | |
876 | err = btintel_secure_send(hdev, 0x01, frag_len, fw_ptr); | |
877 | if (err < 0) { | |
878 | bt_dev_err(hdev, | |
879 | "Failed to send firmware data (%d)", | |
880 | err); | |
881 | goto done; | |
882 | } | |
883 | ||
884 | fw_ptr += frag_len; | |
885 | frag_len = 0; | |
886 | } | |
887 | } | |
888 | ||
889 | done: | |
890 | return err; | |
891 | } | |
e9117215 | 892 | |
ac056546 LAD |
893 | static bool btintel_firmware_version(struct hci_dev *hdev, |
894 | u8 num, u8 ww, u8 yy, | |
895 | const struct firmware *fw, | |
896 | u32 *boot_addr) | |
897 | { | |
898 | const u8 *fw_ptr; | |
899 | ||
900 | fw_ptr = fw->data; | |
901 | ||
902 | while (fw_ptr - fw->data < fw->size) { | |
903 | struct hci_command_hdr *cmd = (void *)(fw_ptr); | |
904 | ||
905 | /* Each SKU has a different reset parameter to use in the | |
906 | * HCI_Intel_Reset command and it is embedded in the firmware | |
907 | * data. So, instead of using static value per SKU, check | |
908 | * the firmware data and save it for later use. | |
909 | */ | |
910 | if (le16_to_cpu(cmd->opcode) == CMD_WRITE_BOOT_PARAMS) { | |
911 | struct cmd_write_boot_params *params; | |
912 | ||
913 | params = (void *)(fw_ptr + sizeof(*cmd)); | |
914 | ||
915 | bt_dev_info(hdev, "Boot Address: 0x%x", | |
916 | le32_to_cpu(params->boot_addr)); | |
917 | ||
918 | bt_dev_info(hdev, "Firmware Version: %u-%u.%u", | |
919 | params->fw_build_num, params->fw_build_ww, | |
920 | params->fw_build_yy); | |
921 | ||
922 | return (num == params->fw_build_num && | |
923 | ww == params->fw_build_ww && | |
924 | yy == params->fw_build_yy); | |
925 | } | |
926 | ||
927 | fw_ptr += sizeof(*cmd) + cmd->plen; | |
928 | } | |
929 | ||
930 | return false; | |
931 | } | |
932 | ||
e9117215 | 933 | int btintel_download_firmware(struct hci_dev *hdev, |
ac056546 | 934 | struct intel_version *ver, |
e9117215 K |
935 | const struct firmware *fw, |
936 | u32 *boot_param) | |
937 | { | |
938 | int err; | |
939 | ||
ac056546 LAD |
940 | /* SfP and WsP don't seem to update the firmware version on file |
941 | * so version checking is currently not possible. | |
942 | */ | |
943 | switch (ver->hw_variant) { | |
944 | case 0x0b: /* SfP */ | |
945 | case 0x0c: /* WsP */ | |
946 | /* Skip version checking */ | |
947 | break; | |
948 | default: | |
949 | /* Skip download if firmware has the same version */ | |
950 | if (btintel_firmware_version(hdev, ver->fw_build_num, | |
951 | ver->fw_build_ww, ver->fw_build_yy, | |
952 | fw, boot_param)) { | |
953 | bt_dev_info(hdev, "Firmware already loaded"); | |
954 | /* Return -EALREADY to indicate that the firmware has | |
955 | * already been loaded. | |
956 | */ | |
957 | return -EALREADY; | |
958 | } | |
959 | } | |
960 | ||
9b16bfbf LAD |
961 | /* The firmware variant determines if the device is in bootloader |
962 | * mode or is running operational firmware. The value 0x06 identifies | |
963 | * the bootloader and the value 0x23 identifies the operational | |
964 | * firmware. | |
965 | * | |
966 | * If the firmware version has changed that means it needs to be reset | |
967 | * to bootloader when operational so the new firmware can be loaded. | |
968 | */ | |
969 | if (ver->fw_variant == 0x23) | |
970 | return -EINVAL; | |
971 | ||
e9117215 K |
972 | err = btintel_sfi_rsa_header_secure_send(hdev, fw); |
973 | if (err) | |
974 | return err; | |
975 | ||
ac056546 | 976 | return btintel_download_firmware_payload(hdev, fw, RSA_HEADER_LEN); |
e9117215 | 977 | } |
fbbe83c5 THJA |
978 | EXPORT_SYMBOL_GPL(btintel_download_firmware); |
979 | ||
81ebea53 | 980 | int btintel_download_firmware_newgen(struct hci_dev *hdev, |
ac056546 | 981 | struct intel_version_tlv *ver, |
81ebea53 K |
982 | const struct firmware *fw, u32 *boot_param, |
983 | u8 hw_variant, u8 sbe_type) | |
984 | { | |
985 | int err; | |
986 | u32 css_header_ver; | |
987 | ||
ac056546 LAD |
988 | /* Skip download if firmware has the same version */ |
989 | if (btintel_firmware_version(hdev, ver->min_fw_build_nn, | |
990 | ver->min_fw_build_cw, ver->min_fw_build_yy, | |
991 | fw, boot_param)) { | |
992 | bt_dev_info(hdev, "Firmware already loaded"); | |
993 | /* Return -EALREADY to indicate that firmware has already been | |
994 | * loaded. | |
995 | */ | |
996 | return -EALREADY; | |
997 | } | |
998 | ||
9b16bfbf LAD |
999 | /* The firmware variant determines if the device is in bootloader |
1000 | * mode or is running operational firmware. The value 0x01 identifies | |
1001 | * the bootloader and the value 0x03 identifies the operational | |
1002 | * firmware. | |
1003 | * | |
1004 | * If the firmware version has changed that means it needs to be reset | |
1005 | * to bootloader when operational so the new firmware can be loaded. | |
1006 | */ | |
1007 | if (ver->img_type == 0x03) | |
1008 | return -EINVAL; | |
1009 | ||
81ebea53 K |
1010 | /* iBT hardware variants 0x0b, 0x0c, 0x11, 0x12, 0x13, 0x14 support |
1011 | * only RSA secure boot engine. Hence, the corresponding sfi file will | |
1012 | * have RSA header of 644 bytes followed by Command Buffer. | |
1013 | * | |
1014 | * iBT hardware variants 0x17, 0x18 onwards support both RSA and ECDSA | |
1015 | * secure boot engine. As a result, the corresponding sfi file will | |
1016 | * have RSA header of 644, ECDSA header of 320 bytes followed by | |
1017 | * Command Buffer. | |
1018 | * | |
1019 | * CSS Header byte positions 0x08 to 0x0B represent the CSS Header | |
1020 | * version: RSA(0x00010000) , ECDSA (0x00020000) | |
1021 | */ | |
1022 | css_header_ver = get_unaligned_le32(fw->data + CSS_HEADER_OFFSET); | |
1023 | if (css_header_ver != 0x00010000) { | |
1024 | bt_dev_err(hdev, "Invalid CSS Header version"); | |
1025 | return -EINVAL; | |
1026 | } | |
1027 | ||
1028 | if (hw_variant <= 0x14) { | |
1029 | if (sbe_type != 0x00) { | |
1030 | bt_dev_err(hdev, "Invalid SBE type for hardware variant (%d)", | |
1031 | hw_variant); | |
1032 | return -EINVAL; | |
1033 | } | |
1034 | ||
1035 | err = btintel_sfi_rsa_header_secure_send(hdev, fw); | |
1036 | if (err) | |
1037 | return err; | |
1038 | ||
ac056546 | 1039 | err = btintel_download_firmware_payload(hdev, fw, RSA_HEADER_LEN); |
81ebea53 K |
1040 | if (err) |
1041 | return err; | |
1042 | } else if (hw_variant >= 0x17) { | |
1043 | /* Check if CSS header for ECDSA follows the RSA header */ | |
1044 | if (fw->data[ECDSA_OFFSET] != 0x06) | |
1045 | return -EINVAL; | |
1046 | ||
1047 | /* Check if the CSS Header version is ECDSA(0x00020000) */ | |
1048 | css_header_ver = get_unaligned_le32(fw->data + ECDSA_OFFSET + CSS_HEADER_OFFSET); | |
1049 | if (css_header_ver != 0x00020000) { | |
1050 | bt_dev_err(hdev, "Invalid CSS Header version"); | |
1051 | return -EINVAL; | |
1052 | } | |
1053 | ||
1054 | if (sbe_type == 0x00) { | |
1055 | err = btintel_sfi_rsa_header_secure_send(hdev, fw); | |
1056 | if (err) | |
1057 | return err; | |
1058 | ||
1059 | err = btintel_download_firmware_payload(hdev, fw, | |
81ebea53 K |
1060 | RSA_HEADER_LEN + ECDSA_HEADER_LEN); |
1061 | if (err) | |
1062 | return err; | |
1063 | } else if (sbe_type == 0x01) { | |
1064 | err = btintel_sfi_ecdsa_header_secure_send(hdev, fw); | |
1065 | if (err) | |
1066 | return err; | |
1067 | ||
1068 | err = btintel_download_firmware_payload(hdev, fw, | |
81ebea53 K |
1069 | RSA_HEADER_LEN + ECDSA_HEADER_LEN); |
1070 | if (err) | |
1071 | return err; | |
1072 | } | |
1073 | } | |
1074 | return 0; | |
1075 | } | |
1076 | EXPORT_SYMBOL_GPL(btintel_download_firmware_newgen); | |
1077 | ||
b9a2562f AB |
1078 | void btintel_reset_to_bootloader(struct hci_dev *hdev) |
1079 | { | |
1080 | struct intel_reset params; | |
1081 | struct sk_buff *skb; | |
1082 | ||
1083 | /* Send Intel Reset command. This will result in | |
1084 | * re-enumeration of BT controller. | |
1085 | * | |
1086 | * Intel Reset parameter description: | |
1087 | * reset_type : 0x00 (Soft reset), | |
1088 | * 0x01 (Hard reset) | |
1089 | * patch_enable : 0x00 (Do not enable), | |
1090 | * 0x01 (Enable) | |
1091 | * ddc_reload : 0x00 (Do not reload), | |
1092 | * 0x01 (Reload) | |
1093 | * boot_option: 0x00 (Current image), | |
1094 | * 0x01 (Specified boot address) | |
1095 | * boot_param: Boot address | |
1096 | * | |
1097 | */ | |
1098 | params.reset_type = 0x01; | |
1099 | params.patch_enable = 0x01; | |
1100 | params.ddc_reload = 0x01; | |
1101 | params.boot_option = 0x00; | |
1102 | params.boot_param = cpu_to_le32(0x00000000); | |
1103 | ||
1104 | skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params), | |
1105 | ¶ms, HCI_INIT_TIMEOUT); | |
1106 | if (IS_ERR(skb)) { | |
1107 | bt_dev_err(hdev, "FW download error recovery failed (%ld)", | |
1108 | PTR_ERR(skb)); | |
1109 | return; | |
1110 | } | |
1111 | bt_dev_info(hdev, "Intel reset sent to retry FW download"); | |
1112 | kfree_skb(skb); | |
1113 | ||
1114 | /* Current Intel BT controllers(ThP/JfP) hold the USB reset | |
1115 | * lines for 2ms when it receives Intel Reset in bootloader mode. | |
1116 | * Whereas, the upcoming Intel BT controllers will hold USB reset | |
1117 | * for 150ms. To keep the delay generic, 150ms is chosen here. | |
1118 | */ | |
1119 | msleep(150); | |
1120 | } | |
1121 | EXPORT_SYMBOL_GPL(btintel_reset_to_bootloader); | |
1122 | ||
d74abe21 C |
1123 | int btintel_read_debug_features(struct hci_dev *hdev, |
1124 | struct intel_debug_features *features) | |
1125 | { | |
1126 | struct sk_buff *skb; | |
1127 | u8 page_no = 1; | |
1128 | ||
1129 | /* Intel controller supports two pages, each page is of 128-bit | |
1130 | * feature bit mask. And each bit defines specific feature support | |
1131 | */ | |
1132 | skb = __hci_cmd_sync(hdev, 0xfca6, sizeof(page_no), &page_no, | |
1133 | HCI_INIT_TIMEOUT); | |
1134 | if (IS_ERR(skb)) { | |
1135 | bt_dev_err(hdev, "Reading supported features failed (%ld)", | |
1136 | PTR_ERR(skb)); | |
1137 | return PTR_ERR(skb); | |
1138 | } | |
1139 | ||
1140 | if (skb->len != (sizeof(features->page1) + 3)) { | |
1141 | bt_dev_err(hdev, "Supported features event size mismatch"); | |
1142 | kfree_skb(skb); | |
1143 | return -EILSEQ; | |
1144 | } | |
1145 | ||
1146 | memcpy(features->page1, skb->data + 3, sizeof(features->page1)); | |
1147 | ||
1148 | /* Read the supported features page2 if required in future. | |
1149 | */ | |
1150 | kfree_skb(skb); | |
1151 | return 0; | |
1152 | } | |
1153 | EXPORT_SYMBOL_GPL(btintel_read_debug_features); | |
1154 | ||
c453b10c C |
1155 | int btintel_set_debug_features(struct hci_dev *hdev, |
1156 | const struct intel_debug_features *features) | |
1157 | { | |
1158 | u8 mask[11] = { 0x0a, 0x92, 0x02, 0x07, 0x00, 0x00, 0x00, 0x00, | |
1159 | 0x00, 0x00, 0x00 }; | |
1160 | struct sk_buff *skb; | |
1161 | ||
1162 | if (!features) | |
1163 | return -EINVAL; | |
1164 | ||
1165 | if (!(features->page1[0] & 0x3f)) { | |
1166 | bt_dev_info(hdev, "Telemetry exception format not supported"); | |
1167 | return 0; | |
1168 | } | |
1169 | ||
1170 | skb = __hci_cmd_sync(hdev, 0xfc8b, 11, mask, HCI_INIT_TIMEOUT); | |
1171 | if (IS_ERR(skb)) { | |
1172 | bt_dev_err(hdev, "Setting Intel telemetry ddc write event mask failed (%ld)", | |
1173 | PTR_ERR(skb)); | |
1174 | return PTR_ERR(skb); | |
1175 | } | |
1176 | ||
1177 | kfree_skb(skb); | |
1178 | return 0; | |
1179 | } | |
1180 | EXPORT_SYMBOL_GPL(btintel_set_debug_features); | |
1181 | ||
48f0ed1b MH |
1182 | MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>"); |
1183 | MODULE_DESCRIPTION("Bluetooth support for Intel devices ver " VERSION); | |
1184 | MODULE_VERSION(VERSION); | |
1185 | MODULE_LICENSE("GPL"); | |
0ed97e82 MH |
1186 | MODULE_FIRMWARE("intel/ibt-11-5.sfi"); |
1187 | MODULE_FIRMWARE("intel/ibt-11-5.ddc"); | |
d1b7abae JB |
1188 | MODULE_FIRMWARE("intel/ibt-12-16.sfi"); |
1189 | MODULE_FIRMWARE("intel/ibt-12-16.ddc"); |