[linux-2.6-block.git] / drivers / bluetooth / btintel.c

/*
 *
 *  Bluetooth support for Intel devices
 *
 *  Copyright (C) 2015  Intel Corporation
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#include <linux/module.h>
#include <linux/firmware.h>
#include <linux/regmap.h>
#include <asm/unaligned.h>

#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>

#include "btintel.h"

#define VERSION "0.1"

#define BDADDR_INTEL (&(bdaddr_t) {{0x00, 0x8b, 0x9e, 0x19, 0x03, 0x00}})

int btintel_check_bdaddr(struct hci_dev *hdev)
{
	struct hci_rp_read_bd_addr *bda;
	struct sk_buff *skb;

	skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL,
			     HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		int err = PTR_ERR(skb);
		bt_dev_err(hdev, "Reading Intel device address failed (%d)",
			   err);
		return err;
	}

	if (skb->len != sizeof(*bda)) {
		bt_dev_err(hdev, "Intel device address length mismatch");
		kfree_skb(skb);
		return -EIO;
	}

	bda = (struct hci_rp_read_bd_addr *)skb->data;

	/* For some Intel based controllers, the default Bluetooth device
	 * address 00:03:19:9E:8B:00 can be found. These controllers are
	 * fully operational, but have the danger of duplicate addresses
	 * and that in turn can cause problems with Bluetooth operation.
	 */
	if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) {
		bt_dev_err(hdev, "Found Intel default device address (%pMR)",
			   &bda->bdaddr);
		set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
	}

	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_check_bdaddr);

int btintel_enter_mfg(struct hci_dev *hdev)
{
	static const u8 param[] = { 0x01, 0x00 };
	struct sk_buff *skb;

	skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)",
			   PTR_ERR(skb));
		return PTR_ERR(skb);
	}
	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_enter_mfg);

int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched)
{
	u8 param[] = { 0x00, 0x00 };
	struct sk_buff *skb;

	/* The 2nd command parameter specifies the manufacturing exit method:
	 * 0x00: Just disable the manufacturing mode (0x00).
	 * 0x01: Disable manufacturing mode and reset with patches deactivated.
	 * 0x02: Disable manufacturing mode and reset with patches activated.
	 */
	if (reset)
		param[1] |= patched ? 0x02 : 0x01;

	skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Exiting manufacturer mode failed (%ld)",
			   PTR_ERR(skb));
		return PTR_ERR(skb);
	}
	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_exit_mfg);

int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
{
	struct sk_buff *skb;
	int err;

	skb = __hci_cmd_sync(hdev, 0xfc31, 6, bdaddr, HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		err = PTR_ERR(skb);
		bt_dev_err(hdev, "Changing Intel device address failed (%d)",
			   err);
		return err;
	}
	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_set_bdaddr);

int btintel_set_diag(struct hci_dev *hdev, bool enable)
{
	struct sk_buff *skb;
	u8 param[3];
	int err;

	if (enable) {
		param[0] = 0x03;
		param[1] = 0x03;
		param[2] = 0x03;
	} else {
		param[0] = 0x00;
		param[1] = 0x00;
		param[2] = 0x00;
	}

	skb = __hci_cmd_sync(hdev, 0xfc43, 3, param, HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		err = PTR_ERR(skb);
		if (err == -ENODATA)
			goto done;
		bt_dev_err(hdev, "Changing Intel diagnostic mode failed (%d)",
			   err);
		return err;
	}
	kfree_skb(skb);

done:
	btintel_set_event_mask(hdev, enable);
	return 0;
}
EXPORT_SYMBOL_GPL(btintel_set_diag);

int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable)
{
	int err, ret;

	err = btintel_enter_mfg(hdev);
	if (err)
		return err;

	ret = btintel_set_diag(hdev, enable);

	err = btintel_exit_mfg(hdev, false, false);
	if (err)
		return err;

	return ret;
}
EXPORT_SYMBOL_GPL(btintel_set_diag_mfg);

void btintel_hw_error(struct hci_dev *hdev, u8 code)
{
	struct sk_buff *skb;
	u8 type = 0x00;

	bt_dev_err(hdev, "Hardware error 0x%2.2x", code);

	skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Reset after hardware error failed (%ld)",
			   PTR_ERR(skb));
		return;
	}
	kfree_skb(skb);

	skb = __hci_cmd_sync(hdev, 0xfc22, 1, &type, HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Retrieving Intel exception info failed (%ld)",
			   PTR_ERR(skb));
		return;
	}

	if (skb->len != 13) {
		bt_dev_err(hdev, "Exception info size mismatch");
		kfree_skb(skb);
		return;
	}

	bt_dev_err(hdev, "Exception info %s", (char *)(skb->data + 1));

	kfree_skb(skb);
}
EXPORT_SYMBOL_GPL(btintel_hw_error);

void btintel_version_info(struct hci_dev *hdev, struct intel_version *ver)
{
	const char *variant;

	switch (ver->fw_variant) {
	case 0x06:
		variant = "Bootloader";
		break;
	case 0x23:
		variant = "Firmware";
		break;
	default:
		return;
	}

	bt_dev_info(hdev, "%s revision %u.%u build %u week %u %u",
		    variant, ver->fw_revision >> 4, ver->fw_revision & 0x0f,
		    ver->fw_build_num, ver->fw_build_ww,
		    2000 + ver->fw_build_yy);
}
EXPORT_SYMBOL_GPL(btintel_version_info);

int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen,
			const void *param)
{
	while (plen > 0) {
		struct sk_buff *skb;
		u8 cmd_param[253], fragment_len = (plen > 252) ? 252 : plen;

		cmd_param[0] = fragment_type;
		memcpy(cmd_param + 1, param, fragment_len);

		skb = __hci_cmd_sync(hdev, 0xfc09, fragment_len + 1,
				     cmd_param, HCI_INIT_TIMEOUT);
		if (IS_ERR(skb))
			return PTR_ERR(skb);

		kfree_skb(skb);

		plen -= fragment_len;
		param += fragment_len;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_secure_send);

int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name)
{
	const struct firmware *fw;
	struct sk_buff *skb;
	const u8 *fw_ptr;
	int err;

	err = request_firmware_direct(&fw, ddc_name, &hdev->dev);
	if (err < 0) {
		bt_dev_err(hdev, "Failed to load Intel DDC file %s (%d)",
			   ddc_name, err);
		return err;
	}

	bt_dev_info(hdev, "Found Intel DDC parameters: %s", ddc_name);

	fw_ptr = fw->data;

	/* DDC file contains one or more DDC structure which has
	 * Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2).
	 */
	while (fw->size > fw_ptr - fw->data) {
		u8 cmd_plen = fw_ptr[0] + sizeof(u8);

		skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr,
				     HCI_INIT_TIMEOUT);
		if (IS_ERR(skb)) {
			bt_dev_err(hdev, "Failed to send Intel_Write_DDC (%ld)",
				   PTR_ERR(skb));
			release_firmware(fw);
			return PTR_ERR(skb);
		}

		fw_ptr += cmd_plen;
		kfree_skb(skb);
	}

	release_firmware(fw);

	bt_dev_info(hdev, "Applying Intel DDC parameters completed");

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_load_ddc_config);

int btintel_set_event_mask(struct hci_dev *hdev, bool debug)
{
	u8 mask[8] = { 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
	struct sk_buff *skb;
	int err;

	if (debug)
		mask[1] |= 0x62;

	skb = __hci_cmd_sync(hdev, 0xfc52, 8, mask, HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		err = PTR_ERR(skb);
		bt_dev_err(hdev, "Setting Intel event mask failed (%d)", err);
		return err;
	}
	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_set_event_mask);

int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug)
{
	int err, ret;

	err = btintel_enter_mfg(hdev);
	if (err)
		return err;

	ret = btintel_set_event_mask(hdev, debug);

	err = btintel_exit_mfg(hdev, false, false);
	if (err)
		return err;

	return ret;
}
EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg);

int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver)
{
	struct sk_buff *skb;

	skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Reading Intel version information failed (%ld)",
			   PTR_ERR(skb));
		return PTR_ERR(skb);
	}

	if (skb->len != sizeof(*ver)) {
		bt_dev_err(hdev, "Intel version event size mismatch");
		kfree_skb(skb);
		return -EILSEQ;
	}

	memcpy(ver, skb->data, sizeof(*ver));

	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_read_version);

/* ------- REGMAP IBT SUPPORT ------- */

#define IBT_REG_MODE_8BIT  0x00
#define IBT_REG_MODE_16BIT 0x01
#define IBT_REG_MODE_32BIT 0x02

struct regmap_ibt_context {
	struct hci_dev *hdev;
	__u16 op_write;
	__u16 op_read;
};

struct ibt_cp_reg_access {
	__le32  addr;
	__u8    mode;
	__u8    len;
	__u8    data[0];
} __packed;

struct ibt_rp_reg_access {
	__u8    status;
	__le32  addr;
	__u8    data[0];
} __packed;

static int regmap_ibt_read(void *context, const void *addr, size_t reg_size,
			   void *val, size_t val_size)
{
	struct regmap_ibt_context *ctx = context;
	struct ibt_cp_reg_access cp;
	struct ibt_rp_reg_access *rp;
	struct sk_buff *skb;
	int err = 0;

	if (reg_size != sizeof(__le32))
		return -EINVAL;

	switch (val_size) {
	case 1:
		cp.mode = IBT_REG_MODE_8BIT;
		break;
	case 2:
		cp.mode = IBT_REG_MODE_16BIT;
		break;
	case 4:
		cp.mode = IBT_REG_MODE_32BIT;
		break;
	default:
		return -EINVAL;
	}

	/* regmap provides a little-endian formatted addr */
	cp.addr = *(__le32 *)addr;
	cp.len = val_size;

	bt_dev_dbg(ctx->hdev, "Register (0x%x) read", le32_to_cpu(cp.addr));

	skb = hci_cmd_sync(ctx->hdev, ctx->op_read, sizeof(cp), &cp,
			   HCI_CMD_TIMEOUT);
	if (IS_ERR(skb)) {
		err = PTR_ERR(skb);
		bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error (%d)",
			   le32_to_cpu(cp.addr), err);
		return err;
	}

	if (skb->len != sizeof(*rp) + val_size) {
		bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad len",
			   le32_to_cpu(cp.addr));
		err = -EINVAL;
		goto done;
	}

	rp = (struct ibt_rp_reg_access *)skb->data;

	if (rp->addr != cp.addr) {
		bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad addr",
			   le32_to_cpu(rp->addr));
		err = -EINVAL;
		goto done;
	}

	memcpy(val, rp->data, val_size);

done:
	kfree_skb(skb);
	return err;
}

static int regmap_ibt_gather_write(void *context,
				   const void *addr, size_t reg_size,
				   const void *val, size_t val_size)
{
	struct regmap_ibt_context *ctx = context;
	struct ibt_cp_reg_access *cp;
	struct sk_buff *skb;
	int plen = sizeof(*cp) + val_size;
	u8 mode;
	int err = 0;

	if (reg_size != sizeof(__le32))
		return -EINVAL;

	switch (val_size) {
	case 1:
		mode = IBT_REG_MODE_8BIT;
		break;
	case 2:
		mode = IBT_REG_MODE_16BIT;
		break;
	case 4:
		mode = IBT_REG_MODE_32BIT;
		break;
	default:
		return -EINVAL;
	}

	cp = kmalloc(plen, GFP_KERNEL);
	if (!cp)
		return -ENOMEM;

	/* regmap provides a little-endian formatted addr/value */
	cp->addr = *(__le32 *)addr;
	cp->mode = mode;
	cp->len = val_size;
	memcpy(&cp->data, val, val_size);

	bt_dev_dbg(ctx->hdev, "Register (0x%x) write", le32_to_cpu(cp->addr));

	skb = hci_cmd_sync(ctx->hdev, ctx->op_write, plen, cp, HCI_CMD_TIMEOUT);
	if (IS_ERR(skb)) {
		err = PTR_ERR(skb);
		bt_dev_err(ctx->hdev, "regmap: Register (0x%x) write error (%d)",
			   le32_to_cpu(cp->addr), err);
		goto done;
	}
	kfree_skb(skb);

done:
	kfree(cp);
	return err;
}

static int regmap_ibt_write(void *context, const void *data, size_t count)
{
	/* data contains register+value, since we only support 32bit addr,
	 * minimum data size is 4 bytes.
	 */
	if (WARN_ONCE(count < 4, "Invalid register access"))
		return -EINVAL;

	return regmap_ibt_gather_write(context, data, 4, data + 4, count - 4);
}

static void regmap_ibt_free_context(void *context)
{
	kfree(context);
}

static struct regmap_bus regmap_ibt = {
	.read = regmap_ibt_read,
	.write = regmap_ibt_write,
	.gather_write = regmap_ibt_gather_write,
	.free_context = regmap_ibt_free_context,
	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
};

/* Config is the same for all register regions */
static const struct regmap_config regmap_ibt_cfg = {
	.name      = "btintel_regmap",
	.reg_bits  = 32,
	.val_bits  = 32,
};

struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read,
				   u16 opcode_write)
{
	struct regmap_ibt_context *ctx;

	bt_dev_info(hdev, "regmap: Init R%x-W%x region", opcode_read,
		    opcode_write);

	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return ERR_PTR(-ENOMEM);

	ctx->op_read = opcode_read;
	ctx->op_write = opcode_write;
	ctx->hdev = hdev;

	return regmap_init(&hdev->dev, &regmap_ibt, ctx, &regmap_ibt_cfg);
}
EXPORT_SYMBOL_GPL(btintel_regmap_init);

int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param)
{
	struct intel_reset params = { 0x00, 0x01, 0x00, 0x01, 0x00000000 };
	struct sk_buff *skb;

	params.boot_param = cpu_to_le32(boot_param);

	skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params), &params,
			     HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Failed to send Intel Reset command");
		return PTR_ERR(skb);
	}

	kfree_skb(skb);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_send_intel_reset);

int btintel_read_boot_params(struct hci_dev *hdev,
			     struct intel_boot_params *params)
{
	struct sk_buff *skb;

	skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_INIT_TIMEOUT);
	if (IS_ERR(skb)) {
		bt_dev_err(hdev, "Reading Intel boot parameters failed (%ld)",
			   PTR_ERR(skb));
		return PTR_ERR(skb);
	}

	if (skb->len != sizeof(*params)) {
		bt_dev_err(hdev, "Intel boot parameters size mismatch");
		kfree_skb(skb);
		return -EILSEQ;
	}

	memcpy(params, skb->data, sizeof(*params));

	kfree_skb(skb);

	if (params->status) {
		bt_dev_err(hdev, "Intel boot parameters command failed (%02x)",
			   params->status);
		return -bt_to_errno(params->status);
	}

	bt_dev_info(hdev, "Device revision is %u",
		    le16_to_cpu(params->dev_revid));

	bt_dev_info(hdev, "Secure boot is %s",
		    params->secure_boot ? "enabled" : "disabled");

	bt_dev_info(hdev, "OTP lock is %s",
		    params->otp_lock ? "enabled" : "disabled");

	bt_dev_info(hdev, "API lock is %s",
		    params->api_lock ? "enabled" : "disabled");

	bt_dev_info(hdev, "Debug lock is %s",
		    params->debug_lock ? "enabled" : "disabled");

	bt_dev_info(hdev, "Minimum firmware build %u week %u %u",
		    params->min_fw_build_nn, params->min_fw_build_cw,
		    2000 + params->min_fw_build_yy);

	return 0;
}
EXPORT_SYMBOL_GPL(btintel_read_boot_params);

int btintel_download_firmware(struct hci_dev *hdev, const struct firmware *fw,
			      u32 *boot_param)
{
	int err;
	const u8 *fw_ptr;
	u32 frag_len;

	/* Start the firmware download transaction with the Init fragment
	 * represented by the 128 bytes of CSS header.
	 */
	err = btintel_secure_send(hdev, 0x00, 128, fw->data);
	if (err < 0) {
		bt_dev_err(hdev, "Failed to send firmware header (%d)", err);
		goto done;
	}

	/* Send the 256 bytes of public key information from the firmware
	 * as the PKey fragment.
	 */
	err = btintel_secure_send(hdev, 0x03, 256, fw->data + 128);
	if (err < 0) {
		bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err);
		goto done;
	}

	/* Send the 256 bytes of signature information from the firmware
	 * as the Sign fragment.
	 */
	err = btintel_secure_send(hdev, 0x02, 256, fw->data + 388);
	if (err < 0) {
		bt_dev_err(hdev, "Failed to send firmware signature (%d)", err);
		goto done;
	}

	fw_ptr = fw->data + 644;
	frag_len = 0;

	while (fw_ptr - fw->data < fw->size) {
		struct hci_command_hdr *cmd = (void *)(fw_ptr + frag_len);

		/* Each SKU has a different reset parameter to use in the
		 * HCI_Intel_Reset command and it is embedded in the firmware
		 * data. So, instead of using static value per SKU, check
		 * the firmware data and save it for later use.
		 */
		if (le16_to_cpu(cmd->opcode) == 0xfc0e) {
			/* The boot parameter is the first 32-bit value
			 * and rest of 3 octets are reserved.
			 */
			*boot_param = get_unaligned_le32(fw_ptr + sizeof(*cmd));

			bt_dev_dbg(hdev, "boot_param=0x%x", *boot_param);
		}

		frag_len += sizeof(*cmd) + cmd->plen;

		/* The parameter length of the secure send command requires
		 * a 4 byte alignment. It happens so that the firmware file
		 * contains proper Intel_NOP commands to align the fragments
		 * as needed.
		 *
		 * Send set of commands with 4 byte alignment from the
		 * firmware data buffer as a single Data fragement.
		 */
		if (!(frag_len % 4)) {
			err = btintel_secure_send(hdev, 0x01, frag_len, fw_ptr);
			if (err < 0) {
				bt_dev_err(hdev,
					   "Failed to send firmware data (%d)",
					   err);
				goto done;
			}

			fw_ptr += frag_len;
			frag_len = 0;
		}
	}

done:
	return err;
}
EXPORT_SYMBOL_GPL(btintel_download_firmware);

MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
MODULE_DESCRIPTION("Bluetooth support for Intel devices ver " VERSION);
MODULE_VERSION(VERSION);
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("intel/ibt-11-5.sfi");
MODULE_FIRMWARE("intel/ibt-11-5.ddc");
MODULE_FIRMWARE("intel/ibt-12-16.sfi");
MODULE_FIRMWARE("intel/ibt-12-16.ddc");
Commit	Line	Data
48f0ed1b MH	1	/*
	2	*
	3	* Bluetooth support for Intel devices
	4	*
	5	* Copyright (C) 2015 Intel Corporation
	6	*
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <linux/module.h>
145f2368	25	#include <linux/firmware.h>
d06f107b	26	#include <linux/regmap.h>
fbbe83c5	27	#include <asm/unaligned.h>
48f0ed1b MH	28
	29	#include <net/bluetooth/bluetooth.h>
	30	#include <net/bluetooth/hci_core.h>
	31
	32	#include "btintel.h"
	33
	34	#define VERSION "0.1"
	35
	36	#define BDADDR_INTEL (&(bdaddr_t) {{0x00, 0x8b, 0x9e, 0x19, 0x03, 0x00}})
	37
	38	int btintel_check_bdaddr(struct hci_dev *hdev)
	39	{
	40	struct hci_rp_read_bd_addr *bda;
	41	struct sk_buff *skb;
	42
	43	skb = __hci_cmd_sync(hdev, HCI_OP_READ_BD_ADDR, 0, NULL,
	44	HCI_INIT_TIMEOUT);
	45	if (IS_ERR(skb)) {
	46	int err = PTR_ERR(skb);
2064ee33 MH	47	bt_dev_err(hdev, "Reading Intel device address failed (%d)",
2064ee33 MH	48	err);
48f0ed1b MH	49	return err;
	50	}
	51
	52	if (skb->len != sizeof(*bda)) {
2064ee33	53	bt_dev_err(hdev, "Intel device address length mismatch");
48f0ed1b MH	54	kfree_skb(skb);
	55	return -EIO;
	56	}
	57
	58	bda = (struct hci_rp_read_bd_addr *)skb->data;
48f0ed1b MH	59
	60	/* For some Intel based controllers, the default Bluetooth device
	61	* address 00:03:19:9E:8B:00 can be found. These controllers are
	62	* fully operational, but have the danger of duplicate addresses
	63	* and that in turn can cause problems with Bluetooth operation.
	64	*/
	65	if (!bacmp(&bda->bdaddr, BDADDR_INTEL)) {
2064ee33 MH	66	bt_dev_err(hdev, "Found Intel default device address (%pMR)",
2064ee33 MH	67	&bda->bdaddr);
48f0ed1b MH	68	set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks);
	69	}
	70
	71	kfree_skb(skb);
	72
	73	return 0;
	74	}
	75	EXPORT_SYMBOL_GPL(btintel_check_bdaddr);
	76
28dc4b92 LP	77	int btintel_enter_mfg(struct hci_dev *hdev)
28dc4b92 LP	78	{
948c7ca0	79	static const u8 param[] = { 0x01, 0x00 };
28dc4b92 LP	80	struct sk_buff *skb;
	81
	82	skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
	83	if (IS_ERR(skb)) {
	84	bt_dev_err(hdev, "Entering manufacturer mode failed (%ld)",
	85	PTR_ERR(skb));
	86	return PTR_ERR(skb);
	87	}
	88	kfree_skb(skb);
	89
	90	return 0;
	91	}
	92	EXPORT_SYMBOL_GPL(btintel_enter_mfg);
	93
	94	int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched)
	95	{
	96	u8 param[] = { 0x00, 0x00 };
	97	struct sk_buff *skb;
	98
	99	/* The 2nd command parameter specifies the manufacturing exit method:
	100	* 0x00: Just disable the manufacturing mode (0x00).
	101	* 0x01: Disable manufacturing mode and reset with patches deactivated.
	102	* 0x02: Disable manufacturing mode and reset with patches activated.
	103	*/
	104	if (reset)
	105	param[1] \|= patched ? 0x02 : 0x01;
	106
	107	skb = __hci_cmd_sync(hdev, 0xfc11, 2, param, HCI_CMD_TIMEOUT);
	108	if (IS_ERR(skb)) {
	109	bt_dev_err(hdev, "Exiting manufacturer mode failed (%ld)",
	110	PTR_ERR(skb));
	111	return PTR_ERR(skb);
	112	}
	113	kfree_skb(skb);
	114
	115	return 0;
	116	}
	117	EXPORT_SYMBOL_GPL(btintel_exit_mfg);
	118
48f0ed1b MH	119	int btintel_set_bdaddr(struct hci_dev hdev, const bdaddr_t bdaddr)
	120	{
	121	struct sk_buff *skb;
	122	int err;
	123
	124	skb = __hci_cmd_sync(hdev, 0xfc31, 6, bdaddr, HCI_INIT_TIMEOUT);
	125	if (IS_ERR(skb)) {
	126	err = PTR_ERR(skb);
2064ee33 MH	127	bt_dev_err(hdev, "Changing Intel device address failed (%d)",
2064ee33 MH	128	err);
48f0ed1b MH	129	return err;
	130	}
	131	kfree_skb(skb);
	132
	133	return 0;
	134	}
	135	EXPORT_SYMBOL_GPL(btintel_set_bdaddr);
	136
6d2e50d2 MH	137	int btintel_set_diag(struct hci_dev *hdev, bool enable)
	138	{
	139	struct sk_buff *skb;
	140	u8 param[3];
	141	int err;
	142
6d2e50d2 MH	143	if (enable) {
	144	param[0] = 0x03;
	145	param[1] = 0x03;
	146	param[2] = 0x03;
	147	} else {
	148	param[0] = 0x00;
	149	param[1] = 0x00;
	150	param[2] = 0x00;
	151	}
	152
	153	skb = __hci_cmd_sync(hdev, 0xfc43, 3, param, HCI_INIT_TIMEOUT);
	154	if (IS_ERR(skb)) {
	155	err = PTR_ERR(skb);
d8270fbb	156	if (err == -ENODATA)
213445b2	157	goto done;
2064ee33 MH	158	bt_dev_err(hdev, "Changing Intel diagnostic mode failed (%d)",
2064ee33 MH	159	err);
6d2e50d2 MH	160	return err;
	161	}
	162	kfree_skb(skb);
	163
213445b2 MH	164	done:
213445b2 MH	165	btintel_set_event_mask(hdev, enable);
6d2e50d2 MH	166	return 0;
	167	}
	168	EXPORT_SYMBOL_GPL(btintel_set_diag);
	169
3e24767b MH	170	int btintel_set_diag_mfg(struct hci_dev *hdev, bool enable)
3e24767b MH	171	{
28dc4b92	172	int err, ret;
3e24767b	173
28dc4b92 LP	174	err = btintel_enter_mfg(hdev);
	175	if (err)
	176	return err;
3e24767b	177
28dc4b92	178	ret = btintel_set_diag(hdev, enable);
3e24767b	179
28dc4b92 LP	180	err = btintel_exit_mfg(hdev, false, false);
	181	if (err)
	182	return err;
3e24767b	183
28dc4b92	184	return ret;
3e24767b MH	185	}
	186	EXPORT_SYMBOL_GPL(btintel_set_diag_mfg);
	187
973bb97e MH	188	void btintel_hw_error(struct hci_dev *hdev, u8 code)
	189	{
	190	struct sk_buff *skb;
	191	u8 type = 0x00;
	192
2064ee33	193	bt_dev_err(hdev, "Hardware error 0x%2.2x", code);
973bb97e MH	194
	195	skb = __hci_cmd_sync(hdev, HCI_OP_RESET, 0, NULL, HCI_INIT_TIMEOUT);
	196	if (IS_ERR(skb)) {
2064ee33 MH	197	bt_dev_err(hdev, "Reset after hardware error failed (%ld)",
2064ee33 MH	198	PTR_ERR(skb));
973bb97e MH	199	return;
	200	}
	201	kfree_skb(skb);
	202
	203	skb = __hci_cmd_sync(hdev, 0xfc22, 1, &type, HCI_INIT_TIMEOUT);
	204	if (IS_ERR(skb)) {
2064ee33 MH	205	bt_dev_err(hdev, "Retrieving Intel exception info failed (%ld)",
2064ee33 MH	206	PTR_ERR(skb));
973bb97e MH	207	return;
	208	}
	209
	210	if (skb->len != 13) {
2064ee33	211	bt_dev_err(hdev, "Exception info size mismatch");
973bb97e MH	212	kfree_skb(skb);
	213	return;
	214	}
	215
2064ee33	216	bt_dev_err(hdev, "Exception info %s", (char *)(skb->data + 1));
973bb97e MH	217
	218	kfree_skb(skb);
	219	}
	220	EXPORT_SYMBOL_GPL(btintel_hw_error);
	221
7feb99e1 MH	222	void btintel_version_info(struct hci_dev hdev, struct intel_version ver)
	223	{
	224	const char *variant;
	225
	226	switch (ver->fw_variant) {
	227	case 0x06:
	228	variant = "Bootloader";
	229	break;
	230	case 0x23:
	231	variant = "Firmware";
	232	break;
	233	default:
	234	return;
	235	}
	236
2064ee33 MH	237	bt_dev_info(hdev, "%s revision %u.%u build %u week %u %u",
	238	variant, ver->fw_revision >> 4, ver->fw_revision & 0x0f,
	239	ver->fw_build_num, ver->fw_build_ww,
	240	2000 + ver->fw_build_yy);
7feb99e1 MH	241	}
	242	EXPORT_SYMBOL_GPL(btintel_version_info);
	243
09df123d MH	244	int btintel_secure_send(struct hci_dev *hdev, u8 fragment_type, u32 plen,
	245	const void *param)
	246	{
	247	while (plen > 0) {
	248	struct sk_buff *skb;
	249	u8 cmd_param[253], fragment_len = (plen > 252) ? 252 : plen;
	250
	251	cmd_param[0] = fragment_type;
	252	memcpy(cmd_param + 1, param, fragment_len);
	253
	254	skb = __hci_cmd_sync(hdev, 0xfc09, fragment_len + 1,
	255	cmd_param, HCI_INIT_TIMEOUT);
	256	if (IS_ERR(skb))
	257	return PTR_ERR(skb);
	258
	259	kfree_skb(skb);
	260
	261	plen -= fragment_len;
	262	param += fragment_len;
	263	}
	264
	265	return 0;
	266	}
	267	EXPORT_SYMBOL_GPL(btintel_secure_send);
	268
145f2368 LP	269	int btintel_load_ddc_config(struct hci_dev hdev, const char ddc_name)
	270	{
	271	const struct firmware *fw;
	272	struct sk_buff *skb;
	273	const u8 *fw_ptr;
	274	int err;
	275
	276	err = request_firmware_direct(&fw, ddc_name, &hdev->dev);
	277	if (err < 0) {
	278	bt_dev_err(hdev, "Failed to load Intel DDC file %s (%d)",
	279	ddc_name, err);
	280	return err;
	281	}
	282
	283	bt_dev_info(hdev, "Found Intel DDC parameters: %s", ddc_name);
	284
	285	fw_ptr = fw->data;
	286
	287	/* DDC file contains one or more DDC structure which has
	288	* Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2).
	289	*/
	290	while (fw->size > fw_ptr - fw->data) {
	291	u8 cmd_plen = fw_ptr[0] + sizeof(u8);
	292
	293	skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr,
	294	HCI_INIT_TIMEOUT);
	295	if (IS_ERR(skb)) {
	296	bt_dev_err(hdev, "Failed to send Intel_Write_DDC (%ld)",
	297	PTR_ERR(skb));
	298	release_firmware(fw);
	299	return PTR_ERR(skb);
	300	}
	301
	302	fw_ptr += cmd_plen;
	303	kfree_skb(skb);
	304	}
	305
	306	release_firmware(fw);
	307
	308	bt_dev_info(hdev, "Applying Intel DDC parameters completed");
	309
	310	return 0;
	311	}
	312	EXPORT_SYMBOL_GPL(btintel_load_ddc_config);
	313
213445b2 MH	314	int btintel_set_event_mask(struct hci_dev *hdev, bool debug)
	315	{
	316	u8 mask[8] = { 0x87, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
	317	struct sk_buff *skb;
	318	int err;
	319
	320	if (debug)
	321	mask[1] \|= 0x62;
	322
	323	skb = __hci_cmd_sync(hdev, 0xfc52, 8, mask, HCI_INIT_TIMEOUT);
	324	if (IS_ERR(skb)) {
	325	err = PTR_ERR(skb);
2064ee33	326	bt_dev_err(hdev, "Setting Intel event mask failed (%d)", err);
213445b2 MH	327	return err;
	328	}
	329	kfree_skb(skb);
	330
	331	return 0;
	332	}
	333	EXPORT_SYMBOL_GPL(btintel_set_event_mask);
	334
	335	int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug)
	336	{
28dc4b92	337	int err, ret;
213445b2	338
28dc4b92 LP	339	err = btintel_enter_mfg(hdev);
	340	if (err)
	341	return err;
213445b2	342
28dc4b92	343	ret = btintel_set_event_mask(hdev, debug);
213445b2	344
28dc4b92 LP	345	err = btintel_exit_mfg(hdev, false, false);
	346	if (err)
	347	return err;
213445b2	348
28dc4b92	349	return ret;
213445b2 MH	350	}
	351	EXPORT_SYMBOL_GPL(btintel_set_event_mask_mfg);
	352
6c483de1 LP	353	int btintel_read_version(struct hci_dev hdev, struct intel_version ver)
	354	{
	355	struct sk_buff *skb;
	356
	357	skb = __hci_cmd_sync(hdev, 0xfc05, 0, NULL, HCI_CMD_TIMEOUT);
	358	if (IS_ERR(skb)) {
	359	bt_dev_err(hdev, "Reading Intel version information failed (%ld)",
	360	PTR_ERR(skb));
	361	return PTR_ERR(skb);
	362	}
	363
	364	if (skb->len != sizeof(*ver)) {
	365	bt_dev_err(hdev, "Intel version event size mismatch");
	366	kfree_skb(skb);
	367	return -EILSEQ;
	368	}
	369
	370	memcpy(ver, skb->data, sizeof(*ver));
	371
	372	kfree_skb(skb);
	373
	374	return 0;
	375	}
	376	EXPORT_SYMBOL_GPL(btintel_read_version);
	377
d06f107b LP	378	/* ------- REGMAP IBT SUPPORT ------- */
	379
	380	#define IBT_REG_MODE_8BIT 0x00
	381	#define IBT_REG_MODE_16BIT 0x01
	382	#define IBT_REG_MODE_32BIT 0x02
	383
	384	struct regmap_ibt_context {
	385	struct hci_dev *hdev;
	386	__u16 op_write;
	387	__u16 op_read;
	388	};
	389
	390	struct ibt_cp_reg_access {
	391	__le32 addr;
	392	__u8 mode;
	393	__u8 len;
	394	__u8 data[0];
	395	} __packed;
	396
	397	struct ibt_rp_reg_access {
	398	__u8 status;
	399	__le32 addr;
	400	__u8 data[0];
	401	} __packed;
	402
	403	static int regmap_ibt_read(void context, const void addr, size_t reg_size,
	404	void *val, size_t val_size)
	405	{
	406	struct regmap_ibt_context *ctx = context;
	407	struct ibt_cp_reg_access cp;
	408	struct ibt_rp_reg_access *rp;
	409	struct sk_buff *skb;
	410	int err = 0;
	411
	412	if (reg_size != sizeof(__le32))
	413	return -EINVAL;
	414
	415	switch (val_size) {
	416	case 1:
	417	cp.mode = IBT_REG_MODE_8BIT;
	418	break;
	419	case 2:
	420	cp.mode = IBT_REG_MODE_16BIT;
	421	break;
	422	case 4:
	423	cp.mode = IBT_REG_MODE_32BIT;
	424	break;
	425	default:
	426	return -EINVAL;
	427	}
	428
	429	/* regmap provides a little-endian formatted addr */
	430	cp.addr = (__le32 )addr;
	431	cp.len = val_size;
	432
	433	bt_dev_dbg(ctx->hdev, "Register (0x%x) read", le32_to_cpu(cp.addr));
	434
	435	skb = hci_cmd_sync(ctx->hdev, ctx->op_read, sizeof(cp), &cp,
	436	HCI_CMD_TIMEOUT);
	437	if (IS_ERR(skb)) {
	438	err = PTR_ERR(skb);
	439	bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error (%d)",
	440	le32_to_cpu(cp.addr), err);
	441	return err;
442	}
443
444	if (skb->len != sizeof(*rp) + val_size) {
445	bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad len",
446	le32_to_cpu(cp.addr));
447	err = -EINVAL;
448	goto done;
449	}
450
451	rp = (struct ibt_rp_reg_access *)skb->data;
452
453	if (rp->addr != cp.addr) {
454	bt_dev_err(ctx->hdev, "regmap: Register (0x%x) read error, bad addr",
455	le32_to_cpu(rp->addr));
456	err = -EINVAL;
457	goto done;
458	}
459
460	memcpy(val, rp->data, val_size);
461
462	done:
463	kfree_skb(skb);
464	return err;
465	}
466
467	static int regmap_ibt_gather_write(void *context,
468	const void *addr, size_t reg_size,
469	const void *val, size_t val_size)
470	{
471	struct regmap_ibt_context *ctx = context;
472	struct ibt_cp_reg_access *cp;
473	struct sk_buff *skb;
474	int plen = sizeof(*cp) + val_size;
475	u8 mode;
476	int err = 0;
477
478	if (reg_size != sizeof(__le32))
479	return -EINVAL;
480
481	switch (val_size) {
482	case 1:
483	mode = IBT_REG_MODE_8BIT;
484	break;
485	case 2:
486	mode = IBT_REG_MODE_16BIT;
487	break;
488	case 4:
489	mode = IBT_REG_MODE_32BIT;
490	break;
491	default:
492	return -EINVAL;
493	}
494
495	cp = kmalloc(plen, GFP_KERNEL);
496	if (!cp)
497	return -ENOMEM;
498
499	/* regmap provides a little-endian formatted addr/value */
500	cp->addr = (__le32 )addr;
501	cp->mode = mode;
502	cp->len = val_size;
503	memcpy(&cp->data, val, val_size);
504
505	bt_dev_dbg(ctx->hdev, "Register (0x%x) write", le32_to_cpu(cp->addr));
506
507	skb = hci_cmd_sync(ctx->hdev, ctx->op_write, plen, cp, HCI_CMD_TIMEOUT);
508	if (IS_ERR(skb)) {
509	err = PTR_ERR(skb);
510	bt_dev_err(ctx->hdev, "regmap: Register (0x%x) write error (%d)",
511	le32_to_cpu(cp->addr), err);
512	goto done;
513	}
514	kfree_skb(skb);
515
516	done:
517	kfree(cp);
518	return err;
519	}
520
521	static int regmap_ibt_write(void context, const void data, size_t count)
522	{
523	/* data contains register+value, since we only support 32bit addr,
524	* minimum data size is 4 bytes.
525	*/
526	if (WARN_ONCE(count < 4, "Invalid register access"))
527	return -EINVAL;
528
529	return regmap_ibt_gather_write(context, data, 4, data + 4, count - 4);
530	}
531
532	static void regmap_ibt_free_context(void *context)
533	{
534	kfree(context);
535	}
536
537	static struct regmap_bus regmap_ibt = {
538	.read = regmap_ibt_read,
539	.write = regmap_ibt_write,
540	.gather_write = regmap_ibt_gather_write,
541	.free_context = regmap_ibt_free_context,
542	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
543	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
544	};
545
546	/* Config is the same for all register regions */
547	static const struct regmap_config regmap_ibt_cfg = {
548	.name = "btintel_regmap",
549	.reg_bits = 32,
550	.val_bits = 32,
551	};
552
553	struct regmap btintel_regmap_init(struct hci_dev hdev, u16 opcode_read,
554	u16 opcode_write)
555	{
556	struct regmap_ibt_context *ctx;
557
558	bt_dev_info(hdev, "regmap: Init R%x-W%x region", opcode_read,
559	opcode_write);
560
561	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
562	if (!ctx)
563	return ERR_PTR(-ENOMEM);
564
565	ctx->op_read = opcode_read;
566	ctx->op_write = opcode_write;
567	ctx->hdev = hdev;
568
569	return regmap_init(&hdev->dev, &regmap_ibt, ctx, &regmap_ibt_cfg);
570	}
571	EXPORT_SYMBOL_GPL(btintel_regmap_init);
572
e5889af6 THJA	573	int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param)
	574	{
	575	struct intel_reset params = { 0x00, 0x01, 0x00, 0x01, 0x00000000 };
	576	struct sk_buff *skb;
	577
	578	params.boot_param = cpu_to_le32(boot_param);
	579
	580	skb = __hci_cmd_sync(hdev, 0xfc01, sizeof(params), &params,
	581	HCI_INIT_TIMEOUT);
	582	if (IS_ERR(skb)) {
	583	bt_dev_err(hdev, "Failed to send Intel Reset command");
	584	return PTR_ERR(skb);
	585	}
	586
	587	kfree_skb(skb);
	588
	589	return 0;
	590	}
	591	EXPORT_SYMBOL_GPL(btintel_send_intel_reset);
	592
faf174d2 THJA	593	int btintel_read_boot_params(struct hci_dev *hdev,
	594	struct intel_boot_params *params)
	595	{
	596	struct sk_buff *skb;
	597
	598	skb = __hci_cmd_sync(hdev, 0xfc0d, 0, NULL, HCI_INIT_TIMEOUT);
	599	if (IS_ERR(skb)) {
	600	bt_dev_err(hdev, "Reading Intel boot parameters failed (%ld)",
	601	PTR_ERR(skb));
	602	return PTR_ERR(skb);
	603	}
	604
	605	if (skb->len != sizeof(*params)) {
	606	bt_dev_err(hdev, "Intel boot parameters size mismatch");
	607	kfree_skb(skb);
	608	return -EILSEQ;
	609	}
	610
	611	memcpy(params, skb->data, sizeof(*params));
	612
	613	kfree_skb(skb);
	614
	615	if (params->status) {
	616	bt_dev_err(hdev, "Intel boot parameters command failed (%02x)",
	617	params->status);
	618	return -bt_to_errno(params->status);
	619	}
	620
	621	bt_dev_info(hdev, "Device revision is %u",
	622	le16_to_cpu(params->dev_revid));
	623
	624	bt_dev_info(hdev, "Secure boot is %s",
	625	params->secure_boot ? "enabled" : "disabled");
	626
	627	bt_dev_info(hdev, "OTP lock is %s",
	628	params->otp_lock ? "enabled" : "disabled");
	629
	630	bt_dev_info(hdev, "API lock is %s",
	631	params->api_lock ? "enabled" : "disabled");
	632
	633	bt_dev_info(hdev, "Debug lock is %s",
	634	params->debug_lock ? "enabled" : "disabled");
	635
	636	bt_dev_info(hdev, "Minimum firmware build %u week %u %u",
	637	params->min_fw_build_nn, params->min_fw_build_cw,
	638	2000 + params->min_fw_build_yy);
	639
	640	return 0;
	641	}
	642	EXPORT_SYMBOL_GPL(btintel_read_boot_params);
	643
fbbe83c5 THJA	644	int btintel_download_firmware(struct hci_dev hdev, const struct firmware fw,
	645	u32 *boot_param)
	646	{
	647	int err;
	648	const u8 *fw_ptr;
	649	u32 frag_len;
	650
	651	/* Start the firmware download transaction with the Init fragment
	652	* represented by the 128 bytes of CSS header.
	653	*/
	654	err = btintel_secure_send(hdev, 0x00, 128, fw->data);
	655	if (err < 0) {
	656	bt_dev_err(hdev, "Failed to send firmware header (%d)", err);
	657	goto done;
	658	}
	659
	660	/* Send the 256 bytes of public key information from the firmware
	661	* as the PKey fragment.
	662	*/
	663	err = btintel_secure_send(hdev, 0x03, 256, fw->data + 128);
	664	if (err < 0) {
	665	bt_dev_err(hdev, "Failed to send firmware pkey (%d)", err);
	666	goto done;
	667	}
	668
	669	/* Send the 256 bytes of signature information from the firmware
	670	* as the Sign fragment.
	671	*/
	672	err = btintel_secure_send(hdev, 0x02, 256, fw->data + 388);
	673	if (err < 0) {
	674	bt_dev_err(hdev, "Failed to send firmware signature (%d)", err);
	675	goto done;
	676	}
	677
	678	fw_ptr = fw->data + 644;
	679	frag_len = 0;
	680
	681	while (fw_ptr - fw->data < fw->size) {
	682	struct hci_command_hdr cmd = (void )(fw_ptr + frag_len);
	683
	684	/* Each SKU has a different reset parameter to use in the
	685	* HCI_Intel_Reset command and it is embedded in the firmware
	686	* data. So, instead of using static value per SKU, check
	687	* the firmware data and save it for later use.
	688	*/
	689	if (le16_to_cpu(cmd->opcode) == 0xfc0e) {
	690	/* The boot parameter is the first 32-bit value
	691	* and rest of 3 octets are reserved.
	692	*/
	693	boot_param = get_unaligned_le32(fw_ptr + sizeof(cmd));
	694
	695	bt_dev_dbg(hdev, "boot_param=0x%x", *boot_param);
	696	}
	697
	698	frag_len += sizeof(*cmd) + cmd->plen;
	699
	700	/* The parameter length of the secure send command requires
	701	* a 4 byte alignment. It happens so that the firmware file
	702	* contains proper Intel_NOP commands to align the fragments
	703	* as needed.
	704	*
	705	* Send set of commands with 4 byte alignment from the
	706	* firmware data buffer as a single Data fragement.
	707	*/
708	if (!(frag_len % 4)) {
709	err = btintel_secure_send(hdev, 0x01, frag_len, fw_ptr);
710	if (err < 0) {
711	bt_dev_err(hdev,
712	"Failed to send firmware data (%d)",
713	err);
714	goto done;
715	}
716
717	fw_ptr += frag_len;
718	frag_len = 0;
719	}
720	}
721
722	done:
723	return err;
724	}
725	EXPORT_SYMBOL_GPL(btintel_download_firmware);
726
48f0ed1b MH	727	MODULE_AUTHOR("Marcel Holtmann <marcel@holtmann.org>");
	728	MODULE_DESCRIPTION("Bluetooth support for Intel devices ver " VERSION);
	729	MODULE_VERSION(VERSION);
	730	MODULE_LICENSE("GPL");
0ed97e82 MH	731	MODULE_FIRMWARE("intel/ibt-11-5.sfi");
0ed97e82 MH	732	MODULE_FIRMWARE("intel/ibt-11-5.ddc");
d1b7abae JB	733	MODULE_FIRMWARE("intel/ibt-12-16.sfi");
d1b7abae JB	734	MODULE_FIRMWARE("intel/ibt-12-16.ddc");