Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * Driver for the SWIM3 (Super Woz Integrated Machine 3) | |
4 | * floppy controller found on Power Macintoshes. | |
5 | * | |
6 | * Copyright (C) 1996 Paul Mackerras. | |
1da177e4 LT |
7 | */ |
8 | ||
9 | /* | |
10 | * TODO: | |
11 | * handle 2 drives | |
12 | * handle GCR disks | |
13 | */ | |
14 | ||
b3025457 BH |
15 | #undef DEBUG |
16 | ||
1da177e4 LT |
17 | #include <linux/stddef.h> |
18 | #include <linux/kernel.h> | |
174cd4b1 | 19 | #include <linux/sched/signal.h> |
1da177e4 LT |
20 | #include <linux/timer.h> |
21 | #include <linux/delay.h> | |
22 | #include <linux/fd.h> | |
23 | #include <linux/ioctl.h> | |
8ccb8cb1 | 24 | #include <linux/blk-mq.h> |
1da177e4 | 25 | #include <linux/interrupt.h> |
2a48fc0a | 26 | #include <linux/mutex.h> |
1da177e4 | 27 | #include <linux/module.h> |
515729ec | 28 | #include <linux/spinlock.h> |
106fd892 | 29 | #include <linux/wait.h> |
1da177e4 LT |
30 | #include <asm/io.h> |
31 | #include <asm/dbdma.h> | |
32 | #include <asm/prom.h> | |
7c0f6ba6 | 33 | #include <linux/uaccess.h> |
1da177e4 LT |
34 | #include <asm/mediabay.h> |
35 | #include <asm/machdep.h> | |
36 | #include <asm/pmac_feature.h> | |
37 | ||
1da177e4 LT |
38 | #define MAX_FLOPPIES 2 |
39 | ||
b3025457 BH |
40 | static DEFINE_MUTEX(swim3_mutex); |
41 | static struct gendisk *disks[MAX_FLOPPIES]; | |
42 | ||
1da177e4 LT |
43 | enum swim_state { |
44 | idle, | |
45 | locating, | |
46 | seeking, | |
47 | settling, | |
48 | do_transfer, | |
49 | jogging, | |
50 | available, | |
51 | revalidating, | |
52 | ejecting | |
53 | }; | |
54 | ||
55 | #define REG(x) unsigned char x; char x ## _pad[15]; | |
56 | ||
57 | /* | |
58 | * The names for these registers mostly represent speculation on my part. | |
59 | * It will be interesting to see how close they are to the names Apple uses. | |
60 | */ | |
61 | struct swim3 { | |
62 | REG(data); | |
63 | REG(timer); /* counts down at 1MHz */ | |
64 | REG(error); | |
65 | REG(mode); | |
66 | REG(select); /* controls CA0, CA1, CA2 and LSTRB signals */ | |
67 | REG(setup); | |
68 | REG(control); /* writing bits clears them */ | |
69 | REG(status); /* writing bits sets them in control */ | |
70 | REG(intr); | |
71 | REG(nseek); /* # tracks to seek */ | |
72 | REG(ctrack); /* current track number */ | |
73 | REG(csect); /* current sector number */ | |
74 | REG(gap3); /* size of gap 3 in track format */ | |
75 | REG(sector); /* sector # to read or write */ | |
76 | REG(nsect); /* # sectors to read or write */ | |
77 | REG(intr_enable); | |
78 | }; | |
79 | ||
80 | #define control_bic control | |
81 | #define control_bis status | |
82 | ||
83 | /* Bits in select register */ | |
84 | #define CA_MASK 7 | |
85 | #define LSTRB 8 | |
86 | ||
87 | /* Bits in control register */ | |
88 | #define DO_SEEK 0x80 | |
89 | #define FORMAT 0x40 | |
90 | #define SELECT 0x20 | |
91 | #define WRITE_SECTORS 0x10 | |
92 | #define DO_ACTION 0x08 | |
93 | #define DRIVE2_ENABLE 0x04 | |
94 | #define DRIVE_ENABLE 0x02 | |
95 | #define INTR_ENABLE 0x01 | |
96 | ||
97 | /* Bits in status register */ | |
98 | #define FIFO_1BYTE 0x80 | |
99 | #define FIFO_2BYTE 0x40 | |
100 | #define ERROR 0x20 | |
101 | #define DATA 0x08 | |
102 | #define RDDATA 0x04 | |
103 | #define INTR_PENDING 0x02 | |
104 | #define MARK_BYTE 0x01 | |
105 | ||
106 | /* Bits in intr and intr_enable registers */ | |
107 | #define ERROR_INTR 0x20 | |
108 | #define DATA_CHANGED 0x10 | |
109 | #define TRANSFER_DONE 0x08 | |
110 | #define SEEN_SECTOR 0x04 | |
111 | #define SEEK_DONE 0x02 | |
112 | #define TIMER_DONE 0x01 | |
113 | ||
114 | /* Bits in error register */ | |
115 | #define ERR_DATA_CRC 0x80 | |
116 | #define ERR_ADDR_CRC 0x40 | |
117 | #define ERR_OVERRUN 0x04 | |
118 | #define ERR_UNDERRUN 0x01 | |
119 | ||
120 | /* Bits in setup register */ | |
121 | #define S_SW_RESET 0x80 | |
122 | #define S_GCR_WRITE 0x40 | |
123 | #define S_IBM_DRIVE 0x20 | |
124 | #define S_TEST_MODE 0x10 | |
125 | #define S_FCLK_DIV2 0x08 | |
126 | #define S_GCR 0x04 | |
127 | #define S_COPY_PROT 0x02 | |
128 | #define S_INV_WDATA 0x01 | |
129 | ||
130 | /* Select values for swim3_action */ | |
131 | #define SEEK_POSITIVE 0 | |
132 | #define SEEK_NEGATIVE 4 | |
133 | #define STEP 1 | |
134 | #define MOTOR_ON 2 | |
135 | #define MOTOR_OFF 6 | |
136 | #define INDEX 3 | |
137 | #define EJECT 7 | |
138 | #define SETMFM 9 | |
139 | #define SETGCR 13 | |
140 | ||
141 | /* Select values for swim3_select and swim3_readbit */ | |
142 | #define STEP_DIR 0 | |
143 | #define STEPPING 1 | |
144 | #define MOTOR_ON 2 | |
145 | #define RELAX 3 /* also eject in progress */ | |
146 | #define READ_DATA_0 4 | |
56a1c5ee | 147 | #define ONEMEG_DRIVE 5 |
1da177e4 LT |
148 | #define SINGLE_SIDED 6 /* drive or diskette is 4MB type? */ |
149 | #define DRIVE_PRESENT 7 | |
150 | #define DISK_IN 8 | |
151 | #define WRITE_PROT 9 | |
152 | #define TRACK_ZERO 10 | |
153 | #define TACHO 11 | |
154 | #define READ_DATA_1 12 | |
56a1c5ee | 155 | #define GCR_MODE 13 |
1da177e4 | 156 | #define SEEK_COMPLETE 14 |
56a1c5ee | 157 | #define TWOMEG_MEDIA 15 |
1da177e4 LT |
158 | |
159 | /* Definitions of values used in writing and formatting */ | |
160 | #define DATA_ESCAPE 0x99 | |
161 | #define GCR_SYNC_EXC 0x3f | |
162 | #define GCR_SYNC_CONV 0x80 | |
163 | #define GCR_FIRST_MARK 0xd5 | |
164 | #define GCR_SECOND_MARK 0xaa | |
165 | #define GCR_ADDR_MARK "\xd5\xaa\x00" | |
166 | #define GCR_DATA_MARK "\xd5\xaa\x0b" | |
167 | #define GCR_SLIP_BYTE "\x27\xaa" | |
168 | #define GCR_SELF_SYNC "\x3f\xbf\x1e\x34\x3c\x3f" | |
169 | ||
170 | #define DATA_99 "\x99\x99" | |
171 | #define MFM_ADDR_MARK "\x99\xa1\x99\xa1\x99\xa1\x99\xfe" | |
172 | #define MFM_INDEX_MARK "\x99\xc2\x99\xc2\x99\xc2\x99\xfc" | |
173 | #define MFM_GAP_LEN 12 | |
174 | ||
175 | struct floppy_state { | |
176 | enum swim_state state; | |
177 | struct swim3 __iomem *swim3; /* hardware registers */ | |
178 | struct dbdma_regs __iomem *dma; /* DMA controller registers */ | |
179 | int swim3_intr; /* interrupt number for SWIM3 */ | |
180 | int dma_intr; /* interrupt number for DMA channel */ | |
181 | int cur_cyl; /* cylinder head is on, or -1 */ | |
182 | int cur_sector; /* last sector we saw go past */ | |
183 | int req_cyl; /* the cylinder for the current r/w request */ | |
184 | int head; /* head number ditto */ | |
185 | int req_sector; /* sector number ditto */ | |
186 | int scount; /* # sectors we're transferring at present */ | |
187 | int retries; | |
188 | int settle_time; | |
189 | int secpercyl; /* disk geometry information */ | |
190 | int secpertrack; | |
191 | int total_secs; | |
192 | int write_prot; /* 1 if write-protected, 0 if not, -1 dunno */ | |
193 | struct dbdma_cmd *dma_cmd; | |
194 | int ref_count; | |
195 | int expect_cyl; | |
196 | struct timer_list timeout; | |
197 | int timeout_pending; | |
198 | int ejected; | |
199 | wait_queue_head_t wait; | |
200 | int wanted; | |
d58b0c39 | 201 | struct macio_dev *mdev; |
1da177e4 | 202 | char dbdma_cmd_space[5 * sizeof(struct dbdma_cmd)]; |
b3025457 BH |
203 | int index; |
204 | struct request *cur_req; | |
8ccb8cb1 | 205 | struct blk_mq_tag_set tag_set; |
1da177e4 LT |
206 | }; |
207 | ||
b3025457 BH |
208 | #define swim3_err(fmt, arg...) dev_err(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) |
209 | #define swim3_warn(fmt, arg...) dev_warn(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) | |
210 | #define swim3_info(fmt, arg...) dev_info(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) | |
211 | ||
212 | #ifdef DEBUG | |
213 | #define swim3_dbg(fmt, arg...) dev_dbg(&fs->mdev->ofdev.dev, "[fd%d] " fmt, fs->index, arg) | |
214 | #else | |
215 | #define swim3_dbg(fmt, arg...) do { } while(0) | |
216 | #endif | |
217 | ||
1da177e4 LT |
218 | static struct floppy_state floppy_states[MAX_FLOPPIES]; |
219 | static int floppy_count = 0; | |
220 | static DEFINE_SPINLOCK(swim3_lock); | |
221 | ||
222 | static unsigned short write_preamble[] = { | |
223 | 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, 0x4e4e, /* gap field */ | |
224 | 0, 0, 0, 0, 0, 0, /* sync field */ | |
225 | 0x99a1, 0x99a1, 0x99a1, 0x99fb, /* data address mark */ | |
226 | 0x990f /* no escape for 512 bytes */ | |
227 | }; | |
228 | ||
229 | static unsigned short write_postamble[] = { | |
230 | 0x9904, /* insert CRC */ | |
231 | 0x4e4e, 0x4e4e, | |
232 | 0x9908, /* stop writing */ | |
233 | 0, 0, 0, 0, 0, 0 | |
234 | }; | |
235 | ||
1da177e4 | 236 | static void seek_track(struct floppy_state *fs, int n); |
1da177e4 | 237 | static void act(struct floppy_state *fs); |
b5775a6b KC |
238 | static void scan_timeout(struct timer_list *t); |
239 | static void seek_timeout(struct timer_list *t); | |
240 | static void settle_timeout(struct timer_list *t); | |
241 | static void xfer_timeout(struct timer_list *t); | |
7d12e780 DH |
242 | static irqreturn_t swim3_interrupt(int irq, void *dev_id); |
243 | /*static void fd_dma_interrupt(int irq, void *dev_id);*/ | |
1da177e4 LT |
244 | static int grab_drive(struct floppy_state *fs, enum swim_state state, |
245 | int interruptible); | |
246 | static void release_drive(struct floppy_state *fs); | |
247 | static int fd_eject(struct floppy_state *fs); | |
b4d9a442 | 248 | static int floppy_ioctl(struct block_device *bdev, fmode_t mode, |
1da177e4 | 249 | unsigned int cmd, unsigned long param); |
b4d9a442 | 250 | static int floppy_open(struct block_device *bdev, fmode_t mode); |
db2a144b | 251 | static void floppy_release(struct gendisk *disk, fmode_t mode); |
4bbde777 TH |
252 | static unsigned int floppy_check_events(struct gendisk *disk, |
253 | unsigned int clearing); | |
1da177e4 | 254 | static int floppy_revalidate(struct gendisk *disk); |
1da177e4 | 255 | |
2a842aca | 256 | static bool swim3_end_request(struct floppy_state *fs, blk_status_t err, unsigned int nr_bytes) |
f4bd4b90 | 257 | { |
b3025457 | 258 | struct request *req = fs->cur_req; |
f4bd4b90 | 259 | |
b3025457 BH |
260 | swim3_dbg(" end request, err=%d nr_bytes=%d, cur_req=%p\n", |
261 | err, nr_bytes, req); | |
f4bd4b90 | 262 | |
b3025457 BH |
263 | if (err) |
264 | nr_bytes = blk_rq_cur_bytes(req); | |
8ccb8cb1 | 265 | if (blk_update_request(req, err, nr_bytes)) |
b3025457 | 266 | return true; |
8ccb8cb1 | 267 | __blk_mq_end_request(req, err); |
b3025457 BH |
268 | fs->cur_req = NULL; |
269 | return false; | |
f4bd4b90 TH |
270 | } |
271 | ||
1da177e4 LT |
272 | static void swim3_select(struct floppy_state *fs, int sel) |
273 | { | |
274 | struct swim3 __iomem *sw = fs->swim3; | |
275 | ||
276 | out_8(&sw->select, RELAX); | |
277 | if (sel & 8) | |
278 | out_8(&sw->control_bis, SELECT); | |
279 | else | |
280 | out_8(&sw->control_bic, SELECT); | |
281 | out_8(&sw->select, sel & CA_MASK); | |
282 | } | |
283 | ||
284 | static void swim3_action(struct floppy_state *fs, int action) | |
285 | { | |
286 | struct swim3 __iomem *sw = fs->swim3; | |
287 | ||
288 | swim3_select(fs, action); | |
289 | udelay(1); | |
290 | out_8(&sw->select, sw->select | LSTRB); | |
291 | udelay(2); | |
292 | out_8(&sw->select, sw->select & ~LSTRB); | |
293 | udelay(1); | |
294 | } | |
295 | ||
296 | static int swim3_readbit(struct floppy_state *fs, int bit) | |
297 | { | |
298 | struct swim3 __iomem *sw = fs->swim3; | |
299 | int stat; | |
300 | ||
301 | swim3_select(fs, bit); | |
302 | udelay(1); | |
303 | stat = in_8(&sw->status); | |
304 | return (stat & DATA) == 0; | |
305 | } | |
306 | ||
8ccb8cb1 OS |
307 | static blk_status_t swim3_queue_rq(struct blk_mq_hw_ctx *hctx, |
308 | const struct blk_mq_queue_data *bd) | |
1da177e4 | 309 | { |
8ccb8cb1 OS |
310 | struct floppy_state *fs = hctx->queue->queuedata; |
311 | struct request *req = bd->rq; | |
1da177e4 LT |
312 | unsigned long x; |
313 | ||
8ccb8cb1 OS |
314 | spin_lock_irq(&swim3_lock); |
315 | if (fs->cur_req || fs->state != idle) { | |
316 | spin_unlock_irq(&swim3_lock); | |
317 | return BLK_STS_DEV_RESOURCE; | |
1da177e4 | 318 | } |
8ccb8cb1 OS |
319 | blk_mq_start_request(req); |
320 | fs->cur_req = req; | |
321 | if (fs->mdev->media_bay && | |
322 | check_media_bay(fs->mdev->media_bay) != MB_FD) { | |
323 | swim3_dbg("%s", " media bay absent, dropping req\n"); | |
324 | swim3_end_request(fs, BLK_STS_IOERR, 0); | |
325 | goto out; | |
326 | } | |
327 | if (fs->ejected) { | |
328 | swim3_dbg("%s", " disk ejected\n"); | |
329 | swim3_end_request(fs, BLK_STS_IOERR, 0); | |
330 | goto out; | |
331 | } | |
332 | if (rq_data_dir(req) == WRITE) { | |
333 | if (fs->write_prot < 0) | |
334 | fs->write_prot = swim3_readbit(fs, WRITE_PROT); | |
335 | if (fs->write_prot) { | |
336 | swim3_dbg("%s", " try to write, disk write protected\n"); | |
2a842aca | 337 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
8ccb8cb1 | 338 | goto out; |
1da177e4 | 339 | } |
1da177e4 | 340 | } |
1da177e4 | 341 | |
8ccb8cb1 OS |
342 | /* |
343 | * Do not remove the cast. blk_rq_pos(req) is now a sector_t and can be | |
344 | * 64 bits, but it will never go past 32 bits for this driver anyway, so | |
345 | * we can safely cast it down and not have to do a 64/32 division | |
346 | */ | |
347 | fs->req_cyl = ((long)blk_rq_pos(req)) / fs->secpercyl; | |
348 | x = ((long)blk_rq_pos(req)) % fs->secpercyl; | |
349 | fs->head = x / fs->secpertrack; | |
350 | fs->req_sector = x % fs->secpertrack + 1; | |
351 | fs->state = do_transfer; | |
352 | fs->retries = 0; | |
353 | ||
354 | act(fs); | |
355 | ||
356 | out: | |
357 | spin_unlock_irq(&swim3_lock); | |
358 | return BLK_STS_OK; | |
b3025457 BH |
359 | } |
360 | ||
1da177e4 | 361 | static void set_timeout(struct floppy_state *fs, int nticks, |
b5775a6b | 362 | void (*proc)(struct timer_list *t)) |
1da177e4 | 363 | { |
1da177e4 LT |
364 | if (fs->timeout_pending) |
365 | del_timer(&fs->timeout); | |
366 | fs->timeout.expires = jiffies + nticks; | |
841b86f3 | 367 | fs->timeout.function = proc; |
1da177e4 LT |
368 | add_timer(&fs->timeout); |
369 | fs->timeout_pending = 1; | |
1da177e4 LT |
370 | } |
371 | ||
372 | static inline void scan_track(struct floppy_state *fs) | |
373 | { | |
374 | struct swim3 __iomem *sw = fs->swim3; | |
375 | ||
376 | swim3_select(fs, READ_DATA_0); | |
377 | in_8(&sw->intr); /* clear SEEN_SECTOR bit */ | |
378 | in_8(&sw->error); | |
379 | out_8(&sw->intr_enable, SEEN_SECTOR); | |
380 | out_8(&sw->control_bis, DO_ACTION); | |
381 | /* enable intr when track found */ | |
382 | set_timeout(fs, HZ, scan_timeout); /* enable timeout */ | |
383 | } | |
384 | ||
385 | static inline void seek_track(struct floppy_state *fs, int n) | |
386 | { | |
387 | struct swim3 __iomem *sw = fs->swim3; | |
388 | ||
389 | if (n >= 0) { | |
390 | swim3_action(fs, SEEK_POSITIVE); | |
391 | sw->nseek = n; | |
392 | } else { | |
393 | swim3_action(fs, SEEK_NEGATIVE); | |
394 | sw->nseek = -n; | |
395 | } | |
396 | fs->expect_cyl = (fs->cur_cyl >= 0)? fs->cur_cyl + n: -1; | |
397 | swim3_select(fs, STEP); | |
398 | in_8(&sw->error); | |
399 | /* enable intr when seek finished */ | |
400 | out_8(&sw->intr_enable, SEEK_DONE); | |
401 | out_8(&sw->control_bis, DO_SEEK); | |
402 | set_timeout(fs, 3*HZ, seek_timeout); /* enable timeout */ | |
403 | fs->settle_time = 0; | |
404 | } | |
405 | ||
b60b270b CH |
406 | /* |
407 | * XXX: this is a horrible hack, but at least allows ppc32 to get | |
408 | * out of defining virt_to_bus, and this driver out of using the | |
409 | * deprecated block layer bounce buffering for highmem addresses | |
410 | * for no good reason. | |
411 | */ | |
412 | static unsigned long swim3_phys_to_bus(phys_addr_t paddr) | |
413 | { | |
414 | return paddr + PCI_DRAM_OFFSET; | |
415 | } | |
416 | ||
417 | static phys_addr_t swim3_bio_phys(struct bio *bio) | |
418 | { | |
419 | return page_to_phys(bio_page(bio)) + bio_offset(bio); | |
420 | } | |
421 | ||
1da177e4 | 422 | static inline void init_dma(struct dbdma_cmd *cp, int cmd, |
b60b270b | 423 | phys_addr_t paddr, int count) |
1da177e4 | 424 | { |
f5718726 DG |
425 | cp->req_count = cpu_to_le16(count); |
426 | cp->command = cpu_to_le16(cmd); | |
b60b270b | 427 | cp->phy_addr = cpu_to_le32(swim3_phys_to_bus(paddr)); |
1da177e4 LT |
428 | cp->xfer_status = 0; |
429 | } | |
430 | ||
431 | static inline void setup_transfer(struct floppy_state *fs) | |
432 | { | |
433 | int n; | |
434 | struct swim3 __iomem *sw = fs->swim3; | |
435 | struct dbdma_cmd *cp = fs->dma_cmd; | |
436 | struct dbdma_regs __iomem *dr = fs->dma; | |
b3025457 | 437 | struct request *req = fs->cur_req; |
1da177e4 | 438 | |
b3025457 BH |
439 | if (blk_rq_cur_sectors(req) <= 0) { |
440 | swim3_warn("%s", "Transfer 0 sectors ?\n"); | |
1da177e4 LT |
441 | return; |
442 | } | |
b3025457 | 443 | if (rq_data_dir(req) == WRITE) |
1da177e4 LT |
444 | n = 1; |
445 | else { | |
446 | n = fs->secpertrack - fs->req_sector + 1; | |
b3025457 BH |
447 | if (n > blk_rq_cur_sectors(req)) |
448 | n = blk_rq_cur_sectors(req); | |
1da177e4 | 449 | } |
b3025457 BH |
450 | |
451 | swim3_dbg(" setup xfer at sect %d (of %d) head %d for %d\n", | |
452 | fs->req_sector, fs->secpertrack, fs->head, n); | |
453 | ||
1da177e4 LT |
454 | fs->scount = n; |
455 | swim3_select(fs, fs->head? READ_DATA_1: READ_DATA_0); | |
456 | out_8(&sw->sector, fs->req_sector); | |
457 | out_8(&sw->nsect, n); | |
458 | out_8(&sw->gap3, 0); | |
b60b270b | 459 | out_le32(&dr->cmdptr, swim3_phys_to_bus(virt_to_phys(cp))); |
b3025457 | 460 | if (rq_data_dir(req) == WRITE) { |
1da177e4 | 461 | /* Set up 3 dma commands: write preamble, data, postamble */ |
b60b270b CH |
462 | init_dma(cp, OUTPUT_MORE, virt_to_phys(write_preamble), |
463 | sizeof(write_preamble)); | |
1da177e4 | 464 | ++cp; |
b60b270b | 465 | init_dma(cp, OUTPUT_MORE, swim3_bio_phys(req->bio), 512); |
1da177e4 | 466 | ++cp; |
b60b270b CH |
467 | init_dma(cp, OUTPUT_LAST, virt_to_phys(write_postamble), |
468 | sizeof(write_postamble)); | |
1da177e4 | 469 | } else { |
b60b270b | 470 | init_dma(cp, INPUT_LAST, swim3_bio_phys(req->bio), n * 512); |
1da177e4 LT |
471 | } |
472 | ++cp; | |
473 | out_le16(&cp->command, DBDMA_STOP); | |
474 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
475 | in_8(&sw->error); | |
476 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
b3025457 | 477 | if (rq_data_dir(req) == WRITE) |
1da177e4 LT |
478 | out_8(&sw->control_bis, WRITE_SECTORS); |
479 | in_8(&sw->intr); | |
480 | out_le32(&dr->control, (RUN << 16) | RUN); | |
481 | /* enable intr when transfer complete */ | |
482 | out_8(&sw->intr_enable, TRANSFER_DONE); | |
483 | out_8(&sw->control_bis, DO_ACTION); | |
484 | set_timeout(fs, 2*HZ, xfer_timeout); /* enable timeout */ | |
485 | } | |
486 | ||
487 | static void act(struct floppy_state *fs) | |
488 | { | |
489 | for (;;) { | |
b3025457 BH |
490 | swim3_dbg(" act loop, state=%d, req_cyl=%d, cur_cyl=%d\n", |
491 | fs->state, fs->req_cyl, fs->cur_cyl); | |
492 | ||
1da177e4 LT |
493 | switch (fs->state) { |
494 | case idle: | |
495 | return; /* XXX shouldn't get here */ | |
496 | ||
497 | case locating: | |
498 | if (swim3_readbit(fs, TRACK_ZERO)) { | |
b3025457 | 499 | swim3_dbg("%s", " locate track 0\n"); |
1da177e4 LT |
500 | fs->cur_cyl = 0; |
501 | if (fs->req_cyl == 0) | |
502 | fs->state = do_transfer; | |
503 | else | |
504 | fs->state = seeking; | |
505 | break; | |
506 | } | |
507 | scan_track(fs); | |
508 | return; | |
509 | ||
510 | case seeking: | |
511 | if (fs->cur_cyl < 0) { | |
512 | fs->expect_cyl = -1; | |
513 | fs->state = locating; | |
514 | break; | |
515 | } | |
516 | if (fs->req_cyl == fs->cur_cyl) { | |
b3025457 | 517 | swim3_warn("%s", "Whoops, seeking 0\n"); |
1da177e4 LT |
518 | fs->state = do_transfer; |
519 | break; | |
520 | } | |
521 | seek_track(fs, fs->req_cyl - fs->cur_cyl); | |
522 | return; | |
523 | ||
524 | case settling: | |
525 | /* check for SEEK_COMPLETE after 30ms */ | |
526 | fs->settle_time = (HZ + 32) / 33; | |
527 | set_timeout(fs, fs->settle_time, settle_timeout); | |
528 | return; | |
529 | ||
530 | case do_transfer: | |
531 | if (fs->cur_cyl != fs->req_cyl) { | |
532 | if (fs->retries > 5) { | |
b3025457 BH |
533 | swim3_err("Wrong cylinder in transfer, want: %d got %d\n", |
534 | fs->req_cyl, fs->cur_cyl); | |
2a842aca | 535 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
536 | fs->state = idle; |
537 | return; | |
538 | } | |
539 | fs->state = seeking; | |
540 | break; | |
541 | } | |
542 | setup_transfer(fs); | |
543 | return; | |
544 | ||
545 | case jogging: | |
546 | seek_track(fs, -5); | |
547 | return; | |
548 | ||
549 | default: | |
b3025457 | 550 | swim3_err("Unknown state %d\n", fs->state); |
1da177e4 LT |
551 | return; |
552 | } | |
553 | } | |
554 | } | |
555 | ||
b5775a6b | 556 | static void scan_timeout(struct timer_list *t) |
1da177e4 | 557 | { |
b5775a6b | 558 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 | 559 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 BH |
560 | unsigned long flags; |
561 | ||
562 | swim3_dbg("* scan timeout, state=%d\n", fs->state); | |
1da177e4 | 563 | |
b3025457 | 564 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
565 | fs->timeout_pending = 0; |
566 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
567 | out_8(&sw->select, RELAX); | |
568 | out_8(&sw->intr_enable, 0); | |
569 | fs->cur_cyl = -1; | |
570 | if (fs->retries > 5) { | |
2a842aca | 571 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 | 572 | fs->state = idle; |
1da177e4 LT |
573 | } else { |
574 | fs->state = jogging; | |
575 | act(fs); | |
576 | } | |
b3025457 | 577 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
578 | } |
579 | ||
b5775a6b | 580 | static void seek_timeout(struct timer_list *t) |
1da177e4 | 581 | { |
b5775a6b | 582 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 | 583 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 BH |
584 | unsigned long flags; |
585 | ||
586 | swim3_dbg("* seek timeout, state=%d\n", fs->state); | |
1da177e4 | 587 | |
b3025457 | 588 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
589 | fs->timeout_pending = 0; |
590 | out_8(&sw->control_bic, DO_SEEK); | |
591 | out_8(&sw->select, RELAX); | |
592 | out_8(&sw->intr_enable, 0); | |
b3025457 | 593 | swim3_err("%s", "Seek timeout\n"); |
2a842aca | 594 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 | 595 | fs->state = idle; |
b3025457 | 596 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
597 | } |
598 | ||
b5775a6b | 599 | static void settle_timeout(struct timer_list *t) |
1da177e4 | 600 | { |
b5775a6b | 601 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 | 602 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 BH |
603 | unsigned long flags; |
604 | ||
605 | swim3_dbg("* settle timeout, state=%d\n", fs->state); | |
1da177e4 | 606 | |
b3025457 | 607 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
608 | fs->timeout_pending = 0; |
609 | if (swim3_readbit(fs, SEEK_COMPLETE)) { | |
610 | out_8(&sw->select, RELAX); | |
611 | fs->state = locating; | |
612 | act(fs); | |
b3025457 | 613 | goto unlock; |
1da177e4 LT |
614 | } |
615 | out_8(&sw->select, RELAX); | |
616 | if (fs->settle_time < 2*HZ) { | |
617 | ++fs->settle_time; | |
618 | set_timeout(fs, 1, settle_timeout); | |
b3025457 | 619 | goto unlock; |
1da177e4 | 620 | } |
b3025457 | 621 | swim3_err("%s", "Seek settle timeout\n"); |
2a842aca | 622 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 | 623 | fs->state = idle; |
b3025457 BH |
624 | unlock: |
625 | spin_unlock_irqrestore(&swim3_lock, flags); | |
1da177e4 LT |
626 | } |
627 | ||
b5775a6b | 628 | static void xfer_timeout(struct timer_list *t) |
1da177e4 | 629 | { |
b5775a6b | 630 | struct floppy_state *fs = from_timer(fs, t, timeout); |
1da177e4 LT |
631 | struct swim3 __iomem *sw = fs->swim3; |
632 | struct dbdma_regs __iomem *dr = fs->dma; | |
b3025457 | 633 | unsigned long flags; |
1da177e4 LT |
634 | int n; |
635 | ||
b3025457 BH |
636 | swim3_dbg("* xfer timeout, state=%d\n", fs->state); |
637 | ||
638 | spin_lock_irqsave(&swim3_lock, flags); | |
1da177e4 LT |
639 | fs->timeout_pending = 0; |
640 | out_le32(&dr->control, RUN << 16); | |
641 | /* We must wait a bit for dbdma to stop */ | |
642 | for (n = 0; (in_le32(&dr->status) & ACTIVE) && n < 1000; n++) | |
643 | udelay(1); | |
644 | out_8(&sw->intr_enable, 0); | |
645 | out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION); | |
646 | out_8(&sw->select, RELAX); | |
b3025457 BH |
647 | swim3_err("Timeout %sing sector %ld\n", |
648 | (rq_data_dir(fs->cur_req)==WRITE? "writ": "read"), | |
649 | (long)blk_rq_pos(fs->cur_req)); | |
2a842aca | 650 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 | 651 | fs->state = idle; |
b3025457 | 652 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
653 | } |
654 | ||
7d12e780 | 655 | static irqreturn_t swim3_interrupt(int irq, void *dev_id) |
1da177e4 LT |
656 | { |
657 | struct floppy_state *fs = (struct floppy_state *) dev_id; | |
658 | struct swim3 __iomem *sw = fs->swim3; | |
659 | int intr, err, n; | |
660 | int stat, resid; | |
661 | struct dbdma_regs __iomem *dr; | |
662 | struct dbdma_cmd *cp; | |
b3025457 BH |
663 | unsigned long flags; |
664 | struct request *req = fs->cur_req; | |
665 | ||
666 | swim3_dbg("* interrupt, state=%d\n", fs->state); | |
1da177e4 | 667 | |
b3025457 | 668 | spin_lock_irqsave(&swim3_lock, flags); |
1da177e4 LT |
669 | intr = in_8(&sw->intr); |
670 | err = (intr & ERROR_INTR)? in_8(&sw->error): 0; | |
671 | if ((intr & ERROR_INTR) && fs->state != do_transfer) | |
b3025457 BH |
672 | swim3_err("Non-transfer error interrupt: state=%d, dir=%x, intr=%x, err=%x\n", |
673 | fs->state, rq_data_dir(req), intr, err); | |
1da177e4 LT |
674 | switch (fs->state) { |
675 | case locating: | |
676 | if (intr & SEEN_SECTOR) { | |
677 | out_8(&sw->control_bic, DO_ACTION | WRITE_SECTORS); | |
678 | out_8(&sw->select, RELAX); | |
679 | out_8(&sw->intr_enable, 0); | |
680 | del_timer(&fs->timeout); | |
681 | fs->timeout_pending = 0; | |
682 | if (sw->ctrack == 0xff) { | |
b3025457 | 683 | swim3_err("%s", "Seen sector but cyl=ff?\n"); |
1da177e4 LT |
684 | fs->cur_cyl = -1; |
685 | if (fs->retries > 5) { | |
2a842aca | 686 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 | 687 | fs->state = idle; |
1da177e4 LT |
688 | } else { |
689 | fs->state = jogging; | |
690 | act(fs); | |
691 | } | |
692 | break; | |
693 | } | |
694 | fs->cur_cyl = sw->ctrack; | |
695 | fs->cur_sector = sw->csect; | |
696 | if (fs->expect_cyl != -1 && fs->expect_cyl != fs->cur_cyl) | |
b3025457 BH |
697 | swim3_err("Expected cyl %d, got %d\n", |
698 | fs->expect_cyl, fs->cur_cyl); | |
1da177e4 LT |
699 | fs->state = do_transfer; |
700 | act(fs); | |
701 | } | |
702 | break; | |
703 | case seeking: | |
704 | case jogging: | |
705 | if (sw->nseek == 0) { | |
706 | out_8(&sw->control_bic, DO_SEEK); | |
707 | out_8(&sw->select, RELAX); | |
708 | out_8(&sw->intr_enable, 0); | |
709 | del_timer(&fs->timeout); | |
710 | fs->timeout_pending = 0; | |
711 | if (fs->state == seeking) | |
712 | ++fs->retries; | |
713 | fs->state = settling; | |
714 | act(fs); | |
715 | } | |
716 | break; | |
717 | case settling: | |
718 | out_8(&sw->intr_enable, 0); | |
719 | del_timer(&fs->timeout); | |
720 | fs->timeout_pending = 0; | |
721 | act(fs); | |
722 | break; | |
723 | case do_transfer: | |
724 | if ((intr & (ERROR_INTR | TRANSFER_DONE)) == 0) | |
725 | break; | |
726 | out_8(&sw->intr_enable, 0); | |
727 | out_8(&sw->control_bic, WRITE_SECTORS | DO_ACTION); | |
728 | out_8(&sw->select, RELAX); | |
729 | del_timer(&fs->timeout); | |
730 | fs->timeout_pending = 0; | |
731 | dr = fs->dma; | |
732 | cp = fs->dma_cmd; | |
b3025457 | 733 | if (rq_data_dir(req) == WRITE) |
1da177e4 LT |
734 | ++cp; |
735 | /* | |
736 | * Check that the main data transfer has finished. | |
737 | * On writing, the swim3 sometimes doesn't use | |
738 | * up all the bytes of the postamble, so we can still | |
739 | * see DMA active here. That doesn't matter as long | |
740 | * as all the sector data has been transferred. | |
741 | */ | |
742 | if ((intr & ERROR_INTR) == 0 && cp->xfer_status == 0) { | |
743 | /* wait a little while for DMA to complete */ | |
744 | for (n = 0; n < 100; ++n) { | |
745 | if (cp->xfer_status != 0) | |
746 | break; | |
747 | udelay(1); | |
748 | barrier(); | |
749 | } | |
750 | } | |
751 | /* turn off DMA */ | |
752 | out_le32(&dr->control, (RUN | PAUSE) << 16); | |
f5718726 DG |
753 | stat = le16_to_cpu(cp->xfer_status); |
754 | resid = le16_to_cpu(cp->res_count); | |
1da177e4 LT |
755 | if (intr & ERROR_INTR) { |
756 | n = fs->scount - 1 - resid / 512; | |
757 | if (n > 0) { | |
b3025457 | 758 | blk_update_request(req, 0, n << 9); |
1da177e4 LT |
759 | fs->req_sector += n; |
760 | } | |
761 | if (fs->retries < 5) { | |
762 | ++fs->retries; | |
763 | act(fs); | |
764 | } else { | |
b3025457 BH |
765 | swim3_err("Error %sing block %ld (err=%x)\n", |
766 | rq_data_dir(req) == WRITE? "writ": "read", | |
767 | (long)blk_rq_pos(req), err); | |
2a842aca | 768 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 LT |
769 | fs->state = idle; |
770 | } | |
771 | } else { | |
772 | if ((stat & ACTIVE) == 0 || resid != 0) { | |
773 | /* musta been an error */ | |
b3025457 BH |
774 | swim3_err("fd dma error: stat=%x resid=%d\n", stat, resid); |
775 | swim3_err(" state=%d, dir=%x, intr=%x, err=%x\n", | |
776 | fs->state, rq_data_dir(req), intr, err); | |
2a842aca | 777 | swim3_end_request(fs, BLK_STS_IOERR, 0); |
1da177e4 | 778 | fs->state = idle; |
1da177e4 LT |
779 | break; |
780 | } | |
b3025457 BH |
781 | fs->retries = 0; |
782 | if (swim3_end_request(fs, 0, fs->scount << 9)) { | |
1da177e4 LT |
783 | fs->req_sector += fs->scount; |
784 | if (fs->req_sector > fs->secpertrack) { | |
785 | fs->req_sector -= fs->secpertrack; | |
786 | if (++fs->head > 1) { | |
787 | fs->head = 0; | |
788 | ++fs->req_cyl; | |
789 | } | |
790 | } | |
791 | act(fs); | |
467ca759 TH |
792 | } else |
793 | fs->state = idle; | |
1da177e4 | 794 | } |
1da177e4 LT |
795 | break; |
796 | default: | |
b3025457 | 797 | swim3_err("Don't know what to do in state %d\n", fs->state); |
1da177e4 | 798 | } |
b3025457 | 799 | spin_unlock_irqrestore(&swim3_lock, flags); |
1da177e4 LT |
800 | return IRQ_HANDLED; |
801 | } | |
802 | ||
803 | /* | |
7d12e780 | 804 | static void fd_dma_interrupt(int irq, void *dev_id) |
1da177e4 LT |
805 | { |
806 | } | |
807 | */ | |
808 | ||
b3025457 | 809 | /* Called under the mutex to grab exclusive access to a drive */ |
1da177e4 LT |
810 | static int grab_drive(struct floppy_state *fs, enum swim_state state, |
811 | int interruptible) | |
812 | { | |
813 | unsigned long flags; | |
814 | ||
b3025457 BH |
815 | swim3_dbg("%s", "-> grab drive\n"); |
816 | ||
817 | spin_lock_irqsave(&swim3_lock, flags); | |
818 | if (fs->state != idle && fs->state != available) { | |
1da177e4 | 819 | ++fs->wanted; |
106fd892 AB |
820 | /* this will enable irqs in order to sleep */ |
821 | if (!interruptible) | |
822 | wait_event_lock_irq(fs->wait, | |
823 | fs->state == available, | |
824 | swim3_lock); | |
825 | else if (wait_event_interruptible_lock_irq(fs->wait, | |
826 | fs->state == available, | |
827 | swim3_lock)) { | |
828 | --fs->wanted; | |
b3025457 | 829 | spin_unlock_irqrestore(&swim3_lock, flags); |
106fd892 | 830 | return -EINTR; |
1da177e4 LT |
831 | } |
832 | --fs->wanted; | |
833 | } | |
834 | fs->state = state; | |
b3025457 BH |
835 | spin_unlock_irqrestore(&swim3_lock, flags); |
836 | ||
1da177e4 LT |
837 | return 0; |
838 | } | |
839 | ||
840 | static void release_drive(struct floppy_state *fs) | |
841 | { | |
8ccb8cb1 | 842 | struct request_queue *q = disks[fs->index]->queue; |
1da177e4 LT |
843 | unsigned long flags; |
844 | ||
b3025457 BH |
845 | swim3_dbg("%s", "-> release drive\n"); |
846 | ||
847 | spin_lock_irqsave(&swim3_lock, flags); | |
1da177e4 | 848 | fs->state = idle; |
b3025457 | 849 | spin_unlock_irqrestore(&swim3_lock, flags); |
8ccb8cb1 OS |
850 | |
851 | blk_mq_freeze_queue(q); | |
852 | blk_mq_quiesce_queue(q); | |
853 | blk_mq_unquiesce_queue(q); | |
854 | blk_mq_unfreeze_queue(q); | |
1da177e4 LT |
855 | } |
856 | ||
857 | static int fd_eject(struct floppy_state *fs) | |
858 | { | |
859 | int err, n; | |
860 | ||
861 | err = grab_drive(fs, ejecting, 1); | |
862 | if (err) | |
863 | return err; | |
864 | swim3_action(fs, EJECT); | |
865 | for (n = 20; n > 0; --n) { | |
866 | if (signal_pending(current)) { | |
867 | err = -EINTR; | |
868 | break; | |
869 | } | |
870 | swim3_select(fs, RELAX); | |
86e84862 | 871 | schedule_timeout_interruptible(1); |
1da177e4 LT |
872 | if (swim3_readbit(fs, DISK_IN) == 0) |
873 | break; | |
874 | } | |
875 | swim3_select(fs, RELAX); | |
876 | udelay(150); | |
877 | fs->ejected = 1; | |
878 | release_drive(fs); | |
879 | return err; | |
880 | } | |
881 | ||
882 | static struct floppy_struct floppy_type = | |
883 | { 2880,18,2,80,0,0x1B,0x00,0xCF,0x6C,NULL }; /* 7 1.44MB 3.5" */ | |
884 | ||
8a6cfeb6 | 885 | static int floppy_locked_ioctl(struct block_device *bdev, fmode_t mode, |
1da177e4 LT |
886 | unsigned int cmd, unsigned long param) |
887 | { | |
b4d9a442 | 888 | struct floppy_state *fs = bdev->bd_disk->private_data; |
1da177e4 LT |
889 | int err; |
890 | ||
891 | if ((cmd & 0x80) && !capable(CAP_SYS_ADMIN)) | |
892 | return -EPERM; | |
893 | ||
d58b0c39 BH |
894 | if (fs->mdev->media_bay && |
895 | check_media_bay(fs->mdev->media_bay) != MB_FD) | |
1da177e4 LT |
896 | return -ENXIO; |
897 | ||
898 | switch (cmd) { | |
899 | case FDEJECT: | |
900 | if (fs->ref_count != 1) | |
901 | return -EBUSY; | |
902 | err = fd_eject(fs); | |
903 | return err; | |
904 | case FDGETPRM: | |
905 | if (copy_to_user((void __user *) param, &floppy_type, | |
906 | sizeof(struct floppy_struct))) | |
907 | return -EFAULT; | |
908 | return 0; | |
909 | } | |
910 | return -ENOTTY; | |
911 | } | |
912 | ||
8a6cfeb6 AB |
913 | static int floppy_ioctl(struct block_device *bdev, fmode_t mode, |
914 | unsigned int cmd, unsigned long param) | |
915 | { | |
916 | int ret; | |
917 | ||
2a48fc0a | 918 | mutex_lock(&swim3_mutex); |
8a6cfeb6 | 919 | ret = floppy_locked_ioctl(bdev, mode, cmd, param); |
2a48fc0a | 920 | mutex_unlock(&swim3_mutex); |
8a6cfeb6 AB |
921 | |
922 | return ret; | |
923 | } | |
924 | ||
b4d9a442 | 925 | static int floppy_open(struct block_device *bdev, fmode_t mode) |
1da177e4 | 926 | { |
b4d9a442 | 927 | struct floppy_state *fs = bdev->bd_disk->private_data; |
1da177e4 LT |
928 | struct swim3 __iomem *sw = fs->swim3; |
929 | int n, err = 0; | |
930 | ||
931 | if (fs->ref_count == 0) { | |
d58b0c39 BH |
932 | if (fs->mdev->media_bay && |
933 | check_media_bay(fs->mdev->media_bay) != MB_FD) | |
1da177e4 LT |
934 | return -ENXIO; |
935 | out_8(&sw->setup, S_IBM_DRIVE | S_FCLK_DIV2); | |
936 | out_8(&sw->control_bic, 0xff); | |
937 | out_8(&sw->mode, 0x95); | |
938 | udelay(10); | |
939 | out_8(&sw->intr_enable, 0); | |
940 | out_8(&sw->control_bis, DRIVE_ENABLE | INTR_ENABLE); | |
941 | swim3_action(fs, MOTOR_ON); | |
942 | fs->write_prot = -1; | |
943 | fs->cur_cyl = -1; | |
944 | for (n = 0; n < 2 * HZ; ++n) { | |
945 | if (n >= HZ/30 && swim3_readbit(fs, SEEK_COMPLETE)) | |
946 | break; | |
947 | if (signal_pending(current)) { | |
948 | err = -EINTR; | |
949 | break; | |
950 | } | |
951 | swim3_select(fs, RELAX); | |
86e84862 | 952 | schedule_timeout_interruptible(1); |
1da177e4 LT |
953 | } |
954 | if (err == 0 && (swim3_readbit(fs, SEEK_COMPLETE) == 0 | |
955 | || swim3_readbit(fs, DISK_IN) == 0)) | |
956 | err = -ENXIO; | |
957 | swim3_action(fs, SETMFM); | |
958 | swim3_select(fs, RELAX); | |
959 | ||
b4d9a442 | 960 | } else if (fs->ref_count == -1 || mode & FMODE_EXCL) |
1da177e4 LT |
961 | return -EBUSY; |
962 | ||
b4d9a442 AV |
963 | if (err == 0 && (mode & FMODE_NDELAY) == 0 |
964 | && (mode & (FMODE_READ|FMODE_WRITE))) { | |
3dcbad29 CH |
965 | if (bdev_check_media_change(bdev)) |
966 | floppy_revalidate(bdev->bd_disk); | |
1da177e4 LT |
967 | if (fs->ejected) |
968 | err = -ENXIO; | |
969 | } | |
970 | ||
b4d9a442 | 971 | if (err == 0 && (mode & FMODE_WRITE)) { |
1da177e4 LT |
972 | if (fs->write_prot < 0) |
973 | fs->write_prot = swim3_readbit(fs, WRITE_PROT); | |
974 | if (fs->write_prot) | |
975 | err = -EROFS; | |
976 | } | |
977 | ||
978 | if (err) { | |
979 | if (fs->ref_count == 0) { | |
980 | swim3_action(fs, MOTOR_OFF); | |
981 | out_8(&sw->control_bic, DRIVE_ENABLE | INTR_ENABLE); | |
982 | swim3_select(fs, RELAX); | |
983 | } | |
984 | return err; | |
985 | } | |
986 | ||
b4d9a442 | 987 | if (mode & FMODE_EXCL) |
1da177e4 LT |
988 | fs->ref_count = -1; |
989 | else | |
990 | ++fs->ref_count; | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
6e9624b8 AB |
995 | static int floppy_unlocked_open(struct block_device *bdev, fmode_t mode) |
996 | { | |
997 | int ret; | |
998 | ||
2a48fc0a | 999 | mutex_lock(&swim3_mutex); |
6e9624b8 | 1000 | ret = floppy_open(bdev, mode); |
2a48fc0a | 1001 | mutex_unlock(&swim3_mutex); |
6e9624b8 AB |
1002 | |
1003 | return ret; | |
1004 | } | |
1005 | ||
db2a144b | 1006 | static void floppy_release(struct gendisk *disk, fmode_t mode) |
1da177e4 | 1007 | { |
b4d9a442 | 1008 | struct floppy_state *fs = disk->private_data; |
1da177e4 | 1009 | struct swim3 __iomem *sw = fs->swim3; |
b3025457 | 1010 | |
2a48fc0a | 1011 | mutex_lock(&swim3_mutex); |
296dcc40 FT |
1012 | if (fs->ref_count > 0) |
1013 | --fs->ref_count; | |
1014 | else if (fs->ref_count == -1) | |
1015 | fs->ref_count = 0; | |
1016 | if (fs->ref_count == 0) { | |
1da177e4 LT |
1017 | swim3_action(fs, MOTOR_OFF); |
1018 | out_8(&sw->control_bic, 0xff); | |
1019 | swim3_select(fs, RELAX); | |
1020 | } | |
2a48fc0a | 1021 | mutex_unlock(&swim3_mutex); |
1da177e4 LT |
1022 | } |
1023 | ||
4bbde777 TH |
1024 | static unsigned int floppy_check_events(struct gendisk *disk, |
1025 | unsigned int clearing) | |
1da177e4 LT |
1026 | { |
1027 | struct floppy_state *fs = disk->private_data; | |
4bbde777 | 1028 | return fs->ejected ? DISK_EVENT_MEDIA_CHANGE : 0; |
1da177e4 LT |
1029 | } |
1030 | ||
1031 | static int floppy_revalidate(struct gendisk *disk) | |
1032 | { | |
1033 | struct floppy_state *fs = disk->private_data; | |
1034 | struct swim3 __iomem *sw; | |
1035 | int ret, n; | |
1036 | ||
d58b0c39 BH |
1037 | if (fs->mdev->media_bay && |
1038 | check_media_bay(fs->mdev->media_bay) != MB_FD) | |
1da177e4 LT |
1039 | return -ENXIO; |
1040 | ||
1041 | sw = fs->swim3; | |
1042 | grab_drive(fs, revalidating, 0); | |
1043 | out_8(&sw->intr_enable, 0); | |
1044 | out_8(&sw->control_bis, DRIVE_ENABLE); | |
1045 | swim3_action(fs, MOTOR_ON); /* necessary? */ | |
1046 | fs->write_prot = -1; | |
1047 | fs->cur_cyl = -1; | |
1048 | mdelay(1); | |
1049 | for (n = HZ; n > 0; --n) { | |
1050 | if (swim3_readbit(fs, SEEK_COMPLETE)) | |
1051 | break; | |
1052 | if (signal_pending(current)) | |
1053 | break; | |
1054 | swim3_select(fs, RELAX); | |
86e84862 | 1055 | schedule_timeout_interruptible(1); |
1da177e4 LT |
1056 | } |
1057 | ret = swim3_readbit(fs, SEEK_COMPLETE) == 0 | |
1058 | || swim3_readbit(fs, DISK_IN) == 0; | |
1059 | if (ret) | |
1060 | swim3_action(fs, MOTOR_OFF); | |
1061 | else { | |
1062 | fs->ejected = 0; | |
1063 | swim3_action(fs, SETMFM); | |
1064 | } | |
1065 | swim3_select(fs, RELAX); | |
1066 | ||
1067 | release_drive(fs); | |
1068 | return ret; | |
1069 | } | |
1070 | ||
83d5cde4 | 1071 | static const struct block_device_operations floppy_fops = { |
6e9624b8 | 1072 | .open = floppy_unlocked_open, |
b4d9a442 | 1073 | .release = floppy_release, |
8a6cfeb6 | 1074 | .ioctl = floppy_ioctl, |
4bbde777 | 1075 | .check_events = floppy_check_events, |
1da177e4 LT |
1076 | }; |
1077 | ||
8ccb8cb1 OS |
1078 | static const struct blk_mq_ops swim3_mq_ops = { |
1079 | .queue_rq = swim3_queue_rq, | |
1080 | }; | |
1081 | ||
b3025457 BH |
1082 | static void swim3_mb_event(struct macio_dev* mdev, int mb_state) |
1083 | { | |
1084 | struct floppy_state *fs = macio_get_drvdata(mdev); | |
7414d4f6 | 1085 | struct swim3 __iomem *sw; |
b3025457 BH |
1086 | |
1087 | if (!fs) | |
1088 | return; | |
7414d4f6 CD |
1089 | |
1090 | sw = fs->swim3; | |
1091 | ||
b3025457 BH |
1092 | if (mb_state != MB_FD) |
1093 | return; | |
1094 | ||
1095 | /* Clear state */ | |
1096 | out_8(&sw->intr_enable, 0); | |
1097 | in_8(&sw->intr); | |
1098 | in_8(&sw->error); | |
1099 | } | |
1100 | ||
3e9a6927 | 1101 | static int swim3_add_device(struct macio_dev *mdev, int index) |
1da177e4 | 1102 | { |
61c7a080 | 1103 | struct device_node *swim = mdev->ofdev.dev.of_node; |
3e9a6927 BH |
1104 | struct floppy_state *fs = &floppy_states[index]; |
1105 | int rc = -EBUSY; | |
1da177e4 | 1106 | |
b3025457 BH |
1107 | fs->mdev = mdev; |
1108 | fs->index = index; | |
1109 | ||
3e9a6927 BH |
1110 | /* Check & Request resources */ |
1111 | if (macio_resource_count(mdev) < 2) { | |
b3025457 | 1112 | swim3_err("%s", "No address in device-tree\n"); |
3e9a6927 | 1113 | return -ENXIO; |
1da177e4 | 1114 | } |
b3025457 BH |
1115 | if (macio_irq_count(mdev) < 1) { |
1116 | swim3_err("%s", "No interrupt in device-tree\n"); | |
1117 | return -ENXIO; | |
cc5d0189 | 1118 | } |
3e9a6927 | 1119 | if (macio_request_resource(mdev, 0, "swim3 (mmio)")) { |
b3025457 | 1120 | swim3_err("%s", "Can't request mmio resource\n"); |
3e9a6927 | 1121 | return -EBUSY; |
1da177e4 | 1122 | } |
3e9a6927 | 1123 | if (macio_request_resource(mdev, 1, "swim3 (dma)")) { |
b3025457 | 1124 | swim3_err("%s", "Can't request dma resource\n"); |
3e9a6927 BH |
1125 | macio_release_resource(mdev, 0); |
1126 | return -EBUSY; | |
1da177e4 | 1127 | } |
3e9a6927 | 1128 | dev_set_drvdata(&mdev->ofdev.dev, fs); |
1da177e4 | 1129 | |
d58b0c39 | 1130 | if (mdev->media_bay == NULL) |
1da177e4 LT |
1131 | pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 1); |
1132 | ||
1da177e4 | 1133 | fs->state = idle; |
3e9a6927 BH |
1134 | fs->swim3 = (struct swim3 __iomem *) |
1135 | ioremap(macio_resource_start(mdev, 0), 0x200); | |
1136 | if (fs->swim3 == NULL) { | |
b3025457 | 1137 | swim3_err("%s", "Couldn't map mmio registers\n"); |
3e9a6927 BH |
1138 | rc = -ENOMEM; |
1139 | goto out_release; | |
1140 | } | |
1141 | fs->dma = (struct dbdma_regs __iomem *) | |
1142 | ioremap(macio_resource_start(mdev, 1), 0x200); | |
1143 | if (fs->dma == NULL) { | |
b3025457 | 1144 | swim3_err("%s", "Couldn't map dma registers\n"); |
3e9a6927 BH |
1145 | iounmap(fs->swim3); |
1146 | rc = -ENOMEM; | |
1147 | goto out_release; | |
1148 | } | |
1149 | fs->swim3_intr = macio_irq(mdev, 0); | |
a419aef8 | 1150 | fs->dma_intr = macio_irq(mdev, 1); |
1da177e4 LT |
1151 | fs->cur_cyl = -1; |
1152 | fs->cur_sector = -1; | |
1153 | fs->secpercyl = 36; | |
1154 | fs->secpertrack = 18; | |
1155 | fs->total_secs = 2880; | |
1da177e4 LT |
1156 | init_waitqueue_head(&fs->wait); |
1157 | ||
1158 | fs->dma_cmd = (struct dbdma_cmd *) DBDMA_ALIGN(fs->dbdma_cmd_space); | |
1159 | memset(fs->dma_cmd, 0, 2 * sizeof(struct dbdma_cmd)); | |
f5718726 | 1160 | fs->dma_cmd[1].command = cpu_to_le16(DBDMA_STOP); |
1da177e4 | 1161 | |
b3025457 BH |
1162 | if (mdev->media_bay == NULL || check_media_bay(mdev->media_bay) == MB_FD) |
1163 | swim3_mb_event(mdev, MB_FD); | |
1164 | ||
1da177e4 | 1165 | if (request_irq(fs->swim3_intr, swim3_interrupt, 0, "SWIM3", fs)) { |
b3025457 | 1166 | swim3_err("%s", "Couldn't request interrupt\n"); |
1da177e4 | 1167 | pmac_call_feature(PMAC_FTR_SWIM3_ENABLE, swim, 0, 0); |
3e9a6927 | 1168 | goto out_unmap; |
1da177e4 | 1169 | } |
1da177e4 | 1170 | |
b5775a6b | 1171 | timer_setup(&fs->timeout, NULL, 0); |
1da177e4 | 1172 | |
b3025457 | 1173 | swim3_info("SWIM3 floppy controller %s\n", |
d58b0c39 | 1174 | mdev->media_bay ? "in media bay" : ""); |
1da177e4 | 1175 | |
3e9a6927 BH |
1176 | return 0; |
1177 | ||
1178 | out_unmap: | |
1179 | iounmap(fs->dma); | |
1180 | iounmap(fs->swim3); | |
1181 | ||
1182 | out_release: | |
1183 | macio_release_resource(mdev, 0); | |
1184 | macio_release_resource(mdev, 1); | |
1185 | ||
1186 | return rc; | |
1187 | } | |
1188 | ||
8d85fce7 GKH |
1189 | static int swim3_attach(struct macio_dev *mdev, |
1190 | const struct of_device_id *match) | |
3e9a6927 | 1191 | { |
dbaa54b6 | 1192 | struct floppy_state *fs; |
3e9a6927 | 1193 | struct gendisk *disk; |
dbaa54b6 | 1194 | int rc; |
b3025457 | 1195 | |
dbaa54b6 | 1196 | if (floppy_count >= MAX_FLOPPIES) |
b3025457 | 1197 | return -ENXIO; |
3e9a6927 | 1198 | |
dbaa54b6 OS |
1199 | if (floppy_count == 0) { |
1200 | rc = register_blkdev(FLOPPY_MAJOR, "fd"); | |
1201 | if (rc) | |
1202 | return rc; | |
1203 | } | |
1204 | ||
427c5ce4 FT |
1205 | fs = &floppy_states[floppy_count]; |
1206 | memset(fs, 0, sizeof(*fs)); | |
1207 | ||
9c8463e8 CH |
1208 | rc = blk_mq_alloc_sq_tag_set(&fs->tag_set, &swim3_mq_ops, 2, |
1209 | BLK_MQ_F_SHOULD_MERGE); | |
1210 | if (rc) | |
1211 | goto out_unregister; | |
1212 | ||
1213 | disk = blk_mq_alloc_disk(&fs->tag_set, fs); | |
1214 | if (IS_ERR(disk)) { | |
1215 | rc = PTR_ERR(disk); | |
1216 | goto out_free_tag_set; | |
b3025457 | 1217 | } |
3e9a6927 | 1218 | |
dbaa54b6 OS |
1219 | rc = swim3_add_device(mdev, floppy_count); |
1220 | if (rc) | |
9c8463e8 | 1221 | goto out_cleanup_disk; |
3e9a6927 | 1222 | |
3e9a6927 | 1223 | disk->major = FLOPPY_MAJOR; |
dbaa54b6 | 1224 | disk->first_minor = floppy_count; |
9c8463e8 | 1225 | disk->minors = 1; |
3e9a6927 | 1226 | disk->fops = &floppy_fops; |
dbaa54b6 | 1227 | disk->private_data = fs; |
773008f6 | 1228 | disk->events = DISK_EVENT_MEDIA_CHANGE; |
3e9a6927 | 1229 | disk->flags |= GENHD_FL_REMOVABLE; |
dbaa54b6 | 1230 | sprintf(disk->disk_name, "fd%d", floppy_count); |
3e9a6927 BH |
1231 | set_capacity(disk, 2880); |
1232 | add_disk(disk); | |
1233 | ||
dbaa54b6 | 1234 | disks[floppy_count++] = disk; |
3e9a6927 | 1235 | return 0; |
dbaa54b6 | 1236 | |
9c8463e8 CH |
1237 | out_cleanup_disk: |
1238 | blk_cleanup_disk(disk); | |
1239 | out_free_tag_set: | |
8ccb8cb1 | 1240 | blk_mq_free_tag_set(&fs->tag_set); |
dbaa54b6 OS |
1241 | out_unregister: |
1242 | if (floppy_count == 0) | |
1243 | unregister_blkdev(FLOPPY_MAJOR, "fd"); | |
1244 | return rc; | |
3e9a6927 BH |
1245 | } |
1246 | ||
cc3f2e9f | 1247 | static const struct of_device_id swim3_match[] = |
3e9a6927 BH |
1248 | { |
1249 | { | |
1250 | .name = "swim3", | |
1251 | }, | |
1252 | { | |
1253 | .compatible = "ohare-swim3" | |
1254 | }, | |
1255 | { | |
1256 | .compatible = "swim3" | |
1257 | }, | |
f41c53a5 | 1258 | { /* end of list */ } |
3e9a6927 BH |
1259 | }; |
1260 | ||
1261 | static struct macio_driver swim3_driver = | |
1262 | { | |
c2cdf6ab BH |
1263 | .driver = { |
1264 | .name = "swim3", | |
1265 | .of_match_table = swim3_match, | |
1266 | }, | |
3e9a6927 | 1267 | .probe = swim3_attach, |
b3025457 BH |
1268 | #ifdef CONFIG_PMAC_MEDIABAY |
1269 | .mediabay_event = swim3_mb_event, | |
1270 | #endif | |
3e9a6927 BH |
1271 | #if 0 |
1272 | .suspend = swim3_suspend, | |
1273 | .resume = swim3_resume, | |
1274 | #endif | |
1275 | }; | |
1276 | ||
1277 | ||
1278 | int swim3_init(void) | |
1279 | { | |
1280 | macio_register_driver(&swim3_driver); | |
1da177e4 LT |
1281 | return 0; |
1282 | } | |
1283 | ||
1284 | module_init(swim3_init) | |
1285 | ||
1286 | MODULE_LICENSE("GPL"); | |
1287 | MODULE_AUTHOR("Paul Mackerras"); | |
1288 | MODULE_ALIAS_BLOCKDEV_MAJOR(FLOPPY_MAJOR); |