Commit | Line | Data |
---|---|---|
bec9e8ac BVA |
1 | /* |
2 | * Driver for sTec s1120 PCIe SSDs. sTec was acquired in 2013 by HGST and HGST | |
3 | * was acquired by Western Digital in 2012. | |
e67f86b3 | 4 | * |
bec9e8ac BVA |
5 | * Copyright 2012 sTec, Inc. |
6 | * Copyright (c) 2017 Western Digital Corporation or its affiliates. | |
7 | * | |
8 | * This file is part of the Linux kernel, and is made available under | |
9 | * the terms of the GNU General Public License version 2. | |
e67f86b3 AB |
10 | */ |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/pci.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/blkdev.h> | |
f18c17c8 | 19 | #include <linux/blk-mq.h> |
e67f86b3 AB |
20 | #include <linux/sched.h> |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/compiler.h> | |
23 | #include <linux/workqueue.h> | |
e67f86b3 AB |
24 | #include <linux/delay.h> |
25 | #include <linux/time.h> | |
26 | #include <linux/hdreg.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/completion.h> | |
29 | #include <linux/scatterlist.h> | |
30 | #include <linux/version.h> | |
31 | #include <linux/err.h> | |
e67f86b3 | 32 | #include <linux/aer.h> |
e67f86b3 | 33 | #include <linux/wait.h> |
2da7b403 | 34 | #include <linux/stringify.h> |
e67f86b3 | 35 | #include <scsi/scsi.h> |
e67f86b3 AB |
36 | #include <scsi/sg.h> |
37 | #include <linux/io.h> | |
38 | #include <linux/uaccess.h> | |
4ca90b53 | 39 | #include <asm/unaligned.h> |
e67f86b3 AB |
40 | |
41 | #include "skd_s1120.h" | |
42 | ||
43 | static int skd_dbg_level; | |
44 | static int skd_isr_comp_limit = 4; | |
45 | ||
e67f86b3 AB |
46 | #define SKD_ASSERT(expr) \ |
47 | do { \ | |
48 | if (unlikely(!(expr))) { \ | |
49 | pr_err("Assertion failed! %s,%s,%s,line=%d\n", \ | |
50 | # expr, __FILE__, __func__, __LINE__); \ | |
51 | } \ | |
52 | } while (0) | |
53 | ||
e67f86b3 | 54 | #define DRV_NAME "skd" |
e67f86b3 | 55 | #define PFX DRV_NAME ": " |
e67f86b3 | 56 | |
bec9e8ac | 57 | MODULE_LICENSE("GPL"); |
e67f86b3 | 58 | |
bb9f7dd3 | 59 | MODULE_DESCRIPTION("STEC s1120 PCIe SSD block driver"); |
e67f86b3 AB |
60 | |
61 | #define PCI_VENDOR_ID_STEC 0x1B39 | |
62 | #define PCI_DEVICE_ID_S1120 0x0001 | |
63 | ||
64 | #define SKD_FUA_NV (1 << 1) | |
65 | #define SKD_MINORS_PER_DEVICE 16 | |
66 | ||
67 | #define SKD_MAX_QUEUE_DEPTH 200u | |
68 | ||
69 | #define SKD_PAUSE_TIMEOUT (5 * 1000) | |
70 | ||
71 | #define SKD_N_FITMSG_BYTES (512u) | |
2da7b403 | 72 | #define SKD_MAX_REQ_PER_MSG 14 |
e67f86b3 | 73 | |
e67f86b3 AB |
74 | #define SKD_N_SPECIAL_FITMSG_BYTES (128u) |
75 | ||
76 | /* SG elements are 32 bytes, so we can make this 4096 and still be under the | |
77 | * 128KB limit. That allows 4096*4K = 16M xfer size | |
78 | */ | |
79 | #define SKD_N_SG_PER_REQ_DEFAULT 256u | |
e67f86b3 AB |
80 | |
81 | #define SKD_N_COMPLETION_ENTRY 256u | |
82 | #define SKD_N_READ_CAP_BYTES (8u) | |
83 | ||
84 | #define SKD_N_INTERNAL_BYTES (512u) | |
85 | ||
6f7c7675 BVA |
86 | #define SKD_SKCOMP_SIZE \ |
87 | ((sizeof(struct fit_completion_entry_v1) + \ | |
88 | sizeof(struct fit_comp_error_info)) * SKD_N_COMPLETION_ENTRY) | |
89 | ||
e67f86b3 | 90 | /* 5 bits of uniqifier, 0xF800 */ |
e67f86b3 AB |
91 | #define SKD_ID_TABLE_MASK (3u << 8u) |
92 | #define SKD_ID_RW_REQUEST (0u << 8u) | |
93 | #define SKD_ID_INTERNAL (1u << 8u) | |
e67f86b3 AB |
94 | #define SKD_ID_FIT_MSG (3u << 8u) |
95 | #define SKD_ID_SLOT_MASK 0x00FFu | |
96 | #define SKD_ID_SLOT_AND_TABLE_MASK 0x03FFu | |
97 | ||
e67f86b3 AB |
98 | #define SKD_N_MAX_SECTORS 2048u |
99 | ||
100 | #define SKD_MAX_RETRIES 2u | |
101 | ||
102 | #define SKD_TIMER_SECONDS(seconds) (seconds) | |
103 | #define SKD_TIMER_MINUTES(minutes) ((minutes) * (60)) | |
104 | ||
105 | #define INQ_STD_NBYTES 36 | |
e67f86b3 AB |
106 | |
107 | enum skd_drvr_state { | |
108 | SKD_DRVR_STATE_LOAD, | |
109 | SKD_DRVR_STATE_IDLE, | |
110 | SKD_DRVR_STATE_BUSY, | |
111 | SKD_DRVR_STATE_STARTING, | |
112 | SKD_DRVR_STATE_ONLINE, | |
113 | SKD_DRVR_STATE_PAUSING, | |
114 | SKD_DRVR_STATE_PAUSED, | |
e67f86b3 AB |
115 | SKD_DRVR_STATE_RESTARTING, |
116 | SKD_DRVR_STATE_RESUMING, | |
117 | SKD_DRVR_STATE_STOPPING, | |
118 | SKD_DRVR_STATE_FAULT, | |
119 | SKD_DRVR_STATE_DISAPPEARED, | |
120 | SKD_DRVR_STATE_PROTOCOL_MISMATCH, | |
121 | SKD_DRVR_STATE_BUSY_ERASE, | |
122 | SKD_DRVR_STATE_BUSY_SANITIZE, | |
123 | SKD_DRVR_STATE_BUSY_IMMINENT, | |
124 | SKD_DRVR_STATE_WAIT_BOOT, | |
125 | SKD_DRVR_STATE_SYNCING, | |
126 | }; | |
127 | ||
128 | #define SKD_WAIT_BOOT_TIMO SKD_TIMER_SECONDS(90u) | |
129 | #define SKD_STARTING_TIMO SKD_TIMER_SECONDS(8u) | |
130 | #define SKD_RESTARTING_TIMO SKD_TIMER_MINUTES(4u) | |
e67f86b3 AB |
131 | #define SKD_BUSY_TIMO SKD_TIMER_MINUTES(20u) |
132 | #define SKD_STARTED_BUSY_TIMO SKD_TIMER_SECONDS(60u) | |
133 | #define SKD_START_WAIT_SECONDS 90u | |
134 | ||
135 | enum skd_req_state { | |
136 | SKD_REQ_STATE_IDLE, | |
137 | SKD_REQ_STATE_SETUP, | |
138 | SKD_REQ_STATE_BUSY, | |
139 | SKD_REQ_STATE_COMPLETED, | |
140 | SKD_REQ_STATE_TIMEOUT, | |
e67f86b3 AB |
141 | }; |
142 | ||
e67f86b3 AB |
143 | enum skd_check_status_action { |
144 | SKD_CHECK_STATUS_REPORT_GOOD, | |
145 | SKD_CHECK_STATUS_REPORT_SMART_ALERT, | |
146 | SKD_CHECK_STATUS_REQUEUE_REQUEST, | |
147 | SKD_CHECK_STATUS_REPORT_ERROR, | |
148 | SKD_CHECK_STATUS_BUSY_IMMINENT, | |
149 | }; | |
150 | ||
d891fe60 BVA |
151 | struct skd_msg_buf { |
152 | struct fit_msg_hdr fmh; | |
153 | struct skd_scsi_request scsi[SKD_MAX_REQ_PER_MSG]; | |
154 | }; | |
155 | ||
e67f86b3 | 156 | struct skd_fitmsg_context { |
e67f86b3 | 157 | u32 id; |
e67f86b3 AB |
158 | |
159 | u32 length; | |
e67f86b3 | 160 | |
d891fe60 | 161 | struct skd_msg_buf *msg_buf; |
e67f86b3 AB |
162 | dma_addr_t mb_dma_address; |
163 | }; | |
164 | ||
165 | struct skd_request_context { | |
166 | enum skd_req_state state; | |
167 | ||
e67f86b3 AB |
168 | u16 id; |
169 | u32 fitmsg_id; | |
170 | ||
e67f86b3 | 171 | u8 flush_cmd; |
e67f86b3 | 172 | |
b1824eef | 173 | enum dma_data_direction data_dir; |
e67f86b3 AB |
174 | struct scatterlist *sg; |
175 | u32 n_sg; | |
176 | u32 sg_byte_count; | |
177 | ||
178 | struct fit_sg_descriptor *sksg_list; | |
179 | dma_addr_t sksg_dma_address; | |
180 | ||
181 | struct fit_completion_entry_v1 completion; | |
182 | ||
183 | struct fit_comp_error_info err_info; | |
184 | ||
f2fe4459 | 185 | blk_status_t status; |
e67f86b3 | 186 | }; |
e67f86b3 AB |
187 | |
188 | struct skd_special_context { | |
189 | struct skd_request_context req; | |
190 | ||
e67f86b3 AB |
191 | void *data_buf; |
192 | dma_addr_t db_dma_address; | |
193 | ||
d891fe60 | 194 | struct skd_msg_buf *msg_buf; |
e67f86b3 AB |
195 | dma_addr_t mb_dma_address; |
196 | }; | |
197 | ||
e67f86b3 AB |
198 | typedef enum skd_irq_type { |
199 | SKD_IRQ_LEGACY, | |
200 | SKD_IRQ_MSI, | |
201 | SKD_IRQ_MSIX | |
202 | } skd_irq_type_t; | |
203 | ||
204 | #define SKD_MAX_BARS 2 | |
205 | ||
206 | struct skd_device { | |
85e34112 | 207 | void __iomem *mem_map[SKD_MAX_BARS]; |
e67f86b3 AB |
208 | resource_size_t mem_phys[SKD_MAX_BARS]; |
209 | u32 mem_size[SKD_MAX_BARS]; | |
210 | ||
e67f86b3 AB |
211 | struct skd_msix_entry *msix_entries; |
212 | ||
213 | struct pci_dev *pdev; | |
214 | int pcie_error_reporting_is_enabled; | |
215 | ||
216 | spinlock_t lock; | |
217 | struct gendisk *disk; | |
ca33dd92 | 218 | struct blk_mq_tag_set tag_set; |
e67f86b3 | 219 | struct request_queue *queue; |
91f85da4 | 220 | struct skd_fitmsg_context *skmsg; |
e67f86b3 AB |
221 | struct device *class_dev; |
222 | int gendisk_on; | |
223 | int sync_done; | |
224 | ||
e67f86b3 AB |
225 | u32 devno; |
226 | u32 major; | |
e67f86b3 AB |
227 | char isr_name[30]; |
228 | ||
229 | enum skd_drvr_state state; | |
230 | u32 drive_state; | |
231 | ||
e67f86b3 AB |
232 | u32 cur_max_queue_depth; |
233 | u32 queue_low_water_mark; | |
234 | u32 dev_max_queue_depth; | |
235 | ||
236 | u32 num_fitmsg_context; | |
237 | u32 num_req_context; | |
238 | ||
e67f86b3 AB |
239 | struct skd_fitmsg_context *skmsg_table; |
240 | ||
e67f86b3 AB |
241 | struct skd_special_context internal_skspcl; |
242 | u32 read_cap_blocksize; | |
243 | u32 read_cap_last_lba; | |
244 | int read_cap_is_valid; | |
245 | int inquiry_is_valid; | |
246 | u8 inq_serial_num[13]; /*12 chars plus null term */ | |
e67f86b3 AB |
247 | |
248 | u8 skcomp_cycle; | |
249 | u32 skcomp_ix; | |
a3db102d BVA |
250 | struct kmem_cache *msgbuf_cache; |
251 | struct kmem_cache *sglist_cache; | |
252 | struct kmem_cache *databuf_cache; | |
e67f86b3 AB |
253 | struct fit_completion_entry_v1 *skcomp_table; |
254 | struct fit_comp_error_info *skerr_table; | |
255 | dma_addr_t cq_dma_address; | |
256 | ||
257 | wait_queue_head_t waitq; | |
258 | ||
259 | struct timer_list timer; | |
260 | u32 timer_countdown; | |
261 | u32 timer_substate; | |
262 | ||
e67f86b3 AB |
263 | int sgs_per_request; |
264 | u32 last_mtd; | |
265 | ||
266 | u32 proto_ver; | |
267 | ||
268 | int dbg_level; | |
269 | u32 connect_time_stamp; | |
270 | int connect_retries; | |
271 | #define SKD_MAX_CONNECT_RETRIES 16 | |
272 | u32 drive_jiffies; | |
273 | ||
274 | u32 timo_slot; | |
275 | ||
ca33dd92 | 276 | struct work_struct start_queue; |
38d4a1bb | 277 | struct work_struct completion_worker; |
e67f86b3 AB |
278 | }; |
279 | ||
280 | #define SKD_WRITEL(DEV, VAL, OFF) skd_reg_write32(DEV, VAL, OFF) | |
281 | #define SKD_READL(DEV, OFF) skd_reg_read32(DEV, OFF) | |
282 | #define SKD_WRITEQ(DEV, VAL, OFF) skd_reg_write64(DEV, VAL, OFF) | |
283 | ||
284 | static inline u32 skd_reg_read32(struct skd_device *skdev, u32 offset) | |
285 | { | |
14262a4b | 286 | u32 val = readl(skdev->mem_map[1] + offset); |
e67f86b3 | 287 | |
14262a4b | 288 | if (unlikely(skdev->dbg_level >= 2)) |
f98806d6 | 289 | dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val); |
14262a4b | 290 | return val; |
e67f86b3 AB |
291 | } |
292 | ||
293 | static inline void skd_reg_write32(struct skd_device *skdev, u32 val, | |
294 | u32 offset) | |
295 | { | |
14262a4b BVA |
296 | writel(val, skdev->mem_map[1] + offset); |
297 | if (unlikely(skdev->dbg_level >= 2)) | |
f98806d6 | 298 | dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val); |
e67f86b3 AB |
299 | } |
300 | ||
301 | static inline void skd_reg_write64(struct skd_device *skdev, u64 val, | |
302 | u32 offset) | |
303 | { | |
14262a4b BVA |
304 | writeq(val, skdev->mem_map[1] + offset); |
305 | if (unlikely(skdev->dbg_level >= 2)) | |
f98806d6 BVA |
306 | dev_dbg(&skdev->pdev->dev, "offset %x = %016llx\n", offset, |
307 | val); | |
e67f86b3 AB |
308 | } |
309 | ||
310 | ||
744353b6 | 311 | #define SKD_IRQ_DEFAULT SKD_IRQ_MSIX |
e67f86b3 AB |
312 | static int skd_isr_type = SKD_IRQ_DEFAULT; |
313 | ||
314 | module_param(skd_isr_type, int, 0444); | |
315 | MODULE_PARM_DESC(skd_isr_type, "Interrupt type capability." | |
316 | " (0==legacy, 1==MSI, 2==MSI-X, default==1)"); | |
317 | ||
318 | #define SKD_MAX_REQ_PER_MSG_DEFAULT 1 | |
319 | static int skd_max_req_per_msg = SKD_MAX_REQ_PER_MSG_DEFAULT; | |
320 | ||
321 | module_param(skd_max_req_per_msg, int, 0444); | |
322 | MODULE_PARM_DESC(skd_max_req_per_msg, | |
323 | "Maximum SCSI requests packed in a single message." | |
2da7b403 | 324 | " (1-" __stringify(SKD_MAX_REQ_PER_MSG) ", default==1)"); |
e67f86b3 AB |
325 | |
326 | #define SKD_MAX_QUEUE_DEPTH_DEFAULT 64 | |
327 | #define SKD_MAX_QUEUE_DEPTH_DEFAULT_STR "64" | |
328 | static int skd_max_queue_depth = SKD_MAX_QUEUE_DEPTH_DEFAULT; | |
329 | ||
330 | module_param(skd_max_queue_depth, int, 0444); | |
331 | MODULE_PARM_DESC(skd_max_queue_depth, | |
332 | "Maximum SCSI requests issued to s1120." | |
333 | " (1-200, default==" SKD_MAX_QUEUE_DEPTH_DEFAULT_STR ")"); | |
334 | ||
335 | static int skd_sgs_per_request = SKD_N_SG_PER_REQ_DEFAULT; | |
336 | module_param(skd_sgs_per_request, int, 0444); | |
337 | MODULE_PARM_DESC(skd_sgs_per_request, | |
338 | "Maximum SG elements per block request." | |
339 | " (1-4096, default==256)"); | |
340 | ||
63214121 | 341 | static int skd_max_pass_thru = 1; |
e67f86b3 AB |
342 | module_param(skd_max_pass_thru, int, 0444); |
343 | MODULE_PARM_DESC(skd_max_pass_thru, | |
63214121 | 344 | "Maximum SCSI pass-thru at a time. IGNORED"); |
e67f86b3 AB |
345 | |
346 | module_param(skd_dbg_level, int, 0444); | |
347 | MODULE_PARM_DESC(skd_dbg_level, "s1120 debug level (0,1,2)"); | |
348 | ||
349 | module_param(skd_isr_comp_limit, int, 0444); | |
350 | MODULE_PARM_DESC(skd_isr_comp_limit, "s1120 isr comp limit (0=none) default=4"); | |
351 | ||
e67f86b3 AB |
352 | /* Major device number dynamically assigned. */ |
353 | static u32 skd_major; | |
354 | ||
e67f86b3 AB |
355 | static void skd_destruct(struct skd_device *skdev); |
356 | static const struct block_device_operations skd_blockdev_ops; | |
357 | static void skd_send_fitmsg(struct skd_device *skdev, | |
358 | struct skd_fitmsg_context *skmsg); | |
359 | static void skd_send_special_fitmsg(struct skd_device *skdev, | |
360 | struct skd_special_context *skspcl); | |
2a842aca | 361 | static bool skd_preop_sg_list(struct skd_device *skdev, |
e67f86b3 AB |
362 | struct skd_request_context *skreq); |
363 | static void skd_postop_sg_list(struct skd_device *skdev, | |
364 | struct skd_request_context *skreq); | |
365 | ||
366 | static void skd_restart_device(struct skd_device *skdev); | |
367 | static int skd_quiesce_dev(struct skd_device *skdev); | |
368 | static int skd_unquiesce_dev(struct skd_device *skdev); | |
e67f86b3 AB |
369 | static void skd_disable_interrupts(struct skd_device *skdev); |
370 | static void skd_isr_fwstate(struct skd_device *skdev); | |
79ce12a8 | 371 | static void skd_recover_requests(struct skd_device *skdev); |
e67f86b3 AB |
372 | static void skd_soft_reset(struct skd_device *skdev); |
373 | ||
e67f86b3 AB |
374 | const char *skd_drive_state_to_str(int state); |
375 | const char *skd_skdev_state_to_str(enum skd_drvr_state state); | |
376 | static void skd_log_skdev(struct skd_device *skdev, const char *event); | |
e67f86b3 AB |
377 | static void skd_log_skreq(struct skd_device *skdev, |
378 | struct skd_request_context *skreq, const char *event); | |
379 | ||
e67f86b3 AB |
380 | /* |
381 | ***************************************************************************** | |
382 | * READ/WRITE REQUESTS | |
383 | ***************************************************************************** | |
384 | */ | |
d4d0f5fc BVA |
385 | static void skd_inc_in_flight(struct request *rq, void *data, bool reserved) |
386 | { | |
387 | int *count = data; | |
388 | ||
389 | count++; | |
390 | } | |
391 | ||
392 | static int skd_in_flight(struct skd_device *skdev) | |
393 | { | |
394 | int count = 0; | |
395 | ||
396 | blk_mq_tagset_busy_iter(&skdev->tag_set, skd_inc_in_flight, &count); | |
397 | ||
398 | return count; | |
399 | } | |
400 | ||
e67f86b3 AB |
401 | static void |
402 | skd_prep_rw_cdb(struct skd_scsi_request *scsi_req, | |
403 | int data_dir, unsigned lba, | |
404 | unsigned count) | |
405 | { | |
406 | if (data_dir == READ) | |
fb4844b8 | 407 | scsi_req->cdb[0] = READ_10; |
e67f86b3 | 408 | else |
fb4844b8 | 409 | scsi_req->cdb[0] = WRITE_10; |
e67f86b3 AB |
410 | |
411 | scsi_req->cdb[1] = 0; | |
412 | scsi_req->cdb[2] = (lba & 0xff000000) >> 24; | |
413 | scsi_req->cdb[3] = (lba & 0xff0000) >> 16; | |
414 | scsi_req->cdb[4] = (lba & 0xff00) >> 8; | |
415 | scsi_req->cdb[5] = (lba & 0xff); | |
416 | scsi_req->cdb[6] = 0; | |
417 | scsi_req->cdb[7] = (count & 0xff00) >> 8; | |
418 | scsi_req->cdb[8] = count & 0xff; | |
419 | scsi_req->cdb[9] = 0; | |
420 | } | |
421 | ||
422 | static void | |
423 | skd_prep_zerosize_flush_cdb(struct skd_scsi_request *scsi_req, | |
38d4a1bb | 424 | struct skd_request_context *skreq) |
e67f86b3 AB |
425 | { |
426 | skreq->flush_cmd = 1; | |
427 | ||
fb4844b8 | 428 | scsi_req->cdb[0] = SYNCHRONIZE_CACHE; |
e67f86b3 AB |
429 | scsi_req->cdb[1] = 0; |
430 | scsi_req->cdb[2] = 0; | |
431 | scsi_req->cdb[3] = 0; | |
432 | scsi_req->cdb[4] = 0; | |
433 | scsi_req->cdb[5] = 0; | |
434 | scsi_req->cdb[6] = 0; | |
435 | scsi_req->cdb[7] = 0; | |
436 | scsi_req->cdb[8] = 0; | |
437 | scsi_req->cdb[9] = 0; | |
438 | } | |
439 | ||
3d17a679 BVA |
440 | /* |
441 | * Return true if and only if all pending requests should be failed. | |
442 | */ | |
443 | static bool skd_fail_all(struct request_queue *q) | |
cb6981b9 BVA |
444 | { |
445 | struct skd_device *skdev = q->queuedata; | |
446 | ||
447 | SKD_ASSERT(skdev->state != SKD_DRVR_STATE_ONLINE); | |
448 | ||
449 | skd_log_skdev(skdev, "req_not_online"); | |
450 | switch (skdev->state) { | |
451 | case SKD_DRVR_STATE_PAUSING: | |
452 | case SKD_DRVR_STATE_PAUSED: | |
453 | case SKD_DRVR_STATE_STARTING: | |
454 | case SKD_DRVR_STATE_RESTARTING: | |
455 | case SKD_DRVR_STATE_WAIT_BOOT: | |
456 | /* In case of starting, we haven't started the queue, | |
457 | * so we can't get here... but requests are | |
458 | * possibly hanging out waiting for us because we | |
459 | * reported the dev/skd0 already. They'll wait | |
460 | * forever if connect doesn't complete. | |
461 | * What to do??? delay dev/skd0 ?? | |
462 | */ | |
463 | case SKD_DRVR_STATE_BUSY: | |
464 | case SKD_DRVR_STATE_BUSY_IMMINENT: | |
465 | case SKD_DRVR_STATE_BUSY_ERASE: | |
3d17a679 | 466 | return false; |
cb6981b9 BVA |
467 | |
468 | case SKD_DRVR_STATE_BUSY_SANITIZE: | |
469 | case SKD_DRVR_STATE_STOPPING: | |
470 | case SKD_DRVR_STATE_SYNCING: | |
471 | case SKD_DRVR_STATE_FAULT: | |
472 | case SKD_DRVR_STATE_DISAPPEARED: | |
473 | default: | |
3d17a679 | 474 | return true; |
cb6981b9 | 475 | } |
cb6981b9 | 476 | } |
e67f86b3 | 477 | |
c39c6c77 BVA |
478 | static blk_status_t skd_mq_queue_rq(struct blk_mq_hw_ctx *hctx, |
479 | const struct blk_mq_queue_data *mqd) | |
e67f86b3 | 480 | { |
c39c6c77 | 481 | struct request *const req = mqd->rq; |
91f85da4 | 482 | struct request_queue *const q = req->q; |
e67f86b3 | 483 | struct skd_device *skdev = q->queuedata; |
91f85da4 BVA |
484 | struct skd_fitmsg_context *skmsg; |
485 | struct fit_msg_hdr *fmh; | |
486 | const u32 tag = blk_mq_unique_tag(req); | |
e7278a8b | 487 | struct skd_request_context *const skreq = blk_mq_rq_to_pdu(req); |
e67f86b3 | 488 | struct skd_scsi_request *scsi_req; |
74c74282 | 489 | unsigned long flags = 0; |
e2bb5548 BVA |
490 | const u32 lba = blk_rq_pos(req); |
491 | const u32 count = blk_rq_sectors(req); | |
492 | const int data_dir = rq_data_dir(req); | |
91f85da4 | 493 | |
c39c6c77 BVA |
494 | if (unlikely(skdev->state != SKD_DRVR_STATE_ONLINE)) |
495 | return skd_fail_all(q) ? BLK_STS_IOERR : BLK_STS_RESOURCE; | |
496 | ||
497 | blk_mq_start_request(req); | |
498 | ||
91f85da4 BVA |
499 | WARN_ONCE(tag >= skd_max_queue_depth, "%#x > %#x (nr_requests = %lu)\n", |
500 | tag, skd_max_queue_depth, q->nr_requests); | |
501 | ||
502 | SKD_ASSERT(skreq->state == SKD_REQ_STATE_IDLE); | |
503 | ||
91f85da4 BVA |
504 | dev_dbg(&skdev->pdev->dev, |
505 | "new req=%p lba=%u(0x%x) count=%u(0x%x) dir=%d\n", req, lba, | |
506 | lba, count, count, data_dir); | |
507 | ||
508 | skreq->id = tag + SKD_ID_RW_REQUEST; | |
509 | skreq->flush_cmd = 0; | |
510 | skreq->n_sg = 0; | |
511 | skreq->sg_byte_count = 0; | |
512 | ||
91f85da4 BVA |
513 | skreq->fitmsg_id = 0; |
514 | ||
515 | skreq->data_dir = data_dir == READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
516 | ||
517 | if (req->bio && !skd_preop_sg_list(skdev, skreq)) { | |
518 | dev_dbg(&skdev->pdev->dev, "error Out\n"); | |
795bc1b5 BVA |
519 | skreq->status = BLK_STS_RESOURCE; |
520 | blk_mq_complete_request(req); | |
c39c6c77 | 521 | return BLK_STS_OK; |
91f85da4 BVA |
522 | } |
523 | ||
a3db102d BVA |
524 | dma_sync_single_for_device(&skdev->pdev->dev, skreq->sksg_dma_address, |
525 | skreq->n_sg * | |
526 | sizeof(struct fit_sg_descriptor), | |
527 | DMA_TO_DEVICE); | |
528 | ||
91f85da4 | 529 | /* Either a FIT msg is in progress or we have to start one. */ |
74c74282 BVA |
530 | if (skd_max_req_per_msg == 1) { |
531 | skmsg = NULL; | |
532 | } else { | |
533 | spin_lock_irqsave(&skdev->lock, flags); | |
534 | skmsg = skdev->skmsg; | |
535 | } | |
91f85da4 BVA |
536 | if (!skmsg) { |
537 | skmsg = &skdev->skmsg_table[tag]; | |
538 | skdev->skmsg = skmsg; | |
539 | ||
540 | /* Initialize the FIT msg header */ | |
541 | fmh = &skmsg->msg_buf->fmh; | |
542 | memset(fmh, 0, sizeof(*fmh)); | |
543 | fmh->protocol_id = FIT_PROTOCOL_ID_SOFIT; | |
544 | skmsg->length = sizeof(*fmh); | |
545 | } else { | |
546 | fmh = &skmsg->msg_buf->fmh; | |
547 | } | |
548 | ||
549 | skreq->fitmsg_id = skmsg->id; | |
550 | ||
551 | scsi_req = &skmsg->msg_buf->scsi[fmh->num_protocol_cmds_coalesced]; | |
552 | memset(scsi_req, 0, sizeof(*scsi_req)); | |
553 | ||
91f85da4 | 554 | scsi_req->hdr.tag = skreq->id; |
e2bb5548 BVA |
555 | scsi_req->hdr.sg_list_dma_address = |
556 | cpu_to_be64(skreq->sksg_dma_address); | |
91f85da4 | 557 | |
e2bb5548 | 558 | if (req_op(req) == REQ_OP_FLUSH) { |
91f85da4 BVA |
559 | skd_prep_zerosize_flush_cdb(scsi_req, skreq); |
560 | SKD_ASSERT(skreq->flush_cmd == 1); | |
561 | } else { | |
562 | skd_prep_rw_cdb(scsi_req, data_dir, lba, count); | |
563 | } | |
564 | ||
e2bb5548 | 565 | if (req->cmd_flags & REQ_FUA) |
91f85da4 BVA |
566 | scsi_req->cdb[1] |= SKD_FUA_NV; |
567 | ||
568 | scsi_req->hdr.sg_list_len_bytes = cpu_to_be32(skreq->sg_byte_count); | |
569 | ||
570 | /* Complete resource allocations. */ | |
571 | skreq->state = SKD_REQ_STATE_BUSY; | |
572 | ||
573 | skmsg->length += sizeof(struct skd_scsi_request); | |
574 | fmh->num_protocol_cmds_coalesced++; | |
575 | ||
91f85da4 | 576 | dev_dbg(&skdev->pdev->dev, "req=0x%x busy=%d\n", skreq->id, |
d4d0f5fc | 577 | skd_in_flight(skdev)); |
91f85da4 BVA |
578 | |
579 | /* | |
580 | * If the FIT msg buffer is full send it. | |
581 | */ | |
74c74282 | 582 | if (skd_max_req_per_msg == 1) { |
91f85da4 | 583 | skd_send_fitmsg(skdev, skmsg); |
74c74282 | 584 | } else { |
c39c6c77 | 585 | if (mqd->last || |
74c74282 BVA |
586 | fmh->num_protocol_cmds_coalesced >= skd_max_req_per_msg) { |
587 | skd_send_fitmsg(skdev, skmsg); | |
588 | skdev->skmsg = NULL; | |
589 | } | |
590 | spin_unlock_irqrestore(&skdev->lock, flags); | |
91f85da4 | 591 | } |
e67f86b3 | 592 | |
ca33dd92 | 593 | return BLK_STS_OK; |
e67f86b3 AB |
594 | } |
595 | ||
f2fe4459 BVA |
596 | static enum blk_eh_timer_return skd_timed_out(struct request *req, |
597 | bool reserved) | |
a74d5b76 BVA |
598 | { |
599 | struct skd_device *skdev = req->q->queuedata; | |
600 | ||
601 | dev_err(&skdev->pdev->dev, "request with tag %#x timed out\n", | |
602 | blk_mq_unique_tag(req)); | |
603 | ||
f2fe4459 | 604 | return BLK_EH_RESET_TIMER; |
a74d5b76 BVA |
605 | } |
606 | ||
296cb94c | 607 | static void skd_complete_rq(struct request *req) |
a74d5b76 | 608 | { |
a74d5b76 | 609 | struct skd_request_context *skreq = blk_mq_rq_to_pdu(req); |
a74d5b76 | 610 | |
f2fe4459 | 611 | blk_mq_end_request(req, skreq->status); |
a74d5b76 BVA |
612 | } |
613 | ||
2a842aca | 614 | static bool skd_preop_sg_list(struct skd_device *skdev, |
38d4a1bb | 615 | struct skd_request_context *skreq) |
e67f86b3 | 616 | { |
e7278a8b | 617 | struct request *req = blk_mq_rq_from_pdu(skreq); |
06f824c4 | 618 | struct scatterlist *sgl = &skreq->sg[0], *sg; |
e67f86b3 AB |
619 | int n_sg; |
620 | int i; | |
621 | ||
622 | skreq->sg_byte_count = 0; | |
623 | ||
b1824eef BVA |
624 | WARN_ON_ONCE(skreq->data_dir != DMA_TO_DEVICE && |
625 | skreq->data_dir != DMA_FROM_DEVICE); | |
e67f86b3 | 626 | |
06f824c4 | 627 | n_sg = blk_rq_map_sg(skdev->queue, req, sgl); |
e67f86b3 | 628 | if (n_sg <= 0) |
2a842aca | 629 | return false; |
e67f86b3 AB |
630 | |
631 | /* | |
632 | * Map scatterlist to PCI bus addresses. | |
633 | * Note PCI might change the number of entries. | |
634 | */ | |
13812621 | 635 | n_sg = dma_map_sg(&skdev->pdev->dev, sgl, n_sg, skreq->data_dir); |
e67f86b3 | 636 | if (n_sg <= 0) |
2a842aca | 637 | return false; |
e67f86b3 AB |
638 | |
639 | SKD_ASSERT(n_sg <= skdev->sgs_per_request); | |
640 | ||
641 | skreq->n_sg = n_sg; | |
642 | ||
06f824c4 | 643 | for_each_sg(sgl, sg, n_sg, i) { |
e67f86b3 | 644 | struct fit_sg_descriptor *sgd = &skreq->sksg_list[i]; |
06f824c4 BVA |
645 | u32 cnt = sg_dma_len(sg); |
646 | uint64_t dma_addr = sg_dma_address(sg); | |
e67f86b3 AB |
647 | |
648 | sgd->control = FIT_SGD_CONTROL_NOT_LAST; | |
649 | sgd->byte_count = cnt; | |
650 | skreq->sg_byte_count += cnt; | |
651 | sgd->host_side_addr = dma_addr; | |
652 | sgd->dev_side_addr = 0; | |
653 | } | |
654 | ||
655 | skreq->sksg_list[n_sg - 1].next_desc_ptr = 0LL; | |
656 | skreq->sksg_list[n_sg - 1].control = FIT_SGD_CONTROL_LAST; | |
657 | ||
658 | if (unlikely(skdev->dbg_level > 1)) { | |
f98806d6 | 659 | dev_dbg(&skdev->pdev->dev, |
ea870bb2 HD |
660 | "skreq=%x sksg_list=%p sksg_dma=%pad\n", |
661 | skreq->id, skreq->sksg_list, &skreq->sksg_dma_address); | |
e67f86b3 AB |
662 | for (i = 0; i < n_sg; i++) { |
663 | struct fit_sg_descriptor *sgd = &skreq->sksg_list[i]; | |
f98806d6 BVA |
664 | |
665 | dev_dbg(&skdev->pdev->dev, | |
666 | " sg[%d] count=%u ctrl=0x%x addr=0x%llx next=0x%llx\n", | |
667 | i, sgd->byte_count, sgd->control, | |
668 | sgd->host_side_addr, sgd->next_desc_ptr); | |
e67f86b3 AB |
669 | } |
670 | } | |
671 | ||
2a842aca | 672 | return true; |
e67f86b3 AB |
673 | } |
674 | ||
fcd37eb3 | 675 | static void skd_postop_sg_list(struct skd_device *skdev, |
38d4a1bb | 676 | struct skd_request_context *skreq) |
e67f86b3 | 677 | { |
e67f86b3 AB |
678 | /* |
679 | * restore the next ptr for next IO request so we | |
680 | * don't have to set it every time. | |
681 | */ | |
682 | skreq->sksg_list[skreq->n_sg - 1].next_desc_ptr = | |
683 | skreq->sksg_dma_address + | |
684 | ((skreq->n_sg) * sizeof(struct fit_sg_descriptor)); | |
13812621 CH |
685 | dma_unmap_sg(&skdev->pdev->dev, &skreq->sg[0], skreq->n_sg, |
686 | skreq->data_dir); | |
e67f86b3 AB |
687 | } |
688 | ||
e67f86b3 AB |
689 | /* |
690 | ***************************************************************************** | |
691 | * TIMER | |
692 | ***************************************************************************** | |
693 | */ | |
694 | ||
695 | static void skd_timer_tick_not_online(struct skd_device *skdev); | |
696 | ||
ca33dd92 BVA |
697 | static void skd_start_queue(struct work_struct *work) |
698 | { | |
699 | struct skd_device *skdev = container_of(work, typeof(*skdev), | |
700 | start_queue); | |
701 | ||
702 | /* | |
703 | * Although it is safe to call blk_start_queue() from interrupt | |
704 | * context, blk_mq_start_hw_queues() must not be called from | |
705 | * interrupt context. | |
706 | */ | |
707 | blk_mq_start_hw_queues(skdev->queue); | |
708 | } | |
709 | ||
e99e88a9 | 710 | static void skd_timer_tick(struct timer_list *t) |
e67f86b3 | 711 | { |
e99e88a9 | 712 | struct skd_device *skdev = from_timer(skdev, t, timer); |
e67f86b3 AB |
713 | unsigned long reqflags; |
714 | u32 state; | |
715 | ||
716 | if (skdev->state == SKD_DRVR_STATE_FAULT) | |
717 | /* The driver has declared fault, and we want it to | |
718 | * stay that way until driver is reloaded. | |
719 | */ | |
720 | return; | |
721 | ||
722 | spin_lock_irqsave(&skdev->lock, reqflags); | |
723 | ||
724 | state = SKD_READL(skdev, FIT_STATUS); | |
725 | state &= FIT_SR_DRIVE_STATE_MASK; | |
726 | if (state != skdev->drive_state) | |
727 | skd_isr_fwstate(skdev); | |
728 | ||
a74d5b76 | 729 | if (skdev->state != SKD_DRVR_STATE_ONLINE) |
e67f86b3 | 730 | skd_timer_tick_not_online(skdev); |
e67f86b3 | 731 | |
e67f86b3 AB |
732 | mod_timer(&skdev->timer, (jiffies + HZ)); |
733 | ||
734 | spin_unlock_irqrestore(&skdev->lock, reqflags); | |
735 | } | |
736 | ||
737 | static void skd_timer_tick_not_online(struct skd_device *skdev) | |
738 | { | |
739 | switch (skdev->state) { | |
740 | case SKD_DRVR_STATE_IDLE: | |
741 | case SKD_DRVR_STATE_LOAD: | |
742 | break; | |
743 | case SKD_DRVR_STATE_BUSY_SANITIZE: | |
f98806d6 BVA |
744 | dev_dbg(&skdev->pdev->dev, |
745 | "drive busy sanitize[%x], driver[%x]\n", | |
746 | skdev->drive_state, skdev->state); | |
e67f86b3 AB |
747 | /* If we've been in sanitize for 3 seconds, we figure we're not |
748 | * going to get anymore completions, so recover requests now | |
749 | */ | |
750 | if (skdev->timer_countdown > 0) { | |
751 | skdev->timer_countdown--; | |
752 | return; | |
753 | } | |
79ce12a8 | 754 | skd_recover_requests(skdev); |
e67f86b3 AB |
755 | break; |
756 | ||
757 | case SKD_DRVR_STATE_BUSY: | |
758 | case SKD_DRVR_STATE_BUSY_IMMINENT: | |
759 | case SKD_DRVR_STATE_BUSY_ERASE: | |
f98806d6 BVA |
760 | dev_dbg(&skdev->pdev->dev, "busy[%x], countdown=%d\n", |
761 | skdev->state, skdev->timer_countdown); | |
e67f86b3 AB |
762 | if (skdev->timer_countdown > 0) { |
763 | skdev->timer_countdown--; | |
764 | return; | |
765 | } | |
f98806d6 BVA |
766 | dev_dbg(&skdev->pdev->dev, |
767 | "busy[%x], timedout=%d, restarting device.", | |
768 | skdev->state, skdev->timer_countdown); | |
e67f86b3 AB |
769 | skd_restart_device(skdev); |
770 | break; | |
771 | ||
772 | case SKD_DRVR_STATE_WAIT_BOOT: | |
773 | case SKD_DRVR_STATE_STARTING: | |
774 | if (skdev->timer_countdown > 0) { | |
775 | skdev->timer_countdown--; | |
776 | return; | |
777 | } | |
778 | /* For now, we fault the drive. Could attempt resets to | |
779 | * revcover at some point. */ | |
780 | skdev->state = SKD_DRVR_STATE_FAULT; | |
781 | ||
f98806d6 BVA |
782 | dev_err(&skdev->pdev->dev, "DriveFault Connect Timeout (%x)\n", |
783 | skdev->drive_state); | |
e67f86b3 AB |
784 | |
785 | /*start the queue so we can respond with error to requests */ | |
786 | /* wakeup anyone waiting for startup complete */ | |
ca33dd92 | 787 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
788 | skdev->gendisk_on = -1; |
789 | wake_up_interruptible(&skdev->waitq); | |
790 | break; | |
791 | ||
792 | case SKD_DRVR_STATE_ONLINE: | |
793 | /* shouldn't get here. */ | |
794 | break; | |
795 | ||
796 | case SKD_DRVR_STATE_PAUSING: | |
797 | case SKD_DRVR_STATE_PAUSED: | |
798 | break; | |
799 | ||
e67f86b3 AB |
800 | case SKD_DRVR_STATE_RESTARTING: |
801 | if (skdev->timer_countdown > 0) { | |
802 | skdev->timer_countdown--; | |
803 | return; | |
804 | } | |
805 | /* For now, we fault the drive. Could attempt resets to | |
806 | * revcover at some point. */ | |
807 | skdev->state = SKD_DRVR_STATE_FAULT; | |
f98806d6 BVA |
808 | dev_err(&skdev->pdev->dev, |
809 | "DriveFault Reconnect Timeout (%x)\n", | |
810 | skdev->drive_state); | |
e67f86b3 AB |
811 | |
812 | /* | |
813 | * Recovering does two things: | |
814 | * 1. completes IO with error | |
815 | * 2. reclaims dma resources | |
816 | * When is it safe to recover requests? | |
817 | * - if the drive state is faulted | |
818 | * - if the state is still soft reset after out timeout | |
819 | * - if the drive registers are dead (state = FF) | |
820 | * If it is "unsafe", we still need to recover, so we will | |
821 | * disable pci bus mastering and disable our interrupts. | |
822 | */ | |
823 | ||
824 | if ((skdev->drive_state == FIT_SR_DRIVE_SOFT_RESET) || | |
825 | (skdev->drive_state == FIT_SR_DRIVE_FAULT) || | |
826 | (skdev->drive_state == FIT_SR_DRIVE_STATE_MASK)) | |
827 | /* It never came out of soft reset. Try to | |
828 | * recover the requests and then let them | |
829 | * fail. This is to mitigate hung processes. */ | |
79ce12a8 | 830 | skd_recover_requests(skdev); |
e67f86b3 | 831 | else { |
f98806d6 BVA |
832 | dev_err(&skdev->pdev->dev, "Disable BusMaster (%x)\n", |
833 | skdev->drive_state); | |
e67f86b3 AB |
834 | pci_disable_device(skdev->pdev); |
835 | skd_disable_interrupts(skdev); | |
79ce12a8 | 836 | skd_recover_requests(skdev); |
e67f86b3 AB |
837 | } |
838 | ||
839 | /*start the queue so we can respond with error to requests */ | |
840 | /* wakeup anyone waiting for startup complete */ | |
ca33dd92 | 841 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
842 | skdev->gendisk_on = -1; |
843 | wake_up_interruptible(&skdev->waitq); | |
844 | break; | |
845 | ||
846 | case SKD_DRVR_STATE_RESUMING: | |
847 | case SKD_DRVR_STATE_STOPPING: | |
848 | case SKD_DRVR_STATE_SYNCING: | |
849 | case SKD_DRVR_STATE_FAULT: | |
850 | case SKD_DRVR_STATE_DISAPPEARED: | |
851 | default: | |
852 | break; | |
853 | } | |
854 | } | |
855 | ||
856 | static int skd_start_timer(struct skd_device *skdev) | |
857 | { | |
858 | int rc; | |
859 | ||
e99e88a9 | 860 | timer_setup(&skdev->timer, skd_timer_tick, 0); |
e67f86b3 AB |
861 | |
862 | rc = mod_timer(&skdev->timer, (jiffies + HZ)); | |
863 | if (rc) | |
f98806d6 | 864 | dev_err(&skdev->pdev->dev, "failed to start timer %d\n", rc); |
e67f86b3 AB |
865 | return rc; |
866 | } | |
867 | ||
868 | static void skd_kill_timer(struct skd_device *skdev) | |
869 | { | |
870 | del_timer_sync(&skdev->timer); | |
871 | } | |
872 | ||
e67f86b3 AB |
873 | /* |
874 | ***************************************************************************** | |
875 | * INTERNAL REQUESTS -- generated by driver itself | |
876 | ***************************************************************************** | |
877 | */ | |
878 | ||
879 | static int skd_format_internal_skspcl(struct skd_device *skdev) | |
880 | { | |
881 | struct skd_special_context *skspcl = &skdev->internal_skspcl; | |
882 | struct fit_sg_descriptor *sgd = &skspcl->req.sksg_list[0]; | |
883 | struct fit_msg_hdr *fmh; | |
884 | uint64_t dma_address; | |
885 | struct skd_scsi_request *scsi; | |
886 | ||
d891fe60 | 887 | fmh = &skspcl->msg_buf->fmh; |
e67f86b3 AB |
888 | fmh->protocol_id = FIT_PROTOCOL_ID_SOFIT; |
889 | fmh->num_protocol_cmds_coalesced = 1; | |
890 | ||
d891fe60 | 891 | scsi = &skspcl->msg_buf->scsi[0]; |
e67f86b3 AB |
892 | memset(scsi, 0, sizeof(*scsi)); |
893 | dma_address = skspcl->req.sksg_dma_address; | |
894 | scsi->hdr.sg_list_dma_address = cpu_to_be64(dma_address); | |
32494df9 | 895 | skspcl->req.n_sg = 1; |
e67f86b3 AB |
896 | sgd->control = FIT_SGD_CONTROL_LAST; |
897 | sgd->byte_count = 0; | |
898 | sgd->host_side_addr = skspcl->db_dma_address; | |
899 | sgd->dev_side_addr = 0; | |
900 | sgd->next_desc_ptr = 0LL; | |
901 | ||
902 | return 1; | |
903 | } | |
904 | ||
905 | #define WR_BUF_SIZE SKD_N_INTERNAL_BYTES | |
906 | ||
907 | static void skd_send_internal_skspcl(struct skd_device *skdev, | |
908 | struct skd_special_context *skspcl, | |
909 | u8 opcode) | |
910 | { | |
911 | struct fit_sg_descriptor *sgd = &skspcl->req.sksg_list[0]; | |
912 | struct skd_scsi_request *scsi; | |
913 | unsigned char *buf = skspcl->data_buf; | |
914 | int i; | |
915 | ||
916 | if (skspcl->req.state != SKD_REQ_STATE_IDLE) | |
917 | /* | |
918 | * A refresh is already in progress. | |
919 | * Just wait for it to finish. | |
920 | */ | |
921 | return; | |
922 | ||
e67f86b3 | 923 | skspcl->req.state = SKD_REQ_STATE_BUSY; |
e67f86b3 | 924 | |
d891fe60 | 925 | scsi = &skspcl->msg_buf->scsi[0]; |
e67f86b3 AB |
926 | scsi->hdr.tag = skspcl->req.id; |
927 | ||
928 | memset(scsi->cdb, 0, sizeof(scsi->cdb)); | |
929 | ||
930 | switch (opcode) { | |
931 | case TEST_UNIT_READY: | |
932 | scsi->cdb[0] = TEST_UNIT_READY; | |
933 | sgd->byte_count = 0; | |
934 | scsi->hdr.sg_list_len_bytes = 0; | |
935 | break; | |
936 | ||
937 | case READ_CAPACITY: | |
938 | scsi->cdb[0] = READ_CAPACITY; | |
939 | sgd->byte_count = SKD_N_READ_CAP_BYTES; | |
940 | scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count); | |
941 | break; | |
942 | ||
943 | case INQUIRY: | |
944 | scsi->cdb[0] = INQUIRY; | |
945 | scsi->cdb[1] = 0x01; /* evpd */ | |
946 | scsi->cdb[2] = 0x80; /* serial number page */ | |
947 | scsi->cdb[4] = 0x10; | |
948 | sgd->byte_count = 16; | |
949 | scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count); | |
950 | break; | |
951 | ||
952 | case SYNCHRONIZE_CACHE: | |
953 | scsi->cdb[0] = SYNCHRONIZE_CACHE; | |
954 | sgd->byte_count = 0; | |
955 | scsi->hdr.sg_list_len_bytes = 0; | |
956 | break; | |
957 | ||
958 | case WRITE_BUFFER: | |
959 | scsi->cdb[0] = WRITE_BUFFER; | |
960 | scsi->cdb[1] = 0x02; | |
961 | scsi->cdb[7] = (WR_BUF_SIZE & 0xFF00) >> 8; | |
962 | scsi->cdb[8] = WR_BUF_SIZE & 0xFF; | |
963 | sgd->byte_count = WR_BUF_SIZE; | |
964 | scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count); | |
965 | /* fill incrementing byte pattern */ | |
966 | for (i = 0; i < sgd->byte_count; i++) | |
967 | buf[i] = i & 0xFF; | |
968 | break; | |
969 | ||
970 | case READ_BUFFER: | |
971 | scsi->cdb[0] = READ_BUFFER; | |
972 | scsi->cdb[1] = 0x02; | |
973 | scsi->cdb[7] = (WR_BUF_SIZE & 0xFF00) >> 8; | |
974 | scsi->cdb[8] = WR_BUF_SIZE & 0xFF; | |
975 | sgd->byte_count = WR_BUF_SIZE; | |
976 | scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count); | |
977 | memset(skspcl->data_buf, 0, sgd->byte_count); | |
978 | break; | |
979 | ||
980 | default: | |
981 | SKD_ASSERT("Don't know what to send"); | |
982 | return; | |
983 | ||
984 | } | |
985 | skd_send_special_fitmsg(skdev, skspcl); | |
986 | } | |
987 | ||
988 | static void skd_refresh_device_data(struct skd_device *skdev) | |
989 | { | |
990 | struct skd_special_context *skspcl = &skdev->internal_skspcl; | |
991 | ||
992 | skd_send_internal_skspcl(skdev, skspcl, TEST_UNIT_READY); | |
993 | } | |
994 | ||
995 | static int skd_chk_read_buf(struct skd_device *skdev, | |
996 | struct skd_special_context *skspcl) | |
997 | { | |
998 | unsigned char *buf = skspcl->data_buf; | |
999 | int i; | |
1000 | ||
1001 | /* check for incrementing byte pattern */ | |
1002 | for (i = 0; i < WR_BUF_SIZE; i++) | |
1003 | if (buf[i] != (i & 0xFF)) | |
1004 | return 1; | |
1005 | ||
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | static void skd_log_check_status(struct skd_device *skdev, u8 status, u8 key, | |
1010 | u8 code, u8 qual, u8 fruc) | |
1011 | { | |
1012 | /* If the check condition is of special interest, log a message */ | |
1013 | if ((status == SAM_STAT_CHECK_CONDITION) && (key == 0x02) | |
1014 | && (code == 0x04) && (qual == 0x06)) { | |
f98806d6 BVA |
1015 | dev_err(&skdev->pdev->dev, |
1016 | "*** LOST_WRITE_DATA ERROR *** key/asc/ascq/fruc %02x/%02x/%02x/%02x\n", | |
1017 | key, code, qual, fruc); | |
e67f86b3 AB |
1018 | } |
1019 | } | |
1020 | ||
1021 | static void skd_complete_internal(struct skd_device *skdev, | |
85e34112 BVA |
1022 | struct fit_completion_entry_v1 *skcomp, |
1023 | struct fit_comp_error_info *skerr, | |
e67f86b3 AB |
1024 | struct skd_special_context *skspcl) |
1025 | { | |
1026 | u8 *buf = skspcl->data_buf; | |
1027 | u8 status; | |
1028 | int i; | |
d891fe60 | 1029 | struct skd_scsi_request *scsi = &skspcl->msg_buf->scsi[0]; |
e67f86b3 | 1030 | |
760b48ca BVA |
1031 | lockdep_assert_held(&skdev->lock); |
1032 | ||
e67f86b3 AB |
1033 | SKD_ASSERT(skspcl == &skdev->internal_skspcl); |
1034 | ||
f98806d6 | 1035 | dev_dbg(&skdev->pdev->dev, "complete internal %x\n", scsi->cdb[0]); |
e67f86b3 | 1036 | |
a3db102d BVA |
1037 | dma_sync_single_for_cpu(&skdev->pdev->dev, |
1038 | skspcl->db_dma_address, | |
1039 | skspcl->req.sksg_list[0].byte_count, | |
1040 | DMA_BIDIRECTIONAL); | |
1041 | ||
e67f86b3 AB |
1042 | skspcl->req.completion = *skcomp; |
1043 | skspcl->req.state = SKD_REQ_STATE_IDLE; | |
e67f86b3 AB |
1044 | |
1045 | status = skspcl->req.completion.status; | |
1046 | ||
1047 | skd_log_check_status(skdev, status, skerr->key, skerr->code, | |
1048 | skerr->qual, skerr->fruc); | |
1049 | ||
1050 | switch (scsi->cdb[0]) { | |
1051 | case TEST_UNIT_READY: | |
1052 | if (status == SAM_STAT_GOOD) | |
1053 | skd_send_internal_skspcl(skdev, skspcl, WRITE_BUFFER); | |
1054 | else if ((status == SAM_STAT_CHECK_CONDITION) && | |
1055 | (skerr->key == MEDIUM_ERROR)) | |
1056 | skd_send_internal_skspcl(skdev, skspcl, WRITE_BUFFER); | |
1057 | else { | |
1058 | if (skdev->state == SKD_DRVR_STATE_STOPPING) { | |
f98806d6 BVA |
1059 | dev_dbg(&skdev->pdev->dev, |
1060 | "TUR failed, don't send anymore state 0x%x\n", | |
1061 | skdev->state); | |
e67f86b3 AB |
1062 | return; |
1063 | } | |
f98806d6 BVA |
1064 | dev_dbg(&skdev->pdev->dev, |
1065 | "**** TUR failed, retry skerr\n"); | |
fb4844b8 BVA |
1066 | skd_send_internal_skspcl(skdev, skspcl, |
1067 | TEST_UNIT_READY); | |
e67f86b3 AB |
1068 | } |
1069 | break; | |
1070 | ||
1071 | case WRITE_BUFFER: | |
1072 | if (status == SAM_STAT_GOOD) | |
1073 | skd_send_internal_skspcl(skdev, skspcl, READ_BUFFER); | |
1074 | else { | |
1075 | if (skdev->state == SKD_DRVR_STATE_STOPPING) { | |
f98806d6 BVA |
1076 | dev_dbg(&skdev->pdev->dev, |
1077 | "write buffer failed, don't send anymore state 0x%x\n", | |
1078 | skdev->state); | |
e67f86b3 AB |
1079 | return; |
1080 | } | |
f98806d6 BVA |
1081 | dev_dbg(&skdev->pdev->dev, |
1082 | "**** write buffer failed, retry skerr\n"); | |
fb4844b8 BVA |
1083 | skd_send_internal_skspcl(skdev, skspcl, |
1084 | TEST_UNIT_READY); | |
e67f86b3 AB |
1085 | } |
1086 | break; | |
1087 | ||
1088 | case READ_BUFFER: | |
1089 | if (status == SAM_STAT_GOOD) { | |
1090 | if (skd_chk_read_buf(skdev, skspcl) == 0) | |
1091 | skd_send_internal_skspcl(skdev, skspcl, | |
1092 | READ_CAPACITY); | |
1093 | else { | |
f98806d6 BVA |
1094 | dev_err(&skdev->pdev->dev, |
1095 | "*** W/R Buffer mismatch %d ***\n", | |
1096 | skdev->connect_retries); | |
e67f86b3 AB |
1097 | if (skdev->connect_retries < |
1098 | SKD_MAX_CONNECT_RETRIES) { | |
1099 | skdev->connect_retries++; | |
1100 | skd_soft_reset(skdev); | |
1101 | } else { | |
f98806d6 BVA |
1102 | dev_err(&skdev->pdev->dev, |
1103 | "W/R Buffer Connect Error\n"); | |
e67f86b3 AB |
1104 | return; |
1105 | } | |
1106 | } | |
1107 | ||
1108 | } else { | |
1109 | if (skdev->state == SKD_DRVR_STATE_STOPPING) { | |
f98806d6 BVA |
1110 | dev_dbg(&skdev->pdev->dev, |
1111 | "read buffer failed, don't send anymore state 0x%x\n", | |
1112 | skdev->state); | |
e67f86b3 AB |
1113 | return; |
1114 | } | |
f98806d6 BVA |
1115 | dev_dbg(&skdev->pdev->dev, |
1116 | "**** read buffer failed, retry skerr\n"); | |
fb4844b8 BVA |
1117 | skd_send_internal_skspcl(skdev, skspcl, |
1118 | TEST_UNIT_READY); | |
e67f86b3 AB |
1119 | } |
1120 | break; | |
1121 | ||
1122 | case READ_CAPACITY: | |
1123 | skdev->read_cap_is_valid = 0; | |
1124 | if (status == SAM_STAT_GOOD) { | |
1125 | skdev->read_cap_last_lba = | |
1126 | (buf[0] << 24) | (buf[1] << 16) | | |
1127 | (buf[2] << 8) | buf[3]; | |
1128 | skdev->read_cap_blocksize = | |
1129 | (buf[4] << 24) | (buf[5] << 16) | | |
1130 | (buf[6] << 8) | buf[7]; | |
1131 | ||
f98806d6 BVA |
1132 | dev_dbg(&skdev->pdev->dev, "last lba %d, bs %d\n", |
1133 | skdev->read_cap_last_lba, | |
1134 | skdev->read_cap_blocksize); | |
e67f86b3 AB |
1135 | |
1136 | set_capacity(skdev->disk, skdev->read_cap_last_lba + 1); | |
1137 | ||
1138 | skdev->read_cap_is_valid = 1; | |
1139 | ||
1140 | skd_send_internal_skspcl(skdev, skspcl, INQUIRY); | |
1141 | } else if ((status == SAM_STAT_CHECK_CONDITION) && | |
1142 | (skerr->key == MEDIUM_ERROR)) { | |
1143 | skdev->read_cap_last_lba = ~0; | |
1144 | set_capacity(skdev->disk, skdev->read_cap_last_lba + 1); | |
f98806d6 | 1145 | dev_dbg(&skdev->pdev->dev, "**** MEDIUM ERROR caused READCAP to fail, ignore failure and continue to inquiry\n"); |
e67f86b3 AB |
1146 | skd_send_internal_skspcl(skdev, skspcl, INQUIRY); |
1147 | } else { | |
f98806d6 | 1148 | dev_dbg(&skdev->pdev->dev, "**** READCAP failed, retry TUR\n"); |
e67f86b3 AB |
1149 | skd_send_internal_skspcl(skdev, skspcl, |
1150 | TEST_UNIT_READY); | |
1151 | } | |
1152 | break; | |
1153 | ||
1154 | case INQUIRY: | |
1155 | skdev->inquiry_is_valid = 0; | |
1156 | if (status == SAM_STAT_GOOD) { | |
1157 | skdev->inquiry_is_valid = 1; | |
1158 | ||
1159 | for (i = 0; i < 12; i++) | |
1160 | skdev->inq_serial_num[i] = buf[i + 4]; | |
1161 | skdev->inq_serial_num[12] = 0; | |
1162 | } | |
1163 | ||
1164 | if (skd_unquiesce_dev(skdev) < 0) | |
f98806d6 | 1165 | dev_dbg(&skdev->pdev->dev, "**** failed, to ONLINE device\n"); |
e67f86b3 AB |
1166 | /* connection is complete */ |
1167 | skdev->connect_retries = 0; | |
1168 | break; | |
1169 | ||
1170 | case SYNCHRONIZE_CACHE: | |
1171 | if (status == SAM_STAT_GOOD) | |
1172 | skdev->sync_done = 1; | |
1173 | else | |
1174 | skdev->sync_done = -1; | |
1175 | wake_up_interruptible(&skdev->waitq); | |
1176 | break; | |
1177 | ||
1178 | default: | |
1179 | SKD_ASSERT("we didn't send this"); | |
1180 | } | |
1181 | } | |
1182 | ||
1183 | /* | |
1184 | ***************************************************************************** | |
1185 | * FIT MESSAGES | |
1186 | ***************************************************************************** | |
1187 | */ | |
1188 | ||
1189 | static void skd_send_fitmsg(struct skd_device *skdev, | |
1190 | struct skd_fitmsg_context *skmsg) | |
1191 | { | |
1192 | u64 qcmd; | |
e67f86b3 | 1193 | |
ea870bb2 HD |
1194 | dev_dbg(&skdev->pdev->dev, "dma address %pad, busy=%d\n", |
1195 | &skmsg->mb_dma_address, skd_in_flight(skdev)); | |
6507f436 | 1196 | dev_dbg(&skdev->pdev->dev, "msg_buf %p\n", skmsg->msg_buf); |
e67f86b3 AB |
1197 | |
1198 | qcmd = skmsg->mb_dma_address; | |
1199 | qcmd |= FIT_QCMD_QID_NORMAL; | |
1200 | ||
e67f86b3 AB |
1201 | if (unlikely(skdev->dbg_level > 1)) { |
1202 | u8 *bp = (u8 *)skmsg->msg_buf; | |
1203 | int i; | |
1204 | for (i = 0; i < skmsg->length; i += 8) { | |
f98806d6 BVA |
1205 | dev_dbg(&skdev->pdev->dev, "msg[%2d] %8ph\n", i, |
1206 | &bp[i]); | |
e67f86b3 AB |
1207 | if (i == 0) |
1208 | i = 64 - 8; | |
1209 | } | |
1210 | } | |
1211 | ||
1212 | if (skmsg->length > 256) | |
1213 | qcmd |= FIT_QCMD_MSGSIZE_512; | |
1214 | else if (skmsg->length > 128) | |
1215 | qcmd |= FIT_QCMD_MSGSIZE_256; | |
1216 | else if (skmsg->length > 64) | |
1217 | qcmd |= FIT_QCMD_MSGSIZE_128; | |
1218 | else | |
1219 | /* | |
1220 | * This makes no sense because the FIT msg header is | |
1221 | * 64 bytes. If the msg is only 64 bytes long it has | |
1222 | * no payload. | |
1223 | */ | |
1224 | qcmd |= FIT_QCMD_MSGSIZE_64; | |
1225 | ||
a3db102d BVA |
1226 | dma_sync_single_for_device(&skdev->pdev->dev, skmsg->mb_dma_address, |
1227 | skmsg->length, DMA_TO_DEVICE); | |
1228 | ||
5fbd545c BVA |
1229 | /* Make sure skd_msg_buf is written before the doorbell is triggered. */ |
1230 | smp_wmb(); | |
1231 | ||
e67f86b3 | 1232 | SKD_WRITEQ(skdev, qcmd, FIT_Q_COMMAND); |
e67f86b3 AB |
1233 | } |
1234 | ||
1235 | static void skd_send_special_fitmsg(struct skd_device *skdev, | |
1236 | struct skd_special_context *skspcl) | |
1237 | { | |
1238 | u64 qcmd; | |
1239 | ||
a3db102d BVA |
1240 | WARN_ON_ONCE(skspcl->req.n_sg != 1); |
1241 | ||
e67f86b3 AB |
1242 | if (unlikely(skdev->dbg_level > 1)) { |
1243 | u8 *bp = (u8 *)skspcl->msg_buf; | |
1244 | int i; | |
1245 | ||
1246 | for (i = 0; i < SKD_N_SPECIAL_FITMSG_BYTES; i += 8) { | |
f98806d6 BVA |
1247 | dev_dbg(&skdev->pdev->dev, " spcl[%2d] %8ph\n", i, |
1248 | &bp[i]); | |
e67f86b3 AB |
1249 | if (i == 0) |
1250 | i = 64 - 8; | |
1251 | } | |
1252 | ||
f98806d6 | 1253 | dev_dbg(&skdev->pdev->dev, |
ea870bb2 | 1254 | "skspcl=%p id=%04x sksg_list=%p sksg_dma=%pad\n", |
f98806d6 | 1255 | skspcl, skspcl->req.id, skspcl->req.sksg_list, |
ea870bb2 | 1256 | &skspcl->req.sksg_dma_address); |
e67f86b3 AB |
1257 | for (i = 0; i < skspcl->req.n_sg; i++) { |
1258 | struct fit_sg_descriptor *sgd = | |
1259 | &skspcl->req.sksg_list[i]; | |
1260 | ||
f98806d6 BVA |
1261 | dev_dbg(&skdev->pdev->dev, |
1262 | " sg[%d] count=%u ctrl=0x%x addr=0x%llx next=0x%llx\n", | |
1263 | i, sgd->byte_count, sgd->control, | |
1264 | sgd->host_side_addr, sgd->next_desc_ptr); | |
e67f86b3 AB |
1265 | } |
1266 | } | |
1267 | ||
1268 | /* | |
1269 | * Special FIT msgs are always 128 bytes: a 64-byte FIT hdr | |
1270 | * and one 64-byte SSDI command. | |
1271 | */ | |
1272 | qcmd = skspcl->mb_dma_address; | |
1273 | qcmd |= FIT_QCMD_QID_NORMAL + FIT_QCMD_MSGSIZE_128; | |
1274 | ||
a3db102d BVA |
1275 | dma_sync_single_for_device(&skdev->pdev->dev, skspcl->mb_dma_address, |
1276 | SKD_N_SPECIAL_FITMSG_BYTES, DMA_TO_DEVICE); | |
1277 | dma_sync_single_for_device(&skdev->pdev->dev, | |
1278 | skspcl->req.sksg_dma_address, | |
1279 | 1 * sizeof(struct fit_sg_descriptor), | |
1280 | DMA_TO_DEVICE); | |
1281 | dma_sync_single_for_device(&skdev->pdev->dev, | |
1282 | skspcl->db_dma_address, | |
1283 | skspcl->req.sksg_list[0].byte_count, | |
1284 | DMA_BIDIRECTIONAL); | |
1285 | ||
5fbd545c BVA |
1286 | /* Make sure skd_msg_buf is written before the doorbell is triggered. */ |
1287 | smp_wmb(); | |
1288 | ||
e67f86b3 AB |
1289 | SKD_WRITEQ(skdev, qcmd, FIT_Q_COMMAND); |
1290 | } | |
1291 | ||
1292 | /* | |
1293 | ***************************************************************************** | |
1294 | * COMPLETION QUEUE | |
1295 | ***************************************************************************** | |
1296 | */ | |
1297 | ||
1298 | static void skd_complete_other(struct skd_device *skdev, | |
85e34112 BVA |
1299 | struct fit_completion_entry_v1 *skcomp, |
1300 | struct fit_comp_error_info *skerr); | |
e67f86b3 | 1301 | |
e67f86b3 AB |
1302 | struct sns_info { |
1303 | u8 type; | |
1304 | u8 stat; | |
1305 | u8 key; | |
1306 | u8 asc; | |
1307 | u8 ascq; | |
1308 | u8 mask; | |
1309 | enum skd_check_status_action action; | |
1310 | }; | |
1311 | ||
1312 | static struct sns_info skd_chkstat_table[] = { | |
1313 | /* Good */ | |
1314 | { 0x70, 0x02, RECOVERED_ERROR, 0, 0, 0x1c, | |
1315 | SKD_CHECK_STATUS_REPORT_GOOD }, | |
1316 | ||
1317 | /* Smart alerts */ | |
1318 | { 0x70, 0x02, NO_SENSE, 0x0B, 0x00, 0x1E, /* warnings */ | |
1319 | SKD_CHECK_STATUS_REPORT_SMART_ALERT }, | |
1320 | { 0x70, 0x02, NO_SENSE, 0x5D, 0x00, 0x1E, /* thresholds */ | |
1321 | SKD_CHECK_STATUS_REPORT_SMART_ALERT }, | |
1322 | { 0x70, 0x02, RECOVERED_ERROR, 0x0B, 0x01, 0x1F, /* temperature over trigger */ | |
1323 | SKD_CHECK_STATUS_REPORT_SMART_ALERT }, | |
1324 | ||
1325 | /* Retry (with limits) */ | |
1326 | { 0x70, 0x02, 0x0B, 0, 0, 0x1C, /* This one is for DMA ERROR */ | |
1327 | SKD_CHECK_STATUS_REQUEUE_REQUEST }, | |
1328 | { 0x70, 0x02, 0x06, 0x0B, 0x00, 0x1E, /* warnings */ | |
1329 | SKD_CHECK_STATUS_REQUEUE_REQUEST }, | |
1330 | { 0x70, 0x02, 0x06, 0x5D, 0x00, 0x1E, /* thresholds */ | |
1331 | SKD_CHECK_STATUS_REQUEUE_REQUEST }, | |
1332 | { 0x70, 0x02, 0x06, 0x80, 0x30, 0x1F, /* backup power */ | |
1333 | SKD_CHECK_STATUS_REQUEUE_REQUEST }, | |
1334 | ||
1335 | /* Busy (or about to be) */ | |
1336 | { 0x70, 0x02, 0x06, 0x3f, 0x01, 0x1F, /* fw changed */ | |
1337 | SKD_CHECK_STATUS_BUSY_IMMINENT }, | |
1338 | }; | |
1339 | ||
1340 | /* | |
1341 | * Look up status and sense data to decide how to handle the error | |
1342 | * from the device. | |
1343 | * mask says which fields must match e.g., mask=0x18 means check | |
1344 | * type and stat, ignore key, asc, ascq. | |
1345 | */ | |
1346 | ||
38d4a1bb MS |
1347 | static enum skd_check_status_action |
1348 | skd_check_status(struct skd_device *skdev, | |
85e34112 | 1349 | u8 cmp_status, struct fit_comp_error_info *skerr) |
e67f86b3 | 1350 | { |
0b2e0c07 | 1351 | int i; |
e67f86b3 | 1352 | |
f98806d6 BVA |
1353 | dev_err(&skdev->pdev->dev, "key/asc/ascq/fruc %02x/%02x/%02x/%02x\n", |
1354 | skerr->key, skerr->code, skerr->qual, skerr->fruc); | |
e67f86b3 | 1355 | |
f98806d6 BVA |
1356 | dev_dbg(&skdev->pdev->dev, |
1357 | "stat: t=%02x stat=%02x k=%02x c=%02x q=%02x fruc=%02x\n", | |
1358 | skerr->type, cmp_status, skerr->key, skerr->code, skerr->qual, | |
1359 | skerr->fruc); | |
e67f86b3 AB |
1360 | |
1361 | /* Does the info match an entry in the good category? */ | |
0b2e0c07 | 1362 | for (i = 0; i < ARRAY_SIZE(skd_chkstat_table); i++) { |
e67f86b3 AB |
1363 | struct sns_info *sns = &skd_chkstat_table[i]; |
1364 | ||
1365 | if (sns->mask & 0x10) | |
1366 | if (skerr->type != sns->type) | |
1367 | continue; | |
1368 | ||
1369 | if (sns->mask & 0x08) | |
1370 | if (cmp_status != sns->stat) | |
1371 | continue; | |
1372 | ||
1373 | if (sns->mask & 0x04) | |
1374 | if (skerr->key != sns->key) | |
1375 | continue; | |
1376 | ||
1377 | if (sns->mask & 0x02) | |
1378 | if (skerr->code != sns->asc) | |
1379 | continue; | |
1380 | ||
1381 | if (sns->mask & 0x01) | |
1382 | if (skerr->qual != sns->ascq) | |
1383 | continue; | |
1384 | ||
1385 | if (sns->action == SKD_CHECK_STATUS_REPORT_SMART_ALERT) { | |
f98806d6 BVA |
1386 | dev_err(&skdev->pdev->dev, |
1387 | "SMART Alert: sense key/asc/ascq %02x/%02x/%02x\n", | |
1388 | skerr->key, skerr->code, skerr->qual); | |
e67f86b3 AB |
1389 | } |
1390 | return sns->action; | |
1391 | } | |
1392 | ||
1393 | /* No other match, so nonzero status means error, | |
1394 | * zero status means good | |
1395 | */ | |
1396 | if (cmp_status) { | |
f98806d6 | 1397 | dev_dbg(&skdev->pdev->dev, "status check: error\n"); |
e67f86b3 AB |
1398 | return SKD_CHECK_STATUS_REPORT_ERROR; |
1399 | } | |
1400 | ||
f98806d6 | 1401 | dev_dbg(&skdev->pdev->dev, "status check good default\n"); |
e67f86b3 AB |
1402 | return SKD_CHECK_STATUS_REPORT_GOOD; |
1403 | } | |
1404 | ||
1405 | static void skd_resolve_req_exception(struct skd_device *skdev, | |
f18c17c8 BVA |
1406 | struct skd_request_context *skreq, |
1407 | struct request *req) | |
e67f86b3 AB |
1408 | { |
1409 | u8 cmp_status = skreq->completion.status; | |
1410 | ||
1411 | switch (skd_check_status(skdev, cmp_status, &skreq->err_info)) { | |
1412 | case SKD_CHECK_STATUS_REPORT_GOOD: | |
1413 | case SKD_CHECK_STATUS_REPORT_SMART_ALERT: | |
795bc1b5 BVA |
1414 | skreq->status = BLK_STS_OK; |
1415 | blk_mq_complete_request(req); | |
e67f86b3 AB |
1416 | break; |
1417 | ||
1418 | case SKD_CHECK_STATUS_BUSY_IMMINENT: | |
1419 | skd_log_skreq(skdev, skreq, "retry(busy)"); | |
6d1f9dfd | 1420 | blk_mq_requeue_request(req, true); |
f98806d6 | 1421 | dev_info(&skdev->pdev->dev, "drive BUSY imminent\n"); |
e67f86b3 AB |
1422 | skdev->state = SKD_DRVR_STATE_BUSY_IMMINENT; |
1423 | skdev->timer_countdown = SKD_TIMER_MINUTES(20); | |
1424 | skd_quiesce_dev(skdev); | |
1425 | break; | |
1426 | ||
1427 | case SKD_CHECK_STATUS_REQUEUE_REQUEST: | |
f18c17c8 | 1428 | if ((unsigned long) ++req->special < SKD_MAX_RETRIES) { |
fcd37eb3 | 1429 | skd_log_skreq(skdev, skreq, "retry"); |
6d1f9dfd | 1430 | blk_mq_requeue_request(req, true); |
fcd37eb3 | 1431 | break; |
e67f86b3 | 1432 | } |
ce6882ba | 1433 | /* fall through */ |
e67f86b3 AB |
1434 | |
1435 | case SKD_CHECK_STATUS_REPORT_ERROR: | |
1436 | default: | |
795bc1b5 BVA |
1437 | skreq->status = BLK_STS_IOERR; |
1438 | blk_mq_complete_request(req); | |
e67f86b3 AB |
1439 | break; |
1440 | } | |
1441 | } | |
1442 | ||
e67f86b3 AB |
1443 | static void skd_release_skreq(struct skd_device *skdev, |
1444 | struct skd_request_context *skreq) | |
1445 | { | |
e67f86b3 AB |
1446 | /* |
1447 | * Reclaim the skd_request_context | |
1448 | */ | |
1449 | skreq->state = SKD_REQ_STATE_IDLE; | |
f18c17c8 BVA |
1450 | } |
1451 | ||
e67f86b3 AB |
1452 | static int skd_isr_completion_posted(struct skd_device *skdev, |
1453 | int limit, int *enqueued) | |
1454 | { | |
85e34112 BVA |
1455 | struct fit_completion_entry_v1 *skcmp; |
1456 | struct fit_comp_error_info *skerr; | |
e67f86b3 | 1457 | u16 req_id; |
f18c17c8 | 1458 | u32 tag; |
ca33dd92 | 1459 | u16 hwq = 0; |
f18c17c8 | 1460 | struct request *rq; |
e67f86b3 | 1461 | struct skd_request_context *skreq; |
c830da8c BVA |
1462 | u16 cmp_cntxt; |
1463 | u8 cmp_status; | |
1464 | u8 cmp_cycle; | |
1465 | u32 cmp_bytes; | |
c0b3dda7 | 1466 | int rc = 0; |
e67f86b3 | 1467 | int processed = 0; |
e67f86b3 | 1468 | |
760b48ca BVA |
1469 | lockdep_assert_held(&skdev->lock); |
1470 | ||
e67f86b3 AB |
1471 | for (;; ) { |
1472 | SKD_ASSERT(skdev->skcomp_ix < SKD_N_COMPLETION_ENTRY); | |
1473 | ||
1474 | skcmp = &skdev->skcomp_table[skdev->skcomp_ix]; | |
1475 | cmp_cycle = skcmp->cycle; | |
1476 | cmp_cntxt = skcmp->tag; | |
1477 | cmp_status = skcmp->status; | |
1478 | cmp_bytes = be32_to_cpu(skcmp->num_returned_bytes); | |
1479 | ||
1480 | skerr = &skdev->skerr_table[skdev->skcomp_ix]; | |
1481 | ||
f98806d6 BVA |
1482 | dev_dbg(&skdev->pdev->dev, |
1483 | "cycle=%d ix=%d got cycle=%d cmdctxt=0x%x stat=%d busy=%d rbytes=0x%x proto=%d\n", | |
1484 | skdev->skcomp_cycle, skdev->skcomp_ix, cmp_cycle, | |
d4d0f5fc | 1485 | cmp_cntxt, cmp_status, skd_in_flight(skdev), |
6fbb2de5 | 1486 | cmp_bytes, skdev->proto_ver); |
e67f86b3 AB |
1487 | |
1488 | if (cmp_cycle != skdev->skcomp_cycle) { | |
f98806d6 | 1489 | dev_dbg(&skdev->pdev->dev, "end of completions\n"); |
e67f86b3 AB |
1490 | break; |
1491 | } | |
1492 | /* | |
1493 | * Update the completion queue head index and possibly | |
1494 | * the completion cycle count. 8-bit wrap-around. | |
1495 | */ | |
1496 | skdev->skcomp_ix++; | |
1497 | if (skdev->skcomp_ix >= SKD_N_COMPLETION_ENTRY) { | |
1498 | skdev->skcomp_ix = 0; | |
1499 | skdev->skcomp_cycle++; | |
1500 | } | |
1501 | ||
1502 | /* | |
1503 | * The command context is a unique 32-bit ID. The low order | |
1504 | * bits help locate the request. The request is usually a | |
1505 | * r/w request (see skd_start() above) or a special request. | |
1506 | */ | |
1507 | req_id = cmp_cntxt; | |
f18c17c8 | 1508 | tag = req_id & SKD_ID_SLOT_AND_TABLE_MASK; |
e67f86b3 AB |
1509 | |
1510 | /* Is this other than a r/w request? */ | |
f18c17c8 | 1511 | if (tag >= skdev->num_req_context) { |
e67f86b3 AB |
1512 | /* |
1513 | * This is not a completion for a r/w request. | |
1514 | */ | |
ca33dd92 BVA |
1515 | WARN_ON_ONCE(blk_mq_tag_to_rq(skdev->tag_set.tags[hwq], |
1516 | tag)); | |
e67f86b3 AB |
1517 | skd_complete_other(skdev, skcmp, skerr); |
1518 | continue; | |
1519 | } | |
1520 | ||
ca33dd92 | 1521 | rq = blk_mq_tag_to_rq(skdev->tag_set.tags[hwq], tag); |
f18c17c8 BVA |
1522 | if (WARN(!rq, "No request for tag %#x -> %#x\n", cmp_cntxt, |
1523 | tag)) | |
1524 | continue; | |
e7278a8b | 1525 | skreq = blk_mq_rq_to_pdu(rq); |
e67f86b3 AB |
1526 | |
1527 | /* | |
1528 | * Make sure the request ID for the slot matches. | |
1529 | */ | |
1530 | if (skreq->id != req_id) { | |
49f16e2f BVA |
1531 | dev_err(&skdev->pdev->dev, |
1532 | "Completion mismatch comp_id=0x%04x skreq=0x%04x new=0x%04x\n", | |
1533 | req_id, skreq->id, cmp_cntxt); | |
e67f86b3 | 1534 | |
49f16e2f | 1535 | continue; |
e67f86b3 AB |
1536 | } |
1537 | ||
1538 | SKD_ASSERT(skreq->state == SKD_REQ_STATE_BUSY); | |
1539 | ||
e67f86b3 AB |
1540 | skreq->completion = *skcmp; |
1541 | if (unlikely(cmp_status == SAM_STAT_CHECK_CONDITION)) { | |
1542 | skreq->err_info = *skerr; | |
1543 | skd_log_check_status(skdev, cmp_status, skerr->key, | |
1544 | skerr->code, skerr->qual, | |
1545 | skerr->fruc); | |
1546 | } | |
1547 | /* Release DMA resources for the request. */ | |
1548 | if (skreq->n_sg > 0) | |
1549 | skd_postop_sg_list(skdev, skreq); | |
1550 | ||
f18c17c8 | 1551 | skd_release_skreq(skdev, skreq); |
e67f86b3 AB |
1552 | |
1553 | /* | |
f18c17c8 | 1554 | * Capture the outcome and post it back to the native request. |
e67f86b3 | 1555 | */ |
795bc1b5 BVA |
1556 | if (likely(cmp_status == SAM_STAT_GOOD)) { |
1557 | skreq->status = BLK_STS_OK; | |
1558 | blk_mq_complete_request(rq); | |
1559 | } else { | |
f18c17c8 | 1560 | skd_resolve_req_exception(skdev, skreq, rq); |
795bc1b5 | 1561 | } |
e67f86b3 AB |
1562 | |
1563 | /* skd_isr_comp_limit equal zero means no limit */ | |
1564 | if (limit) { | |
1565 | if (++processed >= limit) { | |
1566 | rc = 1; | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | } | |
1571 | ||
6fbb2de5 | 1572 | if (skdev->state == SKD_DRVR_STATE_PAUSING && |
d4d0f5fc | 1573 | skd_in_flight(skdev) == 0) { |
e67f86b3 AB |
1574 | skdev->state = SKD_DRVR_STATE_PAUSED; |
1575 | wake_up_interruptible(&skdev->waitq); | |
1576 | } | |
1577 | ||
1578 | return rc; | |
1579 | } | |
1580 | ||
1581 | static void skd_complete_other(struct skd_device *skdev, | |
85e34112 BVA |
1582 | struct fit_completion_entry_v1 *skcomp, |
1583 | struct fit_comp_error_info *skerr) | |
e67f86b3 AB |
1584 | { |
1585 | u32 req_id = 0; | |
1586 | u32 req_table; | |
1587 | u32 req_slot; | |
1588 | struct skd_special_context *skspcl; | |
1589 | ||
760b48ca BVA |
1590 | lockdep_assert_held(&skdev->lock); |
1591 | ||
e67f86b3 AB |
1592 | req_id = skcomp->tag; |
1593 | req_table = req_id & SKD_ID_TABLE_MASK; | |
1594 | req_slot = req_id & SKD_ID_SLOT_MASK; | |
1595 | ||
f98806d6 BVA |
1596 | dev_dbg(&skdev->pdev->dev, "table=0x%x id=0x%x slot=%d\n", req_table, |
1597 | req_id, req_slot); | |
e67f86b3 AB |
1598 | |
1599 | /* | |
1600 | * Based on the request id, determine how to dispatch this completion. | |
1601 | * This swich/case is finding the good cases and forwarding the | |
1602 | * completion entry. Errors are reported below the switch. | |
1603 | */ | |
1604 | switch (req_table) { | |
1605 | case SKD_ID_RW_REQUEST: | |
1606 | /* | |
e1d06f2d | 1607 | * The caller, skd_isr_completion_posted() above, |
e67f86b3 AB |
1608 | * handles r/w requests. The only way we get here |
1609 | * is if the req_slot is out of bounds. | |
1610 | */ | |
1611 | break; | |
1612 | ||
e67f86b3 AB |
1613 | case SKD_ID_INTERNAL: |
1614 | if (req_slot == 0) { | |
1615 | skspcl = &skdev->internal_skspcl; | |
1616 | if (skspcl->req.id == req_id && | |
1617 | skspcl->req.state == SKD_REQ_STATE_BUSY) { | |
1618 | skd_complete_internal(skdev, | |
1619 | skcomp, skerr, skspcl); | |
1620 | return; | |
1621 | } | |
1622 | } | |
1623 | break; | |
1624 | ||
1625 | case SKD_ID_FIT_MSG: | |
1626 | /* | |
1627 | * These id's should never appear in a completion record. | |
1628 | */ | |
1629 | break; | |
1630 | ||
1631 | default: | |
1632 | /* | |
1633 | * These id's should never appear anywhere; | |
1634 | */ | |
1635 | break; | |
1636 | } | |
1637 | ||
1638 | /* | |
1639 | * If we get here it is a bad or stale id. | |
1640 | */ | |
1641 | } | |
1642 | ||
e67f86b3 AB |
1643 | static void skd_reset_skcomp(struct skd_device *skdev) |
1644 | { | |
6f7c7675 | 1645 | memset(skdev->skcomp_table, 0, SKD_SKCOMP_SIZE); |
e67f86b3 AB |
1646 | |
1647 | skdev->skcomp_ix = 0; | |
1648 | skdev->skcomp_cycle = 1; | |
1649 | } | |
1650 | ||
1651 | /* | |
1652 | ***************************************************************************** | |
1653 | * INTERRUPTS | |
1654 | ***************************************************************************** | |
1655 | */ | |
1656 | static void skd_completion_worker(struct work_struct *work) | |
1657 | { | |
1658 | struct skd_device *skdev = | |
1659 | container_of(work, struct skd_device, completion_worker); | |
1660 | unsigned long flags; | |
1661 | int flush_enqueued = 0; | |
1662 | ||
1663 | spin_lock_irqsave(&skdev->lock, flags); | |
1664 | ||
1665 | /* | |
1666 | * pass in limit=0, which means no limit.. | |
1667 | * process everything in compq | |
1668 | */ | |
1669 | skd_isr_completion_posted(skdev, 0, &flush_enqueued); | |
ca33dd92 | 1670 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
1671 | |
1672 | spin_unlock_irqrestore(&skdev->lock, flags); | |
1673 | } | |
1674 | ||
1675 | static void skd_isr_msg_from_dev(struct skd_device *skdev); | |
1676 | ||
41c9499b AB |
1677 | static irqreturn_t |
1678 | skd_isr(int irq, void *ptr) | |
e67f86b3 | 1679 | { |
1cd3c1ab | 1680 | struct skd_device *skdev = ptr; |
e67f86b3 AB |
1681 | u32 intstat; |
1682 | u32 ack; | |
1683 | int rc = 0; | |
1684 | int deferred = 0; | |
1685 | int flush_enqueued = 0; | |
1686 | ||
e67f86b3 AB |
1687 | spin_lock(&skdev->lock); |
1688 | ||
1689 | for (;; ) { | |
1690 | intstat = SKD_READL(skdev, FIT_INT_STATUS_HOST); | |
1691 | ||
1692 | ack = FIT_INT_DEF_MASK; | |
1693 | ack &= intstat; | |
1694 | ||
f98806d6 BVA |
1695 | dev_dbg(&skdev->pdev->dev, "intstat=0x%x ack=0x%x\n", intstat, |
1696 | ack); | |
e67f86b3 AB |
1697 | |
1698 | /* As long as there is an int pending on device, keep | |
1699 | * running loop. When none, get out, but if we've never | |
1700 | * done any processing, call completion handler? | |
1701 | */ | |
1702 | if (ack == 0) { | |
1703 | /* No interrupts on device, but run the completion | |
1704 | * processor anyway? | |
1705 | */ | |
1706 | if (rc == 0) | |
1707 | if (likely (skdev->state | |
1708 | == SKD_DRVR_STATE_ONLINE)) | |
1709 | deferred = 1; | |
1710 | break; | |
1711 | } | |
1712 | ||
1713 | rc = IRQ_HANDLED; | |
1714 | ||
1715 | SKD_WRITEL(skdev, ack, FIT_INT_STATUS_HOST); | |
1716 | ||
1717 | if (likely((skdev->state != SKD_DRVR_STATE_LOAD) && | |
1718 | (skdev->state != SKD_DRVR_STATE_STOPPING))) { | |
1719 | if (intstat & FIT_ISH_COMPLETION_POSTED) { | |
1720 | /* | |
1721 | * If we have already deferred completion | |
1722 | * processing, don't bother running it again | |
1723 | */ | |
1724 | if (deferred == 0) | |
1725 | deferred = | |
1726 | skd_isr_completion_posted(skdev, | |
1727 | skd_isr_comp_limit, &flush_enqueued); | |
1728 | } | |
1729 | ||
1730 | if (intstat & FIT_ISH_FW_STATE_CHANGE) { | |
1731 | skd_isr_fwstate(skdev); | |
1732 | if (skdev->state == SKD_DRVR_STATE_FAULT || | |
1733 | skdev->state == | |
1734 | SKD_DRVR_STATE_DISAPPEARED) { | |
1735 | spin_unlock(&skdev->lock); | |
1736 | return rc; | |
1737 | } | |
1738 | } | |
1739 | ||
1740 | if (intstat & FIT_ISH_MSG_FROM_DEV) | |
1741 | skd_isr_msg_from_dev(skdev); | |
1742 | } | |
1743 | } | |
1744 | ||
1745 | if (unlikely(flush_enqueued)) | |
ca33dd92 | 1746 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
1747 | |
1748 | if (deferred) | |
1749 | schedule_work(&skdev->completion_worker); | |
1750 | else if (!flush_enqueued) | |
ca33dd92 | 1751 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
1752 | |
1753 | spin_unlock(&skdev->lock); | |
1754 | ||
1755 | return rc; | |
1756 | } | |
1757 | ||
e67f86b3 AB |
1758 | static void skd_drive_fault(struct skd_device *skdev) |
1759 | { | |
1760 | skdev->state = SKD_DRVR_STATE_FAULT; | |
f98806d6 | 1761 | dev_err(&skdev->pdev->dev, "Drive FAULT\n"); |
e67f86b3 AB |
1762 | } |
1763 | ||
1764 | static void skd_drive_disappeared(struct skd_device *skdev) | |
1765 | { | |
1766 | skdev->state = SKD_DRVR_STATE_DISAPPEARED; | |
f98806d6 | 1767 | dev_err(&skdev->pdev->dev, "Drive DISAPPEARED\n"); |
e67f86b3 AB |
1768 | } |
1769 | ||
1770 | static void skd_isr_fwstate(struct skd_device *skdev) | |
1771 | { | |
1772 | u32 sense; | |
1773 | u32 state; | |
1774 | u32 mtd; | |
1775 | int prev_driver_state = skdev->state; | |
1776 | ||
1777 | sense = SKD_READL(skdev, FIT_STATUS); | |
1778 | state = sense & FIT_SR_DRIVE_STATE_MASK; | |
1779 | ||
f98806d6 BVA |
1780 | dev_err(&skdev->pdev->dev, "s1120 state %s(%d)=>%s(%d)\n", |
1781 | skd_drive_state_to_str(skdev->drive_state), skdev->drive_state, | |
1782 | skd_drive_state_to_str(state), state); | |
e67f86b3 AB |
1783 | |
1784 | skdev->drive_state = state; | |
1785 | ||
1786 | switch (skdev->drive_state) { | |
1787 | case FIT_SR_DRIVE_INIT: | |
1788 | if (skdev->state == SKD_DRVR_STATE_PROTOCOL_MISMATCH) { | |
1789 | skd_disable_interrupts(skdev); | |
1790 | break; | |
1791 | } | |
1792 | if (skdev->state == SKD_DRVR_STATE_RESTARTING) | |
79ce12a8 | 1793 | skd_recover_requests(skdev); |
e67f86b3 AB |
1794 | if (skdev->state == SKD_DRVR_STATE_WAIT_BOOT) { |
1795 | skdev->timer_countdown = SKD_STARTING_TIMO; | |
1796 | skdev->state = SKD_DRVR_STATE_STARTING; | |
1797 | skd_soft_reset(skdev); | |
1798 | break; | |
1799 | } | |
1800 | mtd = FIT_MXD_CONS(FIT_MTD_FITFW_INIT, 0, 0); | |
1801 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1802 | skdev->last_mtd = mtd; | |
1803 | break; | |
1804 | ||
1805 | case FIT_SR_DRIVE_ONLINE: | |
1806 | skdev->cur_max_queue_depth = skd_max_queue_depth; | |
1807 | if (skdev->cur_max_queue_depth > skdev->dev_max_queue_depth) | |
1808 | skdev->cur_max_queue_depth = skdev->dev_max_queue_depth; | |
1809 | ||
1810 | skdev->queue_low_water_mark = | |
1811 | skdev->cur_max_queue_depth * 2 / 3 + 1; | |
1812 | if (skdev->queue_low_water_mark < 1) | |
1813 | skdev->queue_low_water_mark = 1; | |
f98806d6 BVA |
1814 | dev_info(&skdev->pdev->dev, |
1815 | "Queue depth limit=%d dev=%d lowat=%d\n", | |
1816 | skdev->cur_max_queue_depth, | |
1817 | skdev->dev_max_queue_depth, | |
1818 | skdev->queue_low_water_mark); | |
e67f86b3 AB |
1819 | |
1820 | skd_refresh_device_data(skdev); | |
1821 | break; | |
1822 | ||
1823 | case FIT_SR_DRIVE_BUSY: | |
1824 | skdev->state = SKD_DRVR_STATE_BUSY; | |
1825 | skdev->timer_countdown = SKD_BUSY_TIMO; | |
1826 | skd_quiesce_dev(skdev); | |
1827 | break; | |
1828 | case FIT_SR_DRIVE_BUSY_SANITIZE: | |
1829 | /* set timer for 3 seconds, we'll abort any unfinished | |
1830 | * commands after that expires | |
1831 | */ | |
1832 | skdev->state = SKD_DRVR_STATE_BUSY_SANITIZE; | |
1833 | skdev->timer_countdown = SKD_TIMER_SECONDS(3); | |
ca33dd92 | 1834 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
1835 | break; |
1836 | case FIT_SR_DRIVE_BUSY_ERASE: | |
1837 | skdev->state = SKD_DRVR_STATE_BUSY_ERASE; | |
1838 | skdev->timer_countdown = SKD_BUSY_TIMO; | |
1839 | break; | |
1840 | case FIT_SR_DRIVE_OFFLINE: | |
1841 | skdev->state = SKD_DRVR_STATE_IDLE; | |
1842 | break; | |
1843 | case FIT_SR_DRIVE_SOFT_RESET: | |
1844 | switch (skdev->state) { | |
1845 | case SKD_DRVR_STATE_STARTING: | |
1846 | case SKD_DRVR_STATE_RESTARTING: | |
1847 | /* Expected by a caller of skd_soft_reset() */ | |
1848 | break; | |
1849 | default: | |
1850 | skdev->state = SKD_DRVR_STATE_RESTARTING; | |
1851 | break; | |
1852 | } | |
1853 | break; | |
1854 | case FIT_SR_DRIVE_FW_BOOTING: | |
f98806d6 | 1855 | dev_dbg(&skdev->pdev->dev, "ISR FIT_SR_DRIVE_FW_BOOTING\n"); |
e67f86b3 AB |
1856 | skdev->state = SKD_DRVR_STATE_WAIT_BOOT; |
1857 | skdev->timer_countdown = SKD_WAIT_BOOT_TIMO; | |
1858 | break; | |
1859 | ||
1860 | case FIT_SR_DRIVE_DEGRADED: | |
1861 | case FIT_SR_PCIE_LINK_DOWN: | |
1862 | case FIT_SR_DRIVE_NEED_FW_DOWNLOAD: | |
1863 | break; | |
1864 | ||
1865 | case FIT_SR_DRIVE_FAULT: | |
1866 | skd_drive_fault(skdev); | |
79ce12a8 | 1867 | skd_recover_requests(skdev); |
ca33dd92 | 1868 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
1869 | break; |
1870 | ||
1871 | /* PCIe bus returned all Fs? */ | |
1872 | case 0xFF: | |
f98806d6 BVA |
1873 | dev_info(&skdev->pdev->dev, "state=0x%x sense=0x%x\n", state, |
1874 | sense); | |
e67f86b3 | 1875 | skd_drive_disappeared(skdev); |
79ce12a8 | 1876 | skd_recover_requests(skdev); |
ca33dd92 | 1877 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
1878 | break; |
1879 | default: | |
1880 | /* | |
1881 | * Uknown FW State. Wait for a state we recognize. | |
1882 | */ | |
1883 | break; | |
1884 | } | |
f98806d6 BVA |
1885 | dev_err(&skdev->pdev->dev, "Driver state %s(%d)=>%s(%d)\n", |
1886 | skd_skdev_state_to_str(prev_driver_state), prev_driver_state, | |
1887 | skd_skdev_state_to_str(skdev->state), skdev->state); | |
e67f86b3 AB |
1888 | } |
1889 | ||
ca33dd92 | 1890 | static void skd_recover_request(struct request *req, void *data, bool reserved) |
e67f86b3 | 1891 | { |
ca33dd92 BVA |
1892 | struct skd_device *const skdev = data; |
1893 | struct skd_request_context *skreq = blk_mq_rq_to_pdu(req); | |
e67f86b3 | 1894 | |
4e54b849 BVA |
1895 | if (skreq->state != SKD_REQ_STATE_BUSY) |
1896 | return; | |
e67f86b3 | 1897 | |
4e54b849 | 1898 | skd_log_skreq(skdev, skreq, "recover"); |
e67f86b3 | 1899 | |
4e54b849 BVA |
1900 | /* Release DMA resources for the request. */ |
1901 | if (skreq->n_sg > 0) | |
1902 | skd_postop_sg_list(skdev, skreq); | |
e67f86b3 | 1903 | |
4e54b849 | 1904 | skreq->state = SKD_REQ_STATE_IDLE; |
795bc1b5 BVA |
1905 | skreq->status = BLK_STS_IOERR; |
1906 | blk_mq_complete_request(req); | |
4e54b849 | 1907 | } |
e67f86b3 | 1908 | |
4e54b849 BVA |
1909 | static void skd_recover_requests(struct skd_device *skdev) |
1910 | { | |
ca33dd92 | 1911 | blk_mq_tagset_busy_iter(&skdev->tag_set, skd_recover_request, skdev); |
e67f86b3 AB |
1912 | } |
1913 | ||
1914 | static void skd_isr_msg_from_dev(struct skd_device *skdev) | |
1915 | { | |
1916 | u32 mfd; | |
1917 | u32 mtd; | |
1918 | u32 data; | |
1919 | ||
1920 | mfd = SKD_READL(skdev, FIT_MSG_FROM_DEVICE); | |
1921 | ||
f98806d6 BVA |
1922 | dev_dbg(&skdev->pdev->dev, "mfd=0x%x last_mtd=0x%x\n", mfd, |
1923 | skdev->last_mtd); | |
e67f86b3 AB |
1924 | |
1925 | /* ignore any mtd that is an ack for something we didn't send */ | |
1926 | if (FIT_MXD_TYPE(mfd) != FIT_MXD_TYPE(skdev->last_mtd)) | |
1927 | return; | |
1928 | ||
1929 | switch (FIT_MXD_TYPE(mfd)) { | |
1930 | case FIT_MTD_FITFW_INIT: | |
1931 | skdev->proto_ver = FIT_PROTOCOL_MAJOR_VER(mfd); | |
1932 | ||
1933 | if (skdev->proto_ver != FIT_PROTOCOL_VERSION_1) { | |
f98806d6 BVA |
1934 | dev_err(&skdev->pdev->dev, "protocol mismatch\n"); |
1935 | dev_err(&skdev->pdev->dev, " got=%d support=%d\n", | |
1936 | skdev->proto_ver, FIT_PROTOCOL_VERSION_1); | |
1937 | dev_err(&skdev->pdev->dev, " please upgrade driver\n"); | |
e67f86b3 AB |
1938 | skdev->state = SKD_DRVR_STATE_PROTOCOL_MISMATCH; |
1939 | skd_soft_reset(skdev); | |
1940 | break; | |
1941 | } | |
1942 | mtd = FIT_MXD_CONS(FIT_MTD_GET_CMDQ_DEPTH, 0, 0); | |
1943 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1944 | skdev->last_mtd = mtd; | |
1945 | break; | |
1946 | ||
1947 | case FIT_MTD_GET_CMDQ_DEPTH: | |
1948 | skdev->dev_max_queue_depth = FIT_MXD_DATA(mfd); | |
1949 | mtd = FIT_MXD_CONS(FIT_MTD_SET_COMPQ_DEPTH, 0, | |
1950 | SKD_N_COMPLETION_ENTRY); | |
1951 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1952 | skdev->last_mtd = mtd; | |
1953 | break; | |
1954 | ||
1955 | case FIT_MTD_SET_COMPQ_DEPTH: | |
1956 | SKD_WRITEQ(skdev, skdev->cq_dma_address, FIT_MSG_TO_DEVICE_ARG); | |
1957 | mtd = FIT_MXD_CONS(FIT_MTD_SET_COMPQ_ADDR, 0, 0); | |
1958 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1959 | skdev->last_mtd = mtd; | |
1960 | break; | |
1961 | ||
1962 | case FIT_MTD_SET_COMPQ_ADDR: | |
1963 | skd_reset_skcomp(skdev); | |
1964 | mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_HOST_ID, 0, skdev->devno); | |
1965 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1966 | skdev->last_mtd = mtd; | |
1967 | break; | |
1968 | ||
1969 | case FIT_MTD_CMD_LOG_HOST_ID: | |
474f5da2 AB |
1970 | /* hardware interface overflows in y2106 */ |
1971 | skdev->connect_time_stamp = (u32)ktime_get_real_seconds(); | |
e67f86b3 AB |
1972 | data = skdev->connect_time_stamp & 0xFFFF; |
1973 | mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_TIME_STAMP_LO, 0, data); | |
1974 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1975 | skdev->last_mtd = mtd; | |
1976 | break; | |
1977 | ||
1978 | case FIT_MTD_CMD_LOG_TIME_STAMP_LO: | |
1979 | skdev->drive_jiffies = FIT_MXD_DATA(mfd); | |
1980 | data = (skdev->connect_time_stamp >> 16) & 0xFFFF; | |
1981 | mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_TIME_STAMP_HI, 0, data); | |
1982 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1983 | skdev->last_mtd = mtd; | |
1984 | break; | |
1985 | ||
1986 | case FIT_MTD_CMD_LOG_TIME_STAMP_HI: | |
1987 | skdev->drive_jiffies |= (FIT_MXD_DATA(mfd) << 16); | |
1988 | mtd = FIT_MXD_CONS(FIT_MTD_ARM_QUEUE, 0, 0); | |
1989 | SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE); | |
1990 | skdev->last_mtd = mtd; | |
1991 | ||
f98806d6 BVA |
1992 | dev_err(&skdev->pdev->dev, "Time sync driver=0x%x device=0x%x\n", |
1993 | skdev->connect_time_stamp, skdev->drive_jiffies); | |
e67f86b3 AB |
1994 | break; |
1995 | ||
1996 | case FIT_MTD_ARM_QUEUE: | |
1997 | skdev->last_mtd = 0; | |
1998 | /* | |
1999 | * State should be, or soon will be, FIT_SR_DRIVE_ONLINE. | |
2000 | */ | |
2001 | break; | |
2002 | ||
2003 | default: | |
2004 | break; | |
2005 | } | |
2006 | } | |
2007 | ||
2008 | static void skd_disable_interrupts(struct skd_device *skdev) | |
2009 | { | |
2010 | u32 sense; | |
2011 | ||
2012 | sense = SKD_READL(skdev, FIT_CONTROL); | |
2013 | sense &= ~FIT_CR_ENABLE_INTERRUPTS; | |
2014 | SKD_WRITEL(skdev, sense, FIT_CONTROL); | |
f98806d6 | 2015 | dev_dbg(&skdev->pdev->dev, "sense 0x%x\n", sense); |
e67f86b3 AB |
2016 | |
2017 | /* Note that the 1s is written. A 1-bit means | |
2018 | * disable, a 0 means enable. | |
2019 | */ | |
2020 | SKD_WRITEL(skdev, ~0, FIT_INT_MASK_HOST); | |
2021 | } | |
2022 | ||
2023 | static void skd_enable_interrupts(struct skd_device *skdev) | |
2024 | { | |
2025 | u32 val; | |
2026 | ||
2027 | /* unmask interrupts first */ | |
2028 | val = FIT_ISH_FW_STATE_CHANGE + | |
2029 | FIT_ISH_COMPLETION_POSTED + FIT_ISH_MSG_FROM_DEV; | |
2030 | ||
2031 | /* Note that the compliment of mask is written. A 1-bit means | |
2032 | * disable, a 0 means enable. */ | |
2033 | SKD_WRITEL(skdev, ~val, FIT_INT_MASK_HOST); | |
f98806d6 | 2034 | dev_dbg(&skdev->pdev->dev, "interrupt mask=0x%x\n", ~val); |
e67f86b3 AB |
2035 | |
2036 | val = SKD_READL(skdev, FIT_CONTROL); | |
2037 | val |= FIT_CR_ENABLE_INTERRUPTS; | |
f98806d6 | 2038 | dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val); |
e67f86b3 AB |
2039 | SKD_WRITEL(skdev, val, FIT_CONTROL); |
2040 | } | |
2041 | ||
2042 | /* | |
2043 | ***************************************************************************** | |
2044 | * START, STOP, RESTART, QUIESCE, UNQUIESCE | |
2045 | ***************************************************************************** | |
2046 | */ | |
2047 | ||
2048 | static void skd_soft_reset(struct skd_device *skdev) | |
2049 | { | |
2050 | u32 val; | |
2051 | ||
2052 | val = SKD_READL(skdev, FIT_CONTROL); | |
2053 | val |= (FIT_CR_SOFT_RESET); | |
f98806d6 | 2054 | dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val); |
e67f86b3 AB |
2055 | SKD_WRITEL(skdev, val, FIT_CONTROL); |
2056 | } | |
2057 | ||
2058 | static void skd_start_device(struct skd_device *skdev) | |
2059 | { | |
2060 | unsigned long flags; | |
2061 | u32 sense; | |
2062 | u32 state; | |
2063 | ||
2064 | spin_lock_irqsave(&skdev->lock, flags); | |
2065 | ||
2066 | /* ack all ghost interrupts */ | |
2067 | SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST); | |
2068 | ||
2069 | sense = SKD_READL(skdev, FIT_STATUS); | |
2070 | ||
f98806d6 | 2071 | dev_dbg(&skdev->pdev->dev, "initial status=0x%x\n", sense); |
e67f86b3 AB |
2072 | |
2073 | state = sense & FIT_SR_DRIVE_STATE_MASK; | |
2074 | skdev->drive_state = state; | |
2075 | skdev->last_mtd = 0; | |
2076 | ||
2077 | skdev->state = SKD_DRVR_STATE_STARTING; | |
2078 | skdev->timer_countdown = SKD_STARTING_TIMO; | |
2079 | ||
2080 | skd_enable_interrupts(skdev); | |
2081 | ||
2082 | switch (skdev->drive_state) { | |
2083 | case FIT_SR_DRIVE_OFFLINE: | |
f98806d6 | 2084 | dev_err(&skdev->pdev->dev, "Drive offline...\n"); |
e67f86b3 AB |
2085 | break; |
2086 | ||
2087 | case FIT_SR_DRIVE_FW_BOOTING: | |
f98806d6 | 2088 | dev_dbg(&skdev->pdev->dev, "FIT_SR_DRIVE_FW_BOOTING\n"); |
e67f86b3 AB |
2089 | skdev->state = SKD_DRVR_STATE_WAIT_BOOT; |
2090 | skdev->timer_countdown = SKD_WAIT_BOOT_TIMO; | |
2091 | break; | |
2092 | ||
2093 | case FIT_SR_DRIVE_BUSY_SANITIZE: | |
f98806d6 | 2094 | dev_info(&skdev->pdev->dev, "Start: BUSY_SANITIZE\n"); |
e67f86b3 AB |
2095 | skdev->state = SKD_DRVR_STATE_BUSY_SANITIZE; |
2096 | skdev->timer_countdown = SKD_STARTED_BUSY_TIMO; | |
2097 | break; | |
2098 | ||
2099 | case FIT_SR_DRIVE_BUSY_ERASE: | |
f98806d6 | 2100 | dev_info(&skdev->pdev->dev, "Start: BUSY_ERASE\n"); |
e67f86b3 AB |
2101 | skdev->state = SKD_DRVR_STATE_BUSY_ERASE; |
2102 | skdev->timer_countdown = SKD_STARTED_BUSY_TIMO; | |
2103 | break; | |
2104 | ||
2105 | case FIT_SR_DRIVE_INIT: | |
2106 | case FIT_SR_DRIVE_ONLINE: | |
2107 | skd_soft_reset(skdev); | |
2108 | break; | |
2109 | ||
2110 | case FIT_SR_DRIVE_BUSY: | |
f98806d6 | 2111 | dev_err(&skdev->pdev->dev, "Drive Busy...\n"); |
e67f86b3 AB |
2112 | skdev->state = SKD_DRVR_STATE_BUSY; |
2113 | skdev->timer_countdown = SKD_STARTED_BUSY_TIMO; | |
2114 | break; | |
2115 | ||
2116 | case FIT_SR_DRIVE_SOFT_RESET: | |
f98806d6 | 2117 | dev_err(&skdev->pdev->dev, "drive soft reset in prog\n"); |
e67f86b3 AB |
2118 | break; |
2119 | ||
2120 | case FIT_SR_DRIVE_FAULT: | |
2121 | /* Fault state is bad...soft reset won't do it... | |
2122 | * Hard reset, maybe, but does it work on device? | |
2123 | * For now, just fault so the system doesn't hang. | |
2124 | */ | |
2125 | skd_drive_fault(skdev); | |
2126 | /*start the queue so we can respond with error to requests */ | |
f98806d6 | 2127 | dev_dbg(&skdev->pdev->dev, "starting queue\n"); |
ca33dd92 | 2128 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
2129 | skdev->gendisk_on = -1; |
2130 | wake_up_interruptible(&skdev->waitq); | |
2131 | break; | |
2132 | ||
2133 | case 0xFF: | |
2134 | /* Most likely the device isn't there or isn't responding | |
2135 | * to the BAR1 addresses. */ | |
2136 | skd_drive_disappeared(skdev); | |
2137 | /*start the queue so we can respond with error to requests */ | |
f98806d6 BVA |
2138 | dev_dbg(&skdev->pdev->dev, |
2139 | "starting queue to error-out reqs\n"); | |
ca33dd92 | 2140 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
2141 | skdev->gendisk_on = -1; |
2142 | wake_up_interruptible(&skdev->waitq); | |
2143 | break; | |
2144 | ||
2145 | default: | |
f98806d6 BVA |
2146 | dev_err(&skdev->pdev->dev, "Start: unknown state %x\n", |
2147 | skdev->drive_state); | |
e67f86b3 AB |
2148 | break; |
2149 | } | |
2150 | ||
2151 | state = SKD_READL(skdev, FIT_CONTROL); | |
f98806d6 | 2152 | dev_dbg(&skdev->pdev->dev, "FIT Control Status=0x%x\n", state); |
e67f86b3 AB |
2153 | |
2154 | state = SKD_READL(skdev, FIT_INT_STATUS_HOST); | |
f98806d6 | 2155 | dev_dbg(&skdev->pdev->dev, "Intr Status=0x%x\n", state); |
e67f86b3 AB |
2156 | |
2157 | state = SKD_READL(skdev, FIT_INT_MASK_HOST); | |
f98806d6 | 2158 | dev_dbg(&skdev->pdev->dev, "Intr Mask=0x%x\n", state); |
e67f86b3 AB |
2159 | |
2160 | state = SKD_READL(skdev, FIT_MSG_FROM_DEVICE); | |
f98806d6 | 2161 | dev_dbg(&skdev->pdev->dev, "Msg from Dev=0x%x\n", state); |
e67f86b3 AB |
2162 | |
2163 | state = SKD_READL(skdev, FIT_HW_VERSION); | |
f98806d6 | 2164 | dev_dbg(&skdev->pdev->dev, "HW version=0x%x\n", state); |
e67f86b3 AB |
2165 | |
2166 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2167 | } | |
2168 | ||
2169 | static void skd_stop_device(struct skd_device *skdev) | |
2170 | { | |
2171 | unsigned long flags; | |
2172 | struct skd_special_context *skspcl = &skdev->internal_skspcl; | |
2173 | u32 dev_state; | |
2174 | int i; | |
2175 | ||
2176 | spin_lock_irqsave(&skdev->lock, flags); | |
2177 | ||
2178 | if (skdev->state != SKD_DRVR_STATE_ONLINE) { | |
f98806d6 | 2179 | dev_err(&skdev->pdev->dev, "%s not online no sync\n", __func__); |
e67f86b3 AB |
2180 | goto stop_out; |
2181 | } | |
2182 | ||
2183 | if (skspcl->req.state != SKD_REQ_STATE_IDLE) { | |
f98806d6 | 2184 | dev_err(&skdev->pdev->dev, "%s no special\n", __func__); |
e67f86b3 AB |
2185 | goto stop_out; |
2186 | } | |
2187 | ||
2188 | skdev->state = SKD_DRVR_STATE_SYNCING; | |
2189 | skdev->sync_done = 0; | |
2190 | ||
2191 | skd_send_internal_skspcl(skdev, skspcl, SYNCHRONIZE_CACHE); | |
2192 | ||
2193 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2194 | ||
2195 | wait_event_interruptible_timeout(skdev->waitq, | |
2196 | (skdev->sync_done), (10 * HZ)); | |
2197 | ||
2198 | spin_lock_irqsave(&skdev->lock, flags); | |
2199 | ||
2200 | switch (skdev->sync_done) { | |
2201 | case 0: | |
f98806d6 | 2202 | dev_err(&skdev->pdev->dev, "%s no sync\n", __func__); |
e67f86b3 AB |
2203 | break; |
2204 | case 1: | |
f98806d6 | 2205 | dev_err(&skdev->pdev->dev, "%s sync done\n", __func__); |
e67f86b3 AB |
2206 | break; |
2207 | default: | |
f98806d6 | 2208 | dev_err(&skdev->pdev->dev, "%s sync error\n", __func__); |
e67f86b3 AB |
2209 | } |
2210 | ||
2211 | stop_out: | |
2212 | skdev->state = SKD_DRVR_STATE_STOPPING; | |
2213 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2214 | ||
2215 | skd_kill_timer(skdev); | |
2216 | ||
2217 | spin_lock_irqsave(&skdev->lock, flags); | |
2218 | skd_disable_interrupts(skdev); | |
2219 | ||
2220 | /* ensure all ints on device are cleared */ | |
2221 | /* soft reset the device to unload with a clean slate */ | |
2222 | SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST); | |
2223 | SKD_WRITEL(skdev, FIT_CR_SOFT_RESET, FIT_CONTROL); | |
2224 | ||
2225 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2226 | ||
2227 | /* poll every 100ms, 1 second timeout */ | |
2228 | for (i = 0; i < 10; i++) { | |
2229 | dev_state = | |
2230 | SKD_READL(skdev, FIT_STATUS) & FIT_SR_DRIVE_STATE_MASK; | |
2231 | if (dev_state == FIT_SR_DRIVE_INIT) | |
2232 | break; | |
2233 | set_current_state(TASK_INTERRUPTIBLE); | |
2234 | schedule_timeout(msecs_to_jiffies(100)); | |
2235 | } | |
2236 | ||
2237 | if (dev_state != FIT_SR_DRIVE_INIT) | |
f98806d6 BVA |
2238 | dev_err(&skdev->pdev->dev, "%s state error 0x%02x\n", __func__, |
2239 | dev_state); | |
e67f86b3 AB |
2240 | } |
2241 | ||
2242 | /* assume spinlock is held */ | |
2243 | static void skd_restart_device(struct skd_device *skdev) | |
2244 | { | |
2245 | u32 state; | |
2246 | ||
2247 | /* ack all ghost interrupts */ | |
2248 | SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST); | |
2249 | ||
2250 | state = SKD_READL(skdev, FIT_STATUS); | |
2251 | ||
f98806d6 | 2252 | dev_dbg(&skdev->pdev->dev, "drive status=0x%x\n", state); |
e67f86b3 AB |
2253 | |
2254 | state &= FIT_SR_DRIVE_STATE_MASK; | |
2255 | skdev->drive_state = state; | |
2256 | skdev->last_mtd = 0; | |
2257 | ||
2258 | skdev->state = SKD_DRVR_STATE_RESTARTING; | |
2259 | skdev->timer_countdown = SKD_RESTARTING_TIMO; | |
2260 | ||
2261 | skd_soft_reset(skdev); | |
2262 | } | |
2263 | ||
2264 | /* assume spinlock is held */ | |
2265 | static int skd_quiesce_dev(struct skd_device *skdev) | |
2266 | { | |
2267 | int rc = 0; | |
2268 | ||
2269 | switch (skdev->state) { | |
2270 | case SKD_DRVR_STATE_BUSY: | |
2271 | case SKD_DRVR_STATE_BUSY_IMMINENT: | |
f98806d6 | 2272 | dev_dbg(&skdev->pdev->dev, "stopping queue\n"); |
ca33dd92 | 2273 | blk_mq_stop_hw_queues(skdev->queue); |
e67f86b3 AB |
2274 | break; |
2275 | case SKD_DRVR_STATE_ONLINE: | |
2276 | case SKD_DRVR_STATE_STOPPING: | |
2277 | case SKD_DRVR_STATE_SYNCING: | |
2278 | case SKD_DRVR_STATE_PAUSING: | |
2279 | case SKD_DRVR_STATE_PAUSED: | |
2280 | case SKD_DRVR_STATE_STARTING: | |
2281 | case SKD_DRVR_STATE_RESTARTING: | |
2282 | case SKD_DRVR_STATE_RESUMING: | |
2283 | default: | |
2284 | rc = -EINVAL; | |
f98806d6 BVA |
2285 | dev_dbg(&skdev->pdev->dev, "state [%d] not implemented\n", |
2286 | skdev->state); | |
e67f86b3 AB |
2287 | } |
2288 | return rc; | |
2289 | } | |
2290 | ||
2291 | /* assume spinlock is held */ | |
2292 | static int skd_unquiesce_dev(struct skd_device *skdev) | |
2293 | { | |
2294 | int prev_driver_state = skdev->state; | |
2295 | ||
2296 | skd_log_skdev(skdev, "unquiesce"); | |
2297 | if (skdev->state == SKD_DRVR_STATE_ONLINE) { | |
f98806d6 | 2298 | dev_dbg(&skdev->pdev->dev, "**** device already ONLINE\n"); |
e67f86b3 AB |
2299 | return 0; |
2300 | } | |
2301 | if (skdev->drive_state != FIT_SR_DRIVE_ONLINE) { | |
2302 | /* | |
2303 | * If there has been an state change to other than | |
2304 | * ONLINE, we will rely on controller state change | |
2305 | * to come back online and restart the queue. | |
2306 | * The BUSY state means that driver is ready to | |
2307 | * continue normal processing but waiting for controller | |
2308 | * to become available. | |
2309 | */ | |
2310 | skdev->state = SKD_DRVR_STATE_BUSY; | |
f98806d6 | 2311 | dev_dbg(&skdev->pdev->dev, "drive BUSY state\n"); |
e67f86b3 AB |
2312 | return 0; |
2313 | } | |
2314 | ||
2315 | /* | |
2316 | * Drive has just come online, driver is either in startup, | |
2317 | * paused performing a task, or bust waiting for hardware. | |
2318 | */ | |
2319 | switch (skdev->state) { | |
2320 | case SKD_DRVR_STATE_PAUSED: | |
2321 | case SKD_DRVR_STATE_BUSY: | |
2322 | case SKD_DRVR_STATE_BUSY_IMMINENT: | |
2323 | case SKD_DRVR_STATE_BUSY_ERASE: | |
2324 | case SKD_DRVR_STATE_STARTING: | |
2325 | case SKD_DRVR_STATE_RESTARTING: | |
2326 | case SKD_DRVR_STATE_FAULT: | |
2327 | case SKD_DRVR_STATE_IDLE: | |
2328 | case SKD_DRVR_STATE_LOAD: | |
2329 | skdev->state = SKD_DRVR_STATE_ONLINE; | |
f98806d6 BVA |
2330 | dev_err(&skdev->pdev->dev, "Driver state %s(%d)=>%s(%d)\n", |
2331 | skd_skdev_state_to_str(prev_driver_state), | |
2332 | prev_driver_state, skd_skdev_state_to_str(skdev->state), | |
2333 | skdev->state); | |
2334 | dev_dbg(&skdev->pdev->dev, | |
2335 | "**** device ONLINE...starting block queue\n"); | |
2336 | dev_dbg(&skdev->pdev->dev, "starting queue\n"); | |
2337 | dev_info(&skdev->pdev->dev, "STEC s1120 ONLINE\n"); | |
ca33dd92 | 2338 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
2339 | skdev->gendisk_on = 1; |
2340 | wake_up_interruptible(&skdev->waitq); | |
2341 | break; | |
2342 | ||
2343 | case SKD_DRVR_STATE_DISAPPEARED: | |
2344 | default: | |
f98806d6 BVA |
2345 | dev_dbg(&skdev->pdev->dev, |
2346 | "**** driver state %d, not implemented\n", | |
2347 | skdev->state); | |
e67f86b3 AB |
2348 | return -EBUSY; |
2349 | } | |
2350 | return 0; | |
2351 | } | |
2352 | ||
2353 | /* | |
2354 | ***************************************************************************** | |
2355 | * PCIe MSI/MSI-X INTERRUPT HANDLERS | |
2356 | ***************************************************************************** | |
2357 | */ | |
2358 | ||
2359 | static irqreturn_t skd_reserved_isr(int irq, void *skd_host_data) | |
2360 | { | |
2361 | struct skd_device *skdev = skd_host_data; | |
2362 | unsigned long flags; | |
2363 | ||
2364 | spin_lock_irqsave(&skdev->lock, flags); | |
f98806d6 BVA |
2365 | dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n", |
2366 | SKD_READL(skdev, FIT_INT_STATUS_HOST)); | |
2367 | dev_err(&skdev->pdev->dev, "MSIX reserved irq %d = 0x%x\n", irq, | |
2368 | SKD_READL(skdev, FIT_INT_STATUS_HOST)); | |
e67f86b3 AB |
2369 | SKD_WRITEL(skdev, FIT_INT_RESERVED_MASK, FIT_INT_STATUS_HOST); |
2370 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2371 | return IRQ_HANDLED; | |
2372 | } | |
2373 | ||
2374 | static irqreturn_t skd_statec_isr(int irq, void *skd_host_data) | |
2375 | { | |
2376 | struct skd_device *skdev = skd_host_data; | |
2377 | unsigned long flags; | |
2378 | ||
2379 | spin_lock_irqsave(&skdev->lock, flags); | |
f98806d6 BVA |
2380 | dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n", |
2381 | SKD_READL(skdev, FIT_INT_STATUS_HOST)); | |
e67f86b3 AB |
2382 | SKD_WRITEL(skdev, FIT_ISH_FW_STATE_CHANGE, FIT_INT_STATUS_HOST); |
2383 | skd_isr_fwstate(skdev); | |
2384 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2385 | return IRQ_HANDLED; | |
2386 | } | |
2387 | ||
2388 | static irqreturn_t skd_comp_q(int irq, void *skd_host_data) | |
2389 | { | |
2390 | struct skd_device *skdev = skd_host_data; | |
2391 | unsigned long flags; | |
2392 | int flush_enqueued = 0; | |
2393 | int deferred; | |
2394 | ||
2395 | spin_lock_irqsave(&skdev->lock, flags); | |
f98806d6 BVA |
2396 | dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n", |
2397 | SKD_READL(skdev, FIT_INT_STATUS_HOST)); | |
e67f86b3 AB |
2398 | SKD_WRITEL(skdev, FIT_ISH_COMPLETION_POSTED, FIT_INT_STATUS_HOST); |
2399 | deferred = skd_isr_completion_posted(skdev, skd_isr_comp_limit, | |
2400 | &flush_enqueued); | |
e67f86b3 | 2401 | if (flush_enqueued) |
ca33dd92 | 2402 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
2403 | |
2404 | if (deferred) | |
2405 | schedule_work(&skdev->completion_worker); | |
2406 | else if (!flush_enqueued) | |
ca33dd92 | 2407 | schedule_work(&skdev->start_queue); |
e67f86b3 AB |
2408 | |
2409 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2410 | ||
2411 | return IRQ_HANDLED; | |
2412 | } | |
2413 | ||
2414 | static irqreturn_t skd_msg_isr(int irq, void *skd_host_data) | |
2415 | { | |
2416 | struct skd_device *skdev = skd_host_data; | |
2417 | unsigned long flags; | |
2418 | ||
2419 | spin_lock_irqsave(&skdev->lock, flags); | |
f98806d6 BVA |
2420 | dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n", |
2421 | SKD_READL(skdev, FIT_INT_STATUS_HOST)); | |
e67f86b3 AB |
2422 | SKD_WRITEL(skdev, FIT_ISH_MSG_FROM_DEV, FIT_INT_STATUS_HOST); |
2423 | skd_isr_msg_from_dev(skdev); | |
2424 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2425 | return IRQ_HANDLED; | |
2426 | } | |
2427 | ||
2428 | static irqreturn_t skd_qfull_isr(int irq, void *skd_host_data) | |
2429 | { | |
2430 | struct skd_device *skdev = skd_host_data; | |
2431 | unsigned long flags; | |
2432 | ||
2433 | spin_lock_irqsave(&skdev->lock, flags); | |
f98806d6 BVA |
2434 | dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n", |
2435 | SKD_READL(skdev, FIT_INT_STATUS_HOST)); | |
e67f86b3 AB |
2436 | SKD_WRITEL(skdev, FIT_INT_QUEUE_FULL, FIT_INT_STATUS_HOST); |
2437 | spin_unlock_irqrestore(&skdev->lock, flags); | |
2438 | return IRQ_HANDLED; | |
2439 | } | |
2440 | ||
2441 | /* | |
2442 | ***************************************************************************** | |
2443 | * PCIe MSI/MSI-X SETUP | |
2444 | ***************************************************************************** | |
2445 | */ | |
2446 | ||
2447 | struct skd_msix_entry { | |
e67f86b3 AB |
2448 | char isr_name[30]; |
2449 | }; | |
2450 | ||
2451 | struct skd_init_msix_entry { | |
2452 | const char *name; | |
2453 | irq_handler_t handler; | |
2454 | }; | |
2455 | ||
2456 | #define SKD_MAX_MSIX_COUNT 13 | |
2457 | #define SKD_MIN_MSIX_COUNT 7 | |
2458 | #define SKD_BASE_MSIX_IRQ 4 | |
2459 | ||
2460 | static struct skd_init_msix_entry msix_entries[SKD_MAX_MSIX_COUNT] = { | |
2461 | { "(DMA 0)", skd_reserved_isr }, | |
2462 | { "(DMA 1)", skd_reserved_isr }, | |
2463 | { "(DMA 2)", skd_reserved_isr }, | |
2464 | { "(DMA 3)", skd_reserved_isr }, | |
2465 | { "(State Change)", skd_statec_isr }, | |
2466 | { "(COMPL_Q)", skd_comp_q }, | |
2467 | { "(MSG)", skd_msg_isr }, | |
2468 | { "(Reserved)", skd_reserved_isr }, | |
2469 | { "(Reserved)", skd_reserved_isr }, | |
2470 | { "(Queue Full 0)", skd_qfull_isr }, | |
2471 | { "(Queue Full 1)", skd_qfull_isr }, | |
2472 | { "(Queue Full 2)", skd_qfull_isr }, | |
2473 | { "(Queue Full 3)", skd_qfull_isr }, | |
2474 | }; | |
2475 | ||
e67f86b3 AB |
2476 | static int skd_acquire_msix(struct skd_device *skdev) |
2477 | { | |
a9df8625 | 2478 | int i, rc; |
46817769 | 2479 | struct pci_dev *pdev = skdev->pdev; |
e67f86b3 | 2480 | |
180b0ae7 CH |
2481 | rc = pci_alloc_irq_vectors(pdev, SKD_MAX_MSIX_COUNT, SKD_MAX_MSIX_COUNT, |
2482 | PCI_IRQ_MSIX); | |
2483 | if (rc < 0) { | |
f98806d6 | 2484 | dev_err(&skdev->pdev->dev, "failed to enable MSI-X %d\n", rc); |
3bc8492f | 2485 | goto out; |
e67f86b3 | 2486 | } |
46817769 | 2487 | |
180b0ae7 CH |
2488 | skdev->msix_entries = kcalloc(SKD_MAX_MSIX_COUNT, |
2489 | sizeof(struct skd_msix_entry), GFP_KERNEL); | |
e67f86b3 AB |
2490 | if (!skdev->msix_entries) { |
2491 | rc = -ENOMEM; | |
f98806d6 | 2492 | dev_err(&skdev->pdev->dev, "msix table allocation error\n"); |
3bc8492f | 2493 | goto out; |
e67f86b3 AB |
2494 | } |
2495 | ||
e67f86b3 | 2496 | /* Enable MSI-X vectors for the base queue */ |
180b0ae7 CH |
2497 | for (i = 0; i < SKD_MAX_MSIX_COUNT; i++) { |
2498 | struct skd_msix_entry *qentry = &skdev->msix_entries[i]; | |
2499 | ||
e67f86b3 AB |
2500 | snprintf(qentry->isr_name, sizeof(qentry->isr_name), |
2501 | "%s%d-msix %s", DRV_NAME, skdev->devno, | |
2502 | msix_entries[i].name); | |
180b0ae7 CH |
2503 | |
2504 | rc = devm_request_irq(&skdev->pdev->dev, | |
2505 | pci_irq_vector(skdev->pdev, i), | |
2506 | msix_entries[i].handler, 0, | |
2507 | qentry->isr_name, skdev); | |
e67f86b3 | 2508 | if (rc) { |
f98806d6 BVA |
2509 | dev_err(&skdev->pdev->dev, |
2510 | "Unable to register(%d) MSI-X handler %d: %s\n", | |
2511 | rc, i, qentry->isr_name); | |
e67f86b3 | 2512 | goto msix_out; |
e67f86b3 AB |
2513 | } |
2514 | } | |
180b0ae7 | 2515 | |
f98806d6 BVA |
2516 | dev_dbg(&skdev->pdev->dev, "%d msix irq(s) enabled\n", |
2517 | SKD_MAX_MSIX_COUNT); | |
e67f86b3 AB |
2518 | return 0; |
2519 | ||
2520 | msix_out: | |
180b0ae7 CH |
2521 | while (--i >= 0) |
2522 | devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), skdev); | |
3bc8492f | 2523 | out: |
180b0ae7 CH |
2524 | kfree(skdev->msix_entries); |
2525 | skdev->msix_entries = NULL; | |
e67f86b3 AB |
2526 | return rc; |
2527 | } | |
2528 | ||
2529 | static int skd_acquire_irq(struct skd_device *skdev) | |
2530 | { | |
180b0ae7 CH |
2531 | struct pci_dev *pdev = skdev->pdev; |
2532 | unsigned int irq_flag = PCI_IRQ_LEGACY; | |
e67f86b3 | 2533 | int rc; |
e67f86b3 | 2534 | |
180b0ae7 | 2535 | if (skd_isr_type == SKD_IRQ_MSIX) { |
e67f86b3 AB |
2536 | rc = skd_acquire_msix(skdev); |
2537 | if (!rc) | |
180b0ae7 CH |
2538 | return 0; |
2539 | ||
f98806d6 BVA |
2540 | dev_err(&skdev->pdev->dev, |
2541 | "failed to enable MSI-X, re-trying with MSI %d\n", rc); | |
e67f86b3 | 2542 | } |
180b0ae7 CH |
2543 | |
2544 | snprintf(skdev->isr_name, sizeof(skdev->isr_name), "%s%d", DRV_NAME, | |
2545 | skdev->devno); | |
2546 | ||
2547 | if (skd_isr_type != SKD_IRQ_LEGACY) | |
2548 | irq_flag |= PCI_IRQ_MSI; | |
2549 | rc = pci_alloc_irq_vectors(pdev, 1, 1, irq_flag); | |
2550 | if (rc < 0) { | |
f98806d6 BVA |
2551 | dev_err(&skdev->pdev->dev, |
2552 | "failed to allocate the MSI interrupt %d\n", rc); | |
180b0ae7 CH |
2553 | return rc; |
2554 | } | |
2555 | ||
2556 | rc = devm_request_irq(&pdev->dev, pdev->irq, skd_isr, | |
2557 | pdev->msi_enabled ? 0 : IRQF_SHARED, | |
2558 | skdev->isr_name, skdev); | |
2559 | if (rc) { | |
2560 | pci_free_irq_vectors(pdev); | |
f98806d6 BVA |
2561 | dev_err(&skdev->pdev->dev, "failed to allocate interrupt %d\n", |
2562 | rc); | |
180b0ae7 CH |
2563 | return rc; |
2564 | } | |
2565 | ||
2566 | return 0; | |
e67f86b3 AB |
2567 | } |
2568 | ||
2569 | static void skd_release_irq(struct skd_device *skdev) | |
2570 | { | |
180b0ae7 CH |
2571 | struct pci_dev *pdev = skdev->pdev; |
2572 | ||
2573 | if (skdev->msix_entries) { | |
2574 | int i; | |
2575 | ||
2576 | for (i = 0; i < SKD_MAX_MSIX_COUNT; i++) { | |
2577 | devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), | |
2578 | skdev); | |
2579 | } | |
2580 | ||
2581 | kfree(skdev->msix_entries); | |
2582 | skdev->msix_entries = NULL; | |
2583 | } else { | |
2584 | devm_free_irq(&pdev->dev, pdev->irq, skdev); | |
e67f86b3 | 2585 | } |
180b0ae7 CH |
2586 | |
2587 | pci_free_irq_vectors(pdev); | |
e67f86b3 AB |
2588 | } |
2589 | ||
2590 | /* | |
2591 | ***************************************************************************** | |
2592 | * CONSTRUCT | |
2593 | ***************************************************************************** | |
2594 | */ | |
2595 | ||
a3db102d BVA |
2596 | static void *skd_alloc_dma(struct skd_device *skdev, struct kmem_cache *s, |
2597 | dma_addr_t *dma_handle, gfp_t gfp, | |
2598 | enum dma_data_direction dir) | |
2599 | { | |
2600 | struct device *dev = &skdev->pdev->dev; | |
2601 | void *buf; | |
2602 | ||
2603 | buf = kmem_cache_alloc(s, gfp); | |
2604 | if (!buf) | |
2605 | return NULL; | |
1d518775 AB |
2606 | *dma_handle = dma_map_single(dev, buf, |
2607 | kmem_cache_size(s), dir); | |
a3db102d | 2608 | if (dma_mapping_error(dev, *dma_handle)) { |
09aa97c7 | 2609 | kmem_cache_free(s, buf); |
a3db102d BVA |
2610 | buf = NULL; |
2611 | } | |
2612 | return buf; | |
2613 | } | |
2614 | ||
2615 | static void skd_free_dma(struct skd_device *skdev, struct kmem_cache *s, | |
2616 | void *vaddr, dma_addr_t dma_handle, | |
2617 | enum dma_data_direction dir) | |
2618 | { | |
2619 | if (!vaddr) | |
2620 | return; | |
2621 | ||
1d518775 AB |
2622 | dma_unmap_single(&skdev->pdev->dev, dma_handle, |
2623 | kmem_cache_size(s), dir); | |
a3db102d BVA |
2624 | kmem_cache_free(s, vaddr); |
2625 | } | |
2626 | ||
e67f86b3 AB |
2627 | static int skd_cons_skcomp(struct skd_device *skdev) |
2628 | { | |
2629 | int rc = 0; | |
2630 | struct fit_completion_entry_v1 *skcomp; | |
e67f86b3 | 2631 | |
f98806d6 | 2632 | dev_dbg(&skdev->pdev->dev, |
6f7c7675 BVA |
2633 | "comp pci_alloc, total bytes %zd entries %d\n", |
2634 | SKD_SKCOMP_SIZE, SKD_N_COMPLETION_ENTRY); | |
e67f86b3 | 2635 | |
13812621 CH |
2636 | skcomp = dma_zalloc_coherent(&skdev->pdev->dev, SKD_SKCOMP_SIZE, |
2637 | &skdev->cq_dma_address, GFP_KERNEL); | |
e67f86b3 AB |
2638 | |
2639 | if (skcomp == NULL) { | |
2640 | rc = -ENOMEM; | |
2641 | goto err_out; | |
2642 | } | |
2643 | ||
e67f86b3 AB |
2644 | skdev->skcomp_table = skcomp; |
2645 | skdev->skerr_table = (struct fit_comp_error_info *)((char *)skcomp + | |
2646 | sizeof(*skcomp) * | |
2647 | SKD_N_COMPLETION_ENTRY); | |
2648 | ||
2649 | err_out: | |
2650 | return rc; | |
2651 | } | |
2652 | ||
2653 | static int skd_cons_skmsg(struct skd_device *skdev) | |
2654 | { | |
2655 | int rc = 0; | |
2656 | u32 i; | |
2657 | ||
f98806d6 | 2658 | dev_dbg(&skdev->pdev->dev, |
01433d0d | 2659 | "skmsg_table kcalloc, struct %lu, count %u total %lu\n", |
f98806d6 BVA |
2660 | sizeof(struct skd_fitmsg_context), skdev->num_fitmsg_context, |
2661 | sizeof(struct skd_fitmsg_context) * skdev->num_fitmsg_context); | |
e67f86b3 | 2662 | |
01433d0d BVA |
2663 | skdev->skmsg_table = kcalloc(skdev->num_fitmsg_context, |
2664 | sizeof(struct skd_fitmsg_context), | |
2665 | GFP_KERNEL); | |
e67f86b3 AB |
2666 | if (skdev->skmsg_table == NULL) { |
2667 | rc = -ENOMEM; | |
2668 | goto err_out; | |
2669 | } | |
2670 | ||
2671 | for (i = 0; i < skdev->num_fitmsg_context; i++) { | |
2672 | struct skd_fitmsg_context *skmsg; | |
2673 | ||
2674 | skmsg = &skdev->skmsg_table[i]; | |
2675 | ||
2676 | skmsg->id = i + SKD_ID_FIT_MSG; | |
2677 | ||
13812621 CH |
2678 | skmsg->msg_buf = dma_alloc_coherent(&skdev->pdev->dev, |
2679 | SKD_N_FITMSG_BYTES, | |
2680 | &skmsg->mb_dma_address, | |
2681 | GFP_KERNEL); | |
e67f86b3 AB |
2682 | if (skmsg->msg_buf == NULL) { |
2683 | rc = -ENOMEM; | |
2684 | goto err_out; | |
2685 | } | |
2686 | ||
6507f436 BVA |
2687 | WARN(((uintptr_t)skmsg->msg_buf | skmsg->mb_dma_address) & |
2688 | (FIT_QCMD_ALIGN - 1), | |
ea870bb2 HD |
2689 | "not aligned: msg_buf %p mb_dma_address %pad\n", |
2690 | skmsg->msg_buf, &skmsg->mb_dma_address); | |
e67f86b3 | 2691 | memset(skmsg->msg_buf, 0, SKD_N_FITMSG_BYTES); |
e67f86b3 AB |
2692 | } |
2693 | ||
e67f86b3 AB |
2694 | err_out: |
2695 | return rc; | |
2696 | } | |
2697 | ||
542d7b00 BZ |
2698 | static struct fit_sg_descriptor *skd_cons_sg_list(struct skd_device *skdev, |
2699 | u32 n_sg, | |
2700 | dma_addr_t *ret_dma_addr) | |
2701 | { | |
2702 | struct fit_sg_descriptor *sg_list; | |
542d7b00 | 2703 | |
a3db102d BVA |
2704 | sg_list = skd_alloc_dma(skdev, skdev->sglist_cache, ret_dma_addr, |
2705 | GFP_DMA | __GFP_ZERO, DMA_TO_DEVICE); | |
542d7b00 BZ |
2706 | |
2707 | if (sg_list != NULL) { | |
2708 | uint64_t dma_address = *ret_dma_addr; | |
2709 | u32 i; | |
2710 | ||
542d7b00 BZ |
2711 | for (i = 0; i < n_sg - 1; i++) { |
2712 | uint64_t ndp_off; | |
2713 | ndp_off = (i + 1) * sizeof(struct fit_sg_descriptor); | |
2714 | ||
2715 | sg_list[i].next_desc_ptr = dma_address + ndp_off; | |
2716 | } | |
2717 | sg_list[i].next_desc_ptr = 0LL; | |
2718 | } | |
2719 | ||
2720 | return sg_list; | |
2721 | } | |
2722 | ||
5d003240 | 2723 | static void skd_free_sg_list(struct skd_device *skdev, |
a3db102d | 2724 | struct fit_sg_descriptor *sg_list, |
5d003240 BVA |
2725 | dma_addr_t dma_addr) |
2726 | { | |
5d003240 BVA |
2727 | if (WARN_ON_ONCE(!sg_list)) |
2728 | return; | |
2729 | ||
a3db102d BVA |
2730 | skd_free_dma(skdev, skdev->sglist_cache, sg_list, dma_addr, |
2731 | DMA_TO_DEVICE); | |
5d003240 BVA |
2732 | } |
2733 | ||
ca33dd92 BVA |
2734 | static int skd_init_request(struct blk_mq_tag_set *set, struct request *rq, |
2735 | unsigned int hctx_idx, unsigned int numa_node) | |
e67f86b3 | 2736 | { |
ca33dd92 | 2737 | struct skd_device *skdev = set->driver_data; |
e7278a8b | 2738 | struct skd_request_context *skreq = blk_mq_rq_to_pdu(rq); |
e67f86b3 | 2739 | |
e7278a8b BVA |
2740 | skreq->state = SKD_REQ_STATE_IDLE; |
2741 | skreq->sg = (void *)(skreq + 1); | |
2742 | sg_init_table(skreq->sg, skd_sgs_per_request); | |
2743 | skreq->sksg_list = skd_cons_sg_list(skdev, skd_sgs_per_request, | |
2744 | &skreq->sksg_dma_address); | |
e67f86b3 | 2745 | |
e7278a8b BVA |
2746 | return skreq->sksg_list ? 0 : -ENOMEM; |
2747 | } | |
e67f86b3 | 2748 | |
ca33dd92 BVA |
2749 | static void skd_exit_request(struct blk_mq_tag_set *set, struct request *rq, |
2750 | unsigned int hctx_idx) | |
e7278a8b | 2751 | { |
ca33dd92 | 2752 | struct skd_device *skdev = set->driver_data; |
e7278a8b | 2753 | struct skd_request_context *skreq = blk_mq_rq_to_pdu(rq); |
e67f86b3 | 2754 | |
a3db102d | 2755 | skd_free_sg_list(skdev, skreq->sksg_list, skreq->sksg_dma_address); |
e67f86b3 AB |
2756 | } |
2757 | ||
e67f86b3 AB |
2758 | static int skd_cons_sksb(struct skd_device *skdev) |
2759 | { | |
2760 | int rc = 0; | |
2761 | struct skd_special_context *skspcl; | |
e67f86b3 AB |
2762 | |
2763 | skspcl = &skdev->internal_skspcl; | |
2764 | ||
2765 | skspcl->req.id = 0 + SKD_ID_INTERNAL; | |
2766 | skspcl->req.state = SKD_REQ_STATE_IDLE; | |
2767 | ||
a3db102d BVA |
2768 | skspcl->data_buf = skd_alloc_dma(skdev, skdev->databuf_cache, |
2769 | &skspcl->db_dma_address, | |
2770 | GFP_DMA | __GFP_ZERO, | |
2771 | DMA_BIDIRECTIONAL); | |
e67f86b3 AB |
2772 | if (skspcl->data_buf == NULL) { |
2773 | rc = -ENOMEM; | |
2774 | goto err_out; | |
2775 | } | |
2776 | ||
a3db102d BVA |
2777 | skspcl->msg_buf = skd_alloc_dma(skdev, skdev->msgbuf_cache, |
2778 | &skspcl->mb_dma_address, | |
2779 | GFP_DMA | __GFP_ZERO, DMA_TO_DEVICE); | |
e67f86b3 AB |
2780 | if (skspcl->msg_buf == NULL) { |
2781 | rc = -ENOMEM; | |
2782 | goto err_out; | |
2783 | } | |
2784 | ||
e67f86b3 AB |
2785 | skspcl->req.sksg_list = skd_cons_sg_list(skdev, 1, |
2786 | &skspcl->req.sksg_dma_address); | |
2787 | if (skspcl->req.sksg_list == NULL) { | |
2788 | rc = -ENOMEM; | |
2789 | goto err_out; | |
2790 | } | |
2791 | ||
2792 | if (!skd_format_internal_skspcl(skdev)) { | |
2793 | rc = -EINVAL; | |
2794 | goto err_out; | |
2795 | } | |
2796 | ||
2797 | err_out: | |
2798 | return rc; | |
2799 | } | |
2800 | ||
ca33dd92 BVA |
2801 | static const struct blk_mq_ops skd_mq_ops = { |
2802 | .queue_rq = skd_mq_queue_rq, | |
296cb94c | 2803 | .complete = skd_complete_rq, |
f2fe4459 | 2804 | .timeout = skd_timed_out, |
ca33dd92 BVA |
2805 | .init_request = skd_init_request, |
2806 | .exit_request = skd_exit_request, | |
2807 | }; | |
2808 | ||
e67f86b3 AB |
2809 | static int skd_cons_disk(struct skd_device *skdev) |
2810 | { | |
2811 | int rc = 0; | |
2812 | struct gendisk *disk; | |
2813 | struct request_queue *q; | |
2814 | unsigned long flags; | |
2815 | ||
2816 | disk = alloc_disk(SKD_MINORS_PER_DEVICE); | |
2817 | if (!disk) { | |
2818 | rc = -ENOMEM; | |
2819 | goto err_out; | |
2820 | } | |
2821 | ||
2822 | skdev->disk = disk; | |
2823 | sprintf(disk->disk_name, DRV_NAME "%u", skdev->devno); | |
2824 | ||
2825 | disk->major = skdev->major; | |
2826 | disk->first_minor = skdev->devno * SKD_MINORS_PER_DEVICE; | |
2827 | disk->fops = &skd_blockdev_ops; | |
2828 | disk->private_data = skdev; | |
2829 | ||
ca33dd92 BVA |
2830 | memset(&skdev->tag_set, 0, sizeof(skdev->tag_set)); |
2831 | skdev->tag_set.ops = &skd_mq_ops; | |
2832 | skdev->tag_set.nr_hw_queues = 1; | |
2833 | skdev->tag_set.queue_depth = skd_max_queue_depth; | |
2834 | skdev->tag_set.cmd_size = sizeof(struct skd_request_context) + | |
2835 | skdev->sgs_per_request * sizeof(struct scatterlist); | |
2836 | skdev->tag_set.numa_node = NUMA_NO_NODE; | |
2837 | skdev->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | | |
2838 | BLK_MQ_F_SG_MERGE | | |
2839 | BLK_ALLOC_POLICY_TO_MQ_FLAG(BLK_TAG_ALLOC_FIFO); | |
2840 | skdev->tag_set.driver_data = skdev; | |
92d499d4 DC |
2841 | rc = blk_mq_alloc_tag_set(&skdev->tag_set); |
2842 | if (rc) | |
2843 | goto err_out; | |
2844 | q = blk_mq_init_queue(&skdev->tag_set); | |
2845 | if (IS_ERR(q)) { | |
2846 | blk_mq_free_tag_set(&skdev->tag_set); | |
2847 | rc = PTR_ERR(q); | |
e67f86b3 AB |
2848 | goto err_out; |
2849 | } | |
e7278a8b | 2850 | q->queuedata = skdev; |
e67f86b3 AB |
2851 | |
2852 | skdev->queue = q; | |
2853 | disk->queue = q; | |
e67f86b3 | 2854 | |
6975f732 | 2855 | blk_queue_write_cache(q, true, true); |
e67f86b3 AB |
2856 | blk_queue_max_segments(q, skdev->sgs_per_request); |
2857 | blk_queue_max_hw_sectors(q, SKD_N_MAX_SECTORS); | |
2858 | ||
a5c5b392 | 2859 | /* set optimal I/O size to 8KB */ |
e67f86b3 AB |
2860 | blk_queue_io_opt(q, 8192); |
2861 | ||
8b904b5b BVA |
2862 | blk_queue_flag_set(QUEUE_FLAG_NONROT, q); |
2863 | blk_queue_flag_clear(QUEUE_FLAG_ADD_RANDOM, q); | |
e67f86b3 | 2864 | |
a74d5b76 | 2865 | blk_queue_rq_timeout(q, 8 * HZ); |
a74d5b76 | 2866 | |
e67f86b3 | 2867 | spin_lock_irqsave(&skdev->lock, flags); |
f98806d6 | 2868 | dev_dbg(&skdev->pdev->dev, "stopping queue\n"); |
ca33dd92 | 2869 | blk_mq_stop_hw_queues(skdev->queue); |
e67f86b3 AB |
2870 | spin_unlock_irqrestore(&skdev->lock, flags); |
2871 | ||
2872 | err_out: | |
2873 | return rc; | |
2874 | } | |
2875 | ||
542d7b00 BZ |
2876 | #define SKD_N_DEV_TABLE 16u |
2877 | static u32 skd_next_devno; | |
e67f86b3 | 2878 | |
542d7b00 | 2879 | static struct skd_device *skd_construct(struct pci_dev *pdev) |
e67f86b3 | 2880 | { |
542d7b00 BZ |
2881 | struct skd_device *skdev; |
2882 | int blk_major = skd_major; | |
a3db102d | 2883 | size_t size; |
542d7b00 | 2884 | int rc; |
e67f86b3 | 2885 | |
542d7b00 | 2886 | skdev = kzalloc(sizeof(*skdev), GFP_KERNEL); |
e67f86b3 | 2887 | |
542d7b00 | 2888 | if (!skdev) { |
f98806d6 | 2889 | dev_err(&pdev->dev, "memory alloc failure\n"); |
542d7b00 BZ |
2890 | return NULL; |
2891 | } | |
e67f86b3 | 2892 | |
542d7b00 BZ |
2893 | skdev->state = SKD_DRVR_STATE_LOAD; |
2894 | skdev->pdev = pdev; | |
2895 | skdev->devno = skd_next_devno++; | |
2896 | skdev->major = blk_major; | |
542d7b00 | 2897 | skdev->dev_max_queue_depth = 0; |
e67f86b3 | 2898 | |
542d7b00 BZ |
2899 | skdev->num_req_context = skd_max_queue_depth; |
2900 | skdev->num_fitmsg_context = skd_max_queue_depth; | |
542d7b00 BZ |
2901 | skdev->cur_max_queue_depth = 1; |
2902 | skdev->queue_low_water_mark = 1; | |
2903 | skdev->proto_ver = 99; | |
2904 | skdev->sgs_per_request = skd_sgs_per_request; | |
2905 | skdev->dbg_level = skd_dbg_level; | |
e67f86b3 | 2906 | |
542d7b00 BZ |
2907 | spin_lock_init(&skdev->lock); |
2908 | ||
ca33dd92 | 2909 | INIT_WORK(&skdev->start_queue, skd_start_queue); |
542d7b00 | 2910 | INIT_WORK(&skdev->completion_worker, skd_completion_worker); |
e67f86b3 | 2911 | |
a3db102d BVA |
2912 | size = max(SKD_N_FITMSG_BYTES, SKD_N_SPECIAL_FITMSG_BYTES); |
2913 | skdev->msgbuf_cache = kmem_cache_create("skd-msgbuf", size, 0, | |
2914 | SLAB_HWCACHE_ALIGN, NULL); | |
2915 | if (!skdev->msgbuf_cache) | |
2916 | goto err_out; | |
2917 | WARN_ONCE(kmem_cache_size(skdev->msgbuf_cache) < size, | |
2918 | "skd-msgbuf: %d < %zd\n", | |
2919 | kmem_cache_size(skdev->msgbuf_cache), size); | |
2920 | size = skd_sgs_per_request * sizeof(struct fit_sg_descriptor); | |
2921 | skdev->sglist_cache = kmem_cache_create("skd-sglist", size, 0, | |
2922 | SLAB_HWCACHE_ALIGN, NULL); | |
2923 | if (!skdev->sglist_cache) | |
2924 | goto err_out; | |
2925 | WARN_ONCE(kmem_cache_size(skdev->sglist_cache) < size, | |
2926 | "skd-sglist: %d < %zd\n", | |
2927 | kmem_cache_size(skdev->sglist_cache), size); | |
2928 | size = SKD_N_INTERNAL_BYTES; | |
2929 | skdev->databuf_cache = kmem_cache_create("skd-databuf", size, 0, | |
2930 | SLAB_HWCACHE_ALIGN, NULL); | |
2931 | if (!skdev->databuf_cache) | |
2932 | goto err_out; | |
2933 | WARN_ONCE(kmem_cache_size(skdev->databuf_cache) < size, | |
2934 | "skd-databuf: %d < %zd\n", | |
2935 | kmem_cache_size(skdev->databuf_cache), size); | |
2936 | ||
f98806d6 | 2937 | dev_dbg(&skdev->pdev->dev, "skcomp\n"); |
542d7b00 BZ |
2938 | rc = skd_cons_skcomp(skdev); |
2939 | if (rc < 0) | |
2940 | goto err_out; | |
e67f86b3 | 2941 | |
f98806d6 | 2942 | dev_dbg(&skdev->pdev->dev, "skmsg\n"); |
542d7b00 BZ |
2943 | rc = skd_cons_skmsg(skdev); |
2944 | if (rc < 0) | |
2945 | goto err_out; | |
2946 | ||
f98806d6 | 2947 | dev_dbg(&skdev->pdev->dev, "sksb\n"); |
542d7b00 BZ |
2948 | rc = skd_cons_sksb(skdev); |
2949 | if (rc < 0) | |
2950 | goto err_out; | |
2951 | ||
f98806d6 | 2952 | dev_dbg(&skdev->pdev->dev, "disk\n"); |
542d7b00 BZ |
2953 | rc = skd_cons_disk(skdev); |
2954 | if (rc < 0) | |
2955 | goto err_out; | |
2956 | ||
f98806d6 | 2957 | dev_dbg(&skdev->pdev->dev, "VICTORY\n"); |
542d7b00 BZ |
2958 | return skdev; |
2959 | ||
2960 | err_out: | |
f98806d6 | 2961 | dev_dbg(&skdev->pdev->dev, "construct failed\n"); |
542d7b00 BZ |
2962 | skd_destruct(skdev); |
2963 | return NULL; | |
e67f86b3 AB |
2964 | } |
2965 | ||
542d7b00 BZ |
2966 | /* |
2967 | ***************************************************************************** | |
2968 | * DESTRUCT (FREE) | |
2969 | ***************************************************************************** | |
2970 | */ | |
2971 | ||
e67f86b3 AB |
2972 | static void skd_free_skcomp(struct skd_device *skdev) |
2973 | { | |
7f13bdad | 2974 | if (skdev->skcomp_table) |
13812621 CH |
2975 | dma_free_coherent(&skdev->pdev->dev, SKD_SKCOMP_SIZE, |
2976 | skdev->skcomp_table, skdev->cq_dma_address); | |
e67f86b3 AB |
2977 | |
2978 | skdev->skcomp_table = NULL; | |
2979 | skdev->cq_dma_address = 0; | |
2980 | } | |
2981 | ||
2982 | static void skd_free_skmsg(struct skd_device *skdev) | |
2983 | { | |
2984 | u32 i; | |
2985 | ||
2986 | if (skdev->skmsg_table == NULL) | |
2987 | return; | |
2988 | ||
2989 | for (i = 0; i < skdev->num_fitmsg_context; i++) { | |
2990 | struct skd_fitmsg_context *skmsg; | |
2991 | ||
2992 | skmsg = &skdev->skmsg_table[i]; | |
2993 | ||
2994 | if (skmsg->msg_buf != NULL) { | |
13812621 CH |
2995 | dma_free_coherent(&skdev->pdev->dev, SKD_N_FITMSG_BYTES, |
2996 | skmsg->msg_buf, | |
e67f86b3 AB |
2997 | skmsg->mb_dma_address); |
2998 | } | |
2999 | skmsg->msg_buf = NULL; | |
3000 | skmsg->mb_dma_address = 0; | |
3001 | } | |
3002 | ||
3003 | kfree(skdev->skmsg_table); | |
3004 | skdev->skmsg_table = NULL; | |
3005 | } | |
3006 | ||
e67f86b3 AB |
3007 | static void skd_free_sksb(struct skd_device *skdev) |
3008 | { | |
a3db102d | 3009 | struct skd_special_context *skspcl = &skdev->internal_skspcl; |
e67f86b3 | 3010 | |
a3db102d BVA |
3011 | skd_free_dma(skdev, skdev->databuf_cache, skspcl->data_buf, |
3012 | skspcl->db_dma_address, DMA_BIDIRECTIONAL); | |
e67f86b3 AB |
3013 | |
3014 | skspcl->data_buf = NULL; | |
3015 | skspcl->db_dma_address = 0; | |
3016 | ||
a3db102d BVA |
3017 | skd_free_dma(skdev, skdev->msgbuf_cache, skspcl->msg_buf, |
3018 | skspcl->mb_dma_address, DMA_TO_DEVICE); | |
e67f86b3 AB |
3019 | |
3020 | skspcl->msg_buf = NULL; | |
3021 | skspcl->mb_dma_address = 0; | |
3022 | ||
a3db102d | 3023 | skd_free_sg_list(skdev, skspcl->req.sksg_list, |
e67f86b3 AB |
3024 | skspcl->req.sksg_dma_address); |
3025 | ||
3026 | skspcl->req.sksg_list = NULL; | |
3027 | skspcl->req.sksg_dma_address = 0; | |
3028 | } | |
3029 | ||
e67f86b3 AB |
3030 | static void skd_free_disk(struct skd_device *skdev) |
3031 | { | |
3032 | struct gendisk *disk = skdev->disk; | |
3033 | ||
7277cc67 BVA |
3034 | if (disk && (disk->flags & GENHD_FL_UP)) |
3035 | del_gendisk(disk); | |
3036 | ||
3037 | if (skdev->queue) { | |
3038 | blk_cleanup_queue(skdev->queue); | |
3039 | skdev->queue = NULL; | |
4633504c BVA |
3040 | if (disk) |
3041 | disk->queue = NULL; | |
e67f86b3 | 3042 | } |
7277cc67 | 3043 | |
ca33dd92 BVA |
3044 | if (skdev->tag_set.tags) |
3045 | blk_mq_free_tag_set(&skdev->tag_set); | |
3046 | ||
7277cc67 | 3047 | put_disk(disk); |
e67f86b3 AB |
3048 | skdev->disk = NULL; |
3049 | } | |
3050 | ||
542d7b00 BZ |
3051 | static void skd_destruct(struct skd_device *skdev) |
3052 | { | |
3053 | if (skdev == NULL) | |
3054 | return; | |
3055 | ||
ca33dd92 BVA |
3056 | cancel_work_sync(&skdev->start_queue); |
3057 | ||
f98806d6 | 3058 | dev_dbg(&skdev->pdev->dev, "disk\n"); |
542d7b00 BZ |
3059 | skd_free_disk(skdev); |
3060 | ||
f98806d6 | 3061 | dev_dbg(&skdev->pdev->dev, "sksb\n"); |
542d7b00 BZ |
3062 | skd_free_sksb(skdev); |
3063 | ||
f98806d6 | 3064 | dev_dbg(&skdev->pdev->dev, "skmsg\n"); |
542d7b00 | 3065 | skd_free_skmsg(skdev); |
e67f86b3 | 3066 | |
f98806d6 | 3067 | dev_dbg(&skdev->pdev->dev, "skcomp\n"); |
542d7b00 BZ |
3068 | skd_free_skcomp(skdev); |
3069 | ||
a3db102d BVA |
3070 | kmem_cache_destroy(skdev->databuf_cache); |
3071 | kmem_cache_destroy(skdev->sglist_cache); | |
3072 | kmem_cache_destroy(skdev->msgbuf_cache); | |
3073 | ||
f98806d6 | 3074 | dev_dbg(&skdev->pdev->dev, "skdev\n"); |
542d7b00 BZ |
3075 | kfree(skdev); |
3076 | } | |
e67f86b3 AB |
3077 | |
3078 | /* | |
3079 | ***************************************************************************** | |
3080 | * BLOCK DEVICE (BDEV) GLUE | |
3081 | ***************************************************************************** | |
3082 | */ | |
3083 | ||
3084 | static int skd_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo) | |
3085 | { | |
3086 | struct skd_device *skdev; | |
3087 | u64 capacity; | |
3088 | ||
3089 | skdev = bdev->bd_disk->private_data; | |
3090 | ||
f98806d6 BVA |
3091 | dev_dbg(&skdev->pdev->dev, "%s: CMD[%s] getgeo device\n", |
3092 | bdev->bd_disk->disk_name, current->comm); | |
e67f86b3 AB |
3093 | |
3094 | if (skdev->read_cap_is_valid) { | |
3095 | capacity = get_capacity(skdev->disk); | |
3096 | geo->heads = 64; | |
3097 | geo->sectors = 255; | |
3098 | geo->cylinders = (capacity) / (255 * 64); | |
3099 | ||
3100 | return 0; | |
3101 | } | |
3102 | return -EIO; | |
3103 | } | |
3104 | ||
0d52c756 | 3105 | static int skd_bdev_attach(struct device *parent, struct skd_device *skdev) |
e67f86b3 | 3106 | { |
f98806d6 | 3107 | dev_dbg(&skdev->pdev->dev, "add_disk\n"); |
fef912bf | 3108 | device_add_disk(parent, skdev->disk, NULL); |
e67f86b3 AB |
3109 | return 0; |
3110 | } | |
3111 | ||
3112 | static const struct block_device_operations skd_blockdev_ops = { | |
3113 | .owner = THIS_MODULE, | |
e67f86b3 AB |
3114 | .getgeo = skd_bdev_getgeo, |
3115 | }; | |
3116 | ||
e67f86b3 AB |
3117 | /* |
3118 | ***************************************************************************** | |
3119 | * PCIe DRIVER GLUE | |
3120 | ***************************************************************************** | |
3121 | */ | |
3122 | ||
9baa3c34 | 3123 | static const struct pci_device_id skd_pci_tbl[] = { |
e67f86b3 AB |
3124 | { PCI_VENDOR_ID_STEC, PCI_DEVICE_ID_S1120, |
3125 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, | |
3126 | { 0 } /* terminate list */ | |
3127 | }; | |
3128 | ||
3129 | MODULE_DEVICE_TABLE(pci, skd_pci_tbl); | |
3130 | ||
3131 | static char *skd_pci_info(struct skd_device *skdev, char *str) | |
3132 | { | |
3133 | int pcie_reg; | |
3134 | ||
3135 | strcpy(str, "PCIe ("); | |
3136 | pcie_reg = pci_find_capability(skdev->pdev, PCI_CAP_ID_EXP); | |
3137 | ||
3138 | if (pcie_reg) { | |
3139 | ||
3140 | char lwstr[6]; | |
3141 | uint16_t pcie_lstat, lspeed, lwidth; | |
3142 | ||
3143 | pcie_reg += 0x12; | |
3144 | pci_read_config_word(skdev->pdev, pcie_reg, &pcie_lstat); | |
3145 | lspeed = pcie_lstat & (0xF); | |
3146 | lwidth = (pcie_lstat & 0x3F0) >> 4; | |
3147 | ||
3148 | if (lspeed == 1) | |
3149 | strcat(str, "2.5GT/s "); | |
3150 | else if (lspeed == 2) | |
3151 | strcat(str, "5.0GT/s "); | |
3152 | else | |
3153 | strcat(str, "<unknown> "); | |
3154 | snprintf(lwstr, sizeof(lwstr), "%dX)", lwidth); | |
3155 | strcat(str, lwstr); | |
3156 | } | |
3157 | return str; | |
3158 | } | |
3159 | ||
3160 | static int skd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
3161 | { | |
3162 | int i; | |
3163 | int rc = 0; | |
3164 | char pci_str[32]; | |
3165 | struct skd_device *skdev; | |
3166 | ||
bb9f7dd3 BVA |
3167 | dev_dbg(&pdev->dev, "vendor=%04X device=%04x\n", pdev->vendor, |
3168 | pdev->device); | |
e67f86b3 AB |
3169 | |
3170 | rc = pci_enable_device(pdev); | |
3171 | if (rc) | |
3172 | return rc; | |
3173 | rc = pci_request_regions(pdev, DRV_NAME); | |
3174 | if (rc) | |
3175 | goto err_out; | |
13812621 CH |
3176 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
3177 | if (rc) | |
d91dc172 | 3178 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
13812621 CH |
3179 | if (rc) { |
3180 | dev_err(&pdev->dev, "DMA mask error %d\n", rc); | |
3181 | goto err_out_regions; | |
e67f86b3 AB |
3182 | } |
3183 | ||
b8df6647 BZ |
3184 | if (!skd_major) { |
3185 | rc = register_blkdev(0, DRV_NAME); | |
3186 | if (rc < 0) | |
3187 | goto err_out_regions; | |
3188 | BUG_ON(!rc); | |
3189 | skd_major = rc; | |
3190 | } | |
3191 | ||
e67f86b3 | 3192 | skdev = skd_construct(pdev); |
1762b57f WY |
3193 | if (skdev == NULL) { |
3194 | rc = -ENOMEM; | |
e67f86b3 | 3195 | goto err_out_regions; |
1762b57f | 3196 | } |
e67f86b3 AB |
3197 | |
3198 | skd_pci_info(skdev, pci_str); | |
f98806d6 | 3199 | dev_info(&pdev->dev, "%s 64bit\n", pci_str); |
e67f86b3 AB |
3200 | |
3201 | pci_set_master(pdev); | |
3202 | rc = pci_enable_pcie_error_reporting(pdev); | |
3203 | if (rc) { | |
f98806d6 BVA |
3204 | dev_err(&pdev->dev, |
3205 | "bad enable of PCIe error reporting rc=%d\n", rc); | |
e67f86b3 AB |
3206 | skdev->pcie_error_reporting_is_enabled = 0; |
3207 | } else | |
3208 | skdev->pcie_error_reporting_is_enabled = 1; | |
3209 | ||
e67f86b3 | 3210 | pci_set_drvdata(pdev, skdev); |
ebedd16d | 3211 | |
e67f86b3 AB |
3212 | for (i = 0; i < SKD_MAX_BARS; i++) { |
3213 | skdev->mem_phys[i] = pci_resource_start(pdev, i); | |
3214 | skdev->mem_size[i] = (u32)pci_resource_len(pdev, i); | |
3215 | skdev->mem_map[i] = ioremap(skdev->mem_phys[i], | |
3216 | skdev->mem_size[i]); | |
3217 | if (!skdev->mem_map[i]) { | |
f98806d6 BVA |
3218 | dev_err(&pdev->dev, |
3219 | "Unable to map adapter memory!\n"); | |
e67f86b3 AB |
3220 | rc = -ENODEV; |
3221 | goto err_out_iounmap; | |
3222 | } | |
f98806d6 BVA |
3223 | dev_dbg(&pdev->dev, "mem_map=%p, phyd=%016llx, size=%d\n", |
3224 | skdev->mem_map[i], (uint64_t)skdev->mem_phys[i], | |
3225 | skdev->mem_size[i]); | |
e67f86b3 AB |
3226 | } |
3227 | ||
3228 | rc = skd_acquire_irq(skdev); | |
3229 | if (rc) { | |
f98806d6 | 3230 | dev_err(&pdev->dev, "interrupt resource error %d\n", rc); |
e67f86b3 AB |
3231 | goto err_out_iounmap; |
3232 | } | |
3233 | ||
3234 | rc = skd_start_timer(skdev); | |
3235 | if (rc) | |
3236 | goto err_out_timer; | |
3237 | ||
3238 | init_waitqueue_head(&skdev->waitq); | |
3239 | ||
3240 | skd_start_device(skdev); | |
3241 | ||
3242 | rc = wait_event_interruptible_timeout(skdev->waitq, | |
3243 | (skdev->gendisk_on), | |
3244 | (SKD_START_WAIT_SECONDS * HZ)); | |
3245 | if (skdev->gendisk_on > 0) { | |
3246 | /* device came on-line after reset */ | |
0d52c756 | 3247 | skd_bdev_attach(&pdev->dev, skdev); |
e67f86b3 AB |
3248 | rc = 0; |
3249 | } else { | |
3250 | /* we timed out, something is wrong with the device, | |
3251 | don't add the disk structure */ | |
f98806d6 BVA |
3252 | dev_err(&pdev->dev, "error: waiting for s1120 timed out %d!\n", |
3253 | rc); | |
e67f86b3 AB |
3254 | /* in case of no error; we timeout with ENXIO */ |
3255 | if (!rc) | |
3256 | rc = -ENXIO; | |
3257 | goto err_out_timer; | |
3258 | } | |
3259 | ||
e67f86b3 AB |
3260 | return rc; |
3261 | ||
3262 | err_out_timer: | |
3263 | skd_stop_device(skdev); | |
3264 | skd_release_irq(skdev); | |
3265 | ||
3266 | err_out_iounmap: | |
3267 | for (i = 0; i < SKD_MAX_BARS; i++) | |
3268 | if (skdev->mem_map[i]) | |
3269 | iounmap(skdev->mem_map[i]); | |
3270 | ||
3271 | if (skdev->pcie_error_reporting_is_enabled) | |
3272 | pci_disable_pcie_error_reporting(pdev); | |
3273 | ||
3274 | skd_destruct(skdev); | |
3275 | ||
3276 | err_out_regions: | |
3277 | pci_release_regions(pdev); | |
3278 | ||
3279 | err_out: | |
3280 | pci_disable_device(pdev); | |
3281 | pci_set_drvdata(pdev, NULL); | |
3282 | return rc; | |
3283 | } | |
3284 | ||
3285 | static void skd_pci_remove(struct pci_dev *pdev) | |
3286 | { | |
3287 | int i; | |
3288 | struct skd_device *skdev; | |
3289 | ||
3290 | skdev = pci_get_drvdata(pdev); | |
3291 | if (!skdev) { | |
f98806d6 | 3292 | dev_err(&pdev->dev, "no device data for PCI\n"); |
e67f86b3 AB |
3293 | return; |
3294 | } | |
3295 | skd_stop_device(skdev); | |
3296 | skd_release_irq(skdev); | |
3297 | ||
3298 | for (i = 0; i < SKD_MAX_BARS; i++) | |
3299 | if (skdev->mem_map[i]) | |
4854afe3 | 3300 | iounmap(skdev->mem_map[i]); |
e67f86b3 AB |
3301 | |
3302 | if (skdev->pcie_error_reporting_is_enabled) | |
3303 | pci_disable_pcie_error_reporting(pdev); | |
3304 | ||
3305 | skd_destruct(skdev); | |
3306 | ||
3307 | pci_release_regions(pdev); | |
3308 | pci_disable_device(pdev); | |
3309 | pci_set_drvdata(pdev, NULL); | |
3310 | ||
3311 | return; | |
3312 | } | |
3313 | ||
3314 | static int skd_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
3315 | { | |
3316 | int i; | |
3317 | struct skd_device *skdev; | |
3318 | ||
3319 | skdev = pci_get_drvdata(pdev); | |
3320 | if (!skdev) { | |
f98806d6 | 3321 | dev_err(&pdev->dev, "no device data for PCI\n"); |
e67f86b3 AB |
3322 | return -EIO; |
3323 | } | |
3324 | ||
3325 | skd_stop_device(skdev); | |
3326 | ||
3327 | skd_release_irq(skdev); | |
3328 | ||
3329 | for (i = 0; i < SKD_MAX_BARS; i++) | |
3330 | if (skdev->mem_map[i]) | |
4854afe3 | 3331 | iounmap(skdev->mem_map[i]); |
e67f86b3 AB |
3332 | |
3333 | if (skdev->pcie_error_reporting_is_enabled) | |
3334 | pci_disable_pcie_error_reporting(pdev); | |
3335 | ||
3336 | pci_release_regions(pdev); | |
3337 | pci_save_state(pdev); | |
3338 | pci_disable_device(pdev); | |
3339 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
3340 | return 0; | |
3341 | } | |
3342 | ||
3343 | static int skd_pci_resume(struct pci_dev *pdev) | |
3344 | { | |
3345 | int i; | |
3346 | int rc = 0; | |
3347 | struct skd_device *skdev; | |
3348 | ||
3349 | skdev = pci_get_drvdata(pdev); | |
3350 | if (!skdev) { | |
f98806d6 | 3351 | dev_err(&pdev->dev, "no device data for PCI\n"); |
e67f86b3 AB |
3352 | return -1; |
3353 | } | |
3354 | ||
3355 | pci_set_power_state(pdev, PCI_D0); | |
3356 | pci_enable_wake(pdev, PCI_D0, 0); | |
3357 | pci_restore_state(pdev); | |
3358 | ||
3359 | rc = pci_enable_device(pdev); | |
3360 | if (rc) | |
3361 | return rc; | |
3362 | rc = pci_request_regions(pdev, DRV_NAME); | |
3363 | if (rc) | |
3364 | goto err_out; | |
13812621 CH |
3365 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
3366 | if (rc) | |
d91dc172 | 3367 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
13812621 CH |
3368 | if (rc) { |
3369 | dev_err(&pdev->dev, "DMA mask error %d\n", rc); | |
3370 | goto err_out_regions; | |
e67f86b3 AB |
3371 | } |
3372 | ||
3373 | pci_set_master(pdev); | |
3374 | rc = pci_enable_pcie_error_reporting(pdev); | |
3375 | if (rc) { | |
f98806d6 BVA |
3376 | dev_err(&pdev->dev, |
3377 | "bad enable of PCIe error reporting rc=%d\n", rc); | |
e67f86b3 AB |
3378 | skdev->pcie_error_reporting_is_enabled = 0; |
3379 | } else | |
3380 | skdev->pcie_error_reporting_is_enabled = 1; | |
3381 | ||
3382 | for (i = 0; i < SKD_MAX_BARS; i++) { | |
3383 | ||
3384 | skdev->mem_phys[i] = pci_resource_start(pdev, i); | |
3385 | skdev->mem_size[i] = (u32)pci_resource_len(pdev, i); | |
3386 | skdev->mem_map[i] = ioremap(skdev->mem_phys[i], | |
3387 | skdev->mem_size[i]); | |
3388 | if (!skdev->mem_map[i]) { | |
f98806d6 | 3389 | dev_err(&pdev->dev, "Unable to map adapter memory!\n"); |
e67f86b3 AB |
3390 | rc = -ENODEV; |
3391 | goto err_out_iounmap; | |
3392 | } | |
f98806d6 BVA |
3393 | dev_dbg(&pdev->dev, "mem_map=%p, phyd=%016llx, size=%d\n", |
3394 | skdev->mem_map[i], (uint64_t)skdev->mem_phys[i], | |
3395 | skdev->mem_size[i]); | |
e67f86b3 AB |
3396 | } |
3397 | rc = skd_acquire_irq(skdev); | |
3398 | if (rc) { | |
f98806d6 | 3399 | dev_err(&pdev->dev, "interrupt resource error %d\n", rc); |
e67f86b3 AB |
3400 | goto err_out_iounmap; |
3401 | } | |
3402 | ||
3403 | rc = skd_start_timer(skdev); | |
3404 | if (rc) | |
3405 | goto err_out_timer; | |
3406 | ||
3407 | init_waitqueue_head(&skdev->waitq); | |
3408 | ||
3409 | skd_start_device(skdev); | |
3410 | ||
3411 | return rc; | |
3412 | ||
3413 | err_out_timer: | |
3414 | skd_stop_device(skdev); | |
3415 | skd_release_irq(skdev); | |
3416 | ||
3417 | err_out_iounmap: | |
3418 | for (i = 0; i < SKD_MAX_BARS; i++) | |
3419 | if (skdev->mem_map[i]) | |
3420 | iounmap(skdev->mem_map[i]); | |
3421 | ||
3422 | if (skdev->pcie_error_reporting_is_enabled) | |
3423 | pci_disable_pcie_error_reporting(pdev); | |
3424 | ||
3425 | err_out_regions: | |
3426 | pci_release_regions(pdev); | |
3427 | ||
3428 | err_out: | |
3429 | pci_disable_device(pdev); | |
3430 | return rc; | |
3431 | } | |
3432 | ||
3433 | static void skd_pci_shutdown(struct pci_dev *pdev) | |
3434 | { | |
3435 | struct skd_device *skdev; | |
3436 | ||
f98806d6 | 3437 | dev_err(&pdev->dev, "%s called\n", __func__); |
e67f86b3 AB |
3438 | |
3439 | skdev = pci_get_drvdata(pdev); | |
3440 | if (!skdev) { | |
f98806d6 | 3441 | dev_err(&pdev->dev, "no device data for PCI\n"); |
e67f86b3 AB |
3442 | return; |
3443 | } | |
3444 | ||
f98806d6 | 3445 | dev_err(&pdev->dev, "calling stop\n"); |
e67f86b3 AB |
3446 | skd_stop_device(skdev); |
3447 | } | |
3448 | ||
3449 | static struct pci_driver skd_driver = { | |
3450 | .name = DRV_NAME, | |
3451 | .id_table = skd_pci_tbl, | |
3452 | .probe = skd_pci_probe, | |
3453 | .remove = skd_pci_remove, | |
3454 | .suspend = skd_pci_suspend, | |
3455 | .resume = skd_pci_resume, | |
3456 | .shutdown = skd_pci_shutdown, | |
3457 | }; | |
3458 | ||
3459 | /* | |
3460 | ***************************************************************************** | |
3461 | * LOGGING SUPPORT | |
3462 | ***************************************************************************** | |
3463 | */ | |
3464 | ||
e67f86b3 AB |
3465 | const char *skd_drive_state_to_str(int state) |
3466 | { | |
3467 | switch (state) { | |
3468 | case FIT_SR_DRIVE_OFFLINE: | |
3469 | return "OFFLINE"; | |
3470 | case FIT_SR_DRIVE_INIT: | |
3471 | return "INIT"; | |
3472 | case FIT_SR_DRIVE_ONLINE: | |
3473 | return "ONLINE"; | |
3474 | case FIT_SR_DRIVE_BUSY: | |
3475 | return "BUSY"; | |
3476 | case FIT_SR_DRIVE_FAULT: | |
3477 | return "FAULT"; | |
3478 | case FIT_SR_DRIVE_DEGRADED: | |
3479 | return "DEGRADED"; | |
3480 | case FIT_SR_PCIE_LINK_DOWN: | |
3481 | return "INK_DOWN"; | |
3482 | case FIT_SR_DRIVE_SOFT_RESET: | |
3483 | return "SOFT_RESET"; | |
3484 | case FIT_SR_DRIVE_NEED_FW_DOWNLOAD: | |
3485 | return "NEED_FW"; | |
3486 | case FIT_SR_DRIVE_INIT_FAULT: | |
3487 | return "INIT_FAULT"; | |
3488 | case FIT_SR_DRIVE_BUSY_SANITIZE: | |
3489 | return "BUSY_SANITIZE"; | |
3490 | case FIT_SR_DRIVE_BUSY_ERASE: | |
3491 | return "BUSY_ERASE"; | |
3492 | case FIT_SR_DRIVE_FW_BOOTING: | |
3493 | return "FW_BOOTING"; | |
3494 | default: | |
3495 | return "???"; | |
3496 | } | |
3497 | } | |
3498 | ||
3499 | const char *skd_skdev_state_to_str(enum skd_drvr_state state) | |
3500 | { | |
3501 | switch (state) { | |
3502 | case SKD_DRVR_STATE_LOAD: | |
3503 | return "LOAD"; | |
3504 | case SKD_DRVR_STATE_IDLE: | |
3505 | return "IDLE"; | |
3506 | case SKD_DRVR_STATE_BUSY: | |
3507 | return "BUSY"; | |
3508 | case SKD_DRVR_STATE_STARTING: | |
3509 | return "STARTING"; | |
3510 | case SKD_DRVR_STATE_ONLINE: | |
3511 | return "ONLINE"; | |
3512 | case SKD_DRVR_STATE_PAUSING: | |
3513 | return "PAUSING"; | |
3514 | case SKD_DRVR_STATE_PAUSED: | |
3515 | return "PAUSED"; | |
e67f86b3 AB |
3516 | case SKD_DRVR_STATE_RESTARTING: |
3517 | return "RESTARTING"; | |
3518 | case SKD_DRVR_STATE_RESUMING: | |
3519 | return "RESUMING"; | |
3520 | case SKD_DRVR_STATE_STOPPING: | |
3521 | return "STOPPING"; | |
3522 | case SKD_DRVR_STATE_SYNCING: | |
3523 | return "SYNCING"; | |
3524 | case SKD_DRVR_STATE_FAULT: | |
3525 | return "FAULT"; | |
3526 | case SKD_DRVR_STATE_DISAPPEARED: | |
3527 | return "DISAPPEARED"; | |
3528 | case SKD_DRVR_STATE_BUSY_ERASE: | |
3529 | return "BUSY_ERASE"; | |
3530 | case SKD_DRVR_STATE_BUSY_SANITIZE: | |
3531 | return "BUSY_SANITIZE"; | |
3532 | case SKD_DRVR_STATE_BUSY_IMMINENT: | |
3533 | return "BUSY_IMMINENT"; | |
3534 | case SKD_DRVR_STATE_WAIT_BOOT: | |
3535 | return "WAIT_BOOT"; | |
3536 | ||
3537 | default: | |
3538 | return "???"; | |
3539 | } | |
3540 | } | |
3541 | ||
a26ba7fa | 3542 | static const char *skd_skreq_state_to_str(enum skd_req_state state) |
e67f86b3 AB |
3543 | { |
3544 | switch (state) { | |
3545 | case SKD_REQ_STATE_IDLE: | |
3546 | return "IDLE"; | |
3547 | case SKD_REQ_STATE_SETUP: | |
3548 | return "SETUP"; | |
3549 | case SKD_REQ_STATE_BUSY: | |
3550 | return "BUSY"; | |
3551 | case SKD_REQ_STATE_COMPLETED: | |
3552 | return "COMPLETED"; | |
3553 | case SKD_REQ_STATE_TIMEOUT: | |
3554 | return "TIMEOUT"; | |
e67f86b3 AB |
3555 | default: |
3556 | return "???"; | |
3557 | } | |
3558 | } | |
3559 | ||
3560 | static void skd_log_skdev(struct skd_device *skdev, const char *event) | |
3561 | { | |
f98806d6 BVA |
3562 | dev_dbg(&skdev->pdev->dev, "skdev=%p event='%s'\n", skdev, event); |
3563 | dev_dbg(&skdev->pdev->dev, " drive_state=%s(%d) driver_state=%s(%d)\n", | |
3564 | skd_drive_state_to_str(skdev->drive_state), skdev->drive_state, | |
3565 | skd_skdev_state_to_str(skdev->state), skdev->state); | |
3566 | dev_dbg(&skdev->pdev->dev, " busy=%d limit=%d dev=%d lowat=%d\n", | |
d4d0f5fc | 3567 | skd_in_flight(skdev), skdev->cur_max_queue_depth, |
f98806d6 | 3568 | skdev->dev_max_queue_depth, skdev->queue_low_water_mark); |
a74d5b76 BVA |
3569 | dev_dbg(&skdev->pdev->dev, " cycle=%d cycle_ix=%d\n", |
3570 | skdev->skcomp_cycle, skdev->skcomp_ix); | |
e67f86b3 AB |
3571 | } |
3572 | ||
e67f86b3 AB |
3573 | static void skd_log_skreq(struct skd_device *skdev, |
3574 | struct skd_request_context *skreq, const char *event) | |
3575 | { | |
e7278a8b BVA |
3576 | struct request *req = blk_mq_rq_from_pdu(skreq); |
3577 | u32 lba = blk_rq_pos(req); | |
3578 | u32 count = blk_rq_sectors(req); | |
3579 | ||
f98806d6 BVA |
3580 | dev_dbg(&skdev->pdev->dev, "skreq=%p event='%s'\n", skreq, event); |
3581 | dev_dbg(&skdev->pdev->dev, " state=%s(%d) id=0x%04x fitmsg=0x%04x\n", | |
3582 | skd_skreq_state_to_str(skreq->state), skreq->state, skreq->id, | |
3583 | skreq->fitmsg_id); | |
a74d5b76 BVA |
3584 | dev_dbg(&skdev->pdev->dev, " sg_dir=%d n_sg=%d\n", |
3585 | skreq->data_dir, skreq->n_sg); | |
ca33dd92 | 3586 | |
e7278a8b BVA |
3587 | dev_dbg(&skdev->pdev->dev, |
3588 | "req=%p lba=%u(0x%x) count=%u(0x%x) dir=%d\n", req, lba, lba, | |
3589 | count, count, (int)rq_data_dir(req)); | |
e67f86b3 AB |
3590 | } |
3591 | ||
3592 | /* | |
3593 | ***************************************************************************** | |
3594 | * MODULE GLUE | |
3595 | ***************************************************************************** | |
3596 | */ | |
3597 | ||
3598 | static int __init skd_init(void) | |
3599 | { | |
16a70534 BVA |
3600 | BUILD_BUG_ON(sizeof(struct fit_completion_entry_v1) != 8); |
3601 | BUILD_BUG_ON(sizeof(struct fit_comp_error_info) != 32); | |
3602 | BUILD_BUG_ON(sizeof(struct skd_command_header) != 16); | |
3603 | BUILD_BUG_ON(sizeof(struct skd_scsi_request) != 32); | |
3604 | BUILD_BUG_ON(sizeof(struct driver_inquiry_data) != 44); | |
d891fe60 BVA |
3605 | BUILD_BUG_ON(offsetof(struct skd_msg_buf, fmh) != 0); |
3606 | BUILD_BUG_ON(offsetof(struct skd_msg_buf, scsi) != 64); | |
3607 | BUILD_BUG_ON(sizeof(struct skd_msg_buf) != SKD_N_FITMSG_BYTES); | |
2da7b403 | 3608 | |
e67f86b3 AB |
3609 | switch (skd_isr_type) { |
3610 | case SKD_IRQ_LEGACY: | |
3611 | case SKD_IRQ_MSI: | |
3612 | case SKD_IRQ_MSIX: | |
3613 | break; | |
3614 | default: | |
fbed149a | 3615 | pr_err(PFX "skd_isr_type %d invalid, re-set to %d\n", |
e67f86b3 AB |
3616 | skd_isr_type, SKD_IRQ_DEFAULT); |
3617 | skd_isr_type = SKD_IRQ_DEFAULT; | |
3618 | } | |
3619 | ||
fbed149a BZ |
3620 | if (skd_max_queue_depth < 1 || |
3621 | skd_max_queue_depth > SKD_MAX_QUEUE_DEPTH) { | |
3622 | pr_err(PFX "skd_max_queue_depth %d invalid, re-set to %d\n", | |
e67f86b3 AB |
3623 | skd_max_queue_depth, SKD_MAX_QUEUE_DEPTH_DEFAULT); |
3624 | skd_max_queue_depth = SKD_MAX_QUEUE_DEPTH_DEFAULT; | |
3625 | } | |
3626 | ||
2da7b403 BVA |
3627 | if (skd_max_req_per_msg < 1 || |
3628 | skd_max_req_per_msg > SKD_MAX_REQ_PER_MSG) { | |
fbed149a | 3629 | pr_err(PFX "skd_max_req_per_msg %d invalid, re-set to %d\n", |
e67f86b3 AB |
3630 | skd_max_req_per_msg, SKD_MAX_REQ_PER_MSG_DEFAULT); |
3631 | skd_max_req_per_msg = SKD_MAX_REQ_PER_MSG_DEFAULT; | |
3632 | } | |
3633 | ||
3634 | if (skd_sgs_per_request < 1 || skd_sgs_per_request > 4096) { | |
fbed149a | 3635 | pr_err(PFX "skd_sg_per_request %d invalid, re-set to %d\n", |
e67f86b3 AB |
3636 | skd_sgs_per_request, SKD_N_SG_PER_REQ_DEFAULT); |
3637 | skd_sgs_per_request = SKD_N_SG_PER_REQ_DEFAULT; | |
3638 | } | |
3639 | ||
3640 | if (skd_dbg_level < 0 || skd_dbg_level > 2) { | |
fbed149a | 3641 | pr_err(PFX "skd_dbg_level %d invalid, re-set to %d\n", |
e67f86b3 AB |
3642 | skd_dbg_level, 0); |
3643 | skd_dbg_level = 0; | |
3644 | } | |
3645 | ||
3646 | if (skd_isr_comp_limit < 0) { | |
fbed149a | 3647 | pr_err(PFX "skd_isr_comp_limit %d invalid, set to %d\n", |
e67f86b3 AB |
3648 | skd_isr_comp_limit, 0); |
3649 | skd_isr_comp_limit = 0; | |
3650 | } | |
3651 | ||
b8df6647 | 3652 | return pci_register_driver(&skd_driver); |
e67f86b3 AB |
3653 | } |
3654 | ||
3655 | static void __exit skd_exit(void) | |
3656 | { | |
e67f86b3 | 3657 | pci_unregister_driver(&skd_driver); |
b8df6647 BZ |
3658 | |
3659 | if (skd_major) | |
3660 | unregister_blkdev(skd_major, DRV_NAME); | |
e67f86b3 AB |
3661 | } |
3662 | ||
e67f86b3 AB |
3663 | module_init(skd_init); |
3664 | module_exit(skd_exit); |