Commit | Line | Data |
---|---|---|
b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/moduleparam.h> | |
33 | #include <linux/pci.h> | |
be7b6275 | 34 | #include <linux/poison.h> |
b60503ba MW |
35 | #include <linux/sched.h> |
36 | #include <linux/slab.h> | |
37 | #include <linux/types.h> | |
38 | #include <linux/version.h> | |
39 | ||
40 | #define NVME_Q_DEPTH 1024 | |
41 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
42 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
43 | #define NVME_MINORS 64 | |
e85248e5 MW |
44 | #define IO_TIMEOUT (5 * HZ) |
45 | #define ADMIN_TIMEOUT (60 * HZ) | |
b60503ba MW |
46 | |
47 | static int nvme_major; | |
48 | module_param(nvme_major, int, 0); | |
49 | ||
58ffacb5 MW |
50 | static int use_threaded_interrupts; |
51 | module_param(use_threaded_interrupts, int, 0); | |
52 | ||
b60503ba MW |
53 | /* |
54 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
55 | */ | |
56 | struct nvme_dev { | |
b60503ba MW |
57 | struct nvme_queue **queues; |
58 | u32 __iomem *dbs; | |
59 | struct pci_dev *pci_dev; | |
091b6092 | 60 | struct dma_pool *prp_page_pool; |
99802a7a | 61 | struct dma_pool *prp_small_pool; |
b60503ba MW |
62 | int instance; |
63 | int queue_count; | |
64 | u32 ctrl_config; | |
65 | struct msix_entry *entry; | |
66 | struct nvme_bar __iomem *bar; | |
67 | struct list_head namespaces; | |
51814232 MW |
68 | char serial[20]; |
69 | char model[40]; | |
70 | char firmware_rev[8]; | |
b60503ba MW |
71 | }; |
72 | ||
73 | /* | |
74 | * An NVM Express namespace is equivalent to a SCSI LUN | |
75 | */ | |
76 | struct nvme_ns { | |
77 | struct list_head list; | |
78 | ||
79 | struct nvme_dev *dev; | |
80 | struct request_queue *queue; | |
81 | struct gendisk *disk; | |
82 | ||
83 | int ns_id; | |
84 | int lba_shift; | |
85 | }; | |
86 | ||
87 | /* | |
88 | * An NVM Express queue. Each device has at least two (one for admin | |
89 | * commands and one for I/O commands). | |
90 | */ | |
91 | struct nvme_queue { | |
92 | struct device *q_dmadev; | |
091b6092 | 93 | struct nvme_dev *dev; |
b60503ba MW |
94 | spinlock_t q_lock; |
95 | struct nvme_command *sq_cmds; | |
96 | volatile struct nvme_completion *cqes; | |
97 | dma_addr_t sq_dma_addr; | |
98 | dma_addr_t cq_dma_addr; | |
99 | wait_queue_head_t sq_full; | |
100 | struct bio_list sq_cong; | |
101 | u32 __iomem *q_db; | |
102 | u16 q_depth; | |
103 | u16 cq_vector; | |
104 | u16 sq_head; | |
105 | u16 sq_tail; | |
106 | u16 cq_head; | |
82123460 | 107 | u16 cq_phase; |
b60503ba MW |
108 | unsigned long cmdid_data[]; |
109 | }; | |
110 | ||
9294bbed MW |
111 | static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio); |
112 | ||
b60503ba MW |
113 | /* |
114 | * Check we didin't inadvertently grow the command struct | |
115 | */ | |
116 | static inline void _nvme_check_size(void) | |
117 | { | |
118 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
119 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
120 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
121 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
122 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
123 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
124 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
125 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
126 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
127 | } | |
128 | ||
e85248e5 MW |
129 | struct nvme_cmd_info { |
130 | unsigned long ctx; | |
131 | unsigned long timeout; | |
132 | }; | |
133 | ||
134 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
135 | { | |
136 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
137 | } | |
138 | ||
b60503ba MW |
139 | /** |
140 | * alloc_cmdid - Allocate a Command ID | |
141 | * @param nvmeq The queue that will be used for this command | |
142 | * @param ctx A pointer that will be passed to the handler | |
143 | * @param handler The ID of the handler to call | |
144 | * | |
145 | * Allocate a Command ID for a queue. The data passed in will | |
146 | * be passed to the completion handler. This is implemented by using | |
147 | * the bottom two bits of the ctx pointer to store the handler ID. | |
148 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
149 | * We can change this if it becomes a problem. | |
150 | */ | |
e85248e5 MW |
151 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler, |
152 | unsigned timeout) | |
b60503ba MW |
153 | { |
154 | int depth = nvmeq->q_depth; | |
e85248e5 | 155 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
156 | int cmdid; |
157 | ||
158 | BUG_ON((unsigned long)ctx & 3); | |
159 | ||
160 | do { | |
161 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
162 | if (cmdid >= depth) | |
163 | return -EBUSY; | |
164 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
165 | ||
e85248e5 MW |
166 | info[cmdid].ctx = (unsigned long)ctx | handler; |
167 | info[cmdid].timeout = jiffies + timeout; | |
b60503ba MW |
168 | return cmdid; |
169 | } | |
170 | ||
171 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
e85248e5 | 172 | int handler, unsigned timeout) |
b60503ba MW |
173 | { |
174 | int cmdid; | |
175 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 176 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
177 | return (cmdid < 0) ? -EINTR : cmdid; |
178 | } | |
179 | ||
180 | /* If you need more than four handlers, you'll need to change how | |
be7b6275 MW |
181 | * alloc_cmdid and nvme_process_cq work. Consider using a special |
182 | * CMD_CTX value instead, if that works for your situation. | |
b60503ba MW |
183 | */ |
184 | enum { | |
185 | sync_completion_id = 0, | |
186 | bio_completion_id, | |
187 | }; | |
188 | ||
be7b6275 | 189 | #define CMD_CTX_BASE (POISON_POINTER_DELTA + sync_completion_id) |
d2d87034 MW |
190 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
191 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
192 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 193 | |
b60503ba MW |
194 | static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid) |
195 | { | |
196 | unsigned long data; | |
e85248e5 | 197 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 198 | |
e85248e5 | 199 | if (cmdid >= nvmeq->q_depth) |
48e3d398 | 200 | return CMD_CTX_INVALID; |
e85248e5 MW |
201 | data = info[cmdid].ctx; |
202 | info[cmdid].ctx = CMD_CTX_COMPLETED; | |
b60503ba MW |
203 | clear_bit(cmdid, nvmeq->cmdid_data); |
204 | wake_up(&nvmeq->sq_full); | |
205 | return data; | |
206 | } | |
207 | ||
be7b6275 | 208 | static void cancel_cmdid_data(struct nvme_queue *nvmeq, int cmdid) |
3c0cf138 | 209 | { |
e85248e5 MW |
210 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
211 | info[cmdid].ctx = CMD_CTX_CANCELLED; | |
3c0cf138 MW |
212 | } |
213 | ||
b60503ba MW |
214 | static struct nvme_queue *get_nvmeq(struct nvme_ns *ns) |
215 | { | |
1b23484b MW |
216 | int qid, cpu = get_cpu(); |
217 | if (cpu < ns->dev->queue_count) | |
218 | qid = cpu + 1; | |
219 | else | |
220 | qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1; | |
221 | return ns->dev->queues[qid]; | |
b60503ba MW |
222 | } |
223 | ||
224 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
225 | { | |
1b23484b | 226 | put_cpu(); |
b60503ba MW |
227 | } |
228 | ||
229 | /** | |
230 | * nvme_submit_cmd: Copy a command into a queue and ring the doorbell | |
231 | * @nvmeq: The queue to use | |
232 | * @cmd: The command to send | |
233 | * | |
234 | * Safe to use from interrupt context | |
235 | */ | |
236 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
237 | { | |
238 | unsigned long flags; | |
239 | u16 tail; | |
240 | /* XXX: Need to check tail isn't going to overrun head */ | |
241 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
242 | tail = nvmeq->sq_tail; | |
243 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
244 | writel(tail, nvmeq->q_db); | |
245 | if (++tail == nvmeq->q_depth) | |
246 | tail = 0; | |
247 | nvmeq->sq_tail = tail; | |
248 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
e025344c SMM |
253 | struct nvme_prps { |
254 | int npages; | |
255 | dma_addr_t first_dma; | |
256 | __le64 *list[0]; | |
257 | }; | |
258 | ||
d567760c | 259 | static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps) |
e025344c SMM |
260 | { |
261 | const int last_prp = PAGE_SIZE / 8 - 1; | |
262 | int i; | |
263 | dma_addr_t prp_dma; | |
264 | ||
265 | if (!prps) | |
266 | return; | |
267 | ||
268 | prp_dma = prps->first_dma; | |
99802a7a MW |
269 | |
270 | if (prps->npages == 0) | |
271 | dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma); | |
e025344c SMM |
272 | for (i = 0; i < prps->npages; i++) { |
273 | __le64 *prp_list = prps->list[i]; | |
274 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
091b6092 | 275 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); |
e025344c SMM |
276 | prp_dma = next_prp_dma; |
277 | } | |
278 | kfree(prps); | |
279 | } | |
280 | ||
d534df3c | 281 | struct nvme_bio { |
b60503ba MW |
282 | struct bio *bio; |
283 | int nents; | |
e025344c | 284 | struct nvme_prps *prps; |
b60503ba MW |
285 | struct scatterlist sg[0]; |
286 | }; | |
287 | ||
288 | /* XXX: use a mempool */ | |
d534df3c | 289 | static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp) |
b60503ba | 290 | { |
d534df3c | 291 | return kzalloc(sizeof(struct nvme_bio) + |
b60503ba MW |
292 | sizeof(struct scatterlist) * nseg, gfp); |
293 | } | |
294 | ||
d534df3c | 295 | static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio) |
b60503ba | 296 | { |
d567760c | 297 | nvme_free_prps(nvmeq->dev, nbio->prps); |
d534df3c | 298 | kfree(nbio); |
b60503ba MW |
299 | } |
300 | ||
301 | static void bio_completion(struct nvme_queue *nvmeq, void *ctx, | |
302 | struct nvme_completion *cqe) | |
303 | { | |
d534df3c MW |
304 | struct nvme_bio *nbio = ctx; |
305 | struct bio *bio = nbio->bio; | |
b60503ba MW |
306 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
307 | ||
d534df3c | 308 | dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents, |
b60503ba | 309 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
d534df3c | 310 | free_nbio(nvmeq, nbio); |
b60503ba | 311 | bio_endio(bio, status ? -EIO : 0); |
9294bbed MW |
312 | bio = bio_list_pop(&nvmeq->sq_cong); |
313 | if (bio) | |
314 | nvme_resubmit_bio(nvmeq, bio); | |
b60503ba MW |
315 | } |
316 | ||
ff22b54f | 317 | /* length is in bytes */ |
d567760c | 318 | static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev, |
e025344c | 319 | struct nvme_common_command *cmd, |
ff22b54f MW |
320 | struct scatterlist *sg, int length) |
321 | { | |
99802a7a | 322 | struct dma_pool *pool; |
ff22b54f MW |
323 | int dma_len = sg_dma_len(sg); |
324 | u64 dma_addr = sg_dma_address(sg); | |
325 | int offset = offset_in_page(dma_addr); | |
e025344c SMM |
326 | __le64 *prp_list; |
327 | dma_addr_t prp_dma; | |
328 | int nprps, npages, i, prp_page; | |
329 | struct nvme_prps *prps = NULL; | |
ff22b54f MW |
330 | |
331 | cmd->prp1 = cpu_to_le64(dma_addr); | |
332 | length -= (PAGE_SIZE - offset); | |
333 | if (length <= 0) | |
e025344c | 334 | return prps; |
ff22b54f MW |
335 | |
336 | dma_len -= (PAGE_SIZE - offset); | |
337 | if (dma_len) { | |
338 | dma_addr += (PAGE_SIZE - offset); | |
339 | } else { | |
340 | sg = sg_next(sg); | |
341 | dma_addr = sg_dma_address(sg); | |
342 | dma_len = sg_dma_len(sg); | |
343 | } | |
344 | ||
345 | if (length <= PAGE_SIZE) { | |
346 | cmd->prp2 = cpu_to_le64(dma_addr); | |
e025344c SMM |
347 | return prps; |
348 | } | |
349 | ||
350 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
351 | npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE); | |
352 | prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, GFP_ATOMIC); | |
e025344c | 353 | prp_page = 0; |
99802a7a MW |
354 | if (nprps <= (256 / 8)) { |
355 | pool = dev->prp_small_pool; | |
356 | prps->npages = 0; | |
357 | } else { | |
358 | pool = dev->prp_page_pool; | |
359 | prps->npages = npages; | |
360 | } | |
361 | ||
362 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); | |
e025344c SMM |
363 | prps->list[prp_page++] = prp_list; |
364 | prps->first_dma = prp_dma; | |
365 | cmd->prp2 = cpu_to_le64(prp_dma); | |
366 | i = 0; | |
367 | for (;;) { | |
368 | if (i == PAGE_SIZE / 8 - 1) { | |
369 | __le64 *old_prp_list = prp_list; | |
99802a7a | 370 | prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); |
e025344c SMM |
371 | prps->list[prp_page++] = prp_list; |
372 | old_prp_list[i] = cpu_to_le64(prp_dma); | |
373 | i = 0; | |
374 | } | |
375 | prp_list[i++] = cpu_to_le64(dma_addr); | |
376 | dma_len -= PAGE_SIZE; | |
377 | dma_addr += PAGE_SIZE; | |
378 | length -= PAGE_SIZE; | |
379 | if (length <= 0) | |
380 | break; | |
381 | if (dma_len > 0) | |
382 | continue; | |
383 | BUG_ON(dma_len < 0); | |
384 | sg = sg_next(sg); | |
385 | dma_addr = sg_dma_address(sg); | |
386 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
387 | } |
388 | ||
e025344c | 389 | return prps; |
ff22b54f MW |
390 | } |
391 | ||
d534df3c | 392 | static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio, |
b60503ba MW |
393 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
394 | { | |
395 | struct bio_vec *bvec; | |
d534df3c | 396 | struct scatterlist *sg = nbio->sg; |
b60503ba MW |
397 | int i, nsegs; |
398 | ||
399 | sg_init_table(sg, psegs); | |
400 | bio_for_each_segment(bvec, bio, i) { | |
401 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset); | |
51882d00 | 402 | sg++; |
b60503ba MW |
403 | /* XXX: handle non-mergable here */ |
404 | nsegs++; | |
405 | } | |
d534df3c | 406 | nbio->nents = nsegs; |
b60503ba | 407 | |
d534df3c | 408 | return dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir); |
b60503ba MW |
409 | } |
410 | ||
411 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
412 | struct bio *bio) | |
413 | { | |
ff22b54f | 414 | struct nvme_command *cmnd; |
d534df3c | 415 | struct nvme_bio *nbio; |
b60503ba MW |
416 | enum dma_data_direction dma_dir; |
417 | int cmdid; | |
418 | u16 control; | |
419 | u32 dsmgmt; | |
420 | unsigned long flags; | |
421 | int psegs = bio_phys_segments(ns->queue, bio); | |
422 | ||
d534df3c MW |
423 | nbio = alloc_nbio(psegs, GFP_NOIO); |
424 | if (!nbio) | |
b60503ba | 425 | goto congestion; |
d534df3c | 426 | nbio->bio = bio; |
b60503ba | 427 | |
d534df3c | 428 | cmdid = alloc_cmdid(nvmeq, nbio, bio_completion_id, IO_TIMEOUT); |
b60503ba | 429 | if (unlikely(cmdid < 0)) |
d534df3c | 430 | goto free_nbio; |
b60503ba MW |
431 | |
432 | control = 0; | |
433 | if (bio->bi_rw & REQ_FUA) | |
434 | control |= NVME_RW_FUA; | |
435 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
436 | control |= NVME_RW_LR; | |
437 | ||
438 | dsmgmt = 0; | |
439 | if (bio->bi_rw & REQ_RAHEAD) | |
440 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
441 | ||
442 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
ff22b54f | 443 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 444 | |
b8deb62c | 445 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 446 | if (bio_data_dir(bio)) { |
ff22b54f | 447 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
448 | dma_dir = DMA_TO_DEVICE; |
449 | } else { | |
ff22b54f | 450 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
451 | dma_dir = DMA_FROM_DEVICE; |
452 | } | |
453 | ||
d534df3c | 454 | nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs); |
b60503ba | 455 | |
ff22b54f MW |
456 | cmnd->rw.flags = 1; |
457 | cmnd->rw.command_id = cmdid; | |
458 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
d567760c | 459 | nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg, |
e025344c | 460 | bio->bi_size); |
ff22b54f MW |
461 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); |
462 | cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1); | |
463 | cmnd->rw.control = cpu_to_le16(control); | |
464 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba MW |
465 | |
466 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
467 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
468 | nvmeq->sq_tail = 0; | |
469 | ||
470 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
471 | ||
472 | return 0; | |
473 | ||
d534df3c MW |
474 | free_nbio: |
475 | free_nbio(nvmeq, nbio); | |
b60503ba MW |
476 | congestion: |
477 | return -EBUSY; | |
478 | } | |
479 | ||
9294bbed MW |
480 | static void nvme_resubmit_bio(struct nvme_queue *nvmeq, struct bio *bio) |
481 | { | |
482 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
483 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) | |
484 | bio_list_add_head(&nvmeq->sq_cong, bio); | |
485 | else if (bio_list_empty(&nvmeq->sq_cong)) | |
486 | blk_clear_queue_congested(ns->queue, rw_is_sync(bio->bi_rw)); | |
487 | /* XXX: Need to duplicate the logic from __freed_request here */ | |
488 | } | |
489 | ||
b60503ba MW |
490 | /* |
491 | * NB: return value of non-zero would mean that we were a stacking driver. | |
492 | * make_request must always succeed. | |
493 | */ | |
494 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
495 | { | |
496 | struct nvme_ns *ns = q->queuedata; | |
497 | struct nvme_queue *nvmeq = get_nvmeq(ns); | |
498 | ||
499 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
500 | blk_set_queue_congested(q, rw_is_sync(bio->bi_rw)); | |
9294bbed | 501 | spin_lock_irq(&nvmeq->q_lock); |
b60503ba | 502 | bio_list_add(&nvmeq->sq_cong, bio); |
9294bbed | 503 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
504 | } |
505 | put_nvmeq(nvmeq); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | struct sync_cmd_info { | |
511 | struct task_struct *task; | |
512 | u32 result; | |
513 | int status; | |
514 | }; | |
515 | ||
516 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, | |
517 | struct nvme_completion *cqe) | |
518 | { | |
519 | struct sync_cmd_info *cmdinfo = ctx; | |
be7b6275 MW |
520 | if ((unsigned long)cmdinfo == CMD_CTX_CANCELLED) |
521 | return; | |
b36235df MW |
522 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_COMPLETED)) { |
523 | dev_warn(nvmeq->q_dmadev, | |
524 | "completed id %d twice on queue %d\n", | |
525 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
526 | return; | |
527 | } | |
48e3d398 MW |
528 | if (unlikely((unsigned long)cmdinfo == CMD_CTX_INVALID)) { |
529 | dev_warn(nvmeq->q_dmadev, | |
530 | "invalid id %d completed on queue %d\n", | |
531 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
532 | return; | |
533 | } | |
b60503ba MW |
534 | cmdinfo->result = le32_to_cpup(&cqe->result); |
535 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
536 | wake_up_process(cmdinfo->task); | |
537 | } | |
538 | ||
539 | typedef void (*completion_fn)(struct nvme_queue *, void *, | |
540 | struct nvme_completion *); | |
541 | ||
542 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) | |
543 | { | |
82123460 | 544 | u16 head, phase; |
b60503ba MW |
545 | |
546 | static const completion_fn completions[4] = { | |
547 | [sync_completion_id] = sync_completion, | |
548 | [bio_completion_id] = bio_completion, | |
549 | }; | |
550 | ||
551 | head = nvmeq->cq_head; | |
82123460 | 552 | phase = nvmeq->cq_phase; |
b60503ba MW |
553 | |
554 | for (;;) { | |
555 | unsigned long data; | |
556 | void *ptr; | |
557 | unsigned char handler; | |
558 | struct nvme_completion cqe = nvmeq->cqes[head]; | |
82123460 | 559 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
560 | break; |
561 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
562 | if (++head == nvmeq->q_depth) { | |
563 | head = 0; | |
82123460 | 564 | phase = !phase; |
b60503ba MW |
565 | } |
566 | ||
567 | data = free_cmdid(nvmeq, cqe.command_id); | |
568 | handler = data & 3; | |
569 | ptr = (void *)(data & ~3UL); | |
570 | completions[handler](nvmeq, ptr, &cqe); | |
571 | } | |
572 | ||
573 | /* If the controller ignores the cq head doorbell and continuously | |
574 | * writes to the queue, it is theoretically possible to wrap around | |
575 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
576 | * requires that 0.1% of your interrupts are handled, so this isn't | |
577 | * a big problem. | |
578 | */ | |
82123460 | 579 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
580 | return IRQ_NONE; |
581 | ||
582 | writel(head, nvmeq->q_db + 1); | |
583 | nvmeq->cq_head = head; | |
82123460 | 584 | nvmeq->cq_phase = phase; |
b60503ba MW |
585 | |
586 | return IRQ_HANDLED; | |
587 | } | |
588 | ||
589 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
590 | { |
591 | irqreturn_t result; | |
592 | struct nvme_queue *nvmeq = data; | |
593 | spin_lock(&nvmeq->q_lock); | |
594 | result = nvme_process_cq(nvmeq); | |
595 | spin_unlock(&nvmeq->q_lock); | |
596 | return result; | |
597 | } | |
598 | ||
599 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
600 | { | |
601 | struct nvme_queue *nvmeq = data; | |
602 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
603 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
604 | return IRQ_NONE; | |
605 | return IRQ_WAKE_THREAD; | |
606 | } | |
607 | ||
3c0cf138 MW |
608 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
609 | { | |
610 | spin_lock_irq(&nvmeq->q_lock); | |
be7b6275 | 611 | cancel_cmdid_data(nvmeq, cmdid); |
3c0cf138 MW |
612 | spin_unlock_irq(&nvmeq->q_lock); |
613 | } | |
614 | ||
b60503ba MW |
615 | /* |
616 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
617 | * if the result is positive, it's an NVM Express status code | |
618 | */ | |
3c0cf138 | 619 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
e85248e5 | 620 | struct nvme_command *cmd, u32 *result, unsigned timeout) |
b60503ba MW |
621 | { |
622 | int cmdid; | |
623 | struct sync_cmd_info cmdinfo; | |
624 | ||
625 | cmdinfo.task = current; | |
626 | cmdinfo.status = -EINTR; | |
627 | ||
e85248e5 MW |
628 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id, |
629 | timeout); | |
b60503ba MW |
630 | if (cmdid < 0) |
631 | return cmdid; | |
632 | cmd->common.command_id = cmdid; | |
633 | ||
3c0cf138 MW |
634 | set_current_state(TASK_KILLABLE); |
635 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
636 | schedule(); |
637 | ||
3c0cf138 MW |
638 | if (cmdinfo.status == -EINTR) { |
639 | nvme_abort_command(nvmeq, cmdid); | |
640 | return -EINTR; | |
641 | } | |
642 | ||
b60503ba MW |
643 | if (result) |
644 | *result = cmdinfo.result; | |
645 | ||
646 | return cmdinfo.status; | |
647 | } | |
648 | ||
649 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
650 | u32 *result) | |
651 | { | |
e85248e5 | 652 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
653 | } |
654 | ||
655 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
656 | { | |
657 | int status; | |
658 | struct nvme_command c; | |
659 | ||
660 | memset(&c, 0, sizeof(c)); | |
661 | c.delete_queue.opcode = opcode; | |
662 | c.delete_queue.qid = cpu_to_le16(id); | |
663 | ||
664 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
665 | if (status) | |
666 | return -EIO; | |
667 | return 0; | |
668 | } | |
669 | ||
670 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
671 | struct nvme_queue *nvmeq) | |
672 | { | |
673 | int status; | |
674 | struct nvme_command c; | |
675 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
676 | ||
677 | memset(&c, 0, sizeof(c)); | |
678 | c.create_cq.opcode = nvme_admin_create_cq; | |
679 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
680 | c.create_cq.cqid = cpu_to_le16(qid); | |
681 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
682 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
683 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
684 | ||
685 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
686 | if (status) | |
687 | return -EIO; | |
688 | return 0; | |
689 | } | |
690 | ||
691 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
692 | struct nvme_queue *nvmeq) | |
693 | { | |
694 | int status; | |
695 | struct nvme_command c; | |
696 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
697 | ||
698 | memset(&c, 0, sizeof(c)); | |
699 | c.create_sq.opcode = nvme_admin_create_sq; | |
700 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
701 | c.create_sq.sqid = cpu_to_le16(qid); | |
702 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
703 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
704 | c.create_sq.cqid = cpu_to_le16(qid); | |
705 | ||
706 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
707 | if (status) | |
708 | return -EIO; | |
709 | return 0; | |
710 | } | |
711 | ||
712 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
713 | { | |
714 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
715 | } | |
716 | ||
717 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
718 | { | |
719 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
720 | } | |
721 | ||
722 | static void nvme_free_queue(struct nvme_dev *dev, int qid) | |
723 | { | |
724 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
725 | ||
726 | free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq); | |
727 | ||
728 | /* Don't tell the adapter to delete the admin queue */ | |
729 | if (qid) { | |
730 | adapter_delete_sq(dev, qid); | |
731 | adapter_delete_cq(dev, qid); | |
732 | } | |
733 | ||
734 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
735 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
736 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
737 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
738 | kfree(nvmeq); | |
739 | } | |
740 | ||
741 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
742 | int depth, int vector) | |
743 | { | |
744 | struct device *dmadev = &dev->pci_dev->dev; | |
e85248e5 | 745 | unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info)); |
b60503ba MW |
746 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
747 | if (!nvmeq) | |
748 | return NULL; | |
749 | ||
750 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
751 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
752 | if (!nvmeq->cqes) | |
753 | goto free_nvmeq; | |
754 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
755 | ||
756 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
757 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
758 | if (!nvmeq->sq_cmds) | |
759 | goto free_cqdma; | |
760 | ||
761 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 762 | nvmeq->dev = dev; |
b60503ba MW |
763 | spin_lock_init(&nvmeq->q_lock); |
764 | nvmeq->cq_head = 0; | |
82123460 | 765 | nvmeq->cq_phase = 1; |
b60503ba MW |
766 | init_waitqueue_head(&nvmeq->sq_full); |
767 | bio_list_init(&nvmeq->sq_cong); | |
768 | nvmeq->q_db = &dev->dbs[qid * 2]; | |
769 | nvmeq->q_depth = depth; | |
770 | nvmeq->cq_vector = vector; | |
771 | ||
772 | return nvmeq; | |
773 | ||
774 | free_cqdma: | |
775 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
776 | nvmeq->cq_dma_addr); | |
777 | free_nvmeq: | |
778 | kfree(nvmeq); | |
779 | return NULL; | |
780 | } | |
781 | ||
3001082c MW |
782 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
783 | const char *name) | |
784 | { | |
58ffacb5 MW |
785 | if (use_threaded_interrupts) |
786 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 787 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
788 | IRQF_DISABLED | IRQF_SHARED, |
789 | name, nvmeq); | |
3001082c MW |
790 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
791 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
792 | } | |
793 | ||
b60503ba MW |
794 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
795 | int qid, int cq_size, int vector) | |
796 | { | |
797 | int result; | |
798 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
799 | ||
3f85d50b MW |
800 | if (!nvmeq) |
801 | return NULL; | |
802 | ||
b60503ba MW |
803 | result = adapter_alloc_cq(dev, qid, nvmeq); |
804 | if (result < 0) | |
805 | goto free_nvmeq; | |
806 | ||
807 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
808 | if (result < 0) | |
809 | goto release_cq; | |
810 | ||
3001082c | 811 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
812 | if (result < 0) |
813 | goto release_sq; | |
814 | ||
815 | return nvmeq; | |
816 | ||
817 | release_sq: | |
818 | adapter_delete_sq(dev, qid); | |
819 | release_cq: | |
820 | adapter_delete_cq(dev, qid); | |
821 | free_nvmeq: | |
822 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
823 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
824 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
825 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
826 | kfree(nvmeq); | |
827 | return NULL; | |
828 | } | |
829 | ||
830 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
831 | { | |
832 | int result; | |
833 | u32 aqa; | |
834 | struct nvme_queue *nvmeq; | |
835 | ||
836 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
837 | ||
838 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
839 | if (!nvmeq) |
840 | return -ENOMEM; | |
b60503ba MW |
841 | |
842 | aqa = nvmeq->q_depth - 1; | |
843 | aqa |= aqa << 16; | |
844 | ||
845 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
846 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
847 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
848 | ||
5911f200 | 849 | writel(0, &dev->bar->cc); |
b60503ba MW |
850 | writel(aqa, &dev->bar->aqa); |
851 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
852 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
853 | writel(dev->ctrl_config, &dev->bar->cc); | |
854 | ||
855 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { | |
856 | msleep(100); | |
857 | if (fatal_signal_pending(current)) | |
858 | return -EINTR; | |
859 | } | |
860 | ||
3001082c | 861 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
862 | dev->queues[0] = nvmeq; |
863 | return result; | |
864 | } | |
865 | ||
7fc3cdab MW |
866 | static int nvme_map_user_pages(struct nvme_dev *dev, int write, |
867 | unsigned long addr, unsigned length, | |
868 | struct scatterlist **sgp) | |
b60503ba | 869 | { |
36c14ed9 | 870 | int i, err, count, nents, offset; |
7fc3cdab MW |
871 | struct scatterlist *sg; |
872 | struct page **pages; | |
36c14ed9 MW |
873 | |
874 | if (addr & 3) | |
875 | return -EINVAL; | |
7fc3cdab MW |
876 | if (!length) |
877 | return -EINVAL; | |
878 | ||
36c14ed9 | 879 | offset = offset_in_page(addr); |
7fc3cdab MW |
880 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
881 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
882 | |
883 | err = get_user_pages_fast(addr, count, 1, pages); | |
884 | if (err < count) { | |
885 | count = err; | |
886 | err = -EFAULT; | |
887 | goto put_pages; | |
888 | } | |
7fc3cdab MW |
889 | |
890 | sg = kcalloc(count, sizeof(*sg), GFP_KERNEL); | |
36c14ed9 | 891 | sg_init_table(sg, count); |
ff22b54f | 892 | sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset); |
7fc3cdab MW |
893 | length -= (PAGE_SIZE - offset); |
894 | for (i = 1; i < count; i++) { | |
895 | sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0); | |
896 | length -= PAGE_SIZE; | |
897 | } | |
898 | ||
899 | err = -ENOMEM; | |
900 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
901 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 MW |
902 | if (!nents) |
903 | goto put_pages; | |
b60503ba | 904 | |
7fc3cdab MW |
905 | kfree(pages); |
906 | *sgp = sg; | |
907 | return nents; | |
b60503ba | 908 | |
7fc3cdab MW |
909 | put_pages: |
910 | for (i = 0; i < count; i++) | |
911 | put_page(pages[i]); | |
912 | kfree(pages); | |
913 | return err; | |
914 | } | |
b60503ba | 915 | |
7fc3cdab MW |
916 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
917 | unsigned long addr, int length, | |
918 | struct scatterlist *sg, int nents) | |
919 | { | |
920 | int i, count; | |
b60503ba | 921 | |
7fc3cdab | 922 | count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE); |
36c14ed9 | 923 | dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE); |
7fc3cdab | 924 | |
36c14ed9 | 925 | for (i = 0; i < count; i++) |
7fc3cdab MW |
926 | put_page(sg_page(&sg[i])); |
927 | } | |
b60503ba | 928 | |
7fc3cdab MW |
929 | static int nvme_submit_user_admin_command(struct nvme_dev *dev, |
930 | unsigned long addr, unsigned length, | |
931 | struct nvme_command *cmd) | |
932 | { | |
933 | int err, nents; | |
934 | struct scatterlist *sg; | |
e025344c | 935 | struct nvme_prps *prps; |
7fc3cdab MW |
936 | |
937 | nents = nvme_map_user_pages(dev, 0, addr, length, &sg); | |
938 | if (nents < 0) | |
939 | return nents; | |
d567760c | 940 | prps = nvme_setup_prps(dev, &cmd->common, sg, length); |
7fc3cdab MW |
941 | err = nvme_submit_admin_cmd(dev, cmd, NULL); |
942 | nvme_unmap_user_pages(dev, 0, addr, length, sg, nents); | |
d567760c | 943 | nvme_free_prps(dev, prps); |
7fc3cdab | 944 | return err ? -EIO : 0; |
b60503ba MW |
945 | } |
946 | ||
bd38c555 | 947 | static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns) |
b60503ba | 948 | { |
b60503ba | 949 | struct nvme_command c; |
b60503ba | 950 | |
bd38c555 MW |
951 | memset(&c, 0, sizeof(c)); |
952 | c.identify.opcode = nvme_admin_identify; | |
953 | c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id); | |
954 | c.identify.cns = cpu_to_le32(cns); | |
955 | ||
956 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); | |
957 | } | |
958 | ||
959 | static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr) | |
960 | { | |
961 | struct nvme_command c; | |
b60503ba MW |
962 | |
963 | memset(&c, 0, sizeof(c)); | |
964 | c.features.opcode = nvme_admin_get_features; | |
965 | c.features.nsid = cpu_to_le32(ns->ns_id); | |
b60503ba MW |
966 | c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); |
967 | ||
bd38c555 | 968 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); |
b60503ba MW |
969 | } |
970 | ||
a53295b6 MW |
971 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
972 | { | |
973 | struct nvme_dev *dev = ns->dev; | |
974 | struct nvme_queue *nvmeq; | |
975 | struct nvme_user_io io; | |
976 | struct nvme_command c; | |
977 | unsigned length; | |
978 | u32 result; | |
979 | int nents, status; | |
980 | struct scatterlist *sg; | |
e025344c | 981 | struct nvme_prps *prps; |
a53295b6 MW |
982 | |
983 | if (copy_from_user(&io, uio, sizeof(io))) | |
984 | return -EFAULT; | |
985 | length = io.nblocks << io.block_shift; | |
986 | nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg); | |
987 | if (nents < 0) | |
988 | return nents; | |
989 | ||
990 | memset(&c, 0, sizeof(c)); | |
991 | c.rw.opcode = io.opcode; | |
992 | c.rw.flags = io.flags; | |
993 | c.rw.nsid = cpu_to_le32(io.nsid); | |
994 | c.rw.slba = cpu_to_le64(io.slba); | |
995 | c.rw.length = cpu_to_le16(io.nblocks - 1); | |
996 | c.rw.control = cpu_to_le16(io.control); | |
997 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
998 | c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */ | |
999 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1000 | c.rw.appmask = cpu_to_le16(io.appmask); | |
1001 | /* XXX: metadata */ | |
d567760c | 1002 | prps = nvme_setup_prps(dev, &c.common, sg, length); |
a53295b6 | 1003 | |
d567760c | 1004 | nvmeq = get_nvmeq(ns); |
b1ad37ef MW |
1005 | /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption |
1006 | * disabled. We may be preempted at any point, and be rescheduled | |
1007 | * to a different CPU. That will cause cacheline bouncing, but no | |
1008 | * additional races since q_lock already protects against other CPUs. | |
1009 | */ | |
a53295b6 | 1010 | put_nvmeq(nvmeq); |
e85248e5 | 1011 | status = nvme_submit_sync_cmd(nvmeq, &c, &result, IO_TIMEOUT); |
a53295b6 MW |
1012 | |
1013 | nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents); | |
d567760c | 1014 | nvme_free_prps(dev, prps); |
a53295b6 MW |
1015 | put_user(result, &uio->result); |
1016 | return status; | |
1017 | } | |
1018 | ||
6ee44cdc MW |
1019 | static int nvme_download_firmware(struct nvme_ns *ns, |
1020 | struct nvme_dlfw __user *udlfw) | |
1021 | { | |
1022 | struct nvme_dev *dev = ns->dev; | |
1023 | struct nvme_dlfw dlfw; | |
1024 | struct nvme_command c; | |
1025 | int nents, status; | |
1026 | struct scatterlist *sg; | |
e025344c | 1027 | struct nvme_prps *prps; |
6ee44cdc MW |
1028 | |
1029 | if (copy_from_user(&dlfw, udlfw, sizeof(dlfw))) | |
1030 | return -EFAULT; | |
1031 | if (dlfw.length >= (1 << 30)) | |
1032 | return -EINVAL; | |
1033 | ||
1034 | nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg); | |
1035 | if (nents < 0) | |
1036 | return nents; | |
1037 | ||
1038 | memset(&c, 0, sizeof(c)); | |
1039 | c.dlfw.opcode = nvme_admin_download_fw; | |
1040 | c.dlfw.numd = cpu_to_le32(dlfw.length); | |
1041 | c.dlfw.offset = cpu_to_le32(dlfw.offset); | |
d567760c | 1042 | prps = nvme_setup_prps(dev, &c.common, sg, dlfw.length * 4); |
6ee44cdc MW |
1043 | |
1044 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
1045 | nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents); | |
d567760c | 1046 | nvme_free_prps(dev, prps); |
6ee44cdc MW |
1047 | return status; |
1048 | } | |
1049 | ||
1050 | static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg) | |
1051 | { | |
1052 | struct nvme_dev *dev = ns->dev; | |
1053 | struct nvme_command c; | |
1054 | ||
1055 | memset(&c, 0, sizeof(c)); | |
1056 | c.common.opcode = nvme_admin_activate_fw; | |
1057 | c.common.rsvd10[0] = cpu_to_le32(arg); | |
1058 | ||
1059 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
1060 | } | |
1061 | ||
b60503ba MW |
1062 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1063 | unsigned long arg) | |
1064 | { | |
1065 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1066 | ||
1067 | switch (cmd) { | |
1068 | case NVME_IOCTL_IDENTIFY_NS: | |
36c14ed9 | 1069 | return nvme_identify(ns, arg, 0); |
b60503ba | 1070 | case NVME_IOCTL_IDENTIFY_CTRL: |
36c14ed9 | 1071 | return nvme_identify(ns, arg, 1); |
b60503ba | 1072 | case NVME_IOCTL_GET_RANGE_TYPE: |
bd38c555 | 1073 | return nvme_get_range_type(ns, arg); |
a53295b6 MW |
1074 | case NVME_IOCTL_SUBMIT_IO: |
1075 | return nvme_submit_io(ns, (void __user *)arg); | |
6ee44cdc MW |
1076 | case NVME_IOCTL_DOWNLOAD_FW: |
1077 | return nvme_download_firmware(ns, (void __user *)arg); | |
1078 | case NVME_IOCTL_ACTIVATE_FW: | |
1079 | return nvme_activate_firmware(ns, arg); | |
b60503ba MW |
1080 | default: |
1081 | return -ENOTTY; | |
1082 | } | |
1083 | } | |
1084 | ||
1085 | static const struct block_device_operations nvme_fops = { | |
1086 | .owner = THIS_MODULE, | |
1087 | .ioctl = nvme_ioctl, | |
1088 | }; | |
1089 | ||
1090 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index, | |
1091 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) | |
1092 | { | |
1093 | struct nvme_ns *ns; | |
1094 | struct gendisk *disk; | |
1095 | int lbaf; | |
1096 | ||
1097 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1098 | return NULL; | |
1099 | ||
1100 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1101 | if (!ns) | |
1102 | return NULL; | |
1103 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1104 | if (!ns->queue) | |
1105 | goto out_free_ns; | |
1106 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES | | |
1107 | QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD; | |
1108 | blk_queue_make_request(ns->queue, nvme_make_request); | |
1109 | ns->dev = dev; | |
1110 | ns->queue->queuedata = ns; | |
1111 | ||
1112 | disk = alloc_disk(NVME_MINORS); | |
1113 | if (!disk) | |
1114 | goto out_free_queue; | |
1115 | ns->ns_id = index; | |
1116 | ns->disk = disk; | |
1117 | lbaf = id->flbas & 0xf; | |
1118 | ns->lba_shift = id->lbaf[lbaf].ds; | |
1119 | ||
1120 | disk->major = nvme_major; | |
1121 | disk->minors = NVME_MINORS; | |
1122 | disk->first_minor = NVME_MINORS * index; | |
1123 | disk->fops = &nvme_fops; | |
1124 | disk->private_data = ns; | |
1125 | disk->queue = ns->queue; | |
388f037f | 1126 | disk->driverfs_dev = &dev->pci_dev->dev; |
b60503ba MW |
1127 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index); |
1128 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
1129 | ||
1130 | return ns; | |
1131 | ||
1132 | out_free_queue: | |
1133 | blk_cleanup_queue(ns->queue); | |
1134 | out_free_ns: | |
1135 | kfree(ns); | |
1136 | return NULL; | |
1137 | } | |
1138 | ||
1139 | static void nvme_ns_free(struct nvme_ns *ns) | |
1140 | { | |
1141 | put_disk(ns->disk); | |
1142 | blk_cleanup_queue(ns->queue); | |
1143 | kfree(ns); | |
1144 | } | |
1145 | ||
b3b06812 | 1146 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1147 | { |
1148 | int status; | |
1149 | u32 result; | |
1150 | struct nvme_command c; | |
b3b06812 | 1151 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba MW |
1152 | |
1153 | memset(&c, 0, sizeof(c)); | |
1154 | c.features.opcode = nvme_admin_get_features; | |
1155 | c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES); | |
1156 | c.features.dword11 = cpu_to_le32(q_count); | |
1157 | ||
1158 | status = nvme_submit_admin_cmd(dev, &c, &result); | |
1159 | if (status) | |
1160 | return -EIO; | |
1161 | return min(result & 0xffff, result >> 16) + 1; | |
1162 | } | |
1163 | ||
b60503ba MW |
1164 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1165 | { | |
1b23484b | 1166 | int result, cpu, i, nr_queues; |
b60503ba | 1167 | |
1b23484b MW |
1168 | nr_queues = num_online_cpus(); |
1169 | result = set_queue_count(dev, nr_queues); | |
1170 | if (result < 0) | |
1171 | return result; | |
1172 | if (result < nr_queues) | |
1173 | nr_queues = result; | |
b60503ba | 1174 | |
1b23484b MW |
1175 | /* Deregister the admin queue's interrupt */ |
1176 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1177 | ||
1178 | for (i = 0; i < nr_queues; i++) | |
1179 | dev->entry[i].entry = i; | |
1180 | for (;;) { | |
1181 | result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues); | |
1182 | if (result == 0) { | |
1183 | break; | |
1184 | } else if (result > 0) { | |
1185 | nr_queues = result; | |
1186 | continue; | |
1187 | } else { | |
1188 | nr_queues = 1; | |
1189 | break; | |
1190 | } | |
1191 | } | |
1192 | ||
1193 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1194 | /* XXX: handle failure here */ | |
1195 | ||
1196 | cpu = cpumask_first(cpu_online_mask); | |
1197 | for (i = 0; i < nr_queues; i++) { | |
1198 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); | |
1199 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1200 | } | |
1201 | ||
1202 | for (i = 0; i < nr_queues; i++) { | |
1203 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, | |
1204 | NVME_Q_DEPTH, i); | |
1205 | if (!dev->queues[i + 1]) | |
1206 | return -ENOMEM; | |
1207 | dev->queue_count++; | |
1208 | } | |
b60503ba MW |
1209 | |
1210 | return 0; | |
1211 | } | |
1212 | ||
1213 | static void nvme_free_queues(struct nvme_dev *dev) | |
1214 | { | |
1215 | int i; | |
1216 | ||
1217 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1218 | nvme_free_queue(dev, i); | |
1219 | } | |
1220 | ||
1221 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1222 | { | |
1223 | int res, nn, i; | |
1224 | struct nvme_ns *ns, *next; | |
51814232 | 1225 | struct nvme_id_ctrl *ctrl; |
b60503ba MW |
1226 | void *id; |
1227 | dma_addr_t dma_addr; | |
1228 | struct nvme_command cid, crt; | |
1229 | ||
1230 | res = nvme_setup_io_queues(dev); | |
1231 | if (res) | |
1232 | return res; | |
1233 | ||
1234 | /* XXX: Switch to a SG list once prp2 works */ | |
1235 | id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, | |
1236 | GFP_KERNEL); | |
1237 | ||
1238 | memset(&cid, 0, sizeof(cid)); | |
1239 | cid.identify.opcode = nvme_admin_identify; | |
1240 | cid.identify.nsid = 0; | |
1241 | cid.identify.prp1 = cpu_to_le64(dma_addr); | |
1242 | cid.identify.cns = cpu_to_le32(1); | |
1243 | ||
1244 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1245 | if (res) { | |
1246 | res = -EIO; | |
1247 | goto out_free; | |
1248 | } | |
1249 | ||
51814232 MW |
1250 | ctrl = id; |
1251 | nn = le32_to_cpup(&ctrl->nn); | |
1252 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1253 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1254 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
b60503ba MW |
1255 | |
1256 | cid.identify.cns = 0; | |
1257 | memset(&crt, 0, sizeof(crt)); | |
1258 | crt.features.opcode = nvme_admin_get_features; | |
1259 | crt.features.prp1 = cpu_to_le64(dma_addr + 4096); | |
1260 | crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); | |
1261 | ||
1262 | for (i = 0; i < nn; i++) { | |
1263 | cid.identify.nsid = cpu_to_le32(i); | |
1264 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1265 | if (res) | |
1266 | continue; | |
1267 | ||
1268 | if (((struct nvme_id_ns *)id)->ncap == 0) | |
1269 | continue; | |
1270 | ||
1271 | crt.features.nsid = cpu_to_le32(i); | |
1272 | res = nvme_submit_admin_cmd(dev, &crt, NULL); | |
1273 | if (res) | |
1274 | continue; | |
1275 | ||
1276 | ns = nvme_alloc_ns(dev, i, id, id + 4096); | |
1277 | if (ns) | |
1278 | list_add_tail(&ns->list, &dev->namespaces); | |
1279 | } | |
1280 | list_for_each_entry(ns, &dev->namespaces, list) | |
1281 | add_disk(ns->disk); | |
1282 | ||
1283 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1284 | return 0; | |
1285 | ||
1286 | out_free: | |
1287 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1288 | list_del(&ns->list); | |
1289 | nvme_ns_free(ns); | |
1290 | } | |
1291 | ||
1292 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1293 | return res; | |
1294 | } | |
1295 | ||
1296 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1297 | { | |
1298 | struct nvme_ns *ns, *next; | |
1299 | ||
1300 | /* TODO: wait all I/O finished or cancel them */ | |
1301 | ||
1302 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1303 | list_del(&ns->list); | |
1304 | del_gendisk(ns->disk); | |
1305 | nvme_ns_free(ns); | |
1306 | } | |
1307 | ||
1308 | nvme_free_queues(dev); | |
1309 | ||
1310 | return 0; | |
1311 | } | |
1312 | ||
091b6092 MW |
1313 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1314 | { | |
1315 | struct device *dmadev = &dev->pci_dev->dev; | |
1316 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1317 | PAGE_SIZE, PAGE_SIZE, 0); | |
1318 | if (!dev->prp_page_pool) | |
1319 | return -ENOMEM; | |
1320 | ||
99802a7a MW |
1321 | /* Optimisation for I/Os between 4k and 128k */ |
1322 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1323 | 256, 256, 0); | |
1324 | if (!dev->prp_small_pool) { | |
1325 | dma_pool_destroy(dev->prp_page_pool); | |
1326 | return -ENOMEM; | |
1327 | } | |
091b6092 MW |
1328 | return 0; |
1329 | } | |
1330 | ||
1331 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1332 | { | |
1333 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1334 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1335 | } |
1336 | ||
b60503ba MW |
1337 | /* XXX: Use an ida or something to let remove / add work correctly */ |
1338 | static void nvme_set_instance(struct nvme_dev *dev) | |
1339 | { | |
1340 | static int instance; | |
1341 | dev->instance = instance++; | |
1342 | } | |
1343 | ||
1344 | static void nvme_release_instance(struct nvme_dev *dev) | |
1345 | { | |
1346 | } | |
1347 | ||
1348 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1349 | const struct pci_device_id *id) | |
1350 | { | |
574e8b95 | 1351 | int bars, result = -ENOMEM; |
b60503ba MW |
1352 | struct nvme_dev *dev; |
1353 | ||
1354 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1355 | if (!dev) | |
1356 | return -ENOMEM; | |
1357 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1358 | GFP_KERNEL); | |
1359 | if (!dev->entry) | |
1360 | goto free; | |
1b23484b MW |
1361 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1362 | GFP_KERNEL); | |
b60503ba MW |
1363 | if (!dev->queues) |
1364 | goto free; | |
1365 | ||
0ee5a7d7 SMM |
1366 | if (pci_enable_device_mem(pdev)) |
1367 | goto free; | |
f64d3365 | 1368 | pci_set_master(pdev); |
574e8b95 MW |
1369 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1370 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1371 | goto disable; | |
0ee5a7d7 | 1372 | |
b60503ba MW |
1373 | INIT_LIST_HEAD(&dev->namespaces); |
1374 | dev->pci_dev = pdev; | |
1375 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1376 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1377 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1378 | nvme_set_instance(dev); |
53c9577e | 1379 | dev->entry[0].vector = pdev->irq; |
b60503ba | 1380 | |
091b6092 MW |
1381 | result = nvme_setup_prp_pools(dev); |
1382 | if (result) | |
1383 | goto disable_msix; | |
1384 | ||
b60503ba MW |
1385 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1386 | if (!dev->bar) { | |
1387 | result = -ENOMEM; | |
574e8b95 | 1388 | goto disable_msix; |
b60503ba MW |
1389 | } |
1390 | ||
1391 | result = nvme_configure_admin_queue(dev); | |
1392 | if (result) | |
1393 | goto unmap; | |
1394 | dev->queue_count++; | |
1395 | ||
1396 | result = nvme_dev_add(dev); | |
1397 | if (result) | |
1398 | goto delete; | |
1399 | return 0; | |
1400 | ||
1401 | delete: | |
1402 | nvme_free_queues(dev); | |
1403 | unmap: | |
1404 | iounmap(dev->bar); | |
574e8b95 | 1405 | disable_msix: |
b60503ba MW |
1406 | pci_disable_msix(pdev); |
1407 | nvme_release_instance(dev); | |
091b6092 | 1408 | nvme_release_prp_pools(dev); |
574e8b95 | 1409 | disable: |
0ee5a7d7 | 1410 | pci_disable_device(pdev); |
574e8b95 | 1411 | pci_release_regions(pdev); |
b60503ba MW |
1412 | free: |
1413 | kfree(dev->queues); | |
1414 | kfree(dev->entry); | |
1415 | kfree(dev); | |
1416 | return result; | |
1417 | } | |
1418 | ||
1419 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1420 | { | |
1421 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1422 | nvme_dev_remove(dev); | |
1423 | pci_disable_msix(pdev); | |
1424 | iounmap(dev->bar); | |
1425 | nvme_release_instance(dev); | |
091b6092 | 1426 | nvme_release_prp_pools(dev); |
0ee5a7d7 | 1427 | pci_disable_device(pdev); |
574e8b95 | 1428 | pci_release_regions(pdev); |
b60503ba MW |
1429 | kfree(dev->queues); |
1430 | kfree(dev->entry); | |
1431 | kfree(dev); | |
1432 | } | |
1433 | ||
1434 | /* These functions are yet to be implemented */ | |
1435 | #define nvme_error_detected NULL | |
1436 | #define nvme_dump_registers NULL | |
1437 | #define nvme_link_reset NULL | |
1438 | #define nvme_slot_reset NULL | |
1439 | #define nvme_error_resume NULL | |
1440 | #define nvme_suspend NULL | |
1441 | #define nvme_resume NULL | |
1442 | ||
1443 | static struct pci_error_handlers nvme_err_handler = { | |
1444 | .error_detected = nvme_error_detected, | |
1445 | .mmio_enabled = nvme_dump_registers, | |
1446 | .link_reset = nvme_link_reset, | |
1447 | .slot_reset = nvme_slot_reset, | |
1448 | .resume = nvme_error_resume, | |
1449 | }; | |
1450 | ||
1451 | /* Move to pci_ids.h later */ | |
1452 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1453 | ||
1454 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1455 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1456 | { 0, } | |
1457 | }; | |
1458 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1459 | ||
1460 | static struct pci_driver nvme_driver = { | |
1461 | .name = "nvme", | |
1462 | .id_table = nvme_id_table, | |
1463 | .probe = nvme_probe, | |
1464 | .remove = __devexit_p(nvme_remove), | |
1465 | .suspend = nvme_suspend, | |
1466 | .resume = nvme_resume, | |
1467 | .err_handler = &nvme_err_handler, | |
1468 | }; | |
1469 | ||
1470 | static int __init nvme_init(void) | |
1471 | { | |
1472 | int result; | |
1473 | ||
1474 | nvme_major = register_blkdev(nvme_major, "nvme"); | |
1475 | if (nvme_major <= 0) | |
1476 | return -EBUSY; | |
1477 | ||
1478 | result = pci_register_driver(&nvme_driver); | |
1479 | if (!result) | |
1480 | return 0; | |
1481 | ||
1482 | unregister_blkdev(nvme_major, "nvme"); | |
1483 | return result; | |
1484 | } | |
1485 | ||
1486 | static void __exit nvme_exit(void) | |
1487 | { | |
1488 | pci_unregister_driver(&nvme_driver); | |
1489 | unregister_blkdev(nvme_major, "nvme"); | |
1490 | } | |
1491 | ||
1492 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1493 | MODULE_LICENSE("GPL"); | |
db5d0c19 | 1494 | MODULE_VERSION("0.2"); |
b60503ba MW |
1495 | module_init(nvme_init); |
1496 | module_exit(nvme_exit); |