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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/moduleparam.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/version.h> | |
38 | ||
39 | #define NVME_Q_DEPTH 1024 | |
40 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
41 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
42 | #define NVME_MINORS 64 | |
43 | ||
44 | static int nvme_major; | |
45 | module_param(nvme_major, int, 0); | |
46 | ||
47 | /* | |
48 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
49 | */ | |
50 | struct nvme_dev { | |
b60503ba MW |
51 | struct nvme_queue **queues; |
52 | u32 __iomem *dbs; | |
53 | struct pci_dev *pci_dev; | |
54 | int instance; | |
55 | int queue_count; | |
56 | u32 ctrl_config; | |
57 | struct msix_entry *entry; | |
58 | struct nvme_bar __iomem *bar; | |
59 | struct list_head namespaces; | |
51814232 MW |
60 | char serial[20]; |
61 | char model[40]; | |
62 | char firmware_rev[8]; | |
b60503ba MW |
63 | }; |
64 | ||
65 | /* | |
66 | * An NVM Express namespace is equivalent to a SCSI LUN | |
67 | */ | |
68 | struct nvme_ns { | |
69 | struct list_head list; | |
70 | ||
71 | struct nvme_dev *dev; | |
72 | struct request_queue *queue; | |
73 | struct gendisk *disk; | |
74 | ||
75 | int ns_id; | |
76 | int lba_shift; | |
77 | }; | |
78 | ||
79 | /* | |
80 | * An NVM Express queue. Each device has at least two (one for admin | |
81 | * commands and one for I/O commands). | |
82 | */ | |
83 | struct nvme_queue { | |
84 | struct device *q_dmadev; | |
85 | spinlock_t q_lock; | |
86 | struct nvme_command *sq_cmds; | |
87 | volatile struct nvme_completion *cqes; | |
88 | dma_addr_t sq_dma_addr; | |
89 | dma_addr_t cq_dma_addr; | |
90 | wait_queue_head_t sq_full; | |
91 | struct bio_list sq_cong; | |
92 | u32 __iomem *q_db; | |
93 | u16 q_depth; | |
94 | u16 cq_vector; | |
95 | u16 sq_head; | |
96 | u16 sq_tail; | |
97 | u16 cq_head; | |
82123460 | 98 | u16 cq_phase; |
b60503ba MW |
99 | unsigned long cmdid_data[]; |
100 | }; | |
101 | ||
102 | /* | |
103 | * Check we didin't inadvertently grow the command struct | |
104 | */ | |
105 | static inline void _nvme_check_size(void) | |
106 | { | |
107 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
108 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
109 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
110 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
111 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
112 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
113 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
114 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
115 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
116 | } | |
117 | ||
118 | /** | |
119 | * alloc_cmdid - Allocate a Command ID | |
120 | * @param nvmeq The queue that will be used for this command | |
121 | * @param ctx A pointer that will be passed to the handler | |
122 | * @param handler The ID of the handler to call | |
123 | * | |
124 | * Allocate a Command ID for a queue. The data passed in will | |
125 | * be passed to the completion handler. This is implemented by using | |
126 | * the bottom two bits of the ctx pointer to store the handler ID. | |
127 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
128 | * We can change this if it becomes a problem. | |
129 | */ | |
130 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler) | |
131 | { | |
132 | int depth = nvmeq->q_depth; | |
133 | unsigned long data = (unsigned long)ctx | handler; | |
134 | int cmdid; | |
135 | ||
136 | BUG_ON((unsigned long)ctx & 3); | |
137 | ||
138 | do { | |
139 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
140 | if (cmdid >= depth) | |
141 | return -EBUSY; | |
142 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
143 | ||
144 | nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data; | |
145 | return cmdid; | |
146 | } | |
147 | ||
148 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
149 | int handler) | |
150 | { | |
151 | int cmdid; | |
152 | wait_event_killable(nvmeq->sq_full, | |
153 | (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0); | |
154 | return (cmdid < 0) ? -EINTR : cmdid; | |
155 | } | |
156 | ||
157 | /* If you need more than four handlers, you'll need to change how | |
3c0cf138 MW |
158 | * alloc_cmdid and nvme_process_cq work. Also, aborted commands take |
159 | * the sync_completion path (if they complete), so don't put anything | |
160 | * else in slot zero. | |
b60503ba MW |
161 | */ |
162 | enum { | |
163 | sync_completion_id = 0, | |
164 | bio_completion_id, | |
165 | }; | |
166 | ||
167 | static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid) | |
168 | { | |
169 | unsigned long data; | |
170 | ||
171 | data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)]; | |
172 | clear_bit(cmdid, nvmeq->cmdid_data); | |
173 | wake_up(&nvmeq->sq_full); | |
174 | return data; | |
175 | } | |
176 | ||
3c0cf138 MW |
177 | static void clear_cmdid_data(struct nvme_queue *nvmeq, int cmdid) |
178 | { | |
179 | nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)] = 0; | |
180 | } | |
181 | ||
b60503ba MW |
182 | static struct nvme_queue *get_nvmeq(struct nvme_ns *ns) |
183 | { | |
1b23484b MW |
184 | int qid, cpu = get_cpu(); |
185 | if (cpu < ns->dev->queue_count) | |
186 | qid = cpu + 1; | |
187 | else | |
188 | qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1; | |
189 | return ns->dev->queues[qid]; | |
b60503ba MW |
190 | } |
191 | ||
192 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
193 | { | |
1b23484b | 194 | put_cpu(); |
b60503ba MW |
195 | } |
196 | ||
197 | /** | |
198 | * nvme_submit_cmd: Copy a command into a queue and ring the doorbell | |
199 | * @nvmeq: The queue to use | |
200 | * @cmd: The command to send | |
201 | * | |
202 | * Safe to use from interrupt context | |
203 | */ | |
204 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
205 | { | |
206 | unsigned long flags; | |
207 | u16 tail; | |
208 | /* XXX: Need to check tail isn't going to overrun head */ | |
209 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
210 | tail = nvmeq->sq_tail; | |
211 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
212 | writel(tail, nvmeq->q_db); | |
213 | if (++tail == nvmeq->q_depth) | |
214 | tail = 0; | |
215 | nvmeq->sq_tail = tail; | |
216 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | struct nvme_req_info { | |
222 | struct bio *bio; | |
223 | int nents; | |
224 | struct scatterlist sg[0]; | |
225 | }; | |
226 | ||
227 | /* XXX: use a mempool */ | |
228 | static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp) | |
229 | { | |
230 | return kmalloc(sizeof(struct nvme_req_info) + | |
231 | sizeof(struct scatterlist) * nseg, gfp); | |
232 | } | |
233 | ||
234 | static void free_info(struct nvme_req_info *info) | |
235 | { | |
236 | kfree(info); | |
237 | } | |
238 | ||
239 | static void bio_completion(struct nvme_queue *nvmeq, void *ctx, | |
240 | struct nvme_completion *cqe) | |
241 | { | |
242 | struct nvme_req_info *info = ctx; | |
243 | struct bio *bio = info->bio; | |
244 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
245 | ||
246 | dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents, | |
247 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
248 | free_info(info); | |
249 | bio_endio(bio, status ? -EIO : 0); | |
250 | } | |
251 | ||
ff22b54f MW |
252 | /* length is in bytes */ |
253 | static void nvme_setup_prps(struct nvme_common_command *cmd, | |
254 | struct scatterlist *sg, int length) | |
255 | { | |
256 | int dma_len = sg_dma_len(sg); | |
257 | u64 dma_addr = sg_dma_address(sg); | |
258 | int offset = offset_in_page(dma_addr); | |
259 | ||
260 | cmd->prp1 = cpu_to_le64(dma_addr); | |
261 | length -= (PAGE_SIZE - offset); | |
262 | if (length <= 0) | |
263 | return; | |
264 | ||
265 | dma_len -= (PAGE_SIZE - offset); | |
266 | if (dma_len) { | |
267 | dma_addr += (PAGE_SIZE - offset); | |
268 | } else { | |
269 | sg = sg_next(sg); | |
270 | dma_addr = sg_dma_address(sg); | |
271 | dma_len = sg_dma_len(sg); | |
272 | } | |
273 | ||
274 | if (length <= PAGE_SIZE) { | |
275 | cmd->prp2 = cpu_to_le64(dma_addr); | |
276 | return; | |
277 | } | |
278 | ||
279 | /* XXX: support PRP lists */ | |
280 | } | |
281 | ||
b60503ba MW |
282 | static int nvme_map_bio(struct device *dev, struct nvme_req_info *info, |
283 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) | |
284 | { | |
285 | struct bio_vec *bvec; | |
286 | struct scatterlist *sg = info->sg; | |
287 | int i, nsegs; | |
288 | ||
289 | sg_init_table(sg, psegs); | |
290 | bio_for_each_segment(bvec, bio, i) { | |
291 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset); | |
292 | /* XXX: handle non-mergable here */ | |
293 | nsegs++; | |
294 | } | |
295 | info->nents = nsegs; | |
296 | ||
297 | return dma_map_sg(dev, info->sg, info->nents, dma_dir); | |
298 | } | |
299 | ||
300 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
301 | struct bio *bio) | |
302 | { | |
ff22b54f | 303 | struct nvme_command *cmnd; |
b60503ba MW |
304 | struct nvme_req_info *info; |
305 | enum dma_data_direction dma_dir; | |
306 | int cmdid; | |
307 | u16 control; | |
308 | u32 dsmgmt; | |
309 | unsigned long flags; | |
310 | int psegs = bio_phys_segments(ns->queue, bio); | |
311 | ||
312 | info = alloc_info(psegs, GFP_NOIO); | |
313 | if (!info) | |
314 | goto congestion; | |
315 | info->bio = bio; | |
316 | ||
317 | cmdid = alloc_cmdid(nvmeq, info, bio_completion_id); | |
318 | if (unlikely(cmdid < 0)) | |
319 | goto free_info; | |
320 | ||
321 | control = 0; | |
322 | if (bio->bi_rw & REQ_FUA) | |
323 | control |= NVME_RW_FUA; | |
324 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
325 | control |= NVME_RW_LR; | |
326 | ||
327 | dsmgmt = 0; | |
328 | if (bio->bi_rw & REQ_RAHEAD) | |
329 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
330 | ||
331 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
ff22b54f | 332 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 333 | |
b8deb62c | 334 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 335 | if (bio_data_dir(bio)) { |
ff22b54f | 336 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
337 | dma_dir = DMA_TO_DEVICE; |
338 | } else { | |
ff22b54f | 339 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
340 | dma_dir = DMA_FROM_DEVICE; |
341 | } | |
342 | ||
343 | nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs); | |
344 | ||
ff22b54f MW |
345 | cmnd->rw.flags = 1; |
346 | cmnd->rw.command_id = cmdid; | |
347 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
348 | nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size); | |
349 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); | |
350 | cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1); | |
351 | cmnd->rw.control = cpu_to_le16(control); | |
352 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba MW |
353 | |
354 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
355 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
356 | nvmeq->sq_tail = 0; | |
357 | ||
358 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
359 | ||
360 | return 0; | |
361 | ||
362 | free_info: | |
363 | free_info(info); | |
364 | congestion: | |
365 | return -EBUSY; | |
366 | } | |
367 | ||
368 | /* | |
369 | * NB: return value of non-zero would mean that we were a stacking driver. | |
370 | * make_request must always succeed. | |
371 | */ | |
372 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
373 | { | |
374 | struct nvme_ns *ns = q->queuedata; | |
375 | struct nvme_queue *nvmeq = get_nvmeq(ns); | |
376 | ||
377 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
378 | blk_set_queue_congested(q, rw_is_sync(bio->bi_rw)); | |
379 | bio_list_add(&nvmeq->sq_cong, bio); | |
380 | } | |
381 | put_nvmeq(nvmeq); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | struct sync_cmd_info { | |
387 | struct task_struct *task; | |
388 | u32 result; | |
389 | int status; | |
390 | }; | |
391 | ||
392 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, | |
393 | struct nvme_completion *cqe) | |
394 | { | |
395 | struct sync_cmd_info *cmdinfo = ctx; | |
3c0cf138 MW |
396 | if (!cmdinfo) |
397 | return; /* Command aborted */ | |
b60503ba MW |
398 | cmdinfo->result = le32_to_cpup(&cqe->result); |
399 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
400 | wake_up_process(cmdinfo->task); | |
401 | } | |
402 | ||
403 | typedef void (*completion_fn)(struct nvme_queue *, void *, | |
404 | struct nvme_completion *); | |
405 | ||
406 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) | |
407 | { | |
82123460 | 408 | u16 head, phase; |
b60503ba MW |
409 | |
410 | static const completion_fn completions[4] = { | |
411 | [sync_completion_id] = sync_completion, | |
412 | [bio_completion_id] = bio_completion, | |
413 | }; | |
414 | ||
415 | head = nvmeq->cq_head; | |
82123460 | 416 | phase = nvmeq->cq_phase; |
b60503ba MW |
417 | |
418 | for (;;) { | |
419 | unsigned long data; | |
420 | void *ptr; | |
421 | unsigned char handler; | |
422 | struct nvme_completion cqe = nvmeq->cqes[head]; | |
82123460 | 423 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
424 | break; |
425 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
426 | if (++head == nvmeq->q_depth) { | |
427 | head = 0; | |
82123460 | 428 | phase = !phase; |
b60503ba MW |
429 | } |
430 | ||
431 | data = free_cmdid(nvmeq, cqe.command_id); | |
432 | handler = data & 3; | |
433 | ptr = (void *)(data & ~3UL); | |
434 | completions[handler](nvmeq, ptr, &cqe); | |
435 | } | |
436 | ||
437 | /* If the controller ignores the cq head doorbell and continuously | |
438 | * writes to the queue, it is theoretically possible to wrap around | |
439 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
440 | * requires that 0.1% of your interrupts are handled, so this isn't | |
441 | * a big problem. | |
442 | */ | |
82123460 | 443 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
444 | return IRQ_NONE; |
445 | ||
446 | writel(head, nvmeq->q_db + 1); | |
447 | nvmeq->cq_head = head; | |
82123460 | 448 | nvmeq->cq_phase = phase; |
b60503ba MW |
449 | |
450 | return IRQ_HANDLED; | |
451 | } | |
452 | ||
453 | static irqreturn_t nvme_irq(int irq, void *data) | |
454 | { | |
455 | return nvme_process_cq(data); | |
456 | } | |
457 | ||
3c0cf138 MW |
458 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
459 | { | |
460 | spin_lock_irq(&nvmeq->q_lock); | |
461 | clear_cmdid_data(nvmeq, cmdid); | |
462 | spin_unlock_irq(&nvmeq->q_lock); | |
463 | } | |
464 | ||
b60503ba MW |
465 | /* |
466 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
467 | * if the result is positive, it's an NVM Express status code | |
468 | */ | |
3c0cf138 MW |
469 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
470 | struct nvme_command *cmd, u32 *result) | |
b60503ba MW |
471 | { |
472 | int cmdid; | |
473 | struct sync_cmd_info cmdinfo; | |
474 | ||
475 | cmdinfo.task = current; | |
476 | cmdinfo.status = -EINTR; | |
477 | ||
3c0cf138 | 478 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion_id); |
b60503ba MW |
479 | if (cmdid < 0) |
480 | return cmdid; | |
481 | cmd->common.command_id = cmdid; | |
482 | ||
3c0cf138 MW |
483 | set_current_state(TASK_KILLABLE); |
484 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
485 | schedule(); |
486 | ||
3c0cf138 MW |
487 | if (cmdinfo.status == -EINTR) { |
488 | nvme_abort_command(nvmeq, cmdid); | |
489 | return -EINTR; | |
490 | } | |
491 | ||
b60503ba MW |
492 | if (result) |
493 | *result = cmdinfo.result; | |
494 | ||
495 | return cmdinfo.status; | |
496 | } | |
497 | ||
498 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
499 | u32 *result) | |
500 | { | |
501 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result); | |
502 | } | |
503 | ||
504 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
505 | { | |
506 | int status; | |
507 | struct nvme_command c; | |
508 | ||
509 | memset(&c, 0, sizeof(c)); | |
510 | c.delete_queue.opcode = opcode; | |
511 | c.delete_queue.qid = cpu_to_le16(id); | |
512 | ||
513 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
514 | if (status) | |
515 | return -EIO; | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
520 | struct nvme_queue *nvmeq) | |
521 | { | |
522 | int status; | |
523 | struct nvme_command c; | |
524 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
525 | ||
526 | memset(&c, 0, sizeof(c)); | |
527 | c.create_cq.opcode = nvme_admin_create_cq; | |
528 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
529 | c.create_cq.cqid = cpu_to_le16(qid); | |
530 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
531 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
532 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
533 | ||
534 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
535 | if (status) | |
536 | return -EIO; | |
537 | return 0; | |
538 | } | |
539 | ||
540 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
541 | struct nvme_queue *nvmeq) | |
542 | { | |
543 | int status; | |
544 | struct nvme_command c; | |
545 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
546 | ||
547 | memset(&c, 0, sizeof(c)); | |
548 | c.create_sq.opcode = nvme_admin_create_sq; | |
549 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
550 | c.create_sq.sqid = cpu_to_le16(qid); | |
551 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
552 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
553 | c.create_sq.cqid = cpu_to_le16(qid); | |
554 | ||
555 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
556 | if (status) | |
557 | return -EIO; | |
558 | return 0; | |
559 | } | |
560 | ||
561 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
562 | { | |
563 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
564 | } | |
565 | ||
566 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
567 | { | |
568 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
569 | } | |
570 | ||
571 | static void nvme_free_queue(struct nvme_dev *dev, int qid) | |
572 | { | |
573 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
574 | ||
575 | free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq); | |
576 | ||
577 | /* Don't tell the adapter to delete the admin queue */ | |
578 | if (qid) { | |
579 | adapter_delete_sq(dev, qid); | |
580 | adapter_delete_cq(dev, qid); | |
581 | } | |
582 | ||
583 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
584 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
585 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
586 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
587 | kfree(nvmeq); | |
588 | } | |
589 | ||
590 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
591 | int depth, int vector) | |
592 | { | |
593 | struct device *dmadev = &dev->pci_dev->dev; | |
594 | unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long); | |
595 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); | |
596 | if (!nvmeq) | |
597 | return NULL; | |
598 | ||
599 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
600 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
601 | if (!nvmeq->cqes) | |
602 | goto free_nvmeq; | |
603 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
604 | ||
605 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
606 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
607 | if (!nvmeq->sq_cmds) | |
608 | goto free_cqdma; | |
609 | ||
610 | nvmeq->q_dmadev = dmadev; | |
611 | spin_lock_init(&nvmeq->q_lock); | |
612 | nvmeq->cq_head = 0; | |
82123460 | 613 | nvmeq->cq_phase = 1; |
b60503ba MW |
614 | init_waitqueue_head(&nvmeq->sq_full); |
615 | bio_list_init(&nvmeq->sq_cong); | |
616 | nvmeq->q_db = &dev->dbs[qid * 2]; | |
617 | nvmeq->q_depth = depth; | |
618 | nvmeq->cq_vector = vector; | |
619 | ||
620 | return nvmeq; | |
621 | ||
622 | free_cqdma: | |
623 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
624 | nvmeq->cq_dma_addr); | |
625 | free_nvmeq: | |
626 | kfree(nvmeq); | |
627 | return NULL; | |
628 | } | |
629 | ||
3001082c MW |
630 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
631 | const char *name) | |
632 | { | |
633 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, | |
634 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
635 | } | |
636 | ||
b60503ba MW |
637 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
638 | int qid, int cq_size, int vector) | |
639 | { | |
640 | int result; | |
641 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
642 | ||
3f85d50b MW |
643 | if (!nvmeq) |
644 | return NULL; | |
645 | ||
b60503ba MW |
646 | result = adapter_alloc_cq(dev, qid, nvmeq); |
647 | if (result < 0) | |
648 | goto free_nvmeq; | |
649 | ||
650 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
651 | if (result < 0) | |
652 | goto release_cq; | |
653 | ||
3001082c | 654 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
655 | if (result < 0) |
656 | goto release_sq; | |
657 | ||
658 | return nvmeq; | |
659 | ||
660 | release_sq: | |
661 | adapter_delete_sq(dev, qid); | |
662 | release_cq: | |
663 | adapter_delete_cq(dev, qid); | |
664 | free_nvmeq: | |
665 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
666 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
667 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
668 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
669 | kfree(nvmeq); | |
670 | return NULL; | |
671 | } | |
672 | ||
673 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
674 | { | |
675 | int result; | |
676 | u32 aqa; | |
677 | struct nvme_queue *nvmeq; | |
678 | ||
679 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
680 | ||
681 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
682 | if (!nvmeq) |
683 | return -ENOMEM; | |
b60503ba MW |
684 | |
685 | aqa = nvmeq->q_depth - 1; | |
686 | aqa |= aqa << 16; | |
687 | ||
688 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
689 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
690 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
691 | ||
5911f200 | 692 | writel(0, &dev->bar->cc); |
b60503ba MW |
693 | writel(aqa, &dev->bar->aqa); |
694 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
695 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
696 | writel(dev->ctrl_config, &dev->bar->cc); | |
697 | ||
698 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { | |
699 | msleep(100); | |
700 | if (fatal_signal_pending(current)) | |
701 | return -EINTR; | |
702 | } | |
703 | ||
3001082c | 704 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
705 | dev->queues[0] = nvmeq; |
706 | return result; | |
707 | } | |
708 | ||
7fc3cdab MW |
709 | static int nvme_map_user_pages(struct nvme_dev *dev, int write, |
710 | unsigned long addr, unsigned length, | |
711 | struct scatterlist **sgp) | |
b60503ba | 712 | { |
36c14ed9 | 713 | int i, err, count, nents, offset; |
7fc3cdab MW |
714 | struct scatterlist *sg; |
715 | struct page **pages; | |
36c14ed9 MW |
716 | |
717 | if (addr & 3) | |
718 | return -EINVAL; | |
7fc3cdab MW |
719 | if (!length) |
720 | return -EINVAL; | |
721 | ||
36c14ed9 | 722 | offset = offset_in_page(addr); |
7fc3cdab MW |
723 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
724 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
725 | |
726 | err = get_user_pages_fast(addr, count, 1, pages); | |
727 | if (err < count) { | |
728 | count = err; | |
729 | err = -EFAULT; | |
730 | goto put_pages; | |
731 | } | |
7fc3cdab MW |
732 | |
733 | sg = kcalloc(count, sizeof(*sg), GFP_KERNEL); | |
36c14ed9 | 734 | sg_init_table(sg, count); |
ff22b54f | 735 | sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset); |
7fc3cdab MW |
736 | length -= (PAGE_SIZE - offset); |
737 | for (i = 1; i < count; i++) { | |
738 | sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0); | |
739 | length -= PAGE_SIZE; | |
740 | } | |
741 | ||
742 | err = -ENOMEM; | |
743 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
744 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 MW |
745 | if (!nents) |
746 | goto put_pages; | |
b60503ba | 747 | |
7fc3cdab MW |
748 | kfree(pages); |
749 | *sgp = sg; | |
750 | return nents; | |
b60503ba | 751 | |
7fc3cdab MW |
752 | put_pages: |
753 | for (i = 0; i < count; i++) | |
754 | put_page(pages[i]); | |
755 | kfree(pages); | |
756 | return err; | |
757 | } | |
b60503ba | 758 | |
7fc3cdab MW |
759 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
760 | unsigned long addr, int length, | |
761 | struct scatterlist *sg, int nents) | |
762 | { | |
763 | int i, count; | |
b60503ba | 764 | |
7fc3cdab | 765 | count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE); |
36c14ed9 | 766 | dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE); |
7fc3cdab | 767 | |
36c14ed9 | 768 | for (i = 0; i < count; i++) |
7fc3cdab MW |
769 | put_page(sg_page(&sg[i])); |
770 | } | |
b60503ba | 771 | |
7fc3cdab MW |
772 | static int nvme_submit_user_admin_command(struct nvme_dev *dev, |
773 | unsigned long addr, unsigned length, | |
774 | struct nvme_command *cmd) | |
775 | { | |
776 | int err, nents; | |
777 | struct scatterlist *sg; | |
778 | ||
779 | nents = nvme_map_user_pages(dev, 0, addr, length, &sg); | |
780 | if (nents < 0) | |
781 | return nents; | |
782 | nvme_setup_prps(&cmd->common, sg, length); | |
783 | err = nvme_submit_admin_cmd(dev, cmd, NULL); | |
784 | nvme_unmap_user_pages(dev, 0, addr, length, sg, nents); | |
785 | return err ? -EIO : 0; | |
b60503ba MW |
786 | } |
787 | ||
bd38c555 | 788 | static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns) |
b60503ba | 789 | { |
b60503ba | 790 | struct nvme_command c; |
b60503ba | 791 | |
bd38c555 MW |
792 | memset(&c, 0, sizeof(c)); |
793 | c.identify.opcode = nvme_admin_identify; | |
794 | c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id); | |
795 | c.identify.cns = cpu_to_le32(cns); | |
796 | ||
797 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); | |
798 | } | |
799 | ||
800 | static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr) | |
801 | { | |
802 | struct nvme_command c; | |
b60503ba MW |
803 | |
804 | memset(&c, 0, sizeof(c)); | |
805 | c.features.opcode = nvme_admin_get_features; | |
806 | c.features.nsid = cpu_to_le32(ns->ns_id); | |
b60503ba MW |
807 | c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); |
808 | ||
bd38c555 | 809 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); |
b60503ba MW |
810 | } |
811 | ||
a53295b6 MW |
812 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
813 | { | |
814 | struct nvme_dev *dev = ns->dev; | |
815 | struct nvme_queue *nvmeq; | |
816 | struct nvme_user_io io; | |
817 | struct nvme_command c; | |
818 | unsigned length; | |
819 | u32 result; | |
820 | int nents, status; | |
821 | struct scatterlist *sg; | |
822 | ||
823 | if (copy_from_user(&io, uio, sizeof(io))) | |
824 | return -EFAULT; | |
825 | length = io.nblocks << io.block_shift; | |
826 | nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg); | |
827 | if (nents < 0) | |
828 | return nents; | |
829 | ||
830 | memset(&c, 0, sizeof(c)); | |
831 | c.rw.opcode = io.opcode; | |
832 | c.rw.flags = io.flags; | |
833 | c.rw.nsid = cpu_to_le32(io.nsid); | |
834 | c.rw.slba = cpu_to_le64(io.slba); | |
835 | c.rw.length = cpu_to_le16(io.nblocks - 1); | |
836 | c.rw.control = cpu_to_le16(io.control); | |
837 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
838 | c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */ | |
839 | c.rw.apptag = cpu_to_le16(io.apptag); | |
840 | c.rw.appmask = cpu_to_le16(io.appmask); | |
841 | /* XXX: metadata */ | |
842 | nvme_setup_prps(&c.common, sg, length); | |
843 | ||
844 | nvmeq = get_nvmeq(ns); | |
b1ad37ef MW |
845 | /* Since nvme_submit_sync_cmd sleeps, we can't keep preemption |
846 | * disabled. We may be preempted at any point, and be rescheduled | |
847 | * to a different CPU. That will cause cacheline bouncing, but no | |
848 | * additional races since q_lock already protects against other CPUs. | |
849 | */ | |
a53295b6 | 850 | put_nvmeq(nvmeq); |
b1ad37ef | 851 | status = nvme_submit_sync_cmd(nvmeq, &c, &result); |
a53295b6 MW |
852 | |
853 | nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents); | |
854 | put_user(result, &uio->result); | |
855 | return status; | |
856 | } | |
857 | ||
6ee44cdc MW |
858 | static int nvme_download_firmware(struct nvme_ns *ns, |
859 | struct nvme_dlfw __user *udlfw) | |
860 | { | |
861 | struct nvme_dev *dev = ns->dev; | |
862 | struct nvme_dlfw dlfw; | |
863 | struct nvme_command c; | |
864 | int nents, status; | |
865 | struct scatterlist *sg; | |
866 | ||
867 | if (copy_from_user(&dlfw, udlfw, sizeof(dlfw))) | |
868 | return -EFAULT; | |
869 | if (dlfw.length >= (1 << 30)) | |
870 | return -EINVAL; | |
871 | ||
872 | nents = nvme_map_user_pages(dev, 1, dlfw.addr, dlfw.length * 4, &sg); | |
873 | if (nents < 0) | |
874 | return nents; | |
875 | ||
876 | memset(&c, 0, sizeof(c)); | |
877 | c.dlfw.opcode = nvme_admin_download_fw; | |
878 | c.dlfw.numd = cpu_to_le32(dlfw.length); | |
879 | c.dlfw.offset = cpu_to_le32(dlfw.offset); | |
880 | nvme_setup_prps(&c.common, sg, dlfw.length * 4); | |
881 | ||
882 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
883 | nvme_unmap_user_pages(dev, 0, dlfw.addr, dlfw.length * 4, sg, nents); | |
884 | return status; | |
885 | } | |
886 | ||
887 | static int nvme_activate_firmware(struct nvme_ns *ns, unsigned long arg) | |
888 | { | |
889 | struct nvme_dev *dev = ns->dev; | |
890 | struct nvme_command c; | |
891 | ||
892 | memset(&c, 0, sizeof(c)); | |
893 | c.common.opcode = nvme_admin_activate_fw; | |
894 | c.common.rsvd10[0] = cpu_to_le32(arg); | |
895 | ||
896 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
897 | } | |
898 | ||
b60503ba MW |
899 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
900 | unsigned long arg) | |
901 | { | |
902 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
903 | ||
904 | switch (cmd) { | |
905 | case NVME_IOCTL_IDENTIFY_NS: | |
36c14ed9 | 906 | return nvme_identify(ns, arg, 0); |
b60503ba | 907 | case NVME_IOCTL_IDENTIFY_CTRL: |
36c14ed9 | 908 | return nvme_identify(ns, arg, 1); |
b60503ba | 909 | case NVME_IOCTL_GET_RANGE_TYPE: |
bd38c555 | 910 | return nvme_get_range_type(ns, arg); |
a53295b6 MW |
911 | case NVME_IOCTL_SUBMIT_IO: |
912 | return nvme_submit_io(ns, (void __user *)arg); | |
6ee44cdc MW |
913 | case NVME_IOCTL_DOWNLOAD_FW: |
914 | return nvme_download_firmware(ns, (void __user *)arg); | |
915 | case NVME_IOCTL_ACTIVATE_FW: | |
916 | return nvme_activate_firmware(ns, arg); | |
b60503ba MW |
917 | default: |
918 | return -ENOTTY; | |
919 | } | |
920 | } | |
921 | ||
922 | static const struct block_device_operations nvme_fops = { | |
923 | .owner = THIS_MODULE, | |
924 | .ioctl = nvme_ioctl, | |
925 | }; | |
926 | ||
927 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index, | |
928 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) | |
929 | { | |
930 | struct nvme_ns *ns; | |
931 | struct gendisk *disk; | |
932 | int lbaf; | |
933 | ||
934 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
935 | return NULL; | |
936 | ||
937 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
938 | if (!ns) | |
939 | return NULL; | |
940 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
941 | if (!ns->queue) | |
942 | goto out_free_ns; | |
943 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES | | |
944 | QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD; | |
945 | blk_queue_make_request(ns->queue, nvme_make_request); | |
946 | ns->dev = dev; | |
947 | ns->queue->queuedata = ns; | |
948 | ||
949 | disk = alloc_disk(NVME_MINORS); | |
950 | if (!disk) | |
951 | goto out_free_queue; | |
952 | ns->ns_id = index; | |
953 | ns->disk = disk; | |
954 | lbaf = id->flbas & 0xf; | |
955 | ns->lba_shift = id->lbaf[lbaf].ds; | |
956 | ||
957 | disk->major = nvme_major; | |
958 | disk->minors = NVME_MINORS; | |
959 | disk->first_minor = NVME_MINORS * index; | |
960 | disk->fops = &nvme_fops; | |
961 | disk->private_data = ns; | |
962 | disk->queue = ns->queue; | |
388f037f | 963 | disk->driverfs_dev = &dev->pci_dev->dev; |
b60503ba MW |
964 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index); |
965 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
966 | ||
967 | return ns; | |
968 | ||
969 | out_free_queue: | |
970 | blk_cleanup_queue(ns->queue); | |
971 | out_free_ns: | |
972 | kfree(ns); | |
973 | return NULL; | |
974 | } | |
975 | ||
976 | static void nvme_ns_free(struct nvme_ns *ns) | |
977 | { | |
978 | put_disk(ns->disk); | |
979 | blk_cleanup_queue(ns->queue); | |
980 | kfree(ns); | |
981 | } | |
982 | ||
b3b06812 | 983 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
984 | { |
985 | int status; | |
986 | u32 result; | |
987 | struct nvme_command c; | |
b3b06812 | 988 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba MW |
989 | |
990 | memset(&c, 0, sizeof(c)); | |
991 | c.features.opcode = nvme_admin_get_features; | |
992 | c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES); | |
993 | c.features.dword11 = cpu_to_le32(q_count); | |
994 | ||
995 | status = nvme_submit_admin_cmd(dev, &c, &result); | |
996 | if (status) | |
997 | return -EIO; | |
998 | return min(result & 0xffff, result >> 16) + 1; | |
999 | } | |
1000 | ||
b60503ba MW |
1001 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1002 | { | |
1b23484b | 1003 | int result, cpu, i, nr_queues; |
b60503ba | 1004 | |
1b23484b MW |
1005 | nr_queues = num_online_cpus(); |
1006 | result = set_queue_count(dev, nr_queues); | |
1007 | if (result < 0) | |
1008 | return result; | |
1009 | if (result < nr_queues) | |
1010 | nr_queues = result; | |
b60503ba | 1011 | |
1b23484b MW |
1012 | /* Deregister the admin queue's interrupt */ |
1013 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1014 | ||
1015 | for (i = 0; i < nr_queues; i++) | |
1016 | dev->entry[i].entry = i; | |
1017 | for (;;) { | |
1018 | result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues); | |
1019 | if (result == 0) { | |
1020 | break; | |
1021 | } else if (result > 0) { | |
1022 | nr_queues = result; | |
1023 | continue; | |
1024 | } else { | |
1025 | nr_queues = 1; | |
1026 | break; | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1031 | /* XXX: handle failure here */ | |
1032 | ||
1033 | cpu = cpumask_first(cpu_online_mask); | |
1034 | for (i = 0; i < nr_queues; i++) { | |
1035 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); | |
1036 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1037 | } | |
1038 | ||
1039 | for (i = 0; i < nr_queues; i++) { | |
1040 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, | |
1041 | NVME_Q_DEPTH, i); | |
1042 | if (!dev->queues[i + 1]) | |
1043 | return -ENOMEM; | |
1044 | dev->queue_count++; | |
1045 | } | |
b60503ba MW |
1046 | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | static void nvme_free_queues(struct nvme_dev *dev) | |
1051 | { | |
1052 | int i; | |
1053 | ||
1054 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1055 | nvme_free_queue(dev, i); | |
1056 | } | |
1057 | ||
1058 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1059 | { | |
1060 | int res, nn, i; | |
1061 | struct nvme_ns *ns, *next; | |
51814232 | 1062 | struct nvme_id_ctrl *ctrl; |
b60503ba MW |
1063 | void *id; |
1064 | dma_addr_t dma_addr; | |
1065 | struct nvme_command cid, crt; | |
1066 | ||
1067 | res = nvme_setup_io_queues(dev); | |
1068 | if (res) | |
1069 | return res; | |
1070 | ||
1071 | /* XXX: Switch to a SG list once prp2 works */ | |
1072 | id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, | |
1073 | GFP_KERNEL); | |
1074 | ||
1075 | memset(&cid, 0, sizeof(cid)); | |
1076 | cid.identify.opcode = nvme_admin_identify; | |
1077 | cid.identify.nsid = 0; | |
1078 | cid.identify.prp1 = cpu_to_le64(dma_addr); | |
1079 | cid.identify.cns = cpu_to_le32(1); | |
1080 | ||
1081 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1082 | if (res) { | |
1083 | res = -EIO; | |
1084 | goto out_free; | |
1085 | } | |
1086 | ||
51814232 MW |
1087 | ctrl = id; |
1088 | nn = le32_to_cpup(&ctrl->nn); | |
1089 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1090 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1091 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
b60503ba MW |
1092 | |
1093 | cid.identify.cns = 0; | |
1094 | memset(&crt, 0, sizeof(crt)); | |
1095 | crt.features.opcode = nvme_admin_get_features; | |
1096 | crt.features.prp1 = cpu_to_le64(dma_addr + 4096); | |
1097 | crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); | |
1098 | ||
1099 | for (i = 0; i < nn; i++) { | |
1100 | cid.identify.nsid = cpu_to_le32(i); | |
1101 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1102 | if (res) | |
1103 | continue; | |
1104 | ||
1105 | if (((struct nvme_id_ns *)id)->ncap == 0) | |
1106 | continue; | |
1107 | ||
1108 | crt.features.nsid = cpu_to_le32(i); | |
1109 | res = nvme_submit_admin_cmd(dev, &crt, NULL); | |
1110 | if (res) | |
1111 | continue; | |
1112 | ||
1113 | ns = nvme_alloc_ns(dev, i, id, id + 4096); | |
1114 | if (ns) | |
1115 | list_add_tail(&ns->list, &dev->namespaces); | |
1116 | } | |
1117 | list_for_each_entry(ns, &dev->namespaces, list) | |
1118 | add_disk(ns->disk); | |
1119 | ||
1120 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1121 | return 0; | |
1122 | ||
1123 | out_free: | |
1124 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1125 | list_del(&ns->list); | |
1126 | nvme_ns_free(ns); | |
1127 | } | |
1128 | ||
1129 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1130 | return res; | |
1131 | } | |
1132 | ||
1133 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1134 | { | |
1135 | struct nvme_ns *ns, *next; | |
1136 | ||
1137 | /* TODO: wait all I/O finished or cancel them */ | |
1138 | ||
1139 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1140 | list_del(&ns->list); | |
1141 | del_gendisk(ns->disk); | |
1142 | nvme_ns_free(ns); | |
1143 | } | |
1144 | ||
1145 | nvme_free_queues(dev); | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | /* XXX: Use an ida or something to let remove / add work correctly */ | |
1151 | static void nvme_set_instance(struct nvme_dev *dev) | |
1152 | { | |
1153 | static int instance; | |
1154 | dev->instance = instance++; | |
1155 | } | |
1156 | ||
1157 | static void nvme_release_instance(struct nvme_dev *dev) | |
1158 | { | |
1159 | } | |
1160 | ||
1161 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1162 | const struct pci_device_id *id) | |
1163 | { | |
574e8b95 | 1164 | int bars, result = -ENOMEM; |
b60503ba MW |
1165 | struct nvme_dev *dev; |
1166 | ||
1167 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1168 | if (!dev) | |
1169 | return -ENOMEM; | |
1170 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1171 | GFP_KERNEL); | |
1172 | if (!dev->entry) | |
1173 | goto free; | |
1b23484b MW |
1174 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1175 | GFP_KERNEL); | |
b60503ba MW |
1176 | if (!dev->queues) |
1177 | goto free; | |
1178 | ||
0ee5a7d7 SMM |
1179 | if (pci_enable_device_mem(pdev)) |
1180 | goto free; | |
f64d3365 | 1181 | pci_set_master(pdev); |
574e8b95 MW |
1182 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1183 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1184 | goto disable; | |
0ee5a7d7 | 1185 | |
b60503ba MW |
1186 | INIT_LIST_HEAD(&dev->namespaces); |
1187 | dev->pci_dev = pdev; | |
1188 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1189 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1190 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1191 | nvme_set_instance(dev); |
53c9577e | 1192 | dev->entry[0].vector = pdev->irq; |
b60503ba MW |
1193 | |
1194 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1195 | if (!dev->bar) { | |
1196 | result = -ENOMEM; | |
574e8b95 | 1197 | goto disable_msix; |
b60503ba MW |
1198 | } |
1199 | ||
1200 | result = nvme_configure_admin_queue(dev); | |
1201 | if (result) | |
1202 | goto unmap; | |
1203 | dev->queue_count++; | |
1204 | ||
1205 | result = nvme_dev_add(dev); | |
1206 | if (result) | |
1207 | goto delete; | |
1208 | return 0; | |
1209 | ||
1210 | delete: | |
1211 | nvme_free_queues(dev); | |
1212 | unmap: | |
1213 | iounmap(dev->bar); | |
574e8b95 | 1214 | disable_msix: |
b60503ba MW |
1215 | pci_disable_msix(pdev); |
1216 | nvme_release_instance(dev); | |
574e8b95 | 1217 | disable: |
0ee5a7d7 | 1218 | pci_disable_device(pdev); |
574e8b95 | 1219 | pci_release_regions(pdev); |
b60503ba MW |
1220 | free: |
1221 | kfree(dev->queues); | |
1222 | kfree(dev->entry); | |
1223 | kfree(dev); | |
1224 | return result; | |
1225 | } | |
1226 | ||
1227 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1228 | { | |
1229 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1230 | nvme_dev_remove(dev); | |
1231 | pci_disable_msix(pdev); | |
1232 | iounmap(dev->bar); | |
1233 | nvme_release_instance(dev); | |
0ee5a7d7 | 1234 | pci_disable_device(pdev); |
574e8b95 | 1235 | pci_release_regions(pdev); |
b60503ba MW |
1236 | kfree(dev->queues); |
1237 | kfree(dev->entry); | |
1238 | kfree(dev); | |
1239 | } | |
1240 | ||
1241 | /* These functions are yet to be implemented */ | |
1242 | #define nvme_error_detected NULL | |
1243 | #define nvme_dump_registers NULL | |
1244 | #define nvme_link_reset NULL | |
1245 | #define nvme_slot_reset NULL | |
1246 | #define nvme_error_resume NULL | |
1247 | #define nvme_suspend NULL | |
1248 | #define nvme_resume NULL | |
1249 | ||
1250 | static struct pci_error_handlers nvme_err_handler = { | |
1251 | .error_detected = nvme_error_detected, | |
1252 | .mmio_enabled = nvme_dump_registers, | |
1253 | .link_reset = nvme_link_reset, | |
1254 | .slot_reset = nvme_slot_reset, | |
1255 | .resume = nvme_error_resume, | |
1256 | }; | |
1257 | ||
1258 | /* Move to pci_ids.h later */ | |
1259 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1260 | ||
1261 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1262 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1263 | { 0, } | |
1264 | }; | |
1265 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1266 | ||
1267 | static struct pci_driver nvme_driver = { | |
1268 | .name = "nvme", | |
1269 | .id_table = nvme_id_table, | |
1270 | .probe = nvme_probe, | |
1271 | .remove = __devexit_p(nvme_remove), | |
1272 | .suspend = nvme_suspend, | |
1273 | .resume = nvme_resume, | |
1274 | .err_handler = &nvme_err_handler, | |
1275 | }; | |
1276 | ||
1277 | static int __init nvme_init(void) | |
1278 | { | |
1279 | int result; | |
1280 | ||
1281 | nvme_major = register_blkdev(nvme_major, "nvme"); | |
1282 | if (nvme_major <= 0) | |
1283 | return -EBUSY; | |
1284 | ||
1285 | result = pci_register_driver(&nvme_driver); | |
1286 | if (!result) | |
1287 | return 0; | |
1288 | ||
1289 | unregister_blkdev(nvme_major, "nvme"); | |
1290 | return result; | |
1291 | } | |
1292 | ||
1293 | static void __exit nvme_exit(void) | |
1294 | { | |
1295 | pci_unregister_driver(&nvme_driver); | |
1296 | unregister_blkdev(nvme_major, "nvme"); | |
1297 | } | |
1298 | ||
1299 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1300 | MODULE_LICENSE("GPL"); | |
db5d0c19 | 1301 | MODULE_VERSION("0.2"); |
b60503ba MW |
1302 | module_init(nvme_init); |
1303 | module_exit(nvme_exit); |