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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
21 | #include <linux/blkdev.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/fs.h> | |
24 | #include <linux/genhd.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/interrupt.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/kdev_t.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/mm.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/moduleparam.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/sched.h> | |
35 | #include <linux/slab.h> | |
36 | #include <linux/types.h> | |
37 | #include <linux/version.h> | |
38 | ||
39 | #define NVME_Q_DEPTH 1024 | |
40 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
41 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
42 | #define NVME_MINORS 64 | |
43 | ||
44 | static int nvme_major; | |
45 | module_param(nvme_major, int, 0); | |
46 | ||
47 | /* | |
48 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
49 | */ | |
50 | struct nvme_dev { | |
b60503ba MW |
51 | struct nvme_queue **queues; |
52 | u32 __iomem *dbs; | |
53 | struct pci_dev *pci_dev; | |
54 | int instance; | |
55 | int queue_count; | |
56 | u32 ctrl_config; | |
57 | struct msix_entry *entry; | |
58 | struct nvme_bar __iomem *bar; | |
59 | struct list_head namespaces; | |
51814232 MW |
60 | char serial[20]; |
61 | char model[40]; | |
62 | char firmware_rev[8]; | |
b60503ba MW |
63 | }; |
64 | ||
65 | /* | |
66 | * An NVM Express namespace is equivalent to a SCSI LUN | |
67 | */ | |
68 | struct nvme_ns { | |
69 | struct list_head list; | |
70 | ||
71 | struct nvme_dev *dev; | |
72 | struct request_queue *queue; | |
73 | struct gendisk *disk; | |
74 | ||
75 | int ns_id; | |
76 | int lba_shift; | |
77 | }; | |
78 | ||
79 | /* | |
80 | * An NVM Express queue. Each device has at least two (one for admin | |
81 | * commands and one for I/O commands). | |
82 | */ | |
83 | struct nvme_queue { | |
84 | struct device *q_dmadev; | |
85 | spinlock_t q_lock; | |
86 | struct nvme_command *sq_cmds; | |
87 | volatile struct nvme_completion *cqes; | |
88 | dma_addr_t sq_dma_addr; | |
89 | dma_addr_t cq_dma_addr; | |
90 | wait_queue_head_t sq_full; | |
91 | struct bio_list sq_cong; | |
92 | u32 __iomem *q_db; | |
93 | u16 q_depth; | |
94 | u16 cq_vector; | |
95 | u16 sq_head; | |
96 | u16 sq_tail; | |
97 | u16 cq_head; | |
82123460 | 98 | u16 cq_phase; |
b60503ba MW |
99 | unsigned long cmdid_data[]; |
100 | }; | |
101 | ||
102 | /* | |
103 | * Check we didin't inadvertently grow the command struct | |
104 | */ | |
105 | static inline void _nvme_check_size(void) | |
106 | { | |
107 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
108 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
109 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
110 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
111 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
112 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
113 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
114 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
115 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
116 | } | |
117 | ||
118 | /** | |
119 | * alloc_cmdid - Allocate a Command ID | |
120 | * @param nvmeq The queue that will be used for this command | |
121 | * @param ctx A pointer that will be passed to the handler | |
122 | * @param handler The ID of the handler to call | |
123 | * | |
124 | * Allocate a Command ID for a queue. The data passed in will | |
125 | * be passed to the completion handler. This is implemented by using | |
126 | * the bottom two bits of the ctx pointer to store the handler ID. | |
127 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
128 | * We can change this if it becomes a problem. | |
129 | */ | |
130 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, int handler) | |
131 | { | |
132 | int depth = nvmeq->q_depth; | |
133 | unsigned long data = (unsigned long)ctx | handler; | |
134 | int cmdid; | |
135 | ||
136 | BUG_ON((unsigned long)ctx & 3); | |
137 | ||
138 | do { | |
139 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
140 | if (cmdid >= depth) | |
141 | return -EBUSY; | |
142 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
143 | ||
144 | nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(depth)] = data; | |
145 | return cmdid; | |
146 | } | |
147 | ||
148 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
149 | int handler) | |
150 | { | |
151 | int cmdid; | |
152 | wait_event_killable(nvmeq->sq_full, | |
153 | (cmdid = alloc_cmdid(nvmeq, ctx, handler)) >= 0); | |
154 | return (cmdid < 0) ? -EINTR : cmdid; | |
155 | } | |
156 | ||
157 | /* If you need more than four handlers, you'll need to change how | |
158 | * alloc_cmdid and nvme_process_cq work | |
159 | */ | |
160 | enum { | |
161 | sync_completion_id = 0, | |
162 | bio_completion_id, | |
163 | }; | |
164 | ||
165 | static unsigned long free_cmdid(struct nvme_queue *nvmeq, int cmdid) | |
166 | { | |
167 | unsigned long data; | |
168 | ||
169 | data = nvmeq->cmdid_data[cmdid + BITS_TO_LONGS(nvmeq->q_depth)]; | |
170 | clear_bit(cmdid, nvmeq->cmdid_data); | |
171 | wake_up(&nvmeq->sq_full); | |
172 | return data; | |
173 | } | |
174 | ||
175 | static struct nvme_queue *get_nvmeq(struct nvme_ns *ns) | |
176 | { | |
1b23484b MW |
177 | int qid, cpu = get_cpu(); |
178 | if (cpu < ns->dev->queue_count) | |
179 | qid = cpu + 1; | |
180 | else | |
181 | qid = (cpu % rounddown_pow_of_two(ns->dev->queue_count)) + 1; | |
182 | return ns->dev->queues[qid]; | |
b60503ba MW |
183 | } |
184 | ||
185 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
186 | { | |
1b23484b | 187 | put_cpu(); |
b60503ba MW |
188 | } |
189 | ||
190 | /** | |
191 | * nvme_submit_cmd: Copy a command into a queue and ring the doorbell | |
192 | * @nvmeq: The queue to use | |
193 | * @cmd: The command to send | |
194 | * | |
195 | * Safe to use from interrupt context | |
196 | */ | |
197 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
198 | { | |
199 | unsigned long flags; | |
200 | u16 tail; | |
201 | /* XXX: Need to check tail isn't going to overrun head */ | |
202 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
203 | tail = nvmeq->sq_tail; | |
204 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
205 | writel(tail, nvmeq->q_db); | |
206 | if (++tail == nvmeq->q_depth) | |
207 | tail = 0; | |
208 | nvmeq->sq_tail = tail; | |
209 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | struct nvme_req_info { | |
215 | struct bio *bio; | |
216 | int nents; | |
217 | struct scatterlist sg[0]; | |
218 | }; | |
219 | ||
220 | /* XXX: use a mempool */ | |
221 | static struct nvme_req_info *alloc_info(unsigned nseg, gfp_t gfp) | |
222 | { | |
223 | return kmalloc(sizeof(struct nvme_req_info) + | |
224 | sizeof(struct scatterlist) * nseg, gfp); | |
225 | } | |
226 | ||
227 | static void free_info(struct nvme_req_info *info) | |
228 | { | |
229 | kfree(info); | |
230 | } | |
231 | ||
232 | static void bio_completion(struct nvme_queue *nvmeq, void *ctx, | |
233 | struct nvme_completion *cqe) | |
234 | { | |
235 | struct nvme_req_info *info = ctx; | |
236 | struct bio *bio = info->bio; | |
237 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
238 | ||
239 | dma_unmap_sg(nvmeq->q_dmadev, info->sg, info->nents, | |
240 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
241 | free_info(info); | |
242 | bio_endio(bio, status ? -EIO : 0); | |
243 | } | |
244 | ||
ff22b54f MW |
245 | /* length is in bytes */ |
246 | static void nvme_setup_prps(struct nvme_common_command *cmd, | |
247 | struct scatterlist *sg, int length) | |
248 | { | |
249 | int dma_len = sg_dma_len(sg); | |
250 | u64 dma_addr = sg_dma_address(sg); | |
251 | int offset = offset_in_page(dma_addr); | |
252 | ||
253 | cmd->prp1 = cpu_to_le64(dma_addr); | |
254 | length -= (PAGE_SIZE - offset); | |
255 | if (length <= 0) | |
256 | return; | |
257 | ||
258 | dma_len -= (PAGE_SIZE - offset); | |
259 | if (dma_len) { | |
260 | dma_addr += (PAGE_SIZE - offset); | |
261 | } else { | |
262 | sg = sg_next(sg); | |
263 | dma_addr = sg_dma_address(sg); | |
264 | dma_len = sg_dma_len(sg); | |
265 | } | |
266 | ||
267 | if (length <= PAGE_SIZE) { | |
268 | cmd->prp2 = cpu_to_le64(dma_addr); | |
269 | return; | |
270 | } | |
271 | ||
272 | /* XXX: support PRP lists */ | |
273 | } | |
274 | ||
b60503ba MW |
275 | static int nvme_map_bio(struct device *dev, struct nvme_req_info *info, |
276 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) | |
277 | { | |
278 | struct bio_vec *bvec; | |
279 | struct scatterlist *sg = info->sg; | |
280 | int i, nsegs; | |
281 | ||
282 | sg_init_table(sg, psegs); | |
283 | bio_for_each_segment(bvec, bio, i) { | |
284 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset); | |
285 | /* XXX: handle non-mergable here */ | |
286 | nsegs++; | |
287 | } | |
288 | info->nents = nsegs; | |
289 | ||
290 | return dma_map_sg(dev, info->sg, info->nents, dma_dir); | |
291 | } | |
292 | ||
293 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
294 | struct bio *bio) | |
295 | { | |
ff22b54f | 296 | struct nvme_command *cmnd; |
b60503ba MW |
297 | struct nvme_req_info *info; |
298 | enum dma_data_direction dma_dir; | |
299 | int cmdid; | |
300 | u16 control; | |
301 | u32 dsmgmt; | |
302 | unsigned long flags; | |
303 | int psegs = bio_phys_segments(ns->queue, bio); | |
304 | ||
305 | info = alloc_info(psegs, GFP_NOIO); | |
306 | if (!info) | |
307 | goto congestion; | |
308 | info->bio = bio; | |
309 | ||
310 | cmdid = alloc_cmdid(nvmeq, info, bio_completion_id); | |
311 | if (unlikely(cmdid < 0)) | |
312 | goto free_info; | |
313 | ||
314 | control = 0; | |
315 | if (bio->bi_rw & REQ_FUA) | |
316 | control |= NVME_RW_FUA; | |
317 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
318 | control |= NVME_RW_LR; | |
319 | ||
320 | dsmgmt = 0; | |
321 | if (bio->bi_rw & REQ_RAHEAD) | |
322 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
323 | ||
324 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
ff22b54f | 325 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 326 | |
b8deb62c | 327 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 328 | if (bio_data_dir(bio)) { |
ff22b54f | 329 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
330 | dma_dir = DMA_TO_DEVICE; |
331 | } else { | |
ff22b54f | 332 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
333 | dma_dir = DMA_FROM_DEVICE; |
334 | } | |
335 | ||
336 | nvme_map_bio(nvmeq->q_dmadev, info, bio, dma_dir, psegs); | |
337 | ||
ff22b54f MW |
338 | cmnd->rw.flags = 1; |
339 | cmnd->rw.command_id = cmdid; | |
340 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
341 | nvme_setup_prps(&cmnd->common, info->sg, bio->bi_size); | |
342 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); | |
343 | cmnd->rw.length = cpu_to_le16((bio->bi_size >> ns->lba_shift) - 1); | |
344 | cmnd->rw.control = cpu_to_le16(control); | |
345 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba MW |
346 | |
347 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
348 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
349 | nvmeq->sq_tail = 0; | |
350 | ||
351 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
352 | ||
353 | return 0; | |
354 | ||
355 | free_info: | |
356 | free_info(info); | |
357 | congestion: | |
358 | return -EBUSY; | |
359 | } | |
360 | ||
361 | /* | |
362 | * NB: return value of non-zero would mean that we were a stacking driver. | |
363 | * make_request must always succeed. | |
364 | */ | |
365 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
366 | { | |
367 | struct nvme_ns *ns = q->queuedata; | |
368 | struct nvme_queue *nvmeq = get_nvmeq(ns); | |
369 | ||
370 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
371 | blk_set_queue_congested(q, rw_is_sync(bio->bi_rw)); | |
372 | bio_list_add(&nvmeq->sq_cong, bio); | |
373 | } | |
374 | put_nvmeq(nvmeq); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | struct sync_cmd_info { | |
380 | struct task_struct *task; | |
381 | u32 result; | |
382 | int status; | |
383 | }; | |
384 | ||
385 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, | |
386 | struct nvme_completion *cqe) | |
387 | { | |
388 | struct sync_cmd_info *cmdinfo = ctx; | |
389 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
390 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
391 | wake_up_process(cmdinfo->task); | |
392 | } | |
393 | ||
394 | typedef void (*completion_fn)(struct nvme_queue *, void *, | |
395 | struct nvme_completion *); | |
396 | ||
397 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) | |
398 | { | |
82123460 | 399 | u16 head, phase; |
b60503ba MW |
400 | |
401 | static const completion_fn completions[4] = { | |
402 | [sync_completion_id] = sync_completion, | |
403 | [bio_completion_id] = bio_completion, | |
404 | }; | |
405 | ||
406 | head = nvmeq->cq_head; | |
82123460 | 407 | phase = nvmeq->cq_phase; |
b60503ba MW |
408 | |
409 | for (;;) { | |
410 | unsigned long data; | |
411 | void *ptr; | |
412 | unsigned char handler; | |
413 | struct nvme_completion cqe = nvmeq->cqes[head]; | |
82123460 | 414 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
415 | break; |
416 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
417 | if (++head == nvmeq->q_depth) { | |
418 | head = 0; | |
82123460 | 419 | phase = !phase; |
b60503ba MW |
420 | } |
421 | ||
422 | data = free_cmdid(nvmeq, cqe.command_id); | |
423 | handler = data & 3; | |
424 | ptr = (void *)(data & ~3UL); | |
425 | completions[handler](nvmeq, ptr, &cqe); | |
426 | } | |
427 | ||
428 | /* If the controller ignores the cq head doorbell and continuously | |
429 | * writes to the queue, it is theoretically possible to wrap around | |
430 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
431 | * requires that 0.1% of your interrupts are handled, so this isn't | |
432 | * a big problem. | |
433 | */ | |
82123460 | 434 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
435 | return IRQ_NONE; |
436 | ||
437 | writel(head, nvmeq->q_db + 1); | |
438 | nvmeq->cq_head = head; | |
82123460 | 439 | nvmeq->cq_phase = phase; |
b60503ba MW |
440 | |
441 | return IRQ_HANDLED; | |
442 | } | |
443 | ||
444 | static irqreturn_t nvme_irq(int irq, void *data) | |
445 | { | |
446 | return nvme_process_cq(data); | |
447 | } | |
448 | ||
449 | /* | |
450 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
451 | * if the result is positive, it's an NVM Express status code | |
452 | */ | |
453 | static int nvme_submit_sync_cmd(struct nvme_queue *q, struct nvme_command *cmd, | |
454 | u32 *result) | |
455 | { | |
456 | int cmdid; | |
457 | struct sync_cmd_info cmdinfo; | |
458 | ||
459 | cmdinfo.task = current; | |
460 | cmdinfo.status = -EINTR; | |
461 | ||
462 | cmdid = alloc_cmdid_killable(q, &cmdinfo, sync_completion_id); | |
463 | if (cmdid < 0) | |
464 | return cmdid; | |
465 | cmd->common.command_id = cmdid; | |
466 | ||
467 | set_current_state(TASK_UNINTERRUPTIBLE); | |
468 | nvme_submit_cmd(q, cmd); | |
469 | schedule(); | |
470 | ||
471 | if (result) | |
472 | *result = cmdinfo.result; | |
473 | ||
474 | return cmdinfo.status; | |
475 | } | |
476 | ||
477 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
478 | u32 *result) | |
479 | { | |
480 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result); | |
481 | } | |
482 | ||
483 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
484 | { | |
485 | int status; | |
486 | struct nvme_command c; | |
487 | ||
488 | memset(&c, 0, sizeof(c)); | |
489 | c.delete_queue.opcode = opcode; | |
490 | c.delete_queue.qid = cpu_to_le16(id); | |
491 | ||
492 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
493 | if (status) | |
494 | return -EIO; | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
499 | struct nvme_queue *nvmeq) | |
500 | { | |
501 | int status; | |
502 | struct nvme_command c; | |
503 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
504 | ||
505 | memset(&c, 0, sizeof(c)); | |
506 | c.create_cq.opcode = nvme_admin_create_cq; | |
507 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
508 | c.create_cq.cqid = cpu_to_le16(qid); | |
509 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
510 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
511 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
512 | ||
513 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
514 | if (status) | |
515 | return -EIO; | |
516 | return 0; | |
517 | } | |
518 | ||
519 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
520 | struct nvme_queue *nvmeq) | |
521 | { | |
522 | int status; | |
523 | struct nvme_command c; | |
524 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
525 | ||
526 | memset(&c, 0, sizeof(c)); | |
527 | c.create_sq.opcode = nvme_admin_create_sq; | |
528 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
529 | c.create_sq.sqid = cpu_to_le16(qid); | |
530 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
531 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
532 | c.create_sq.cqid = cpu_to_le16(qid); | |
533 | ||
534 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
535 | if (status) | |
536 | return -EIO; | |
537 | return 0; | |
538 | } | |
539 | ||
540 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
541 | { | |
542 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
543 | } | |
544 | ||
545 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
546 | { | |
547 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
548 | } | |
549 | ||
550 | static void nvme_free_queue(struct nvme_dev *dev, int qid) | |
551 | { | |
552 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
553 | ||
554 | free_irq(dev->entry[nvmeq->cq_vector].vector, nvmeq); | |
555 | ||
556 | /* Don't tell the adapter to delete the admin queue */ | |
557 | if (qid) { | |
558 | adapter_delete_sq(dev, qid); | |
559 | adapter_delete_cq(dev, qid); | |
560 | } | |
561 | ||
562 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
563 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
564 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
565 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
566 | kfree(nvmeq); | |
567 | } | |
568 | ||
569 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
570 | int depth, int vector) | |
571 | { | |
572 | struct device *dmadev = &dev->pci_dev->dev; | |
573 | unsigned extra = (depth + BITS_TO_LONGS(depth)) * sizeof(long); | |
574 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); | |
575 | if (!nvmeq) | |
576 | return NULL; | |
577 | ||
578 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
579 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
580 | if (!nvmeq->cqes) | |
581 | goto free_nvmeq; | |
582 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
583 | ||
584 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
585 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
586 | if (!nvmeq->sq_cmds) | |
587 | goto free_cqdma; | |
588 | ||
589 | nvmeq->q_dmadev = dmadev; | |
590 | spin_lock_init(&nvmeq->q_lock); | |
591 | nvmeq->cq_head = 0; | |
82123460 | 592 | nvmeq->cq_phase = 1; |
b60503ba MW |
593 | init_waitqueue_head(&nvmeq->sq_full); |
594 | bio_list_init(&nvmeq->sq_cong); | |
595 | nvmeq->q_db = &dev->dbs[qid * 2]; | |
596 | nvmeq->q_depth = depth; | |
597 | nvmeq->cq_vector = vector; | |
598 | ||
599 | return nvmeq; | |
600 | ||
601 | free_cqdma: | |
602 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
603 | nvmeq->cq_dma_addr); | |
604 | free_nvmeq: | |
605 | kfree(nvmeq); | |
606 | return NULL; | |
607 | } | |
608 | ||
3001082c MW |
609 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
610 | const char *name) | |
611 | { | |
612 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, | |
613 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
614 | } | |
615 | ||
b60503ba MW |
616 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
617 | int qid, int cq_size, int vector) | |
618 | { | |
619 | int result; | |
620 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
621 | ||
3f85d50b MW |
622 | if (!nvmeq) |
623 | return NULL; | |
624 | ||
b60503ba MW |
625 | result = adapter_alloc_cq(dev, qid, nvmeq); |
626 | if (result < 0) | |
627 | goto free_nvmeq; | |
628 | ||
629 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
630 | if (result < 0) | |
631 | goto release_cq; | |
632 | ||
3001082c | 633 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
634 | if (result < 0) |
635 | goto release_sq; | |
636 | ||
637 | return nvmeq; | |
638 | ||
639 | release_sq: | |
640 | adapter_delete_sq(dev, qid); | |
641 | release_cq: | |
642 | adapter_delete_cq(dev, qid); | |
643 | free_nvmeq: | |
644 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
645 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
646 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
647 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
648 | kfree(nvmeq); | |
649 | return NULL; | |
650 | } | |
651 | ||
652 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
653 | { | |
654 | int result; | |
655 | u32 aqa; | |
656 | struct nvme_queue *nvmeq; | |
657 | ||
658 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
659 | ||
660 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
661 | if (!nvmeq) |
662 | return -ENOMEM; | |
b60503ba MW |
663 | |
664 | aqa = nvmeq->q_depth - 1; | |
665 | aqa |= aqa << 16; | |
666 | ||
667 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
668 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
669 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
670 | ||
671 | writel(aqa, &dev->bar->aqa); | |
672 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
673 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
674 | writel(dev->ctrl_config, &dev->bar->cc); | |
675 | ||
676 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { | |
677 | msleep(100); | |
678 | if (fatal_signal_pending(current)) | |
679 | return -EINTR; | |
680 | } | |
681 | ||
3001082c | 682 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
683 | dev->queues[0] = nvmeq; |
684 | return result; | |
685 | } | |
686 | ||
7fc3cdab MW |
687 | static int nvme_map_user_pages(struct nvme_dev *dev, int write, |
688 | unsigned long addr, unsigned length, | |
689 | struct scatterlist **sgp) | |
b60503ba | 690 | { |
36c14ed9 | 691 | int i, err, count, nents, offset; |
7fc3cdab MW |
692 | struct scatterlist *sg; |
693 | struct page **pages; | |
36c14ed9 MW |
694 | |
695 | if (addr & 3) | |
696 | return -EINVAL; | |
7fc3cdab MW |
697 | if (!length) |
698 | return -EINVAL; | |
699 | ||
36c14ed9 | 700 | offset = offset_in_page(addr); |
7fc3cdab MW |
701 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
702 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
703 | |
704 | err = get_user_pages_fast(addr, count, 1, pages); | |
705 | if (err < count) { | |
706 | count = err; | |
707 | err = -EFAULT; | |
708 | goto put_pages; | |
709 | } | |
7fc3cdab MW |
710 | |
711 | sg = kcalloc(count, sizeof(*sg), GFP_KERNEL); | |
36c14ed9 | 712 | sg_init_table(sg, count); |
ff22b54f | 713 | sg_set_page(&sg[0], pages[0], PAGE_SIZE - offset, offset); |
7fc3cdab MW |
714 | length -= (PAGE_SIZE - offset); |
715 | for (i = 1; i < count; i++) { | |
716 | sg_set_page(&sg[i], pages[i], min_t(int, length, PAGE_SIZE), 0); | |
717 | length -= PAGE_SIZE; | |
718 | } | |
719 | ||
720 | err = -ENOMEM; | |
721 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
722 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 MW |
723 | if (!nents) |
724 | goto put_pages; | |
b60503ba | 725 | |
7fc3cdab MW |
726 | kfree(pages); |
727 | *sgp = sg; | |
728 | return nents; | |
b60503ba | 729 | |
7fc3cdab MW |
730 | put_pages: |
731 | for (i = 0; i < count; i++) | |
732 | put_page(pages[i]); | |
733 | kfree(pages); | |
734 | return err; | |
735 | } | |
b60503ba | 736 | |
7fc3cdab MW |
737 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
738 | unsigned long addr, int length, | |
739 | struct scatterlist *sg, int nents) | |
740 | { | |
741 | int i, count; | |
b60503ba | 742 | |
7fc3cdab | 743 | count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE); |
36c14ed9 | 744 | dma_unmap_sg(&dev->pci_dev->dev, sg, nents, DMA_FROM_DEVICE); |
7fc3cdab | 745 | |
36c14ed9 | 746 | for (i = 0; i < count; i++) |
7fc3cdab MW |
747 | put_page(sg_page(&sg[i])); |
748 | } | |
b60503ba | 749 | |
7fc3cdab MW |
750 | static int nvme_submit_user_admin_command(struct nvme_dev *dev, |
751 | unsigned long addr, unsigned length, | |
752 | struct nvme_command *cmd) | |
753 | { | |
754 | int err, nents; | |
755 | struct scatterlist *sg; | |
756 | ||
757 | nents = nvme_map_user_pages(dev, 0, addr, length, &sg); | |
758 | if (nents < 0) | |
759 | return nents; | |
760 | nvme_setup_prps(&cmd->common, sg, length); | |
761 | err = nvme_submit_admin_cmd(dev, cmd, NULL); | |
762 | nvme_unmap_user_pages(dev, 0, addr, length, sg, nents); | |
763 | return err ? -EIO : 0; | |
b60503ba MW |
764 | } |
765 | ||
bd38c555 | 766 | static int nvme_identify(struct nvme_ns *ns, unsigned long addr, int cns) |
b60503ba | 767 | { |
b60503ba | 768 | struct nvme_command c; |
b60503ba | 769 | |
bd38c555 MW |
770 | memset(&c, 0, sizeof(c)); |
771 | c.identify.opcode = nvme_admin_identify; | |
772 | c.identify.nsid = cns ? 0 : cpu_to_le32(ns->ns_id); | |
773 | c.identify.cns = cpu_to_le32(cns); | |
774 | ||
775 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); | |
776 | } | |
777 | ||
778 | static int nvme_get_range_type(struct nvme_ns *ns, unsigned long addr) | |
779 | { | |
780 | struct nvme_command c; | |
b60503ba MW |
781 | |
782 | memset(&c, 0, sizeof(c)); | |
783 | c.features.opcode = nvme_admin_get_features; | |
784 | c.features.nsid = cpu_to_le32(ns->ns_id); | |
b60503ba MW |
785 | c.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); |
786 | ||
bd38c555 | 787 | return nvme_submit_user_admin_command(ns->dev, addr, 4096, &c); |
b60503ba MW |
788 | } |
789 | ||
a53295b6 MW |
790 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
791 | { | |
792 | struct nvme_dev *dev = ns->dev; | |
793 | struct nvme_queue *nvmeq; | |
794 | struct nvme_user_io io; | |
795 | struct nvme_command c; | |
796 | unsigned length; | |
797 | u32 result; | |
798 | int nents, status; | |
799 | struct scatterlist *sg; | |
800 | ||
801 | if (copy_from_user(&io, uio, sizeof(io))) | |
802 | return -EFAULT; | |
803 | length = io.nblocks << io.block_shift; | |
804 | nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length, &sg); | |
805 | if (nents < 0) | |
806 | return nents; | |
807 | ||
808 | memset(&c, 0, sizeof(c)); | |
809 | c.rw.opcode = io.opcode; | |
810 | c.rw.flags = io.flags; | |
811 | c.rw.nsid = cpu_to_le32(io.nsid); | |
812 | c.rw.slba = cpu_to_le64(io.slba); | |
813 | c.rw.length = cpu_to_le16(io.nblocks - 1); | |
814 | c.rw.control = cpu_to_le16(io.control); | |
815 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
816 | c.rw.reftag = cpu_to_le32(io.reftag); /* XXX: endian? */ | |
817 | c.rw.apptag = cpu_to_le16(io.apptag); | |
818 | c.rw.appmask = cpu_to_le16(io.appmask); | |
819 | /* XXX: metadata */ | |
820 | nvme_setup_prps(&c.common, sg, length); | |
821 | ||
822 | nvmeq = get_nvmeq(ns); | |
823 | status = nvme_submit_sync_cmd(nvmeq, &c, &result); | |
824 | put_nvmeq(nvmeq); | |
825 | ||
826 | nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg, nents); | |
827 | put_user(result, &uio->result); | |
828 | return status; | |
829 | } | |
830 | ||
b60503ba MW |
831 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
832 | unsigned long arg) | |
833 | { | |
834 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
835 | ||
836 | switch (cmd) { | |
837 | case NVME_IOCTL_IDENTIFY_NS: | |
36c14ed9 | 838 | return nvme_identify(ns, arg, 0); |
b60503ba | 839 | case NVME_IOCTL_IDENTIFY_CTRL: |
36c14ed9 | 840 | return nvme_identify(ns, arg, 1); |
b60503ba | 841 | case NVME_IOCTL_GET_RANGE_TYPE: |
bd38c555 | 842 | return nvme_get_range_type(ns, arg); |
a53295b6 MW |
843 | case NVME_IOCTL_SUBMIT_IO: |
844 | return nvme_submit_io(ns, (void __user *)arg); | |
b60503ba MW |
845 | default: |
846 | return -ENOTTY; | |
847 | } | |
848 | } | |
849 | ||
850 | static const struct block_device_operations nvme_fops = { | |
851 | .owner = THIS_MODULE, | |
852 | .ioctl = nvme_ioctl, | |
853 | }; | |
854 | ||
855 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int index, | |
856 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) | |
857 | { | |
858 | struct nvme_ns *ns; | |
859 | struct gendisk *disk; | |
860 | int lbaf; | |
861 | ||
862 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
863 | return NULL; | |
864 | ||
865 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
866 | if (!ns) | |
867 | return NULL; | |
868 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
869 | if (!ns->queue) | |
870 | goto out_free_ns; | |
871 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES | | |
872 | QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD; | |
873 | blk_queue_make_request(ns->queue, nvme_make_request); | |
874 | ns->dev = dev; | |
875 | ns->queue->queuedata = ns; | |
876 | ||
877 | disk = alloc_disk(NVME_MINORS); | |
878 | if (!disk) | |
879 | goto out_free_queue; | |
880 | ns->ns_id = index; | |
881 | ns->disk = disk; | |
882 | lbaf = id->flbas & 0xf; | |
883 | ns->lba_shift = id->lbaf[lbaf].ds; | |
884 | ||
885 | disk->major = nvme_major; | |
886 | disk->minors = NVME_MINORS; | |
887 | disk->first_minor = NVME_MINORS * index; | |
888 | disk->fops = &nvme_fops; | |
889 | disk->private_data = ns; | |
890 | disk->queue = ns->queue; | |
891 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, index); | |
892 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
893 | ||
894 | return ns; | |
895 | ||
896 | out_free_queue: | |
897 | blk_cleanup_queue(ns->queue); | |
898 | out_free_ns: | |
899 | kfree(ns); | |
900 | return NULL; | |
901 | } | |
902 | ||
903 | static void nvme_ns_free(struct nvme_ns *ns) | |
904 | { | |
905 | put_disk(ns->disk); | |
906 | blk_cleanup_queue(ns->queue); | |
907 | kfree(ns); | |
908 | } | |
909 | ||
b3b06812 | 910 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
911 | { |
912 | int status; | |
913 | u32 result; | |
914 | struct nvme_command c; | |
b3b06812 | 915 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba MW |
916 | |
917 | memset(&c, 0, sizeof(c)); | |
918 | c.features.opcode = nvme_admin_get_features; | |
919 | c.features.fid = cpu_to_le32(NVME_FEAT_NUM_QUEUES); | |
920 | c.features.dword11 = cpu_to_le32(q_count); | |
921 | ||
922 | status = nvme_submit_admin_cmd(dev, &c, &result); | |
923 | if (status) | |
924 | return -EIO; | |
925 | return min(result & 0xffff, result >> 16) + 1; | |
926 | } | |
927 | ||
b60503ba MW |
928 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
929 | { | |
1b23484b | 930 | int result, cpu, i, nr_queues; |
b60503ba | 931 | |
1b23484b MW |
932 | nr_queues = num_online_cpus(); |
933 | result = set_queue_count(dev, nr_queues); | |
934 | if (result < 0) | |
935 | return result; | |
936 | if (result < nr_queues) | |
937 | nr_queues = result; | |
b60503ba | 938 | |
1b23484b MW |
939 | /* Deregister the admin queue's interrupt */ |
940 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
941 | ||
942 | for (i = 0; i < nr_queues; i++) | |
943 | dev->entry[i].entry = i; | |
944 | for (;;) { | |
945 | result = pci_enable_msix(dev->pci_dev, dev->entry, nr_queues); | |
946 | if (result == 0) { | |
947 | break; | |
948 | } else if (result > 0) { | |
949 | nr_queues = result; | |
950 | continue; | |
951 | } else { | |
952 | nr_queues = 1; | |
953 | break; | |
954 | } | |
955 | } | |
956 | ||
957 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
958 | /* XXX: handle failure here */ | |
959 | ||
960 | cpu = cpumask_first(cpu_online_mask); | |
961 | for (i = 0; i < nr_queues; i++) { | |
962 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); | |
963 | cpu = cpumask_next(cpu, cpu_online_mask); | |
964 | } | |
965 | ||
966 | for (i = 0; i < nr_queues; i++) { | |
967 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, | |
968 | NVME_Q_DEPTH, i); | |
969 | if (!dev->queues[i + 1]) | |
970 | return -ENOMEM; | |
971 | dev->queue_count++; | |
972 | } | |
b60503ba MW |
973 | |
974 | return 0; | |
975 | } | |
976 | ||
977 | static void nvme_free_queues(struct nvme_dev *dev) | |
978 | { | |
979 | int i; | |
980 | ||
981 | for (i = dev->queue_count - 1; i >= 0; i--) | |
982 | nvme_free_queue(dev, i); | |
983 | } | |
984 | ||
985 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
986 | { | |
987 | int res, nn, i; | |
988 | struct nvme_ns *ns, *next; | |
51814232 | 989 | struct nvme_id_ctrl *ctrl; |
b60503ba MW |
990 | void *id; |
991 | dma_addr_t dma_addr; | |
992 | struct nvme_command cid, crt; | |
993 | ||
994 | res = nvme_setup_io_queues(dev); | |
995 | if (res) | |
996 | return res; | |
997 | ||
998 | /* XXX: Switch to a SG list once prp2 works */ | |
999 | id = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, | |
1000 | GFP_KERNEL); | |
1001 | ||
1002 | memset(&cid, 0, sizeof(cid)); | |
1003 | cid.identify.opcode = nvme_admin_identify; | |
1004 | cid.identify.nsid = 0; | |
1005 | cid.identify.prp1 = cpu_to_le64(dma_addr); | |
1006 | cid.identify.cns = cpu_to_le32(1); | |
1007 | ||
1008 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1009 | if (res) { | |
1010 | res = -EIO; | |
1011 | goto out_free; | |
1012 | } | |
1013 | ||
51814232 MW |
1014 | ctrl = id; |
1015 | nn = le32_to_cpup(&ctrl->nn); | |
1016 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1017 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1018 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
b60503ba MW |
1019 | |
1020 | cid.identify.cns = 0; | |
1021 | memset(&crt, 0, sizeof(crt)); | |
1022 | crt.features.opcode = nvme_admin_get_features; | |
1023 | crt.features.prp1 = cpu_to_le64(dma_addr + 4096); | |
1024 | crt.features.fid = cpu_to_le32(NVME_FEAT_LBA_RANGE); | |
1025 | ||
1026 | for (i = 0; i < nn; i++) { | |
1027 | cid.identify.nsid = cpu_to_le32(i); | |
1028 | res = nvme_submit_admin_cmd(dev, &cid, NULL); | |
1029 | if (res) | |
1030 | continue; | |
1031 | ||
1032 | if (((struct nvme_id_ns *)id)->ncap == 0) | |
1033 | continue; | |
1034 | ||
1035 | crt.features.nsid = cpu_to_le32(i); | |
1036 | res = nvme_submit_admin_cmd(dev, &crt, NULL); | |
1037 | if (res) | |
1038 | continue; | |
1039 | ||
1040 | ns = nvme_alloc_ns(dev, i, id, id + 4096); | |
1041 | if (ns) | |
1042 | list_add_tail(&ns->list, &dev->namespaces); | |
1043 | } | |
1044 | list_for_each_entry(ns, &dev->namespaces, list) | |
1045 | add_disk(ns->disk); | |
1046 | ||
1047 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1048 | return 0; | |
1049 | ||
1050 | out_free: | |
1051 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1052 | list_del(&ns->list); | |
1053 | nvme_ns_free(ns); | |
1054 | } | |
1055 | ||
1056 | dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr); | |
1057 | return res; | |
1058 | } | |
1059 | ||
1060 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1061 | { | |
1062 | struct nvme_ns *ns, *next; | |
1063 | ||
1064 | /* TODO: wait all I/O finished or cancel them */ | |
1065 | ||
1066 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1067 | list_del(&ns->list); | |
1068 | del_gendisk(ns->disk); | |
1069 | nvme_ns_free(ns); | |
1070 | } | |
1071 | ||
1072 | nvme_free_queues(dev); | |
1073 | ||
1074 | return 0; | |
1075 | } | |
1076 | ||
1077 | /* XXX: Use an ida or something to let remove / add work correctly */ | |
1078 | static void nvme_set_instance(struct nvme_dev *dev) | |
1079 | { | |
1080 | static int instance; | |
1081 | dev->instance = instance++; | |
1082 | } | |
1083 | ||
1084 | static void nvme_release_instance(struct nvme_dev *dev) | |
1085 | { | |
1086 | } | |
1087 | ||
1088 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1089 | const struct pci_device_id *id) | |
1090 | { | |
574e8b95 | 1091 | int bars, result = -ENOMEM; |
b60503ba MW |
1092 | struct nvme_dev *dev; |
1093 | ||
1094 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1095 | if (!dev) | |
1096 | return -ENOMEM; | |
1097 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1098 | GFP_KERNEL); | |
1099 | if (!dev->entry) | |
1100 | goto free; | |
1b23484b MW |
1101 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1102 | GFP_KERNEL); | |
b60503ba MW |
1103 | if (!dev->queues) |
1104 | goto free; | |
1105 | ||
0ee5a7d7 SMM |
1106 | if (pci_enable_device_mem(pdev)) |
1107 | goto free; | |
f64d3365 | 1108 | pci_set_master(pdev); |
574e8b95 MW |
1109 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1110 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1111 | goto disable; | |
0ee5a7d7 | 1112 | |
b60503ba MW |
1113 | INIT_LIST_HEAD(&dev->namespaces); |
1114 | dev->pci_dev = pdev; | |
1115 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1116 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1117 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1118 | nvme_set_instance(dev); |
53c9577e | 1119 | dev->entry[0].vector = pdev->irq; |
b60503ba MW |
1120 | |
1121 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); | |
1122 | if (!dev->bar) { | |
1123 | result = -ENOMEM; | |
574e8b95 | 1124 | goto disable_msix; |
b60503ba MW |
1125 | } |
1126 | ||
1127 | result = nvme_configure_admin_queue(dev); | |
1128 | if (result) | |
1129 | goto unmap; | |
1130 | dev->queue_count++; | |
1131 | ||
1132 | result = nvme_dev_add(dev); | |
1133 | if (result) | |
1134 | goto delete; | |
1135 | return 0; | |
1136 | ||
1137 | delete: | |
1138 | nvme_free_queues(dev); | |
1139 | unmap: | |
1140 | iounmap(dev->bar); | |
574e8b95 | 1141 | disable_msix: |
b60503ba MW |
1142 | pci_disable_msix(pdev); |
1143 | nvme_release_instance(dev); | |
574e8b95 | 1144 | disable: |
0ee5a7d7 | 1145 | pci_disable_device(pdev); |
574e8b95 | 1146 | pci_release_regions(pdev); |
b60503ba MW |
1147 | free: |
1148 | kfree(dev->queues); | |
1149 | kfree(dev->entry); | |
1150 | kfree(dev); | |
1151 | return result; | |
1152 | } | |
1153 | ||
1154 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1155 | { | |
1156 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1157 | nvme_dev_remove(dev); | |
1158 | pci_disable_msix(pdev); | |
1159 | iounmap(dev->bar); | |
1160 | nvme_release_instance(dev); | |
0ee5a7d7 | 1161 | pci_disable_device(pdev); |
574e8b95 | 1162 | pci_release_regions(pdev); |
b60503ba MW |
1163 | kfree(dev->queues); |
1164 | kfree(dev->entry); | |
1165 | kfree(dev); | |
1166 | } | |
1167 | ||
1168 | /* These functions are yet to be implemented */ | |
1169 | #define nvme_error_detected NULL | |
1170 | #define nvme_dump_registers NULL | |
1171 | #define nvme_link_reset NULL | |
1172 | #define nvme_slot_reset NULL | |
1173 | #define nvme_error_resume NULL | |
1174 | #define nvme_suspend NULL | |
1175 | #define nvme_resume NULL | |
1176 | ||
1177 | static struct pci_error_handlers nvme_err_handler = { | |
1178 | .error_detected = nvme_error_detected, | |
1179 | .mmio_enabled = nvme_dump_registers, | |
1180 | .link_reset = nvme_link_reset, | |
1181 | .slot_reset = nvme_slot_reset, | |
1182 | .resume = nvme_error_resume, | |
1183 | }; | |
1184 | ||
1185 | /* Move to pci_ids.h later */ | |
1186 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1187 | ||
1188 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1189 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1190 | { 0, } | |
1191 | }; | |
1192 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1193 | ||
1194 | static struct pci_driver nvme_driver = { | |
1195 | .name = "nvme", | |
1196 | .id_table = nvme_id_table, | |
1197 | .probe = nvme_probe, | |
1198 | .remove = __devexit_p(nvme_remove), | |
1199 | .suspend = nvme_suspend, | |
1200 | .resume = nvme_resume, | |
1201 | .err_handler = &nvme_err_handler, | |
1202 | }; | |
1203 | ||
1204 | static int __init nvme_init(void) | |
1205 | { | |
1206 | int result; | |
1207 | ||
1208 | nvme_major = register_blkdev(nvme_major, "nvme"); | |
1209 | if (nvme_major <= 0) | |
1210 | return -EBUSY; | |
1211 | ||
1212 | result = pci_register_driver(&nvme_driver); | |
1213 | if (!result) | |
1214 | return 0; | |
1215 | ||
1216 | unregister_blkdev(nvme_major, "nvme"); | |
1217 | return result; | |
1218 | } | |
1219 | ||
1220 | static void __exit nvme_exit(void) | |
1221 | { | |
1222 | pci_unregister_driver(&nvme_driver); | |
1223 | unregister_blkdev(nvme_major, "nvme"); | |
1224 | } | |
1225 | ||
1226 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1227 | MODULE_LICENSE("GPL"); | |
1228 | MODULE_VERSION("0.1"); | |
1229 | module_init(nvme_init); | |
1230 | module_exit(nvme_exit); |