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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
b60503ba | 42 | |
797a796a HM |
43 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
44 | ||
b60503ba MW |
45 | #define NVME_Q_DEPTH 1024 |
46 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
47 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
48 | #define NVME_MINORS 64 | |
ff976d72 | 49 | #define NVME_IO_TIMEOUT (5 * HZ) |
e85248e5 | 50 | #define ADMIN_TIMEOUT (60 * HZ) |
b60503ba MW |
51 | |
52 | static int nvme_major; | |
53 | module_param(nvme_major, int, 0); | |
54 | ||
58ffacb5 MW |
55 | static int use_threaded_interrupts; |
56 | module_param(use_threaded_interrupts, int, 0); | |
57 | ||
1fa6aead MW |
58 | static DEFINE_SPINLOCK(dev_list_lock); |
59 | static LIST_HEAD(dev_list); | |
60 | static struct task_struct *nvme_thread; | |
61 | ||
b60503ba MW |
62 | /* |
63 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
64 | */ | |
65 | struct nvme_dev { | |
1fa6aead | 66 | struct list_head node; |
b60503ba MW |
67 | struct nvme_queue **queues; |
68 | u32 __iomem *dbs; | |
69 | struct pci_dev *pci_dev; | |
091b6092 | 70 | struct dma_pool *prp_page_pool; |
99802a7a | 71 | struct dma_pool *prp_small_pool; |
b60503ba MW |
72 | int instance; |
73 | int queue_count; | |
f1938f6e | 74 | int db_stride; |
b60503ba MW |
75 | u32 ctrl_config; |
76 | struct msix_entry *entry; | |
77 | struct nvme_bar __iomem *bar; | |
78 | struct list_head namespaces; | |
51814232 MW |
79 | char serial[20]; |
80 | char model[40]; | |
81 | char firmware_rev[8]; | |
8fc23e03 | 82 | u32 max_hw_sectors; |
b60503ba MW |
83 | }; |
84 | ||
85 | /* | |
86 | * An NVM Express namespace is equivalent to a SCSI LUN | |
87 | */ | |
88 | struct nvme_ns { | |
89 | struct list_head list; | |
90 | ||
91 | struct nvme_dev *dev; | |
92 | struct request_queue *queue; | |
93 | struct gendisk *disk; | |
94 | ||
95 | int ns_id; | |
96 | int lba_shift; | |
97 | }; | |
98 | ||
99 | /* | |
100 | * An NVM Express queue. Each device has at least two (one for admin | |
101 | * commands and one for I/O commands). | |
102 | */ | |
103 | struct nvme_queue { | |
104 | struct device *q_dmadev; | |
091b6092 | 105 | struct nvme_dev *dev; |
b60503ba MW |
106 | spinlock_t q_lock; |
107 | struct nvme_command *sq_cmds; | |
108 | volatile struct nvme_completion *cqes; | |
109 | dma_addr_t sq_dma_addr; | |
110 | dma_addr_t cq_dma_addr; | |
111 | wait_queue_head_t sq_full; | |
1fa6aead | 112 | wait_queue_t sq_cong_wait; |
b60503ba MW |
113 | struct bio_list sq_cong; |
114 | u32 __iomem *q_db; | |
115 | u16 q_depth; | |
116 | u16 cq_vector; | |
117 | u16 sq_head; | |
118 | u16 sq_tail; | |
119 | u16 cq_head; | |
82123460 | 120 | u16 cq_phase; |
b60503ba MW |
121 | unsigned long cmdid_data[]; |
122 | }; | |
123 | ||
124 | /* | |
125 | * Check we didin't inadvertently grow the command struct | |
126 | */ | |
127 | static inline void _nvme_check_size(void) | |
128 | { | |
129 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
130 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
131 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
132 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
133 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
135 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
136 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
137 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
138 | } | |
139 | ||
5c1281a3 | 140 | typedef void (*nvme_completion_fn)(struct nvme_dev *, void *, |
c2f5b650 MW |
141 | struct nvme_completion *); |
142 | ||
e85248e5 | 143 | struct nvme_cmd_info { |
c2f5b650 MW |
144 | nvme_completion_fn fn; |
145 | void *ctx; | |
e85248e5 MW |
146 | unsigned long timeout; |
147 | }; | |
148 | ||
149 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
150 | { | |
151 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
152 | } | |
153 | ||
b60503ba | 154 | /** |
714a7a22 MW |
155 | * alloc_cmdid() - Allocate a Command ID |
156 | * @nvmeq: The queue that will be used for this command | |
157 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 158 | * @handler: The function to call on completion |
b60503ba MW |
159 | * |
160 | * Allocate a Command ID for a queue. The data passed in will | |
161 | * be passed to the completion handler. This is implemented by using | |
162 | * the bottom two bits of the ctx pointer to store the handler ID. | |
163 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
164 | * We can change this if it becomes a problem. | |
184d2944 MW |
165 | * |
166 | * May be called with local interrupts disabled and the q_lock held, | |
167 | * or with interrupts enabled and no locks held. | |
b60503ba | 168 | */ |
c2f5b650 MW |
169 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
170 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 171 | { |
e6d15f79 | 172 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 173 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
174 | int cmdid; |
175 | ||
b60503ba MW |
176 | do { |
177 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
178 | if (cmdid >= depth) | |
179 | return -EBUSY; | |
180 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
181 | ||
c2f5b650 MW |
182 | info[cmdid].fn = handler; |
183 | info[cmdid].ctx = ctx; | |
e85248e5 | 184 | info[cmdid].timeout = jiffies + timeout; |
b60503ba MW |
185 | return cmdid; |
186 | } | |
187 | ||
188 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 189 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
190 | { |
191 | int cmdid; | |
192 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 193 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
194 | return (cmdid < 0) ? -EINTR : cmdid; |
195 | } | |
196 | ||
c2f5b650 MW |
197 | /* Special values must be less than 0x1000 */ |
198 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
199 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
200 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
201 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 202 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 203 | |
5c1281a3 | 204 | static void special_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
205 | struct nvme_completion *cqe) |
206 | { | |
207 | if (ctx == CMD_CTX_CANCELLED) | |
208 | return; | |
209 | if (ctx == CMD_CTX_FLUSH) | |
210 | return; | |
211 | if (ctx == CMD_CTX_COMPLETED) { | |
5c1281a3 | 212 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
213 | "completed id %d twice on queue %d\n", |
214 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
215 | return; | |
216 | } | |
217 | if (ctx == CMD_CTX_INVALID) { | |
5c1281a3 | 218 | dev_warn(&dev->pci_dev->dev, |
c2f5b650 MW |
219 | "invalid id %d completed on queue %d\n", |
220 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
221 | return; | |
222 | } | |
223 | ||
5c1281a3 | 224 | dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
225 | } |
226 | ||
184d2944 MW |
227 | /* |
228 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
229 | */ | |
c2f5b650 MW |
230 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
231 | nvme_completion_fn *fn) | |
b60503ba | 232 | { |
c2f5b650 | 233 | void *ctx; |
e85248e5 | 234 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 235 | |
c2f5b650 MW |
236 | if (cmdid >= nvmeq->q_depth) { |
237 | *fn = special_completion; | |
48e3d398 | 238 | return CMD_CTX_INVALID; |
c2f5b650 | 239 | } |
859361a2 KB |
240 | if (fn) |
241 | *fn = info[cmdid].fn; | |
c2f5b650 MW |
242 | ctx = info[cmdid].ctx; |
243 | info[cmdid].fn = special_completion; | |
e85248e5 | 244 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
245 | clear_bit(cmdid, nvmeq->cmdid_data); |
246 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 247 | return ctx; |
b60503ba MW |
248 | } |
249 | ||
c2f5b650 MW |
250 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
251 | nvme_completion_fn *fn) | |
3c0cf138 | 252 | { |
c2f5b650 | 253 | void *ctx; |
e85248e5 | 254 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
255 | if (fn) |
256 | *fn = info[cmdid].fn; | |
257 | ctx = info[cmdid].ctx; | |
258 | info[cmdid].fn = special_completion; | |
e85248e5 | 259 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 260 | return ctx; |
3c0cf138 MW |
261 | } |
262 | ||
040a93b5 | 263 | static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) |
b60503ba | 264 | { |
040a93b5 | 265 | return dev->queues[get_cpu() + 1]; |
b60503ba MW |
266 | } |
267 | ||
268 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
269 | { | |
1b23484b | 270 | put_cpu(); |
b60503ba MW |
271 | } |
272 | ||
273 | /** | |
714a7a22 | 274 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
275 | * @nvmeq: The queue to use |
276 | * @cmd: The command to send | |
277 | * | |
278 | * Safe to use from interrupt context | |
279 | */ | |
280 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
281 | { | |
282 | unsigned long flags; | |
283 | u16 tail; | |
b60503ba MW |
284 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
285 | tail = nvmeq->sq_tail; | |
286 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
287 | if (++tail == nvmeq->q_depth) |
288 | tail = 0; | |
7547881d | 289 | writel(tail, nvmeq->q_db); |
b60503ba MW |
290 | nvmeq->sq_tail = tail; |
291 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
eca18b23 MW |
296 | /* |
297 | * The nvme_iod describes the data in an I/O, including the list of PRP | |
298 | * entries. You can't see it in this data structure because C doesn't let | |
299 | * me express that. Use nvme_alloc_iod to ensure there's enough space | |
300 | * allocated to store the PRP list. | |
301 | */ | |
302 | struct nvme_iod { | |
303 | void *private; /* For the use of the submitter of the I/O */ | |
304 | int npages; /* In the PRP list. 0 means small pool in use */ | |
305 | int offset; /* Of PRP list */ | |
306 | int nents; /* Used in scatterlist */ | |
307 | int length; /* Of data, in bytes */ | |
e025344c | 308 | dma_addr_t first_dma; |
eca18b23 | 309 | struct scatterlist sg[0]; |
e025344c SMM |
310 | }; |
311 | ||
eca18b23 | 312 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 313 | { |
eca18b23 | 314 | return ((void *)iod) + iod->offset; |
e025344c SMM |
315 | } |
316 | ||
eca18b23 MW |
317 | /* |
318 | * Will slightly overestimate the number of pages needed. This is OK | |
319 | * as it only leads to a small amount of wasted memory for the lifetime of | |
320 | * the I/O. | |
321 | */ | |
322 | static int nvme_npages(unsigned size) | |
323 | { | |
324 | unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE); | |
325 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
326 | } | |
b60503ba | 327 | |
eca18b23 MW |
328 | static struct nvme_iod * |
329 | nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp) | |
b60503ba | 330 | { |
eca18b23 MW |
331 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
332 | sizeof(__le64 *) * nvme_npages(nbytes) + | |
333 | sizeof(struct scatterlist) * nseg, gfp); | |
334 | ||
335 | if (iod) { | |
336 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
337 | iod->npages = -1; | |
338 | iod->length = nbytes; | |
339 | } | |
340 | ||
341 | return iod; | |
b60503ba MW |
342 | } |
343 | ||
eca18b23 | 344 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 345 | { |
eca18b23 MW |
346 | const int last_prp = PAGE_SIZE / 8 - 1; |
347 | int i; | |
348 | __le64 **list = iod_list(iod); | |
349 | dma_addr_t prp_dma = iod->first_dma; | |
350 | ||
351 | if (iod->npages == 0) | |
352 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
353 | for (i = 0; i < iod->npages; i++) { | |
354 | __le64 *prp_list = list[i]; | |
355 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
356 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
357 | prp_dma = next_prp_dma; | |
358 | } | |
359 | kfree(iod); | |
b60503ba MW |
360 | } |
361 | ||
5c1281a3 MW |
362 | static void requeue_bio(struct nvme_dev *dev, struct bio *bio) |
363 | { | |
364 | struct nvme_queue *nvmeq = get_nvmeq(dev); | |
365 | if (bio_list_empty(&nvmeq->sq_cong)) | |
366 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
367 | bio_list_add(&nvmeq->sq_cong, bio); | |
368 | put_nvmeq(nvmeq); | |
369 | wake_up_process(nvme_thread); | |
370 | } | |
371 | ||
372 | static void bio_completion(struct nvme_dev *dev, void *ctx, | |
b60503ba MW |
373 | struct nvme_completion *cqe) |
374 | { | |
eca18b23 MW |
375 | struct nvme_iod *iod = ctx; |
376 | struct bio *bio = iod->private; | |
b60503ba MW |
377 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
378 | ||
eca18b23 | 379 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
b60503ba | 380 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
eca18b23 | 381 | nvme_free_iod(dev, iod); |
09a58f53 | 382 | if (status) { |
1ad2f893 | 383 | bio_endio(bio, -EIO); |
09a58f53 | 384 | } else if (bio->bi_vcnt > bio->bi_idx) { |
5c1281a3 | 385 | requeue_bio(dev, bio); |
1ad2f893 MW |
386 | } else { |
387 | bio_endio(bio, 0); | |
388 | } | |
b60503ba MW |
389 | } |
390 | ||
184d2944 | 391 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
eca18b23 MW |
392 | static int nvme_setup_prps(struct nvme_dev *dev, |
393 | struct nvme_common_command *cmd, struct nvme_iod *iod, | |
394 | int total_len, gfp_t gfp) | |
ff22b54f | 395 | { |
99802a7a | 396 | struct dma_pool *pool; |
eca18b23 MW |
397 | int length = total_len; |
398 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
399 | int dma_len = sg_dma_len(sg); |
400 | u64 dma_addr = sg_dma_address(sg); | |
401 | int offset = offset_in_page(dma_addr); | |
e025344c | 402 | __le64 *prp_list; |
eca18b23 | 403 | __le64 **list = iod_list(iod); |
e025344c | 404 | dma_addr_t prp_dma; |
eca18b23 | 405 | int nprps, i; |
ff22b54f MW |
406 | |
407 | cmd->prp1 = cpu_to_le64(dma_addr); | |
408 | length -= (PAGE_SIZE - offset); | |
409 | if (length <= 0) | |
eca18b23 | 410 | return total_len; |
ff22b54f MW |
411 | |
412 | dma_len -= (PAGE_SIZE - offset); | |
413 | if (dma_len) { | |
414 | dma_addr += (PAGE_SIZE - offset); | |
415 | } else { | |
416 | sg = sg_next(sg); | |
417 | dma_addr = sg_dma_address(sg); | |
418 | dma_len = sg_dma_len(sg); | |
419 | } | |
420 | ||
421 | if (length <= PAGE_SIZE) { | |
422 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 | 423 | return total_len; |
e025344c SMM |
424 | } |
425 | ||
426 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
99802a7a MW |
427 | if (nprps <= (256 / 8)) { |
428 | pool = dev->prp_small_pool; | |
eca18b23 | 429 | iod->npages = 0; |
99802a7a MW |
430 | } else { |
431 | pool = dev->prp_page_pool; | |
eca18b23 | 432 | iod->npages = 1; |
99802a7a MW |
433 | } |
434 | ||
b77954cb MW |
435 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
436 | if (!prp_list) { | |
437 | cmd->prp2 = cpu_to_le64(dma_addr); | |
eca18b23 MW |
438 | iod->npages = -1; |
439 | return (total_len - length) + PAGE_SIZE; | |
b77954cb | 440 | } |
eca18b23 MW |
441 | list[0] = prp_list; |
442 | iod->first_dma = prp_dma; | |
e025344c SMM |
443 | cmd->prp2 = cpu_to_le64(prp_dma); |
444 | i = 0; | |
445 | for (;;) { | |
7523d834 | 446 | if (i == PAGE_SIZE / 8) { |
e025344c | 447 | __le64 *old_prp_list = prp_list; |
b77954cb | 448 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
449 | if (!prp_list) |
450 | return total_len - length; | |
451 | list[iod->npages++] = prp_list; | |
7523d834 MW |
452 | prp_list[0] = old_prp_list[i - 1]; |
453 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
454 | i = 1; | |
e025344c SMM |
455 | } |
456 | prp_list[i++] = cpu_to_le64(dma_addr); | |
457 | dma_len -= PAGE_SIZE; | |
458 | dma_addr += PAGE_SIZE; | |
459 | length -= PAGE_SIZE; | |
460 | if (length <= 0) | |
461 | break; | |
462 | if (dma_len > 0) | |
463 | continue; | |
464 | BUG_ON(dma_len < 0); | |
465 | sg = sg_next(sg); | |
466 | dma_addr = sg_dma_address(sg); | |
467 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
468 | } |
469 | ||
eca18b23 | 470 | return total_len; |
ff22b54f MW |
471 | } |
472 | ||
1ad2f893 MW |
473 | /* NVMe scatterlists require no holes in the virtual address */ |
474 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
475 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
476 | ||
eca18b23 | 477 | static int nvme_map_bio(struct device *dev, struct nvme_iod *iod, |
b60503ba MW |
478 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
479 | { | |
76830840 MW |
480 | struct bio_vec *bvec, *bvprv = NULL; |
481 | struct scatterlist *sg = NULL; | |
1ad2f893 | 482 | int i, old_idx, length = 0, nsegs = 0; |
b60503ba | 483 | |
eca18b23 | 484 | sg_init_table(iod->sg, psegs); |
1ad2f893 | 485 | old_idx = bio->bi_idx; |
b60503ba | 486 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
487 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
488 | sg->length += bvec->bv_len; | |
489 | } else { | |
1ad2f893 MW |
490 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
491 | break; | |
eca18b23 | 492 | sg = sg ? sg + 1 : iod->sg; |
76830840 MW |
493 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, |
494 | bvec->bv_offset); | |
495 | nsegs++; | |
496 | } | |
1ad2f893 | 497 | length += bvec->bv_len; |
76830840 | 498 | bvprv = bvec; |
b60503ba | 499 | } |
1ad2f893 | 500 | bio->bi_idx = i; |
eca18b23 | 501 | iod->nents = nsegs; |
76830840 | 502 | sg_mark_end(sg); |
eca18b23 | 503 | if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) { |
1ad2f893 MW |
504 | bio->bi_idx = old_idx; |
505 | return -ENOMEM; | |
506 | } | |
507 | return length; | |
b60503ba MW |
508 | } |
509 | ||
00df5cb4 MW |
510 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
511 | int cmdid) | |
512 | { | |
513 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
514 | ||
515 | memset(cmnd, 0, sizeof(*cmnd)); | |
516 | cmnd->common.opcode = nvme_cmd_flush; | |
517 | cmnd->common.command_id = cmdid; | |
518 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
519 | ||
520 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
521 | nvmeq->sq_tail = 0; | |
522 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) | |
528 | { | |
529 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
ff976d72 | 530 | special_completion, NVME_IO_TIMEOUT); |
00df5cb4 MW |
531 | if (unlikely(cmdid < 0)) |
532 | return cmdid; | |
533 | ||
534 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
535 | } | |
536 | ||
184d2944 MW |
537 | /* |
538 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
539 | */ | |
b60503ba MW |
540 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
541 | struct bio *bio) | |
542 | { | |
ff22b54f | 543 | struct nvme_command *cmnd; |
eca18b23 | 544 | struct nvme_iod *iod; |
b60503ba | 545 | enum dma_data_direction dma_dir; |
1ad2f893 | 546 | int cmdid, length, result = -ENOMEM; |
b60503ba MW |
547 | u16 control; |
548 | u32 dsmgmt; | |
b60503ba MW |
549 | int psegs = bio_phys_segments(ns->queue, bio); |
550 | ||
00df5cb4 MW |
551 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
552 | result = nvme_submit_flush_data(nvmeq, ns); | |
553 | if (result) | |
554 | return result; | |
555 | } | |
556 | ||
eca18b23 MW |
557 | iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC); |
558 | if (!iod) | |
eeee3226 | 559 | goto nomem; |
eca18b23 | 560 | iod->private = bio; |
b60503ba | 561 | |
eeee3226 | 562 | result = -EBUSY; |
ff976d72 | 563 | cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT); |
b60503ba | 564 | if (unlikely(cmdid < 0)) |
eca18b23 | 565 | goto free_iod; |
b60503ba | 566 | |
00df5cb4 MW |
567 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
568 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
569 | ||
b60503ba MW |
570 | control = 0; |
571 | if (bio->bi_rw & REQ_FUA) | |
572 | control |= NVME_RW_FUA; | |
573 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
574 | control |= NVME_RW_LR; | |
575 | ||
576 | dsmgmt = 0; | |
577 | if (bio->bi_rw & REQ_RAHEAD) | |
578 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
579 | ||
ff22b54f | 580 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 581 | |
b8deb62c | 582 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 583 | if (bio_data_dir(bio)) { |
ff22b54f | 584 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
585 | dma_dir = DMA_TO_DEVICE; |
586 | } else { | |
ff22b54f | 587 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
588 | dma_dir = DMA_FROM_DEVICE; |
589 | } | |
590 | ||
eca18b23 | 591 | result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs); |
1ad2f893 | 592 | if (result < 0) |
859361a2 | 593 | goto free_cmdid; |
1ad2f893 | 594 | length = result; |
b60503ba | 595 | |
ff22b54f MW |
596 | cmnd->rw.command_id = cmdid; |
597 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
eca18b23 MW |
598 | length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length, |
599 | GFP_ATOMIC); | |
ff22b54f | 600 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); |
1ad2f893 | 601 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
602 | cmnd->rw.control = cpu_to_le16(control); |
603 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 604 | |
d8ee9d69 MW |
605 | bio->bi_sector += length >> 9; |
606 | ||
b60503ba MW |
607 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
608 | nvmeq->sq_tail = 0; | |
7547881d | 609 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 610 | |
1974b1ae MW |
611 | return 0; |
612 | ||
859361a2 KB |
613 | free_cmdid: |
614 | free_cmdid(nvmeq, cmdid, NULL); | |
eca18b23 MW |
615 | free_iod: |
616 | nvme_free_iod(nvmeq->dev, iod); | |
eeee3226 MW |
617 | nomem: |
618 | return result; | |
b60503ba MW |
619 | } |
620 | ||
93c3d65b | 621 | static void nvme_make_request(struct request_queue *q, struct bio *bio) |
b60503ba MW |
622 | { |
623 | struct nvme_ns *ns = q->queuedata; | |
040a93b5 | 624 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); |
eeee3226 MW |
625 | int result = -EBUSY; |
626 | ||
627 | spin_lock_irq(&nvmeq->q_lock); | |
628 | if (bio_list_empty(&nvmeq->sq_cong)) | |
629 | result = nvme_submit_bio_queue(nvmeq, ns, bio); | |
630 | if (unlikely(result)) { | |
631 | if (bio_list_empty(&nvmeq->sq_cong)) | |
632 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
b60503ba MW |
633 | bio_list_add(&nvmeq->sq_cong, bio); |
634 | } | |
eeee3226 MW |
635 | |
636 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba | 637 | put_nvmeq(nvmeq); |
b60503ba MW |
638 | } |
639 | ||
b60503ba MW |
640 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) |
641 | { | |
82123460 | 642 | u16 head, phase; |
b60503ba | 643 | |
b60503ba | 644 | head = nvmeq->cq_head; |
82123460 | 645 | phase = nvmeq->cq_phase; |
b60503ba MW |
646 | |
647 | for (;;) { | |
c2f5b650 MW |
648 | void *ctx; |
649 | nvme_completion_fn fn; | |
b60503ba | 650 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 651 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
652 | break; |
653 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
654 | if (++head == nvmeq->q_depth) { | |
655 | head = 0; | |
82123460 | 656 | phase = !phase; |
b60503ba MW |
657 | } |
658 | ||
c2f5b650 | 659 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
5c1281a3 | 660 | fn(nvmeq->dev, ctx, &cqe); |
b60503ba MW |
661 | } |
662 | ||
663 | /* If the controller ignores the cq head doorbell and continuously | |
664 | * writes to the queue, it is theoretically possible to wrap around | |
665 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
666 | * requires that 0.1% of your interrupts are handled, so this isn't | |
667 | * a big problem. | |
668 | */ | |
82123460 | 669 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
670 | return IRQ_NONE; |
671 | ||
f1938f6e | 672 | writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride)); |
b60503ba | 673 | nvmeq->cq_head = head; |
82123460 | 674 | nvmeq->cq_phase = phase; |
b60503ba MW |
675 | |
676 | return IRQ_HANDLED; | |
677 | } | |
678 | ||
679 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
680 | { |
681 | irqreturn_t result; | |
682 | struct nvme_queue *nvmeq = data; | |
683 | spin_lock(&nvmeq->q_lock); | |
684 | result = nvme_process_cq(nvmeq); | |
685 | spin_unlock(&nvmeq->q_lock); | |
686 | return result; | |
687 | } | |
688 | ||
689 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
690 | { | |
691 | struct nvme_queue *nvmeq = data; | |
692 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
693 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
694 | return IRQ_NONE; | |
695 | return IRQ_WAKE_THREAD; | |
696 | } | |
697 | ||
3c0cf138 MW |
698 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
699 | { | |
700 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 701 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
702 | spin_unlock_irq(&nvmeq->q_lock); |
703 | } | |
704 | ||
c2f5b650 MW |
705 | struct sync_cmd_info { |
706 | struct task_struct *task; | |
707 | u32 result; | |
708 | int status; | |
709 | }; | |
710 | ||
5c1281a3 | 711 | static void sync_completion(struct nvme_dev *dev, void *ctx, |
c2f5b650 MW |
712 | struct nvme_completion *cqe) |
713 | { | |
714 | struct sync_cmd_info *cmdinfo = ctx; | |
715 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
716 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
717 | wake_up_process(cmdinfo->task); | |
718 | } | |
719 | ||
b60503ba MW |
720 | /* |
721 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
722 | * if the result is positive, it's an NVM Express status code | |
723 | */ | |
3c0cf138 | 724 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
e85248e5 | 725 | struct nvme_command *cmd, u32 *result, unsigned timeout) |
b60503ba MW |
726 | { |
727 | int cmdid; | |
728 | struct sync_cmd_info cmdinfo; | |
729 | ||
730 | cmdinfo.task = current; | |
731 | cmdinfo.status = -EINTR; | |
732 | ||
c2f5b650 | 733 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion, |
e85248e5 | 734 | timeout); |
b60503ba MW |
735 | if (cmdid < 0) |
736 | return cmdid; | |
737 | cmd->common.command_id = cmdid; | |
738 | ||
3c0cf138 MW |
739 | set_current_state(TASK_KILLABLE); |
740 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
741 | schedule(); |
742 | ||
3c0cf138 MW |
743 | if (cmdinfo.status == -EINTR) { |
744 | nvme_abort_command(nvmeq, cmdid); | |
745 | return -EINTR; | |
746 | } | |
747 | ||
b60503ba MW |
748 | if (result) |
749 | *result = cmdinfo.result; | |
750 | ||
751 | return cmdinfo.status; | |
752 | } | |
753 | ||
754 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
755 | u32 *result) | |
756 | { | |
e85248e5 | 757 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
758 | } |
759 | ||
760 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
761 | { | |
762 | int status; | |
763 | struct nvme_command c; | |
764 | ||
765 | memset(&c, 0, sizeof(c)); | |
766 | c.delete_queue.opcode = opcode; | |
767 | c.delete_queue.qid = cpu_to_le16(id); | |
768 | ||
769 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
770 | if (status) | |
771 | return -EIO; | |
772 | return 0; | |
773 | } | |
774 | ||
775 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
776 | struct nvme_queue *nvmeq) | |
777 | { | |
778 | int status; | |
779 | struct nvme_command c; | |
780 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
781 | ||
782 | memset(&c, 0, sizeof(c)); | |
783 | c.create_cq.opcode = nvme_admin_create_cq; | |
784 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
785 | c.create_cq.cqid = cpu_to_le16(qid); | |
786 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
787 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
788 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
789 | ||
790 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
791 | if (status) | |
792 | return -EIO; | |
793 | return 0; | |
794 | } | |
795 | ||
796 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
797 | struct nvme_queue *nvmeq) | |
798 | { | |
799 | int status; | |
800 | struct nvme_command c; | |
801 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
802 | ||
803 | memset(&c, 0, sizeof(c)); | |
804 | c.create_sq.opcode = nvme_admin_create_sq; | |
805 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
806 | c.create_sq.sqid = cpu_to_le16(qid); | |
807 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
808 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
809 | c.create_sq.cqid = cpu_to_le16(qid); | |
810 | ||
811 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
812 | if (status) | |
813 | return -EIO; | |
814 | return 0; | |
815 | } | |
816 | ||
817 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
818 | { | |
819 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
820 | } | |
821 | ||
822 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
823 | { | |
824 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
825 | } | |
826 | ||
bc5fc7e4 MW |
827 | static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
828 | dma_addr_t dma_addr) | |
829 | { | |
830 | struct nvme_command c; | |
831 | ||
832 | memset(&c, 0, sizeof(c)); | |
833 | c.identify.opcode = nvme_admin_identify; | |
834 | c.identify.nsid = cpu_to_le32(nsid); | |
835 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
836 | c.identify.cns = cpu_to_le32(cns); | |
837 | ||
838 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
839 | } | |
840 | ||
841 | static int nvme_get_features(struct nvme_dev *dev, unsigned fid, | |
a42cecce | 842 | unsigned nsid, dma_addr_t dma_addr) |
bc5fc7e4 MW |
843 | { |
844 | struct nvme_command c; | |
845 | ||
846 | memset(&c, 0, sizeof(c)); | |
847 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 848 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
849 | c.features.prp1 = cpu_to_le64(dma_addr); |
850 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 851 | |
df348139 MW |
852 | return nvme_submit_admin_cmd(dev, &c, NULL); |
853 | } | |
854 | ||
855 | static int nvme_set_features(struct nvme_dev *dev, unsigned fid, | |
856 | unsigned dword11, dma_addr_t dma_addr, u32 *result) | |
857 | { | |
858 | struct nvme_command c; | |
859 | ||
860 | memset(&c, 0, sizeof(c)); | |
861 | c.features.opcode = nvme_admin_set_features; | |
862 | c.features.prp1 = cpu_to_le64(dma_addr); | |
863 | c.features.fid = cpu_to_le32(fid); | |
864 | c.features.dword11 = cpu_to_le32(dword11); | |
865 | ||
bc5fc7e4 MW |
866 | return nvme_submit_admin_cmd(dev, &c, result); |
867 | } | |
868 | ||
a09115b2 MW |
869 | /** |
870 | * nvme_cancel_ios - Cancel outstanding I/Os | |
871 | * @queue: The queue to cancel I/Os on | |
872 | * @timeout: True to only cancel I/Os which have timed out | |
873 | */ | |
874 | static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout) | |
875 | { | |
876 | int depth = nvmeq->q_depth - 1; | |
877 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
878 | unsigned long now = jiffies; | |
879 | int cmdid; | |
880 | ||
881 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
882 | void *ctx; | |
883 | nvme_completion_fn fn; | |
884 | static struct nvme_completion cqe = { | |
885 | .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, | |
886 | }; | |
887 | ||
888 | if (timeout && !time_after(now, info[cmdid].timeout)) | |
889 | continue; | |
890 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid); | |
891 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); | |
892 | fn(nvmeq->dev, ctx, &cqe); | |
893 | } | |
894 | } | |
895 | ||
9e866774 MW |
896 | static void nvme_free_queue_mem(struct nvme_queue *nvmeq) |
897 | { | |
898 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
899 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
900 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
901 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
902 | kfree(nvmeq); | |
903 | } | |
904 | ||
b60503ba MW |
905 | static void nvme_free_queue(struct nvme_dev *dev, int qid) |
906 | { | |
907 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 908 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 909 | |
a09115b2 MW |
910 | spin_lock_irq(&nvmeq->q_lock); |
911 | nvme_cancel_ios(nvmeq, false); | |
3295874b KB |
912 | while (bio_list_peek(&nvmeq->sq_cong)) { |
913 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
914 | bio_endio(bio, -EIO); | |
915 | } | |
a09115b2 MW |
916 | spin_unlock_irq(&nvmeq->q_lock); |
917 | ||
aba2080f MW |
918 | irq_set_affinity_hint(vector, NULL); |
919 | free_irq(vector, nvmeq); | |
b60503ba MW |
920 | |
921 | /* Don't tell the adapter to delete the admin queue */ | |
922 | if (qid) { | |
923 | adapter_delete_sq(dev, qid); | |
924 | adapter_delete_cq(dev, qid); | |
925 | } | |
926 | ||
9e866774 | 927 | nvme_free_queue_mem(nvmeq); |
b60503ba MW |
928 | } |
929 | ||
930 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
931 | int depth, int vector) | |
932 | { | |
933 | struct device *dmadev = &dev->pci_dev->dev; | |
a0cadb85 KB |
934 | unsigned extra = DIV_ROUND_UP(depth, 8) + (depth * |
935 | sizeof(struct nvme_cmd_info)); | |
b60503ba MW |
936 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
937 | if (!nvmeq) | |
938 | return NULL; | |
939 | ||
940 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
941 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
942 | if (!nvmeq->cqes) | |
943 | goto free_nvmeq; | |
944 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
945 | ||
946 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
947 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
948 | if (!nvmeq->sq_cmds) | |
949 | goto free_cqdma; | |
950 | ||
951 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 952 | nvmeq->dev = dev; |
b60503ba MW |
953 | spin_lock_init(&nvmeq->q_lock); |
954 | nvmeq->cq_head = 0; | |
82123460 | 955 | nvmeq->cq_phase = 1; |
b60503ba | 956 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 957 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 958 | bio_list_init(&nvmeq->sq_cong); |
f1938f6e | 959 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; |
b60503ba MW |
960 | nvmeq->q_depth = depth; |
961 | nvmeq->cq_vector = vector; | |
962 | ||
963 | return nvmeq; | |
964 | ||
965 | free_cqdma: | |
966 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
967 | nvmeq->cq_dma_addr); | |
968 | free_nvmeq: | |
969 | kfree(nvmeq); | |
970 | return NULL; | |
971 | } | |
972 | ||
3001082c MW |
973 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
974 | const char *name) | |
975 | { | |
58ffacb5 MW |
976 | if (use_threaded_interrupts) |
977 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 978 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
979 | IRQF_DISABLED | IRQF_SHARED, |
980 | name, nvmeq); | |
3001082c MW |
981 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
982 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
983 | } | |
984 | ||
b60503ba MW |
985 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
986 | int qid, int cq_size, int vector) | |
987 | { | |
988 | int result; | |
989 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
990 | ||
3f85d50b | 991 | if (!nvmeq) |
6f0f5449 | 992 | return ERR_PTR(-ENOMEM); |
3f85d50b | 993 | |
b60503ba MW |
994 | result = adapter_alloc_cq(dev, qid, nvmeq); |
995 | if (result < 0) | |
996 | goto free_nvmeq; | |
997 | ||
998 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
999 | if (result < 0) | |
1000 | goto release_cq; | |
1001 | ||
3001082c | 1002 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
1003 | if (result < 0) |
1004 | goto release_sq; | |
1005 | ||
1006 | return nvmeq; | |
1007 | ||
1008 | release_sq: | |
1009 | adapter_delete_sq(dev, qid); | |
1010 | release_cq: | |
1011 | adapter_delete_cq(dev, qid); | |
1012 | free_nvmeq: | |
1013 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
1014 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1015 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1016 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1017 | kfree(nvmeq); | |
6f0f5449 | 1018 | return ERR_PTR(result); |
b60503ba MW |
1019 | } |
1020 | ||
1021 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
1022 | { | |
9e866774 | 1023 | int result = 0; |
b60503ba | 1024 | u32 aqa; |
22605f96 MW |
1025 | u64 cap; |
1026 | unsigned long timeout; | |
b60503ba MW |
1027 | struct nvme_queue *nvmeq; |
1028 | ||
1029 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1030 | ||
1031 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
1032 | if (!nvmeq) |
1033 | return -ENOMEM; | |
b60503ba MW |
1034 | |
1035 | aqa = nvmeq->q_depth - 1; | |
1036 | aqa |= aqa << 16; | |
1037 | ||
1038 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
1039 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
1040 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 1041 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 1042 | |
5911f200 | 1043 | writel(0, &dev->bar->cc); |
b60503ba MW |
1044 | writel(aqa, &dev->bar->aqa); |
1045 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1046 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
1047 | writel(dev->ctrl_config, &dev->bar->cc); | |
1048 | ||
22605f96 MW |
1049 | cap = readq(&dev->bar->cap); |
1050 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
f1938f6e | 1051 | dev->db_stride = NVME_CAP_STRIDE(cap); |
22605f96 | 1052 | |
9e866774 | 1053 | while (!result && !(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { |
b60503ba MW |
1054 | msleep(100); |
1055 | if (fatal_signal_pending(current)) | |
9e866774 | 1056 | result = -EINTR; |
22605f96 MW |
1057 | if (time_after(jiffies, timeout)) { |
1058 | dev_err(&dev->pci_dev->dev, | |
1059 | "Device not ready; aborting initialisation\n"); | |
9e866774 | 1060 | result = -ENODEV; |
22605f96 | 1061 | } |
b60503ba MW |
1062 | } |
1063 | ||
9e866774 MW |
1064 | if (result) { |
1065 | nvme_free_queue_mem(nvmeq); | |
1066 | return result; | |
1067 | } | |
1068 | ||
3001082c | 1069 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
1070 | dev->queues[0] = nvmeq; |
1071 | return result; | |
1072 | } | |
1073 | ||
eca18b23 MW |
1074 | static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write, |
1075 | unsigned long addr, unsigned length) | |
b60503ba | 1076 | { |
36c14ed9 | 1077 | int i, err, count, nents, offset; |
7fc3cdab MW |
1078 | struct scatterlist *sg; |
1079 | struct page **pages; | |
eca18b23 | 1080 | struct nvme_iod *iod; |
36c14ed9 MW |
1081 | |
1082 | if (addr & 3) | |
eca18b23 | 1083 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1084 | if (!length) |
eca18b23 | 1085 | return ERR_PTR(-EINVAL); |
7fc3cdab | 1086 | |
36c14ed9 | 1087 | offset = offset_in_page(addr); |
7fc3cdab MW |
1088 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1089 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
22fff826 DC |
1090 | if (!pages) |
1091 | return ERR_PTR(-ENOMEM); | |
36c14ed9 MW |
1092 | |
1093 | err = get_user_pages_fast(addr, count, 1, pages); | |
1094 | if (err < count) { | |
1095 | count = err; | |
1096 | err = -EFAULT; | |
1097 | goto put_pages; | |
1098 | } | |
7fc3cdab | 1099 | |
eca18b23 MW |
1100 | iod = nvme_alloc_iod(count, length, GFP_KERNEL); |
1101 | sg = iod->sg; | |
36c14ed9 | 1102 | sg_init_table(sg, count); |
d0ba1e49 MW |
1103 | for (i = 0; i < count; i++) { |
1104 | sg_set_page(&sg[i], pages[i], | |
1105 | min_t(int, length, PAGE_SIZE - offset), offset); | |
1106 | length -= (PAGE_SIZE - offset); | |
1107 | offset = 0; | |
7fc3cdab | 1108 | } |
fe304c43 | 1109 | sg_mark_end(&sg[i - 1]); |
1c2ad9fa | 1110 | iod->nents = count; |
7fc3cdab MW |
1111 | |
1112 | err = -ENOMEM; | |
1113 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1114 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 | 1115 | if (!nents) |
eca18b23 | 1116 | goto free_iod; |
b60503ba | 1117 | |
7fc3cdab | 1118 | kfree(pages); |
eca18b23 | 1119 | return iod; |
b60503ba | 1120 | |
eca18b23 MW |
1121 | free_iod: |
1122 | kfree(iod); | |
7fc3cdab MW |
1123 | put_pages: |
1124 | for (i = 0; i < count; i++) | |
1125 | put_page(pages[i]); | |
1126 | kfree(pages); | |
eca18b23 | 1127 | return ERR_PTR(err); |
7fc3cdab | 1128 | } |
b60503ba | 1129 | |
7fc3cdab | 1130 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
1c2ad9fa | 1131 | struct nvme_iod *iod) |
7fc3cdab | 1132 | { |
1c2ad9fa | 1133 | int i; |
b60503ba | 1134 | |
1c2ad9fa MW |
1135 | dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents, |
1136 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
7fc3cdab | 1137 | |
1c2ad9fa MW |
1138 | for (i = 0; i < iod->nents; i++) |
1139 | put_page(sg_page(&iod->sg[i])); | |
7fc3cdab | 1140 | } |
b60503ba | 1141 | |
a53295b6 MW |
1142 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1143 | { | |
1144 | struct nvme_dev *dev = ns->dev; | |
1145 | struct nvme_queue *nvmeq; | |
1146 | struct nvme_user_io io; | |
1147 | struct nvme_command c; | |
1148 | unsigned length; | |
eca18b23 MW |
1149 | int status; |
1150 | struct nvme_iod *iod; | |
a53295b6 MW |
1151 | |
1152 | if (copy_from_user(&io, uio, sizeof(io))) | |
1153 | return -EFAULT; | |
6c7d4945 MW |
1154 | length = (io.nblocks + 1) << ns->lba_shift; |
1155 | ||
1156 | switch (io.opcode) { | |
1157 | case nvme_cmd_write: | |
1158 | case nvme_cmd_read: | |
6bbf1acd | 1159 | case nvme_cmd_compare: |
eca18b23 | 1160 | iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length); |
6413214c | 1161 | break; |
6c7d4945 | 1162 | default: |
6bbf1acd | 1163 | return -EINVAL; |
6c7d4945 MW |
1164 | } |
1165 | ||
eca18b23 MW |
1166 | if (IS_ERR(iod)) |
1167 | return PTR_ERR(iod); | |
a53295b6 MW |
1168 | |
1169 | memset(&c, 0, sizeof(c)); | |
1170 | c.rw.opcode = io.opcode; | |
1171 | c.rw.flags = io.flags; | |
6c7d4945 | 1172 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1173 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1174 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 MW |
1175 | c.rw.control = cpu_to_le16(io.control); |
1176 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
6c7d4945 MW |
1177 | c.rw.reftag = io.reftag; |
1178 | c.rw.apptag = io.apptag; | |
1179 | c.rw.appmask = io.appmask; | |
a53295b6 | 1180 | /* XXX: metadata */ |
eca18b23 | 1181 | length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL); |
a53295b6 | 1182 | |
040a93b5 | 1183 | nvmeq = get_nvmeq(dev); |
fa922821 MW |
1184 | /* |
1185 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1186 | * disabled. We may be preempted at any point, and be rescheduled |
1187 | * to a different CPU. That will cause cacheline bouncing, but no | |
1188 | * additional races since q_lock already protects against other CPUs. | |
1189 | */ | |
a53295b6 | 1190 | put_nvmeq(nvmeq); |
b77954cb MW |
1191 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1192 | status = -ENOMEM; | |
1193 | else | |
ff976d72 | 1194 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT); |
a53295b6 | 1195 | |
1c2ad9fa | 1196 | nvme_unmap_user_pages(dev, io.opcode & 1, iod); |
eca18b23 | 1197 | nvme_free_iod(dev, iod); |
a53295b6 MW |
1198 | return status; |
1199 | } | |
1200 | ||
50af8bae | 1201 | static int nvme_user_admin_cmd(struct nvme_dev *dev, |
6bbf1acd | 1202 | struct nvme_admin_cmd __user *ucmd) |
6ee44cdc | 1203 | { |
6bbf1acd | 1204 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1205 | struct nvme_command c; |
eca18b23 | 1206 | int status, length; |
c7d36ab8 | 1207 | struct nvme_iod *uninitialized_var(iod); |
6ee44cdc | 1208 | |
6bbf1acd MW |
1209 | if (!capable(CAP_SYS_ADMIN)) |
1210 | return -EACCES; | |
1211 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1212 | return -EFAULT; |
6ee44cdc MW |
1213 | |
1214 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1215 | c.common.opcode = cmd.opcode; |
1216 | c.common.flags = cmd.flags; | |
1217 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1218 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1219 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1220 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1221 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1222 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1223 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1224 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1225 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1226 | ||
1227 | length = cmd.data_len; | |
1228 | if (cmd.data_len) { | |
49742188 MW |
1229 | iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr, |
1230 | length); | |
eca18b23 MW |
1231 | if (IS_ERR(iod)) |
1232 | return PTR_ERR(iod); | |
1233 | length = nvme_setup_prps(dev, &c.common, iod, length, | |
1234 | GFP_KERNEL); | |
6bbf1acd MW |
1235 | } |
1236 | ||
1237 | if (length != cmd.data_len) | |
b77954cb MW |
1238 | status = -ENOMEM; |
1239 | else | |
1240 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
eca18b23 | 1241 | |
6bbf1acd | 1242 | if (cmd.data_len) { |
1c2ad9fa | 1243 | nvme_unmap_user_pages(dev, cmd.opcode & 1, iod); |
eca18b23 | 1244 | nvme_free_iod(dev, iod); |
6bbf1acd | 1245 | } |
6ee44cdc MW |
1246 | return status; |
1247 | } | |
1248 | ||
b60503ba MW |
1249 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1250 | unsigned long arg) | |
1251 | { | |
1252 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1253 | ||
1254 | switch (cmd) { | |
6bbf1acd MW |
1255 | case NVME_IOCTL_ID: |
1256 | return ns->ns_id; | |
1257 | case NVME_IOCTL_ADMIN_CMD: | |
50af8bae | 1258 | return nvme_user_admin_cmd(ns->dev, (void __user *)arg); |
a53295b6 MW |
1259 | case NVME_IOCTL_SUBMIT_IO: |
1260 | return nvme_submit_io(ns, (void __user *)arg); | |
b60503ba MW |
1261 | default: |
1262 | return -ENOTTY; | |
1263 | } | |
1264 | } | |
1265 | ||
1266 | static const struct block_device_operations nvme_fops = { | |
1267 | .owner = THIS_MODULE, | |
1268 | .ioctl = nvme_ioctl, | |
49481682 | 1269 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1270 | }; |
1271 | ||
1fa6aead MW |
1272 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1273 | { | |
1274 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1275 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1276 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
1277 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
1278 | bio_list_add_head(&nvmeq->sq_cong, bio); | |
1279 | break; | |
1280 | } | |
3cb967c0 MW |
1281 | if (bio_list_empty(&nvmeq->sq_cong)) |
1282 | remove_wait_queue(&nvmeq->sq_full, | |
1283 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1284 | } |
1285 | } | |
1286 | ||
1287 | static int nvme_kthread(void *data) | |
1288 | { | |
1289 | struct nvme_dev *dev; | |
1290 | ||
1291 | while (!kthread_should_stop()) { | |
1292 | __set_current_state(TASK_RUNNING); | |
1293 | spin_lock(&dev_list_lock); | |
1294 | list_for_each_entry(dev, &dev_list, node) { | |
1295 | int i; | |
1296 | for (i = 0; i < dev->queue_count; i++) { | |
1297 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1298 | if (!nvmeq) |
1299 | continue; | |
1fa6aead MW |
1300 | spin_lock_irq(&nvmeq->q_lock); |
1301 | if (nvme_process_cq(nvmeq)) | |
1302 | printk("process_cq did something\n"); | |
a09115b2 | 1303 | nvme_cancel_ios(nvmeq, true); |
1fa6aead MW |
1304 | nvme_resubmit_bios(nvmeq); |
1305 | spin_unlock_irq(&nvmeq->q_lock); | |
1306 | } | |
1307 | } | |
1308 | spin_unlock(&dev_list_lock); | |
1309 | set_current_state(TASK_INTERRUPTIBLE); | |
1310 | schedule_timeout(HZ); | |
1311 | } | |
1312 | return 0; | |
1313 | } | |
1314 | ||
5aff9382 MW |
1315 | static DEFINE_IDA(nvme_index_ida); |
1316 | ||
1317 | static int nvme_get_ns_idx(void) | |
1318 | { | |
1319 | int index, error; | |
1320 | ||
1321 | do { | |
1322 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1323 | return -1; | |
1324 | ||
1325 | spin_lock(&dev_list_lock); | |
1326 | error = ida_get_new(&nvme_index_ida, &index); | |
1327 | spin_unlock(&dev_list_lock); | |
1328 | } while (error == -EAGAIN); | |
1329 | ||
1330 | if (error) | |
1331 | index = -1; | |
1332 | return index; | |
1333 | } | |
1334 | ||
1335 | static void nvme_put_ns_idx(int index) | |
1336 | { | |
1337 | spin_lock(&dev_list_lock); | |
1338 | ida_remove(&nvme_index_ida, index); | |
1339 | spin_unlock(&dev_list_lock); | |
1340 | } | |
1341 | ||
1342 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid, | |
b60503ba MW |
1343 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1344 | { | |
1345 | struct nvme_ns *ns; | |
1346 | struct gendisk *disk; | |
1347 | int lbaf; | |
1348 | ||
1349 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1350 | return NULL; | |
1351 | ||
1352 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1353 | if (!ns) | |
1354 | return NULL; | |
1355 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1356 | if (!ns->queue) | |
1357 | goto out_free_ns; | |
4eeb9215 MW |
1358 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT; |
1359 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); | |
1360 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
1361 | /* queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */ | |
b60503ba MW |
1362 | blk_queue_make_request(ns->queue, nvme_make_request); |
1363 | ns->dev = dev; | |
1364 | ns->queue->queuedata = ns; | |
1365 | ||
1366 | disk = alloc_disk(NVME_MINORS); | |
1367 | if (!disk) | |
1368 | goto out_free_queue; | |
5aff9382 | 1369 | ns->ns_id = nsid; |
b60503ba MW |
1370 | ns->disk = disk; |
1371 | lbaf = id->flbas & 0xf; | |
1372 | ns->lba_shift = id->lbaf[lbaf].ds; | |
e9ef4636 | 1373 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
1374 | if (dev->max_hw_sectors) |
1375 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
b60503ba MW |
1376 | |
1377 | disk->major = nvme_major; | |
1378 | disk->minors = NVME_MINORS; | |
5aff9382 | 1379 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1380 | disk->fops = &nvme_fops; |
1381 | disk->private_data = ns; | |
1382 | disk->queue = ns->queue; | |
388f037f | 1383 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1384 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1385 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1386 | ||
1387 | return ns; | |
1388 | ||
1389 | out_free_queue: | |
1390 | blk_cleanup_queue(ns->queue); | |
1391 | out_free_ns: | |
1392 | kfree(ns); | |
1393 | return NULL; | |
1394 | } | |
1395 | ||
1396 | static void nvme_ns_free(struct nvme_ns *ns) | |
1397 | { | |
5aff9382 | 1398 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1399 | put_disk(ns->disk); |
5aff9382 | 1400 | nvme_put_ns_idx(index); |
b60503ba MW |
1401 | blk_cleanup_queue(ns->queue); |
1402 | kfree(ns); | |
1403 | } | |
1404 | ||
b3b06812 | 1405 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1406 | { |
1407 | int status; | |
1408 | u32 result; | |
b3b06812 | 1409 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1410 | |
df348139 | 1411 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 1412 | &result); |
b60503ba MW |
1413 | if (status) |
1414 | return -EIO; | |
1415 | return min(result & 0xffff, result >> 16) + 1; | |
1416 | } | |
1417 | ||
b60503ba MW |
1418 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1419 | { | |
a0cadb85 | 1420 | int result, cpu, i, nr_io_queues, db_bar_size, q_depth; |
b60503ba | 1421 | |
b348b7d5 MW |
1422 | nr_io_queues = num_online_cpus(); |
1423 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1424 | if (result < 0) |
1425 | return result; | |
b348b7d5 MW |
1426 | if (result < nr_io_queues) |
1427 | nr_io_queues = result; | |
b60503ba | 1428 | |
1b23484b MW |
1429 | /* Deregister the admin queue's interrupt */ |
1430 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1431 | ||
f1938f6e MW |
1432 | db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3)); |
1433 | if (db_bar_size > 8192) { | |
1434 | iounmap(dev->bar); | |
1435 | dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0), | |
1436 | db_bar_size); | |
1437 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1438 | dev->queues[0]->q_db = dev->dbs; | |
1439 | } | |
1440 | ||
b348b7d5 | 1441 | for (i = 0; i < nr_io_queues; i++) |
1b23484b MW |
1442 | dev->entry[i].entry = i; |
1443 | for (;;) { | |
b348b7d5 MW |
1444 | result = pci_enable_msix(dev->pci_dev, dev->entry, |
1445 | nr_io_queues); | |
1b23484b MW |
1446 | if (result == 0) { |
1447 | break; | |
1448 | } else if (result > 0) { | |
b348b7d5 | 1449 | nr_io_queues = result; |
1b23484b MW |
1450 | continue; |
1451 | } else { | |
b348b7d5 | 1452 | nr_io_queues = 1; |
1b23484b MW |
1453 | break; |
1454 | } | |
1455 | } | |
1456 | ||
1457 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1458 | /* XXX: handle failure here */ | |
1459 | ||
1460 | cpu = cpumask_first(cpu_online_mask); | |
b348b7d5 | 1461 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1462 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1463 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1464 | } | |
1465 | ||
a0cadb85 KB |
1466 | q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1, |
1467 | NVME_Q_DEPTH); | |
b348b7d5 | 1468 | for (i = 0; i < nr_io_queues; i++) { |
a0cadb85 | 1469 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i); |
6f0f5449 MW |
1470 | if (IS_ERR(dev->queues[i + 1])) |
1471 | return PTR_ERR(dev->queues[i + 1]); | |
1b23484b MW |
1472 | dev->queue_count++; |
1473 | } | |
b60503ba | 1474 | |
9ecdc946 MW |
1475 | for (; i < num_possible_cpus(); i++) { |
1476 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1477 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1478 | } | |
1479 | ||
b60503ba MW |
1480 | return 0; |
1481 | } | |
1482 | ||
1483 | static void nvme_free_queues(struct nvme_dev *dev) | |
1484 | { | |
1485 | int i; | |
1486 | ||
1487 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1488 | nvme_free_queue(dev, i); | |
1489 | } | |
1490 | ||
1491 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1492 | { | |
1493 | int res, nn, i; | |
1494 | struct nvme_ns *ns, *next; | |
51814232 | 1495 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
1496 | struct nvme_id_ns *id_ns; |
1497 | void *mem; | |
b60503ba | 1498 | dma_addr_t dma_addr; |
b60503ba MW |
1499 | |
1500 | res = nvme_setup_io_queues(dev); | |
1501 | if (res) | |
1502 | return res; | |
1503 | ||
bc5fc7e4 | 1504 | mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, |
b60503ba MW |
1505 | GFP_KERNEL); |
1506 | ||
bc5fc7e4 | 1507 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
1508 | if (res) { |
1509 | res = -EIO; | |
1510 | goto out_free; | |
1511 | } | |
1512 | ||
bc5fc7e4 | 1513 | ctrl = mem; |
51814232 MW |
1514 | nn = le32_to_cpup(&ctrl->nn); |
1515 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1516 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1517 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
8fc23e03 KB |
1518 | if (ctrl->mdts) { |
1519 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; | |
1520 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); | |
1521 | } | |
b60503ba | 1522 | |
bc5fc7e4 | 1523 | id_ns = mem; |
2b2c1896 | 1524 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 1525 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
1526 | if (res) |
1527 | continue; | |
1528 | ||
bc5fc7e4 | 1529 | if (id_ns->ncap == 0) |
b60503ba MW |
1530 | continue; |
1531 | ||
bc5fc7e4 | 1532 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
df348139 | 1533 | dma_addr + 4096); |
b60503ba MW |
1534 | if (res) |
1535 | continue; | |
1536 | ||
bc5fc7e4 | 1537 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
1538 | if (ns) |
1539 | list_add_tail(&ns->list, &dev->namespaces); | |
1540 | } | |
1541 | list_for_each_entry(ns, &dev->namespaces, list) | |
1542 | add_disk(ns->disk); | |
1543 | ||
bc5fc7e4 | 1544 | goto out; |
b60503ba MW |
1545 | |
1546 | out_free: | |
1547 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1548 | list_del(&ns->list); | |
1549 | nvme_ns_free(ns); | |
1550 | } | |
1551 | ||
bc5fc7e4 | 1552 | out: |
684f5c20 | 1553 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
1554 | return res; |
1555 | } | |
1556 | ||
1557 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1558 | { | |
1559 | struct nvme_ns *ns, *next; | |
1560 | ||
1fa6aead MW |
1561 | spin_lock(&dev_list_lock); |
1562 | list_del(&dev->node); | |
1563 | spin_unlock(&dev_list_lock); | |
1564 | ||
b60503ba MW |
1565 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { |
1566 | list_del(&ns->list); | |
1567 | del_gendisk(ns->disk); | |
1568 | nvme_ns_free(ns); | |
1569 | } | |
1570 | ||
1571 | nvme_free_queues(dev); | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
091b6092 MW |
1576 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1577 | { | |
1578 | struct device *dmadev = &dev->pci_dev->dev; | |
1579 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1580 | PAGE_SIZE, PAGE_SIZE, 0); | |
1581 | if (!dev->prp_page_pool) | |
1582 | return -ENOMEM; | |
1583 | ||
99802a7a MW |
1584 | /* Optimisation for I/Os between 4k and 128k */ |
1585 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1586 | 256, 256, 0); | |
1587 | if (!dev->prp_small_pool) { | |
1588 | dma_pool_destroy(dev->prp_page_pool); | |
1589 | return -ENOMEM; | |
1590 | } | |
091b6092 MW |
1591 | return 0; |
1592 | } | |
1593 | ||
1594 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1595 | { | |
1596 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1597 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1598 | } |
1599 | ||
cd58ad7d QSA |
1600 | static DEFINE_IDA(nvme_instance_ida); |
1601 | ||
1602 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 1603 | { |
cd58ad7d QSA |
1604 | int instance, error; |
1605 | ||
1606 | do { | |
1607 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
1608 | return -ENODEV; | |
1609 | ||
1610 | spin_lock(&dev_list_lock); | |
1611 | error = ida_get_new(&nvme_instance_ida, &instance); | |
1612 | spin_unlock(&dev_list_lock); | |
1613 | } while (error == -EAGAIN); | |
1614 | ||
1615 | if (error) | |
1616 | return -ENODEV; | |
1617 | ||
1618 | dev->instance = instance; | |
1619 | return 0; | |
b60503ba MW |
1620 | } |
1621 | ||
1622 | static void nvme_release_instance(struct nvme_dev *dev) | |
1623 | { | |
cd58ad7d QSA |
1624 | spin_lock(&dev_list_lock); |
1625 | ida_remove(&nvme_instance_ida, dev->instance); | |
1626 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
1627 | } |
1628 | ||
1629 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1630 | const struct pci_device_id *id) | |
1631 | { | |
574e8b95 | 1632 | int bars, result = -ENOMEM; |
b60503ba MW |
1633 | struct nvme_dev *dev; |
1634 | ||
1635 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1636 | if (!dev) | |
1637 | return -ENOMEM; | |
1638 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1639 | GFP_KERNEL); | |
1640 | if (!dev->entry) | |
1641 | goto free; | |
1b23484b MW |
1642 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1643 | GFP_KERNEL); | |
b60503ba MW |
1644 | if (!dev->queues) |
1645 | goto free; | |
1646 | ||
0ee5a7d7 SMM |
1647 | if (pci_enable_device_mem(pdev)) |
1648 | goto free; | |
f64d3365 | 1649 | pci_set_master(pdev); |
574e8b95 MW |
1650 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1651 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1652 | goto disable; | |
0ee5a7d7 | 1653 | |
b60503ba MW |
1654 | INIT_LIST_HEAD(&dev->namespaces); |
1655 | dev->pci_dev = pdev; | |
1656 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1657 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1658 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
cd58ad7d QSA |
1659 | result = nvme_set_instance(dev); |
1660 | if (result) | |
1661 | goto disable; | |
1662 | ||
53c9577e | 1663 | dev->entry[0].vector = pdev->irq; |
b60503ba | 1664 | |
091b6092 MW |
1665 | result = nvme_setup_prp_pools(dev); |
1666 | if (result) | |
1667 | goto disable_msix; | |
1668 | ||
b60503ba MW |
1669 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1670 | if (!dev->bar) { | |
1671 | result = -ENOMEM; | |
574e8b95 | 1672 | goto disable_msix; |
b60503ba MW |
1673 | } |
1674 | ||
1675 | result = nvme_configure_admin_queue(dev); | |
1676 | if (result) | |
1677 | goto unmap; | |
1678 | dev->queue_count++; | |
1679 | ||
1fa6aead MW |
1680 | spin_lock(&dev_list_lock); |
1681 | list_add(&dev->node, &dev_list); | |
1682 | spin_unlock(&dev_list_lock); | |
1683 | ||
740216fc MW |
1684 | result = nvme_dev_add(dev); |
1685 | if (result) | |
1686 | goto delete; | |
1687 | ||
b60503ba MW |
1688 | return 0; |
1689 | ||
1690 | delete: | |
740216fc MW |
1691 | spin_lock(&dev_list_lock); |
1692 | list_del(&dev->node); | |
1693 | spin_unlock(&dev_list_lock); | |
1694 | ||
b60503ba MW |
1695 | nvme_free_queues(dev); |
1696 | unmap: | |
1697 | iounmap(dev->bar); | |
574e8b95 | 1698 | disable_msix: |
b60503ba MW |
1699 | pci_disable_msix(pdev); |
1700 | nvme_release_instance(dev); | |
091b6092 | 1701 | nvme_release_prp_pools(dev); |
574e8b95 | 1702 | disable: |
0ee5a7d7 | 1703 | pci_disable_device(pdev); |
574e8b95 | 1704 | pci_release_regions(pdev); |
b60503ba MW |
1705 | free: |
1706 | kfree(dev->queues); | |
1707 | kfree(dev->entry); | |
1708 | kfree(dev); | |
1709 | return result; | |
1710 | } | |
1711 | ||
1712 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1713 | { | |
1714 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1715 | nvme_dev_remove(dev); | |
1716 | pci_disable_msix(pdev); | |
1717 | iounmap(dev->bar); | |
1718 | nvme_release_instance(dev); | |
091b6092 | 1719 | nvme_release_prp_pools(dev); |
0ee5a7d7 | 1720 | pci_disable_device(pdev); |
574e8b95 | 1721 | pci_release_regions(pdev); |
b60503ba MW |
1722 | kfree(dev->queues); |
1723 | kfree(dev->entry); | |
1724 | kfree(dev); | |
1725 | } | |
1726 | ||
1727 | /* These functions are yet to be implemented */ | |
1728 | #define nvme_error_detected NULL | |
1729 | #define nvme_dump_registers NULL | |
1730 | #define nvme_link_reset NULL | |
1731 | #define nvme_slot_reset NULL | |
1732 | #define nvme_error_resume NULL | |
1733 | #define nvme_suspend NULL | |
1734 | #define nvme_resume NULL | |
1735 | ||
1d352035 | 1736 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
1737 | .error_detected = nvme_error_detected, |
1738 | .mmio_enabled = nvme_dump_registers, | |
1739 | .link_reset = nvme_link_reset, | |
1740 | .slot_reset = nvme_slot_reset, | |
1741 | .resume = nvme_error_resume, | |
1742 | }; | |
1743 | ||
1744 | /* Move to pci_ids.h later */ | |
1745 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1746 | ||
1747 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1748 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1749 | { 0, } | |
1750 | }; | |
1751 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1752 | ||
1753 | static struct pci_driver nvme_driver = { | |
1754 | .name = "nvme", | |
1755 | .id_table = nvme_id_table, | |
1756 | .probe = nvme_probe, | |
1757 | .remove = __devexit_p(nvme_remove), | |
1758 | .suspend = nvme_suspend, | |
1759 | .resume = nvme_resume, | |
1760 | .err_handler = &nvme_err_handler, | |
1761 | }; | |
1762 | ||
1763 | static int __init nvme_init(void) | |
1764 | { | |
0ac13140 | 1765 | int result; |
1fa6aead MW |
1766 | |
1767 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1768 | if (IS_ERR(nvme_thread)) | |
1769 | return PTR_ERR(nvme_thread); | |
b60503ba | 1770 | |
5c42ea16 KB |
1771 | result = register_blkdev(nvme_major, "nvme"); |
1772 | if (result < 0) | |
1fa6aead | 1773 | goto kill_kthread; |
5c42ea16 | 1774 | else if (result > 0) |
0ac13140 | 1775 | nvme_major = result; |
b60503ba MW |
1776 | |
1777 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
1778 | if (result) |
1779 | goto unregister_blkdev; | |
1780 | return 0; | |
b60503ba | 1781 | |
1fa6aead | 1782 | unregister_blkdev: |
b60503ba | 1783 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
1784 | kill_kthread: |
1785 | kthread_stop(nvme_thread); | |
b60503ba MW |
1786 | return result; |
1787 | } | |
1788 | ||
1789 | static void __exit nvme_exit(void) | |
1790 | { | |
1791 | pci_unregister_driver(&nvme_driver); | |
1792 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 1793 | kthread_stop(nvme_thread); |
b60503ba MW |
1794 | } |
1795 | ||
1796 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1797 | MODULE_LICENSE("GPL"); | |
366e8217 | 1798 | MODULE_VERSION("0.8"); |
b60503ba MW |
1799 | module_init(nvme_init); |
1800 | module_exit(nvme_exit); |