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NVMe: Add discard support for capable devices
[linux-2.6-block.git] / drivers / block / nvme.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
fd63e9ce 23#include <linux/delay.h>
b60503ba
MW		 24#include <linux/errno.h>
25#include <linux/fs.h>
26#include <linux/genhd.h>
5aff9382 27#include <linux/idr.h>
b60503ba
MW		 28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/kdev_t.h>
1fa6aead 32#include <linux/kthread.h>
b60503ba
MW		 33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/pci.h>
be7b6275 38#include <linux/poison.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
b60503ba 42
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b60503ba
MW		 45#define NVME_Q_DEPTH 1024
46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
48#define NVME_MINORS 64
ff976d72 49#define NVME_IO_TIMEOUT (5 * HZ)
e85248e5 50#define ADMIN_TIMEOUT (60 * HZ)
b60503ba
MW		 51
52static int nvme_major;
53module_param(nvme_major, int, 0);
54
58ffacb5
MW		 55static int use_threaded_interrupts;
56module_param(use_threaded_interrupts, int, 0);
57
1fa6aead
MW		 58static DEFINE_SPINLOCK(dev_list_lock);
59static LIST_HEAD(dev_list);
60static struct task_struct *nvme_thread;
61
b60503ba
MW		 62/*
63 * Represents an NVM Express device. Each nvme_dev is a PCI function.
64 */
65struct nvme_dev {
1fa6aead 66 struct list_head node;
b60503ba
MW		 67 struct nvme_queue **queues;
68 u32 __iomem *dbs;
69 struct pci_dev *pci_dev;
091b6092 70 struct dma_pool *prp_page_pool;
99802a7a 71 struct dma_pool *prp_small_pool;
b60503ba
MW		 72 int instance;
73 int queue_count;
f1938f6e 74 int db_stride;
b60503ba
MW		 75 u32 ctrl_config;
76 struct msix_entry *entry;
77 struct nvme_bar __iomem *bar;
78 struct list_head namespaces;
51814232
MW		 79 char serial[20];
80 char model[40];
81 char firmware_rev[8];
8fc23e03 82 u32 max_hw_sectors;
0e5e4f0e 83 u16 oncs;
b60503ba
MW		 84};
85
86/*
87 * An NVM Express namespace is equivalent to a SCSI LUN
88 */
89struct nvme_ns {
90 struct list_head list;
91
92 struct nvme_dev *dev;
93 struct request_queue *queue;
94 struct gendisk *disk;
95
96 int ns_id;
97 int lba_shift;
98};
99
100/*
101 * An NVM Express queue. Each device has at least two (one for admin
102 * commands and one for I/O commands).
103 */
104struct nvme_queue {
105 struct device *q_dmadev;
091b6092 106 struct nvme_dev *dev;
b60503ba
MW		 107 spinlock_t q_lock;
108 struct nvme_command *sq_cmds;
109 volatile struct nvme_completion *cqes;
110 dma_addr_t sq_dma_addr;
111 dma_addr_t cq_dma_addr;
112 wait_queue_head_t sq_full;
1fa6aead 113 wait_queue_t sq_cong_wait;
b60503ba
MW		 114 struct bio_list sq_cong;
115 u32 __iomem *q_db;
116 u16 q_depth;
117 u16 cq_vector;
118 u16 sq_head;
119 u16 sq_tail;
120 u16 cq_head;
82123460 121 u16 cq_phase;
b60503ba
MW		 122 unsigned long cmdid_data[];
123};
124
125/*
126 * Check we didin't inadvertently grow the command struct
127 */
128static inline void _nvme_check_size(void)
129{
130 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
131 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
132 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
135 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
136 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
137 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
138 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 139 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 140}
141
5c1281a3 142typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
c2f5b650
MW		 143 struct nvme_completion *);
144
e85248e5 145struct nvme_cmd_info {
c2f5b650
MW		 146 nvme_completion_fn fn;
147 void *ctx;
e85248e5
MW		 148 unsigned long timeout;
149};
150
151static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
152{
153 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
154}
155
b60503ba 156/**
714a7a22
MW		 157 * alloc_cmdid() - Allocate a Command ID
158 * @nvmeq: The queue that will be used for this command
159 * @ctx: A pointer that will be passed to the handler
c2f5b650 160 * @handler: The function to call on completion
b60503ba
MW		 161 *
162 * Allocate a Command ID for a queue. The data passed in will
163 * be passed to the completion handler. This is implemented by using
164 * the bottom two bits of the ctx pointer to store the handler ID.
165 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
166 * We can change this if it becomes a problem.
184d2944
MW		 167 *
168 * May be called with local interrupts disabled and the q_lock held,
169 * or with interrupts enabled and no locks held.
b60503ba 170 */
c2f5b650
MW		 171static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
172 nvme_completion_fn handler, unsigned timeout)
b60503ba 173{
e6d15f79 174 int depth = nvmeq->q_depth - 1;
e85248e5 175 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 176 int cmdid;
177
b60503ba
MW		 178 do {
179 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
180 if (cmdid >= depth)
181 return -EBUSY;
182 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
183
c2f5b650
MW		 184 info[cmdid].fn = handler;
185 info[cmdid].ctx = ctx;
e85248e5 186 info[cmdid].timeout = jiffies + timeout;
b60503ba
MW		 187 return cmdid;
188}
189
190static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 191 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 192{
193 int cmdid;
194 wait_event_killable(nvmeq->sq_full,
e85248e5 195 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 196 return (cmdid < 0) ? -EINTR : cmdid;
197}
198
c2f5b650
MW		 199/* Special values must be less than 0x1000 */
200#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 201#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
202#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
203#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 204#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
be7b6275 205
5c1281a3 206static void special_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 207 struct nvme_completion *cqe)
208{
209 if (ctx == CMD_CTX_CANCELLED)
210 return;
211 if (ctx == CMD_CTX_FLUSH)
212 return;
213 if (ctx == CMD_CTX_COMPLETED) {
5c1281a3 214 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 215 "completed id %d twice on queue %d\n",
216 cqe->command_id, le16_to_cpup(&cqe->sq_id));
217 return;
218 }
219 if (ctx == CMD_CTX_INVALID) {
5c1281a3 220 dev_warn(&dev->pci_dev->dev,
c2f5b650
MW		 221 "invalid id %d completed on queue %d\n",
222 cqe->command_id, le16_to_cpup(&cqe->sq_id));
223 return;
224 }
225
5c1281a3 226 dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 227}
228
184d2944
MW		 229/*
230 * Called with local interrupts disabled and the q_lock held. May not sleep.
231 */
c2f5b650
MW		 232static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
233 nvme_completion_fn *fn)
b60503ba 234{
c2f5b650 235 void *ctx;
e85248e5 236 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 237
c2f5b650
MW		 238 if (cmdid >= nvmeq->q_depth) {
239 *fn = special_completion;
48e3d398 240 return CMD_CTX_INVALID;
c2f5b650 241 }
859361a2
KB		 242 if (fn)
243 *fn = info[cmdid].fn;
c2f5b650
MW		 244 ctx = info[cmdid].ctx;
245 info[cmdid].fn = special_completion;
e85248e5 246 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 247 clear_bit(cmdid, nvmeq->cmdid_data);
248 wake_up(&nvmeq->sq_full);
c2f5b650 249 return ctx;
b60503ba
MW		 250}
251
c2f5b650
MW		 252static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
253 nvme_completion_fn *fn)
3c0cf138 254{
c2f5b650 255 void *ctx;
e85248e5 256 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 257 if (fn)
258 *fn = info[cmdid].fn;
259 ctx = info[cmdid].ctx;
260 info[cmdid].fn = special_completion;
e85248e5 261 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 262 return ctx;
3c0cf138
MW		 263}
264
040a93b5 265static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
b60503ba 266{
040a93b5 267 return dev->queues[get_cpu() + 1];
b60503ba
MW		 268}
269
270static void put_nvmeq(struct nvme_queue *nvmeq)
271{
1b23484b 272 put_cpu();
b60503ba
MW		 273}
274
275/**
714a7a22 276 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 277 * @nvmeq: The queue to use
278 * @cmd: The command to send
279 *
280 * Safe to use from interrupt context
281 */
282static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
283{
284 unsigned long flags;
285 u16 tail;
b60503ba
MW		 286 spin_lock_irqsave(&nvmeq->q_lock, flags);
287 tail = nvmeq->sq_tail;
288 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 289 if (++tail == nvmeq->q_depth)
290 tail = 0;
7547881d 291 writel(tail, nvmeq->q_db);
b60503ba
MW		 292 nvmeq->sq_tail = tail;
293 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
294
295 return 0;
296}
297
eca18b23
MW		 298/*
299 * The nvme_iod describes the data in an I/O, including the list of PRP
300 * entries. You can't see it in this data structure because C doesn't let
301 * me express that. Use nvme_alloc_iod to ensure there's enough space
302 * allocated to store the PRP list.
303 */
304struct nvme_iod {
305 void *private; /* For the use of the submitter of the I/O */
306 int npages; /* In the PRP list. 0 means small pool in use */
307 int offset; /* Of PRP list */
308 int nents; /* Used in scatterlist */
309 int length; /* Of data, in bytes */
e025344c 310 dma_addr_t first_dma;
eca18b23 311 struct scatterlist sg[0];
e025344c
SMM		 312};
313
eca18b23 314static __le64 **iod_list(struct nvme_iod *iod)
e025344c 315{
eca18b23 316 return ((void *)iod) + iod->offset;
e025344c
SMM		 317}
318
eca18b23
MW		 319/*
320 * Will slightly overestimate the number of pages needed. This is OK
321 * as it only leads to a small amount of wasted memory for the lifetime of
322 * the I/O.
323 */
324static int nvme_npages(unsigned size)
325{
326 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
327 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
328}
b60503ba 329
eca18b23
MW		 330static struct nvme_iod *
331nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 332{
eca18b23
MW		 333 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
334 sizeof(__le64 *) * nvme_npages(nbytes) +
335 sizeof(struct scatterlist) * nseg, gfp);
336
337 if (iod) {
338 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
339 iod->npages = -1;
340 iod->length = nbytes;
2b196034 341 iod->nents = 0;
eca18b23
MW		 342 }
343
344 return iod;
b60503ba
MW		 345}
346
eca18b23 347static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 348{
eca18b23
MW		 349 const int last_prp = PAGE_SIZE / 8 - 1;
350 int i;
351 __le64 **list = iod_list(iod);
352 dma_addr_t prp_dma = iod->first_dma;
353
354 if (iod->npages == 0)
355 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
356 for (i = 0; i < iod->npages; i++) {
357 __le64 *prp_list = list[i];
358 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
359 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
360 prp_dma = next_prp_dma;
361 }
362 kfree(iod);
b60503ba
MW		 363}
364
5c1281a3
MW		 365static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
366{
367 struct nvme_queue *nvmeq = get_nvmeq(dev);
368 if (bio_list_empty(&nvmeq->sq_cong))
369 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
370 bio_list_add(&nvmeq->sq_cong, bio);
371 put_nvmeq(nvmeq);
372 wake_up_process(nvme_thread);
373}
374
375static void bio_completion(struct nvme_dev *dev, void *ctx,
b60503ba
MW		 376 struct nvme_completion *cqe)
377{
eca18b23
MW		 378 struct nvme_iod *iod = ctx;
379 struct bio *bio = iod->private;
b60503ba
MW		 380 u16 status = le16_to_cpup(&cqe->status) >> 1;
381
2b196034
KB		 382 if (iod->nents)
383 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
b60503ba 384 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
eca18b23 385 nvme_free_iod(dev, iod);
09a58f53 386 if (status) {
1ad2f893 387 bio_endio(bio, -EIO);
09a58f53 388 } else if (bio->bi_vcnt > bio->bi_idx) {
5c1281a3 389 requeue_bio(dev, bio);
1ad2f893
MW		 390 } else {
391 bio_endio(bio, 0);
392 }
b60503ba
MW		 393}
394
184d2944 395/* length is in bytes. gfp flags indicates whether we may sleep. */
eca18b23
MW		 396static int nvme_setup_prps(struct nvme_dev *dev,
397 struct nvme_common_command *cmd, struct nvme_iod *iod,
398 int total_len, gfp_t gfp)
ff22b54f 399{
99802a7a 400 struct dma_pool *pool;
eca18b23
MW		 401 int length = total_len;
402 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 403 int dma_len = sg_dma_len(sg);
404 u64 dma_addr = sg_dma_address(sg);
405 int offset = offset_in_page(dma_addr);
e025344c 406 __le64 *prp_list;
eca18b23 407 __le64 **list = iod_list(iod);
e025344c 408 dma_addr_t prp_dma;
eca18b23 409 int nprps, i;
ff22b54f
MW		 410
411 cmd->prp1 = cpu_to_le64(dma_addr);
412 length -= (PAGE_SIZE - offset);
413 if (length <= 0)
eca18b23 414 return total_len;
ff22b54f
MW		 415
416 dma_len -= (PAGE_SIZE - offset);
417 if (dma_len) {
418 dma_addr += (PAGE_SIZE - offset);
419 } else {
420 sg = sg_next(sg);
421 dma_addr = sg_dma_address(sg);
422 dma_len = sg_dma_len(sg);
423 }
424
425 if (length <= PAGE_SIZE) {
426 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23 427 return total_len;
e025344c
SMM		 428 }
429
430 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 431 if (nprps <= (256 / 8)) {
432 pool = dev->prp_small_pool;
eca18b23 433 iod->npages = 0;
99802a7a
MW		 434 } else {
435 pool = dev->prp_page_pool;
eca18b23 436 iod->npages = 1;
99802a7a
MW		 437 }
438
b77954cb
MW		 439 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
440 if (!prp_list) {
441 cmd->prp2 = cpu_to_le64(dma_addr);
eca18b23
MW		 442 iod->npages = -1;
443 return (total_len - length) + PAGE_SIZE;
b77954cb 444 }
eca18b23
MW		 445 list[0] = prp_list;
446 iod->first_dma = prp_dma;
e025344c
SMM		 447 cmd->prp2 = cpu_to_le64(prp_dma);
448 i = 0;
449 for (;;) {
7523d834 450 if (i == PAGE_SIZE / 8) {
e025344c 451 __le64 *old_prp_list = prp_list;
b77954cb 452 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 453 if (!prp_list)
454 return total_len - length;
455 list[iod->npages++] = prp_list;
7523d834
MW		 456 prp_list[0] = old_prp_list[i - 1];
457 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
458 i = 1;
e025344c
SMM		 459 }
460 prp_list[i++] = cpu_to_le64(dma_addr);
461 dma_len -= PAGE_SIZE;
462 dma_addr += PAGE_SIZE;
463 length -= PAGE_SIZE;
464 if (length <= 0)
465 break;
466 if (dma_len > 0)
467 continue;
468 BUG_ON(dma_len < 0);
469 sg = sg_next(sg);
470 dma_addr = sg_dma_address(sg);
471 dma_len = sg_dma_len(sg);
ff22b54f
MW		 472 }
473
eca18b23 474 return total_len;
ff22b54f
MW		 475}
476
1ad2f893
MW		 477/* NVMe scatterlists require no holes in the virtual address */
478#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
479 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
480
eca18b23 481static int nvme_map_bio(struct device *dev, struct nvme_iod *iod,
b60503ba
MW		 482 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
483{
76830840
MW		 484 struct bio_vec *bvec, *bvprv = NULL;
485 struct scatterlist *sg = NULL;
1ad2f893 486 int i, old_idx, length = 0, nsegs = 0;
b60503ba 487
eca18b23 488 sg_init_table(iod->sg, psegs);
1ad2f893 489 old_idx = bio->bi_idx;
b60503ba 490 bio_for_each_segment(bvec, bio, i) {
76830840
MW		 491 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
492 sg->length += bvec->bv_len;
493 } else {
1ad2f893
MW		 494 if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
495 break;
eca18b23 496 sg = sg ? sg + 1 : iod->sg;
76830840
MW		 497 sg_set_page(sg, bvec->bv_page, bvec->bv_len,
498 bvec->bv_offset);
499 nsegs++;
500 }
1ad2f893 501 length += bvec->bv_len;
76830840 502 bvprv = bvec;
b60503ba 503 }
1ad2f893 504 bio->bi_idx = i;
eca18b23 505 iod->nents = nsegs;
76830840 506 sg_mark_end(sg);
eca18b23 507 if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) {
1ad2f893
MW		 508 bio->bi_idx = old_idx;
509 return -ENOMEM;
510 }
511 return length;
b60503ba
MW		 512}
513
0e5e4f0e
KB		 514/*
515 * We reuse the small pool to allocate the 16-byte range here as it is not
516 * worth having a special pool for these or additional cases to handle freeing
517 * the iod.
518 */
519static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
520 struct bio *bio, struct nvme_iod *iod, int cmdid)
521{
522 struct nvme_dsm_range *range;
523 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
524
525 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC,
526 &iod->first_dma);
527 if (!range)
528 return -ENOMEM;
529
530 iod_list(iod)[0] = (__le64 *)range;
531 iod->npages = 0;
532
533 range->cattr = cpu_to_le32(0);
534 range->nlb = cpu_to_le32(bio->bi_size >> ns->lba_shift);
535 range->slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
536
537 memset(cmnd, 0, sizeof(*cmnd));
538 cmnd->dsm.opcode = nvme_cmd_dsm;
539 cmnd->dsm.command_id = cmdid;
540 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
541 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
542 cmnd->dsm.nr = 0;
543 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
544
545 if (++nvmeq->sq_tail == nvmeq->q_depth)
546 nvmeq->sq_tail = 0;
547 writel(nvmeq->sq_tail, nvmeq->q_db);
548
549 return 0;
550}
551
00df5cb4
MW		 552static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
553 int cmdid)
554{
555 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
556
557 memset(cmnd, 0, sizeof(*cmnd));
558 cmnd->common.opcode = nvme_cmd_flush;
559 cmnd->common.command_id = cmdid;
560 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
561
562 if (++nvmeq->sq_tail == nvmeq->q_depth)
563 nvmeq->sq_tail = 0;
564 writel(nvmeq->sq_tail, nvmeq->q_db);
565
566 return 0;
567}
568
569static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
570{
571 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 572 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 573 if (unlikely(cmdid < 0))
574 return cmdid;
575
576 return nvme_submit_flush(nvmeq, ns, cmdid);
577}
578
184d2944
MW		 579/*
580 * Called with local interrupts disabled and the q_lock held. May not sleep.
581 */
b60503ba
MW		 582static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
583 struct bio *bio)
584{
ff22b54f 585 struct nvme_command *cmnd;
eca18b23 586 struct nvme_iod *iod;
b60503ba 587 enum dma_data_direction dma_dir;
1ad2f893 588 int cmdid, length, result = -ENOMEM;
b60503ba
MW		 589 u16 control;
590 u32 dsmgmt;
b60503ba
MW		 591 int psegs = bio_phys_segments(ns->queue, bio);
592
00df5cb4
MW		 593 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
594 result = nvme_submit_flush_data(nvmeq, ns);
595 if (result)
596 return result;
597 }
598
eca18b23
MW		 599 iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
600 if (!iod)
eeee3226 601 goto nomem;
eca18b23 602 iod->private = bio;
b60503ba 603
eeee3226 604 result = -EBUSY;
ff976d72 605 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 606 if (unlikely(cmdid < 0))
eca18b23 607 goto free_iod;
b60503ba 608
0e5e4f0e
KB		 609 if (bio->bi_rw & REQ_DISCARD) {
610 result = nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
611 if (result)
612 goto free_cmdid;
613 return result;
614 }
00df5cb4
MW		 615 if ((bio->bi_rw & REQ_FLUSH) && !psegs)
616 return nvme_submit_flush(nvmeq, ns, cmdid);
617
b60503ba
MW		 618 control = 0;
619 if (bio->bi_rw & REQ_FUA)
620 control |= NVME_RW_FUA;
621 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
622 control |= NVME_RW_LR;
623
624 dsmgmt = 0;
625 if (bio->bi_rw & REQ_RAHEAD)
626 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
627
ff22b54f 628 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b60503ba 629
b8deb62c 630 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 631 if (bio_data_dir(bio)) {
ff22b54f 632 cmnd->rw.opcode = nvme_cmd_write;
b60503ba
MW		 633 dma_dir = DMA_TO_DEVICE;
634 } else {
ff22b54f 635 cmnd->rw.opcode = nvme_cmd_read;
b60503ba
MW		 636 dma_dir = DMA_FROM_DEVICE;
637 }
638
eca18b23 639 result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs);
1ad2f893 640 if (result < 0)
859361a2 641 goto free_cmdid;
1ad2f893 642 length = result;
b60503ba 643
ff22b54f
MW		 644 cmnd->rw.command_id = cmdid;
645 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
eca18b23
MW		 646 length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
647 GFP_ATOMIC);
ff22b54f 648 cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
1ad2f893 649 cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
ff22b54f
MW		 650 cmnd->rw.control = cpu_to_le16(control);
651 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 652
d8ee9d69
MW		 653 bio->bi_sector += length >> 9;
654
b60503ba
MW		 655 if (++nvmeq->sq_tail == nvmeq->q_depth)
656 nvmeq->sq_tail = 0;
7547881d 657 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 658
1974b1ae
MW		 659 return 0;
660
859361a2
KB		 661 free_cmdid:
662 free_cmdid(nvmeq, cmdid, NULL);
eca18b23
MW		 663 free_iod:
664 nvme_free_iod(nvmeq->dev, iod);
eeee3226
MW		 665 nomem:
666 return result;
b60503ba
MW		 667}
668
93c3d65b 669static void nvme_make_request(struct request_queue *q, struct bio *bio)
b60503ba
MW		 670{
671 struct nvme_ns *ns = q->queuedata;
040a93b5 672 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
eeee3226
MW		 673 int result = -EBUSY;
674
675 spin_lock_irq(&nvmeq->q_lock);
676 if (bio_list_empty(&nvmeq->sq_cong))
677 result = nvme_submit_bio_queue(nvmeq, ns, bio);
678 if (unlikely(result)) {
679 if (bio_list_empty(&nvmeq->sq_cong))
680 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
b60503ba
MW		 681 bio_list_add(&nvmeq->sq_cong, bio);
682 }
eeee3226
MW		 683
684 spin_unlock_irq(&nvmeq->q_lock);
b60503ba 685 put_nvmeq(nvmeq);
b60503ba
MW		 686}
687
b60503ba
MW		 688static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
689{
82123460 690 u16 head, phase;
b60503ba 691
b60503ba 692 head = nvmeq->cq_head;
82123460 693 phase = nvmeq->cq_phase;
b60503ba
MW		 694
695 for (;;) {
c2f5b650
MW		 696 void *ctx;
697 nvme_completion_fn fn;
b60503ba 698 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 699 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 700 break;
701 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
702 if (++head == nvmeq->q_depth) {
703 head = 0;
82123460 704 phase = !phase;
b60503ba
MW		 705 }
706
c2f5b650 707 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
5c1281a3 708 fn(nvmeq->dev, ctx, &cqe);
b60503ba
MW		 709 }
710
711 /* If the controller ignores the cq head doorbell and continuously
712 * writes to the queue, it is theoretically possible to wrap around
713 * the queue twice and mistakenly return IRQ_NONE. Linux only
714 * requires that 0.1% of your interrupts are handled, so this isn't
715 * a big problem.
716 */
82123460 717 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
b60503ba
MW		 718 return IRQ_NONE;
719
f1938f6e 720 writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
b60503ba 721 nvmeq->cq_head = head;
82123460 722 nvmeq->cq_phase = phase;
b60503ba
MW		 723
724 return IRQ_HANDLED;
725}
726
727static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 728{
729 irqreturn_t result;
730 struct nvme_queue *nvmeq = data;
731 spin_lock(&nvmeq->q_lock);
732 result = nvme_process_cq(nvmeq);
733 spin_unlock(&nvmeq->q_lock);
734 return result;
735}
736
737static irqreturn_t nvme_irq_check(int irq, void *data)
738{
739 struct nvme_queue *nvmeq = data;
740 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
741 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
742 return IRQ_NONE;
743 return IRQ_WAKE_THREAD;
744}
745
3c0cf138
MW		 746static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
747{
748 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 749 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 750 spin_unlock_irq(&nvmeq->q_lock);
751}
752
c2f5b650
MW		 753struct sync_cmd_info {
754 struct task_struct *task;
755 u32 result;
756 int status;
757};
758
5c1281a3 759static void sync_completion(struct nvme_dev *dev, void *ctx,
c2f5b650
MW		 760 struct nvme_completion *cqe)
761{
762 struct sync_cmd_info *cmdinfo = ctx;
763 cmdinfo->result = le32_to_cpup(&cqe->result);
764 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
765 wake_up_process(cmdinfo->task);
766}
767
b60503ba
MW		 768/*
769 * Returns 0 on success. If the result is negative, it's a Linux error code;
770 * if the result is positive, it's an NVM Express status code
771 */
3c0cf138 772static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
e85248e5 773 struct nvme_command *cmd, u32 *result, unsigned timeout)
b60503ba
MW		 774{
775 int cmdid;
776 struct sync_cmd_info cmdinfo;
777
778 cmdinfo.task = current;
779 cmdinfo.status = -EINTR;
780
c2f5b650 781 cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
e85248e5 782 timeout);
b60503ba
MW		 783 if (cmdid < 0)
784 return cmdid;
785 cmd->common.command_id = cmdid;
786
3c0cf138
MW		 787 set_current_state(TASK_KILLABLE);
788 nvme_submit_cmd(nvmeq, cmd);
b60503ba
MW		 789 schedule();
790
3c0cf138
MW		 791 if (cmdinfo.status == -EINTR) {
792 nvme_abort_command(nvmeq, cmdid);
793 return -EINTR;
794 }
795
b60503ba
MW		 796 if (result)
797 *result = cmdinfo.result;
798
799 return cmdinfo.status;
800}
801
802static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
803 u32 *result)
804{
e85248e5 805 return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 806}
807
808static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
809{
810 int status;
811 struct nvme_command c;
812
813 memset(&c, 0, sizeof(c));
814 c.delete_queue.opcode = opcode;
815 c.delete_queue.qid = cpu_to_le16(id);
816
817 status = nvme_submit_admin_cmd(dev, &c, NULL);
818 if (status)
819 return -EIO;
820 return 0;
821}
822
823static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
824 struct nvme_queue *nvmeq)
825{
826 int status;
827 struct nvme_command c;
828 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
829
830 memset(&c, 0, sizeof(c));
831 c.create_cq.opcode = nvme_admin_create_cq;
832 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
833 c.create_cq.cqid = cpu_to_le16(qid);
834 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
835 c.create_cq.cq_flags = cpu_to_le16(flags);
836 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
837
838 status = nvme_submit_admin_cmd(dev, &c, NULL);
839 if (status)
840 return -EIO;
841 return 0;
842}
843
844static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
845 struct nvme_queue *nvmeq)
846{
847 int status;
848 struct nvme_command c;
849 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
850
851 memset(&c, 0, sizeof(c));
852 c.create_sq.opcode = nvme_admin_create_sq;
853 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
854 c.create_sq.sqid = cpu_to_le16(qid);
855 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
856 c.create_sq.sq_flags = cpu_to_le16(flags);
857 c.create_sq.cqid = cpu_to_le16(qid);
858
859 status = nvme_submit_admin_cmd(dev, &c, NULL);
860 if (status)
861 return -EIO;
862 return 0;
863}
864
865static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
866{
867 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
868}
869
870static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
871{
872 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
873}
874
bc5fc7e4
MW		 875static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
876 dma_addr_t dma_addr)
877{
878 struct nvme_command c;
879
880 memset(&c, 0, sizeof(c));
881 c.identify.opcode = nvme_admin_identify;
882 c.identify.nsid = cpu_to_le32(nsid);
883 c.identify.prp1 = cpu_to_le64(dma_addr);
884 c.identify.cns = cpu_to_le32(cns);
885
886 return nvme_submit_admin_cmd(dev, &c, NULL);
887}
888
08df1e05
KB		 889static int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
890 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 891{
892 struct nvme_command c;
893
894 memset(&c, 0, sizeof(c));
895 c.features.opcode = nvme_admin_get_features;
a42cecce 896 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 897 c.features.prp1 = cpu_to_le64(dma_addr);
898 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 899
08df1e05 900 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 901}
902
903static int nvme_set_features(struct nvme_dev *dev, unsigned fid,
904 unsigned dword11, dma_addr_t dma_addr, u32 *result)
905{
906 struct nvme_command c;
907
908 memset(&c, 0, sizeof(c));
909 c.features.opcode = nvme_admin_set_features;
910 c.features.prp1 = cpu_to_le64(dma_addr);
911 c.features.fid = cpu_to_le32(fid);
912 c.features.dword11 = cpu_to_le32(dword11);
913
bc5fc7e4
MW		 914 return nvme_submit_admin_cmd(dev, &c, result);
915}
916
a09115b2
MW		 917/**
918 * nvme_cancel_ios - Cancel outstanding I/Os
919 * @queue: The queue to cancel I/Os on
920 * @timeout: True to only cancel I/Os which have timed out
921 */
922static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
923{
924 int depth = nvmeq->q_depth - 1;
925 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
926 unsigned long now = jiffies;
927 int cmdid;
928
929 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
930 void *ctx;
931 nvme_completion_fn fn;
932 static struct nvme_completion cqe = {
933 .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1,
934 };
935
936 if (timeout && !time_after(now, info[cmdid].timeout))
937 continue;
938 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
939 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
940 fn(nvmeq->dev, ctx, &cqe);
941 }
942}
943
9e866774
MW		 944static void nvme_free_queue_mem(struct nvme_queue *nvmeq)
945{
946 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
947 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
948 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
949 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
950 kfree(nvmeq);
951}
952
b60503ba
MW		 953static void nvme_free_queue(struct nvme_dev *dev, int qid)
954{
955 struct nvme_queue *nvmeq = dev->queues[qid];
aba2080f 956 int vector = dev->entry[nvmeq->cq_vector].vector;
b60503ba 957
a09115b2
MW		 958 spin_lock_irq(&nvmeq->q_lock);
959 nvme_cancel_ios(nvmeq, false);
3295874b
KB		 960 while (bio_list_peek(&nvmeq->sq_cong)) {
961 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
962 bio_endio(bio, -EIO);
963 }
a09115b2
MW		 964 spin_unlock_irq(&nvmeq->q_lock);
965
aba2080f
MW		 966 irq_set_affinity_hint(vector, NULL);
967 free_irq(vector, nvmeq);
b60503ba
MW		 968
969 /* Don't tell the adapter to delete the admin queue */
970 if (qid) {
971 adapter_delete_sq(dev, qid);
972 adapter_delete_cq(dev, qid);
973 }
974
9e866774 975 nvme_free_queue_mem(nvmeq);
b60503ba
MW		 976}
977
978static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
979 int depth, int vector)
980{
981 struct device *dmadev = &dev->pci_dev->dev;
a0cadb85
KB		 982 unsigned extra = DIV_ROUND_UP(depth, 8) + (depth *
983 sizeof(struct nvme_cmd_info));
b60503ba
MW		 984 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
985 if (!nvmeq)
986 return NULL;
987
988 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
989 &nvmeq->cq_dma_addr, GFP_KERNEL);
990 if (!nvmeq->cqes)
991 goto free_nvmeq;
992 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
993
994 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
995 &nvmeq->sq_dma_addr, GFP_KERNEL);
996 if (!nvmeq->sq_cmds)
997 goto free_cqdma;
998
999 nvmeq->q_dmadev = dmadev;
091b6092 1000 nvmeq->dev = dev;
b60503ba
MW		 1001 spin_lock_init(&nvmeq->q_lock);
1002 nvmeq->cq_head = 0;
82123460 1003 nvmeq->cq_phase = 1;
b60503ba 1004 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1005 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1006 bio_list_init(&nvmeq->sq_cong);
f1938f6e 1007 nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
b60503ba
MW		 1008 nvmeq->q_depth = depth;
1009 nvmeq->cq_vector = vector;
1010
1011 return nvmeq;
1012
1013 free_cqdma:
1014 dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
1015 nvmeq->cq_dma_addr);
1016 free_nvmeq:
1017 kfree(nvmeq);
1018 return NULL;
1019}
1020
3001082c
MW		 1021static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1022 const char *name)
1023{
58ffacb5
MW		 1024 if (use_threaded_interrupts)
1025 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
ec6ce618 1026 nvme_irq_check, nvme_irq,
58ffacb5
MW		 1027 IRQF_DISABLED | IRQF_SHARED,
1028 name, nvmeq);
3001082c
MW		 1029 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1030 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
1031}
1032
8d85fce7
GKH		 1033static struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, int qid,
1034 int cq_size, int vector)
b60503ba
MW		 1035{
1036 int result;
1037 struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
1038
3f85d50b 1039 if (!nvmeq)
6f0f5449 1040 return ERR_PTR(-ENOMEM);
3f85d50b 1041
b60503ba
MW		 1042 result = adapter_alloc_cq(dev, qid, nvmeq);
1043 if (result < 0)
1044 goto free_nvmeq;
1045
1046 result = adapter_alloc_sq(dev, qid, nvmeq);
1047 if (result < 0)
1048 goto release_cq;
1049
3001082c 1050 result = queue_request_irq(dev, nvmeq, "nvme");
b60503ba
MW		 1051 if (result < 0)
1052 goto release_sq;
1053
1054 return nvmeq;
1055
1056 release_sq:
1057 adapter_delete_sq(dev, qid);
1058 release_cq:
1059 adapter_delete_cq(dev, qid);
1060 free_nvmeq:
1061 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1062 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1063 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1064 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1065 kfree(nvmeq);
6f0f5449 1066 return ERR_PTR(result);
b60503ba
MW		 1067}
1068
8d85fce7 1069static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1070{
9e866774 1071 int result = 0;
b60503ba 1072 u32 aqa;
22605f96
MW		 1073 u64 cap;
1074 unsigned long timeout;
b60503ba
MW		 1075 struct nvme_queue *nvmeq;
1076
1077 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1078
1079 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
3f85d50b
MW		 1080 if (!nvmeq)
1081 return -ENOMEM;
b60503ba
MW		 1082
1083 aqa = nvmeq->q_depth - 1;
1084 aqa |= aqa << 16;
1085
1086 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1087 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1088 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1089 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba 1090
5911f200 1091 writel(0, &dev->bar->cc);
b60503ba
MW		 1092 writel(aqa, &dev->bar->aqa);
1093 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1094 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1095 writel(dev->ctrl_config, &dev->bar->cc);
1096
22605f96
MW		 1097 cap = readq(&dev->bar->cap);
1098 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
f1938f6e 1099 dev->db_stride = NVME_CAP_STRIDE(cap);
22605f96 1100
9e866774 1101 while (!result && !(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
b60503ba
MW		 1102 msleep(100);
1103 if (fatal_signal_pending(current))
9e866774 1104 result = -EINTR;
22605f96
MW		 1105 if (time_after(jiffies, timeout)) {
1106 dev_err(&dev->pci_dev->dev,
1107 "Device not ready; aborting initialisation\n");
9e866774 1108 result = -ENODEV;
22605f96 1109 }
b60503ba
MW		 1110 }
1111
9e866774
MW		 1112 if (result) {
1113 nvme_free_queue_mem(nvmeq);
1114 return result;
1115 }
1116
3001082c 1117 result = queue_request_irq(dev, nvmeq, "nvme admin");
b60503ba
MW		 1118 dev->queues[0] = nvmeq;
1119 return result;
1120}
1121
eca18b23
MW		 1122static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1123 unsigned long addr, unsigned length)
b60503ba 1124{
36c14ed9 1125 int i, err, count, nents, offset;
7fc3cdab
MW		 1126 struct scatterlist *sg;
1127 struct page **pages;
eca18b23 1128 struct nvme_iod *iod;
36c14ed9
MW		 1129
1130 if (addr & 3)
eca18b23 1131 return ERR_PTR(-EINVAL);
7fc3cdab 1132 if (!length)
eca18b23 1133 return ERR_PTR(-EINVAL);
7fc3cdab 1134
36c14ed9 1135 offset = offset_in_page(addr);
7fc3cdab
MW		 1136 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1137 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1138 if (!pages)
1139 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1140
1141 err = get_user_pages_fast(addr, count, 1, pages);
1142 if (err < count) {
1143 count = err;
1144 err = -EFAULT;
1145 goto put_pages;
1146 }
7fc3cdab 1147
eca18b23
MW		 1148 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1149 sg = iod->sg;
36c14ed9 1150 sg_init_table(sg, count);
d0ba1e49
MW		 1151 for (i = 0; i < count; i++) {
1152 sg_set_page(&sg[i], pages[i],
1153 min_t(int, length, PAGE_SIZE - offset), offset);
1154 length -= (PAGE_SIZE - offset);
1155 offset = 0;
7fc3cdab 1156 }
fe304c43 1157 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1158 iod->nents = count;
7fc3cdab
MW		 1159
1160 err = -ENOMEM;
1161 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1162 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1163 if (!nents)
eca18b23 1164 goto free_iod;
b60503ba 1165
7fc3cdab 1166 kfree(pages);
eca18b23 1167 return iod;
b60503ba 1168
eca18b23
MW		 1169 free_iod:
1170 kfree(iod);
7fc3cdab
MW		 1171 put_pages:
1172 for (i = 0; i < count; i++)
1173 put_page(pages[i]);
1174 kfree(pages);
eca18b23 1175 return ERR_PTR(err);
7fc3cdab 1176}
b60503ba 1177
7fc3cdab 1178static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1179 struct nvme_iod *iod)
7fc3cdab 1180{
1c2ad9fa 1181 int i;
b60503ba 1182
1c2ad9fa
MW		 1183 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1184 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1185
1c2ad9fa
MW		 1186 for (i = 0; i < iod->nents; i++)
1187 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1188}
b60503ba 1189
a53295b6
MW		 1190static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1191{
1192 struct nvme_dev *dev = ns->dev;
1193 struct nvme_queue *nvmeq;
1194 struct nvme_user_io io;
1195 struct nvme_command c;
1196 unsigned length;
eca18b23
MW		 1197 int status;
1198 struct nvme_iod *iod;
a53295b6
MW		 1199
1200 if (copy_from_user(&io, uio, sizeof(io)))
1201 return -EFAULT;
6c7d4945
MW		 1202 length = (io.nblocks + 1) << ns->lba_shift;
1203
1204 switch (io.opcode) {
1205 case nvme_cmd_write:
1206 case nvme_cmd_read:
6bbf1acd 1207 case nvme_cmd_compare:
eca18b23 1208 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1209 break;
6c7d4945 1210 default:
6bbf1acd 1211 return -EINVAL;
6c7d4945
MW		 1212 }
1213
eca18b23
MW		 1214 if (IS_ERR(iod))
1215 return PTR_ERR(iod);
a53295b6
MW		 1216
1217 memset(&c, 0, sizeof(c));
1218 c.rw.opcode = io.opcode;
1219 c.rw.flags = io.flags;
6c7d4945 1220 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1221 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1222 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6
MW		 1223 c.rw.control = cpu_to_le16(io.control);
1224 c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
6c7d4945
MW		 1225 c.rw.reftag = io.reftag;
1226 c.rw.apptag = io.apptag;
1227 c.rw.appmask = io.appmask;
a53295b6 1228 /* XXX: metadata */
eca18b23 1229 length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
a53295b6 1230
040a93b5 1231 nvmeq = get_nvmeq(dev);
fa922821
MW		 1232 /*
1233 * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
b1ad37ef
MW		 1234 * disabled. We may be preempted at any point, and be rescheduled
1235 * to a different CPU. That will cause cacheline bouncing, but no
1236 * additional races since q_lock already protects against other CPUs.
1237 */
a53295b6 1238 put_nvmeq(nvmeq);
b77954cb
MW		 1239 if (length != (io.nblocks + 1) << ns->lba_shift)
1240 status = -ENOMEM;
1241 else
ff976d72 1242 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
a53295b6 1243
1c2ad9fa 1244 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1245 nvme_free_iod(dev, iod);
a53295b6
MW		 1246 return status;
1247}
1248
50af8bae 1249static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1250 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1251{
6bbf1acd 1252 struct nvme_admin_cmd cmd;
6ee44cdc 1253 struct nvme_command c;
eca18b23 1254 int status, length;
c7d36ab8 1255 struct nvme_iod *uninitialized_var(iod);
6ee44cdc 1256
6bbf1acd
MW		 1257 if (!capable(CAP_SYS_ADMIN))
1258 return -EACCES;
1259 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1260 return -EFAULT;
6ee44cdc
MW		 1261
1262 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1263 c.common.opcode = cmd.opcode;
1264 c.common.flags = cmd.flags;
1265 c.common.nsid = cpu_to_le32(cmd.nsid);
1266 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1267 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1268 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1269 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1270 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1271 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1272 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1273 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1274
1275 length = cmd.data_len;
1276 if (cmd.data_len) {
49742188
MW		 1277 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1278 length);
eca18b23
MW		 1279 if (IS_ERR(iod))
1280 return PTR_ERR(iod);
1281 length = nvme_setup_prps(dev, &c.common, iod, length,
1282 GFP_KERNEL);
6bbf1acd
MW		 1283 }
1284
1285 if (length != cmd.data_len)
b77954cb
MW		 1286 status = -ENOMEM;
1287 else
f4f117f6 1288 status = nvme_submit_admin_cmd(dev, &c, &cmd.result);
eca18b23 1289
6bbf1acd 1290 if (cmd.data_len) {
1c2ad9fa 1291 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1292 nvme_free_iod(dev, iod);
6bbf1acd 1293 }
f4f117f6
KB		 1294
1295 if (!status && copy_to_user(&ucmd->result, &cmd.result,
1296 sizeof(cmd.result)))
1297 status = -EFAULT;
1298
6ee44cdc
MW		 1299 return status;
1300}
1301
b60503ba
MW		 1302static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1303 unsigned long arg)
1304{
1305 struct nvme_ns *ns = bdev->bd_disk->private_data;
1306
1307 switch (cmd) {
6bbf1acd
MW		 1308 case NVME_IOCTL_ID:
1309 return ns->ns_id;
1310 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1311 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1312 case NVME_IOCTL_SUBMIT_IO:
1313 return nvme_submit_io(ns, (void __user *)arg);
b60503ba
MW		 1314 default:
1315 return -ENOTTY;
1316 }
1317}
1318
1319static const struct block_device_operations nvme_fops = {
1320 .owner = THIS_MODULE,
1321 .ioctl = nvme_ioctl,
49481682 1322 .compat_ioctl = nvme_ioctl,
b60503ba
MW		 1323};
1324
1fa6aead
MW		 1325static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1326{
1327 while (bio_list_peek(&nvmeq->sq_cong)) {
1328 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1329 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1330 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1331 bio_list_add_head(&nvmeq->sq_cong, bio);
1332 break;
1333 }
3cb967c0
MW		 1334 if (bio_list_empty(&nvmeq->sq_cong))
1335 remove_wait_queue(&nvmeq->sq_full,
1336 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1337 }
1338}
1339
1340static int nvme_kthread(void *data)
1341{
1342 struct nvme_dev *dev;
1343
1344 while (!kthread_should_stop()) {
1345 __set_current_state(TASK_RUNNING);
1346 spin_lock(&dev_list_lock);
1347 list_for_each_entry(dev, &dev_list, node) {
1348 int i;
1349 for (i = 0; i < dev->queue_count; i++) {
1350 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1351 if (!nvmeq)
1352 continue;
1fa6aead
MW		 1353 spin_lock_irq(&nvmeq->q_lock);
1354 if (nvme_process_cq(nvmeq))
1355 printk("process_cq did something\n");
a09115b2 1356 nvme_cancel_ios(nvmeq, true);
1fa6aead
MW		 1357 nvme_resubmit_bios(nvmeq);
1358 spin_unlock_irq(&nvmeq->q_lock);
1359 }
1360 }
1361 spin_unlock(&dev_list_lock);
1362 set_current_state(TASK_INTERRUPTIBLE);
1363 schedule_timeout(HZ);
1364 }
1365 return 0;
1366}
1367
5aff9382
MW		 1368static DEFINE_IDA(nvme_index_ida);
1369
1370static int nvme_get_ns_idx(void)
1371{
1372 int index, error;
1373
1374 do {
1375 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1376 return -1;
1377
1378 spin_lock(&dev_list_lock);
1379 error = ida_get_new(&nvme_index_ida, &index);
1380 spin_unlock(&dev_list_lock);
1381 } while (error == -EAGAIN);
1382
1383 if (error)
1384 index = -1;
1385 return index;
1386}
1387
1388static void nvme_put_ns_idx(int index)
1389{
1390 spin_lock(&dev_list_lock);
1391 ida_remove(&nvme_index_ida, index);
1392 spin_unlock(&dev_list_lock);
1393}
1394
0e5e4f0e
KB		 1395static void nvme_config_discard(struct nvme_ns *ns)
1396{
1397 u32 logical_block_size = queue_logical_block_size(ns->queue);
1398 ns->queue->limits.discard_zeroes_data = 0;
1399 ns->queue->limits.discard_alignment = logical_block_size;
1400 ns->queue->limits.discard_granularity = logical_block_size;
1401 ns->queue->limits.max_discard_sectors = 0xffffffff;
1402 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1403}
1404
5aff9382 1405static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
b60503ba
MW		 1406 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1407{
1408 struct nvme_ns *ns;
1409 struct gendisk *disk;
1410 int lbaf;
1411
1412 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1413 return NULL;
1414
1415 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1416 if (!ns)
1417 return NULL;
1418 ns->queue = blk_alloc_queue(GFP_KERNEL);
1419 if (!ns->queue)
1420 goto out_free_ns;
4eeb9215
MW		 1421 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1422 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1423 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1424 blk_queue_make_request(ns->queue, nvme_make_request);
1425 ns->dev = dev;
1426 ns->queue->queuedata = ns;
1427
1428 disk = alloc_disk(NVME_MINORS);
1429 if (!disk)
1430 goto out_free_queue;
5aff9382 1431 ns->ns_id = nsid;
b60503ba
MW		 1432 ns->disk = disk;
1433 lbaf = id->flbas & 0xf;
1434 ns->lba_shift = id->lbaf[lbaf].ds;
e9ef4636 1435 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1436 if (dev->max_hw_sectors)
1437 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1438
1439 disk->major = nvme_major;
1440 disk->minors = NVME_MINORS;
5aff9382 1441 disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
b60503ba
MW		 1442 disk->fops = &nvme_fops;
1443 disk->private_data = ns;
1444 disk->queue = ns->queue;
388f037f 1445 disk->driverfs_dev = &dev->pci_dev->dev;
5aff9382 1446 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1447 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1448
0e5e4f0e
KB		 1449 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1450 nvme_config_discard(ns);
1451
b60503ba
MW		 1452 return ns;
1453
1454 out_free_queue:
1455 blk_cleanup_queue(ns->queue);
1456 out_free_ns:
1457 kfree(ns);
1458 return NULL;
1459}
1460
1461static void nvme_ns_free(struct nvme_ns *ns)
1462{
5aff9382 1463 int index = ns->disk->first_minor / NVME_MINORS;
b60503ba 1464 put_disk(ns->disk);
5aff9382 1465 nvme_put_ns_idx(index);
b60503ba
MW		 1466 blk_cleanup_queue(ns->queue);
1467 kfree(ns);
1468}
1469
b3b06812 1470static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1471{
1472 int status;
1473 u32 result;
b3b06812 1474 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1475
df348139 1476 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1477 &result);
b60503ba
MW		 1478 if (status)
1479 return -EIO;
1480 return min(result & 0xffff, result >> 16) + 1;
1481}
1482
8d85fce7 1483static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1484{
a0cadb85 1485 int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
b60503ba 1486
b348b7d5
MW		 1487 nr_io_queues = num_online_cpus();
1488 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 1489 if (result < 0)
1490 return result;
b348b7d5
MW		 1491 if (result < nr_io_queues)
1492 nr_io_queues = result;
b60503ba 1493
1b23484b
MW		 1494 /* Deregister the admin queue's interrupt */
1495 free_irq(dev->entry[0].vector, dev->queues[0]);
1496
f1938f6e
MW		 1497 db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1498 if (db_bar_size > 8192) {
1499 iounmap(dev->bar);
1500 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1501 db_bar_size);
1502 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1503 dev->queues[0]->q_db = dev->dbs;
1504 }
1505
b348b7d5 1506 for (i = 0; i < nr_io_queues; i++)
1b23484b
MW		 1507 dev->entry[i].entry = i;
1508 for (;;) {
b348b7d5
MW		 1509 result = pci_enable_msix(dev->pci_dev, dev->entry,
1510 nr_io_queues);
1b23484b
MW		 1511 if (result == 0) {
1512 break;
1513 } else if (result > 0) {
b348b7d5 1514 nr_io_queues = result;
1b23484b
MW		 1515 continue;
1516 } else {
b348b7d5 1517 nr_io_queues = 1;
1b23484b
MW		 1518 break;
1519 }
1520 }
1521
1522 result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1523 /* XXX: handle failure here */
1524
1525 cpu = cpumask_first(cpu_online_mask);
b348b7d5 1526 for (i = 0; i < nr_io_queues; i++) {
1b23484b
MW		 1527 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1528 cpu = cpumask_next(cpu, cpu_online_mask);
1529 }
1530
a0cadb85
KB		 1531 q_depth = min_t(int, NVME_CAP_MQES(readq(&dev->bar->cap)) + 1,
1532 NVME_Q_DEPTH);
b348b7d5 1533 for (i = 0; i < nr_io_queues; i++) {
a0cadb85 1534 dev->queues[i + 1] = nvme_create_queue(dev, i + 1, q_depth, i);
6f0f5449
MW		 1535 if (IS_ERR(dev->queues[i + 1]))
1536 return PTR_ERR(dev->queues[i + 1]);
1b23484b
MW		 1537 dev->queue_count++;
1538 }
b60503ba 1539
9ecdc946
MW		 1540 for (; i < num_possible_cpus(); i++) {
1541 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1542 dev->queues[i + 1] = dev->queues[target + 1];
1543 }
1544
b60503ba
MW		 1545 return 0;
1546}
1547
1548static void nvme_free_queues(struct nvme_dev *dev)
1549{
1550 int i;
1551
1552 for (i = dev->queue_count - 1; i >= 0; i--)
1553 nvme_free_queue(dev, i);
1554}
1555
8d85fce7 1556static int nvme_dev_add(struct nvme_dev *dev)
b60503ba
MW		 1557{
1558 int res, nn, i;
1559 struct nvme_ns *ns, *next;
51814232 1560 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 1561 struct nvme_id_ns *id_ns;
1562 void *mem;
b60503ba 1563 dma_addr_t dma_addr;
b60503ba
MW		 1564
1565 res = nvme_setup_io_queues(dev);
1566 if (res)
1567 return res;
1568
bc5fc7e4 1569 mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
b60503ba
MW		 1570 GFP_KERNEL);
1571
bc5fc7e4 1572 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 1573 if (res) {
1574 res = -EIO;
1575 goto out_free;
1576 }
1577
bc5fc7e4 1578 ctrl = mem;
51814232 1579 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 1580 dev->oncs = le16_to_cpup(&ctrl->oncs);
51814232
MW		 1581 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1582 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1583 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
8fc23e03
KB		 1584 if (ctrl->mdts) {
1585 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
1586 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
1587 }
b60503ba 1588
bc5fc7e4 1589 id_ns = mem;
2b2c1896 1590 for (i = 1; i <= nn; i++) {
bc5fc7e4 1591 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 1592 if (res)
1593 continue;
1594
bc5fc7e4 1595 if (id_ns->ncap == 0)
b60503ba
MW		 1596 continue;
1597
bc5fc7e4 1598 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 1599 dma_addr + 4096, NULL);
b60503ba 1600 if (res)
12209036 1601 memset(mem + 4096, 0, 4096);
b60503ba 1602
bc5fc7e4 1603 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 1604 if (ns)
1605 list_add_tail(&ns->list, &dev->namespaces);
1606 }
1607 list_for_each_entry(ns, &dev->namespaces, list)
1608 add_disk(ns->disk);
1609
bc5fc7e4 1610 goto out;
b60503ba
MW		 1611
1612 out_free:
1613 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1614 list_del(&ns->list);
1615 nvme_ns_free(ns);
1616 }
1617
bc5fc7e4 1618 out:
684f5c20 1619 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 1620 return res;
1621}
1622
1623static int nvme_dev_remove(struct nvme_dev *dev)
1624{
1625 struct nvme_ns *ns, *next;
1626
1fa6aead
MW		 1627 spin_lock(&dev_list_lock);
1628 list_del(&dev->node);
1629 spin_unlock(&dev_list_lock);
1630
b60503ba
MW		 1631 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1632 list_del(&ns->list);
1633 del_gendisk(ns->disk);
1634 nvme_ns_free(ns);
1635 }
1636
1637 nvme_free_queues(dev);
1638
1639 return 0;
1640}
1641
091b6092
MW		 1642static int nvme_setup_prp_pools(struct nvme_dev *dev)
1643{
1644 struct device *dmadev = &dev->pci_dev->dev;
1645 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1646 PAGE_SIZE, PAGE_SIZE, 0);
1647 if (!dev->prp_page_pool)
1648 return -ENOMEM;
1649
99802a7a
MW		 1650 /* Optimisation for I/Os between 4k and 128k */
1651 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1652 256, 256, 0);
1653 if (!dev->prp_small_pool) {
1654 dma_pool_destroy(dev->prp_page_pool);
1655 return -ENOMEM;
1656 }
091b6092
MW		 1657 return 0;
1658}
1659
1660static void nvme_release_prp_pools(struct nvme_dev *dev)
1661{
1662 dma_pool_destroy(dev->prp_page_pool);
99802a7a 1663 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 1664}
1665
cd58ad7d
QSA		 1666static DEFINE_IDA(nvme_instance_ida);
1667
1668static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 1669{
cd58ad7d
QSA		 1670 int instance, error;
1671
1672 do {
1673 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
1674 return -ENODEV;
1675
1676 spin_lock(&dev_list_lock);
1677 error = ida_get_new(&nvme_instance_ida, &instance);
1678 spin_unlock(&dev_list_lock);
1679 } while (error == -EAGAIN);
1680
1681 if (error)
1682 return -ENODEV;
1683
1684 dev->instance = instance;
1685 return 0;
b60503ba
MW		 1686}
1687
1688static void nvme_release_instance(struct nvme_dev *dev)
1689{
cd58ad7d
QSA		 1690 spin_lock(&dev_list_lock);
1691 ida_remove(&nvme_instance_ida, dev->instance);
1692 spin_unlock(&dev_list_lock);
b60503ba
MW		 1693}
1694
8d85fce7 1695static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 1696{
574e8b95 1697 int bars, result = -ENOMEM;
b60503ba
MW		 1698 struct nvme_dev *dev;
1699
1700 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1701 if (!dev)
1702 return -ENOMEM;
1703 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1704 GFP_KERNEL);
1705 if (!dev->entry)
1706 goto free;
1b23484b
MW		 1707 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1708 GFP_KERNEL);
b60503ba
MW		 1709 if (!dev->queues)
1710 goto free;
1711
0ee5a7d7
SMM		 1712 if (pci_enable_device_mem(pdev))
1713 goto free;
f64d3365 1714 pci_set_master(pdev);
574e8b95
MW		 1715 bars = pci_select_bars(pdev, IORESOURCE_MEM);
1716 if (pci_request_selected_regions(pdev, bars, "nvme"))
1717 goto disable;
0ee5a7d7 1718
b60503ba
MW		 1719 INIT_LIST_HEAD(&dev->namespaces);
1720 dev->pci_dev = pdev;
1721 pci_set_drvdata(pdev, dev);
2930353f
MW		 1722 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1723 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
cd58ad7d
QSA		 1724 result = nvme_set_instance(dev);
1725 if (result)
1726 goto disable;
1727
53c9577e 1728 dev->entry[0].vector = pdev->irq;
b60503ba 1729
091b6092
MW		 1730 result = nvme_setup_prp_pools(dev);
1731 if (result)
1732 goto disable_msix;
1733
b60503ba
MW		 1734 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1735 if (!dev->bar) {
1736 result = -ENOMEM;
574e8b95 1737 goto disable_msix;
b60503ba
MW		 1738 }
1739
1740 result = nvme_configure_admin_queue(dev);
1741 if (result)
1742 goto unmap;
1743 dev->queue_count++;
1744
1fa6aead
MW		 1745 spin_lock(&dev_list_lock);
1746 list_add(&dev->node, &dev_list);
1747 spin_unlock(&dev_list_lock);
1748
740216fc
MW		 1749 result = nvme_dev_add(dev);
1750 if (result)
1751 goto delete;
1752
b60503ba
MW		 1753 return 0;
1754
1755 delete:
740216fc
MW		 1756 spin_lock(&dev_list_lock);
1757 list_del(&dev->node);
1758 spin_unlock(&dev_list_lock);
1759
b60503ba
MW		 1760 nvme_free_queues(dev);
1761 unmap:
1762 iounmap(dev->bar);
574e8b95 1763 disable_msix:
b60503ba
MW		 1764 pci_disable_msix(pdev);
1765 nvme_release_instance(dev);
091b6092 1766 nvme_release_prp_pools(dev);
574e8b95 1767 disable:
0ee5a7d7 1768 pci_disable_device(pdev);
574e8b95 1769 pci_release_regions(pdev);
b60503ba
MW		 1770 free:
1771 kfree(dev->queues);
1772 kfree(dev->entry);
1773 kfree(dev);
1774 return result;
1775}
1776
8d85fce7 1777static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 1778{
1779 struct nvme_dev *dev = pci_get_drvdata(pdev);
1780 nvme_dev_remove(dev);
1781 pci_disable_msix(pdev);
1782 iounmap(dev->bar);
1783 nvme_release_instance(dev);
091b6092 1784 nvme_release_prp_pools(dev);
0ee5a7d7 1785 pci_disable_device(pdev);
574e8b95 1786 pci_release_regions(pdev);
b60503ba
MW		 1787 kfree(dev->queues);
1788 kfree(dev->entry);
1789 kfree(dev);
1790}
1791
1792/* These functions are yet to be implemented */
1793#define nvme_error_detected NULL
1794#define nvme_dump_registers NULL
1795#define nvme_link_reset NULL
1796#define nvme_slot_reset NULL
1797#define nvme_error_resume NULL
1798#define nvme_suspend NULL
1799#define nvme_resume NULL
1800
1d352035 1801static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 1802 .error_detected = nvme_error_detected,
1803 .mmio_enabled = nvme_dump_registers,
1804 .link_reset = nvme_link_reset,
1805 .slot_reset = nvme_slot_reset,
1806 .resume = nvme_error_resume,
1807};
1808
1809/* Move to pci_ids.h later */
1810#define PCI_CLASS_STORAGE_EXPRESS 0x010802
1811
1812static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1813 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1814 { 0, }
1815};
1816MODULE_DEVICE_TABLE(pci, nvme_id_table);
1817
1818static struct pci_driver nvme_driver = {
1819 .name = "nvme",
1820 .id_table = nvme_id_table,
1821 .probe = nvme_probe,
8d85fce7 1822 .remove = nvme_remove,
b60503ba
MW		 1823 .suspend = nvme_suspend,
1824 .resume = nvme_resume,
1825 .err_handler = &nvme_err_handler,
1826};
1827
1828static int __init nvme_init(void)
1829{
0ac13140 1830 int result;
1fa6aead
MW		 1831
1832 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1833 if (IS_ERR(nvme_thread))
1834 return PTR_ERR(nvme_thread);
b60503ba 1835
5c42ea16
KB		 1836 result = register_blkdev(nvme_major, "nvme");
1837 if (result < 0)
1fa6aead 1838 goto kill_kthread;
5c42ea16 1839 else if (result > 0)
0ac13140 1840 nvme_major = result;
b60503ba
MW		 1841
1842 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 1843 if (result)
1844 goto unregister_blkdev;
1845 return 0;
b60503ba 1846
1fa6aead 1847 unregister_blkdev:
b60503ba 1848 unregister_blkdev(nvme_major, "nvme");
1fa6aead
MW		 1849 kill_kthread:
1850 kthread_stop(nvme_thread);
b60503ba
MW		 1851 return result;
1852}
1853
1854static void __exit nvme_exit(void)
1855{
1856 pci_unregister_driver(&nvme_driver);
1857 unregister_blkdev(nvme_major, "nvme");
1fa6aead 1858 kthread_stop(nvme_thread);
b60503ba
MW		 1859}
1860
1861MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1862MODULE_LICENSE("GPL");
366e8217 1863MODULE_VERSION("0.8");
b60503ba
MW		 1864module_init(nvme_init);
1865module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)