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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
3 | * Copyright (c) 2011, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | */ | |
18 | ||
19 | #include <linux/nvme.h> | |
20 | #include <linux/bio.h> | |
8de05535 | 21 | #include <linux/bitops.h> |
b60503ba | 22 | #include <linux/blkdev.h> |
fd63e9ce | 23 | #include <linux/delay.h> |
b60503ba MW |
24 | #include <linux/errno.h> |
25 | #include <linux/fs.h> | |
26 | #include <linux/genhd.h> | |
5aff9382 | 27 | #include <linux/idr.h> |
b60503ba MW |
28 | #include <linux/init.h> |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/kdev_t.h> | |
1fa6aead | 32 | #include <linux/kthread.h> |
b60503ba MW |
33 | #include <linux/kernel.h> |
34 | #include <linux/mm.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/moduleparam.h> | |
37 | #include <linux/pci.h> | |
be7b6275 | 38 | #include <linux/poison.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
41 | #include <linux/types.h> | |
42 | #include <linux/version.h> | |
43 | ||
44 | #define NVME_Q_DEPTH 1024 | |
45 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) | |
46 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
47 | #define NVME_MINORS 64 | |
e85248e5 MW |
48 | #define IO_TIMEOUT (5 * HZ) |
49 | #define ADMIN_TIMEOUT (60 * HZ) | |
b60503ba MW |
50 | |
51 | static int nvme_major; | |
52 | module_param(nvme_major, int, 0); | |
53 | ||
58ffacb5 MW |
54 | static int use_threaded_interrupts; |
55 | module_param(use_threaded_interrupts, int, 0); | |
56 | ||
1fa6aead MW |
57 | static DEFINE_SPINLOCK(dev_list_lock); |
58 | static LIST_HEAD(dev_list); | |
59 | static struct task_struct *nvme_thread; | |
60 | ||
b60503ba MW |
61 | /* |
62 | * Represents an NVM Express device. Each nvme_dev is a PCI function. | |
63 | */ | |
64 | struct nvme_dev { | |
1fa6aead | 65 | struct list_head node; |
b60503ba MW |
66 | struct nvme_queue **queues; |
67 | u32 __iomem *dbs; | |
68 | struct pci_dev *pci_dev; | |
091b6092 | 69 | struct dma_pool *prp_page_pool; |
99802a7a | 70 | struct dma_pool *prp_small_pool; |
b60503ba MW |
71 | int instance; |
72 | int queue_count; | |
f1938f6e | 73 | int db_stride; |
b60503ba MW |
74 | u32 ctrl_config; |
75 | struct msix_entry *entry; | |
76 | struct nvme_bar __iomem *bar; | |
77 | struct list_head namespaces; | |
51814232 MW |
78 | char serial[20]; |
79 | char model[40]; | |
80 | char firmware_rev[8]; | |
b60503ba MW |
81 | }; |
82 | ||
83 | /* | |
84 | * An NVM Express namespace is equivalent to a SCSI LUN | |
85 | */ | |
86 | struct nvme_ns { | |
87 | struct list_head list; | |
88 | ||
89 | struct nvme_dev *dev; | |
90 | struct request_queue *queue; | |
91 | struct gendisk *disk; | |
92 | ||
93 | int ns_id; | |
94 | int lba_shift; | |
95 | }; | |
96 | ||
97 | /* | |
98 | * An NVM Express queue. Each device has at least two (one for admin | |
99 | * commands and one for I/O commands). | |
100 | */ | |
101 | struct nvme_queue { | |
102 | struct device *q_dmadev; | |
091b6092 | 103 | struct nvme_dev *dev; |
b60503ba MW |
104 | spinlock_t q_lock; |
105 | struct nvme_command *sq_cmds; | |
106 | volatile struct nvme_completion *cqes; | |
107 | dma_addr_t sq_dma_addr; | |
108 | dma_addr_t cq_dma_addr; | |
109 | wait_queue_head_t sq_full; | |
1fa6aead | 110 | wait_queue_t sq_cong_wait; |
b60503ba MW |
111 | struct bio_list sq_cong; |
112 | u32 __iomem *q_db; | |
113 | u16 q_depth; | |
114 | u16 cq_vector; | |
115 | u16 sq_head; | |
116 | u16 sq_tail; | |
117 | u16 cq_head; | |
82123460 | 118 | u16 cq_phase; |
b60503ba MW |
119 | unsigned long cmdid_data[]; |
120 | }; | |
121 | ||
122 | /* | |
123 | * Check we didin't inadvertently grow the command struct | |
124 | */ | |
125 | static inline void _nvme_check_size(void) | |
126 | { | |
127 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
128 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
129 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
130 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
131 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
132 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); | |
133 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
134 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
135 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
136 | } | |
137 | ||
c2f5b650 MW |
138 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
139 | struct nvme_completion *); | |
140 | ||
e85248e5 | 141 | struct nvme_cmd_info { |
c2f5b650 MW |
142 | nvme_completion_fn fn; |
143 | void *ctx; | |
e85248e5 MW |
144 | unsigned long timeout; |
145 | }; | |
146 | ||
147 | static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq) | |
148 | { | |
149 | return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)]; | |
150 | } | |
151 | ||
b60503ba | 152 | /** |
714a7a22 MW |
153 | * alloc_cmdid() - Allocate a Command ID |
154 | * @nvmeq: The queue that will be used for this command | |
155 | * @ctx: A pointer that will be passed to the handler | |
c2f5b650 | 156 | * @handler: The function to call on completion |
b60503ba MW |
157 | * |
158 | * Allocate a Command ID for a queue. The data passed in will | |
159 | * be passed to the completion handler. This is implemented by using | |
160 | * the bottom two bits of the ctx pointer to store the handler ID. | |
161 | * Passing in a pointer that's not 4-byte aligned will cause a BUG. | |
162 | * We can change this if it becomes a problem. | |
184d2944 MW |
163 | * |
164 | * May be called with local interrupts disabled and the q_lock held, | |
165 | * or with interrupts enabled and no locks held. | |
b60503ba | 166 | */ |
c2f5b650 MW |
167 | static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx, |
168 | nvme_completion_fn handler, unsigned timeout) | |
b60503ba | 169 | { |
e6d15f79 | 170 | int depth = nvmeq->q_depth - 1; |
e85248e5 | 171 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba MW |
172 | int cmdid; |
173 | ||
b60503ba MW |
174 | do { |
175 | cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth); | |
176 | if (cmdid >= depth) | |
177 | return -EBUSY; | |
178 | } while (test_and_set_bit(cmdid, nvmeq->cmdid_data)); | |
179 | ||
c2f5b650 MW |
180 | info[cmdid].fn = handler; |
181 | info[cmdid].ctx = ctx; | |
e85248e5 | 182 | info[cmdid].timeout = jiffies + timeout; |
b60503ba MW |
183 | return cmdid; |
184 | } | |
185 | ||
186 | static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx, | |
c2f5b650 | 187 | nvme_completion_fn handler, unsigned timeout) |
b60503ba MW |
188 | { |
189 | int cmdid; | |
190 | wait_event_killable(nvmeq->sq_full, | |
e85248e5 | 191 | (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0); |
b60503ba MW |
192 | return (cmdid < 0) ? -EINTR : cmdid; |
193 | } | |
194 | ||
c2f5b650 MW |
195 | /* Special values must be less than 0x1000 */ |
196 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
197 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
198 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
199 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
00df5cb4 | 200 | #define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE) |
be7b6275 | 201 | |
c2f5b650 MW |
202 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
203 | struct nvme_completion *cqe) | |
204 | { | |
205 | if (ctx == CMD_CTX_CANCELLED) | |
206 | return; | |
207 | if (ctx == CMD_CTX_FLUSH) | |
208 | return; | |
209 | if (ctx == CMD_CTX_COMPLETED) { | |
210 | dev_warn(nvmeq->q_dmadev, | |
211 | "completed id %d twice on queue %d\n", | |
212 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
213 | return; | |
214 | } | |
215 | if (ctx == CMD_CTX_INVALID) { | |
216 | dev_warn(nvmeq->q_dmadev, | |
217 | "invalid id %d completed on queue %d\n", | |
218 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
219 | return; | |
220 | } | |
221 | ||
222 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); | |
223 | } | |
224 | ||
184d2944 MW |
225 | /* |
226 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
227 | */ | |
c2f5b650 MW |
228 | static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid, |
229 | nvme_completion_fn *fn) | |
b60503ba | 230 | { |
c2f5b650 | 231 | void *ctx; |
e85248e5 | 232 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
b60503ba | 233 | |
c2f5b650 MW |
234 | if (cmdid >= nvmeq->q_depth) { |
235 | *fn = special_completion; | |
48e3d398 | 236 | return CMD_CTX_INVALID; |
c2f5b650 MW |
237 | } |
238 | *fn = info[cmdid].fn; | |
239 | ctx = info[cmdid].ctx; | |
240 | info[cmdid].fn = special_completion; | |
e85248e5 | 241 | info[cmdid].ctx = CMD_CTX_COMPLETED; |
b60503ba MW |
242 | clear_bit(cmdid, nvmeq->cmdid_data); |
243 | wake_up(&nvmeq->sq_full); | |
c2f5b650 | 244 | return ctx; |
b60503ba MW |
245 | } |
246 | ||
c2f5b650 MW |
247 | static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid, |
248 | nvme_completion_fn *fn) | |
3c0cf138 | 249 | { |
c2f5b650 | 250 | void *ctx; |
e85248e5 | 251 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); |
c2f5b650 MW |
252 | if (fn) |
253 | *fn = info[cmdid].fn; | |
254 | ctx = info[cmdid].ctx; | |
255 | info[cmdid].fn = special_completion; | |
e85248e5 | 256 | info[cmdid].ctx = CMD_CTX_CANCELLED; |
c2f5b650 | 257 | return ctx; |
3c0cf138 MW |
258 | } |
259 | ||
040a93b5 | 260 | static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) |
b60503ba | 261 | { |
040a93b5 | 262 | return dev->queues[get_cpu() + 1]; |
b60503ba MW |
263 | } |
264 | ||
265 | static void put_nvmeq(struct nvme_queue *nvmeq) | |
266 | { | |
1b23484b | 267 | put_cpu(); |
b60503ba MW |
268 | } |
269 | ||
270 | /** | |
714a7a22 | 271 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
272 | * @nvmeq: The queue to use |
273 | * @cmd: The command to send | |
274 | * | |
275 | * Safe to use from interrupt context | |
276 | */ | |
277 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) | |
278 | { | |
279 | unsigned long flags; | |
280 | u16 tail; | |
b60503ba MW |
281 | spin_lock_irqsave(&nvmeq->q_lock, flags); |
282 | tail = nvmeq->sq_tail; | |
283 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); | |
b60503ba MW |
284 | if (++tail == nvmeq->q_depth) |
285 | tail = 0; | |
7547881d | 286 | writel(tail, nvmeq->q_db); |
b60503ba MW |
287 | nvmeq->sq_tail = tail; |
288 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
289 | ||
290 | return 0; | |
291 | } | |
292 | ||
e025344c | 293 | struct nvme_prps { |
0d1bc912 | 294 | int npages; /* 0 means small pool in use */ |
e025344c SMM |
295 | dma_addr_t first_dma; |
296 | __le64 *list[0]; | |
297 | }; | |
298 | ||
d567760c | 299 | static void nvme_free_prps(struct nvme_dev *dev, struct nvme_prps *prps) |
e025344c SMM |
300 | { |
301 | const int last_prp = PAGE_SIZE / 8 - 1; | |
302 | int i; | |
303 | dma_addr_t prp_dma; | |
304 | ||
305 | if (!prps) | |
306 | return; | |
307 | ||
308 | prp_dma = prps->first_dma; | |
99802a7a MW |
309 | |
310 | if (prps->npages == 0) | |
311 | dma_pool_free(dev->prp_small_pool, prps->list[0], prp_dma); | |
e025344c SMM |
312 | for (i = 0; i < prps->npages; i++) { |
313 | __le64 *prp_list = prps->list[i]; | |
314 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
091b6092 | 315 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); |
e025344c SMM |
316 | prp_dma = next_prp_dma; |
317 | } | |
318 | kfree(prps); | |
319 | } | |
320 | ||
d534df3c | 321 | struct nvme_bio { |
b60503ba MW |
322 | struct bio *bio; |
323 | int nents; | |
e025344c | 324 | struct nvme_prps *prps; |
b60503ba MW |
325 | struct scatterlist sg[0]; |
326 | }; | |
327 | ||
328 | /* XXX: use a mempool */ | |
d534df3c | 329 | static struct nvme_bio *alloc_nbio(unsigned nseg, gfp_t gfp) |
b60503ba | 330 | { |
d534df3c | 331 | return kzalloc(sizeof(struct nvme_bio) + |
b60503ba MW |
332 | sizeof(struct scatterlist) * nseg, gfp); |
333 | } | |
334 | ||
d534df3c | 335 | static void free_nbio(struct nvme_queue *nvmeq, struct nvme_bio *nbio) |
b60503ba | 336 | { |
d567760c | 337 | nvme_free_prps(nvmeq->dev, nbio->prps); |
d534df3c | 338 | kfree(nbio); |
b60503ba MW |
339 | } |
340 | ||
341 | static void bio_completion(struct nvme_queue *nvmeq, void *ctx, | |
342 | struct nvme_completion *cqe) | |
343 | { | |
d534df3c MW |
344 | struct nvme_bio *nbio = ctx; |
345 | struct bio *bio = nbio->bio; | |
b60503ba MW |
346 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
347 | ||
d534df3c | 348 | dma_unmap_sg(nvmeq->q_dmadev, nbio->sg, nbio->nents, |
b60503ba | 349 | bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
d534df3c | 350 | free_nbio(nvmeq, nbio); |
09a58f53 | 351 | if (status) { |
1ad2f893 | 352 | bio_endio(bio, -EIO); |
09a58f53 | 353 | } else if (bio->bi_vcnt > bio->bi_idx) { |
eac623ba MW |
354 | if (bio_list_empty(&nvmeq->sq_cong)) |
355 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
1ad2f893 MW |
356 | bio_list_add(&nvmeq->sq_cong, bio); |
357 | wake_up_process(nvme_thread); | |
358 | } else { | |
359 | bio_endio(bio, 0); | |
360 | } | |
b60503ba MW |
361 | } |
362 | ||
184d2944 | 363 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
d567760c | 364 | static struct nvme_prps *nvme_setup_prps(struct nvme_dev *dev, |
e025344c | 365 | struct nvme_common_command *cmd, |
b77954cb MW |
366 | struct scatterlist *sg, int *len, |
367 | gfp_t gfp) | |
ff22b54f | 368 | { |
99802a7a | 369 | struct dma_pool *pool; |
b77954cb | 370 | int length = *len; |
ff22b54f MW |
371 | int dma_len = sg_dma_len(sg); |
372 | u64 dma_addr = sg_dma_address(sg); | |
373 | int offset = offset_in_page(dma_addr); | |
e025344c SMM |
374 | __le64 *prp_list; |
375 | dma_addr_t prp_dma; | |
0d1bc912 | 376 | int nprps, npages, i; |
e025344c | 377 | struct nvme_prps *prps = NULL; |
ff22b54f MW |
378 | |
379 | cmd->prp1 = cpu_to_le64(dma_addr); | |
380 | length -= (PAGE_SIZE - offset); | |
381 | if (length <= 0) | |
e025344c | 382 | return prps; |
ff22b54f MW |
383 | |
384 | dma_len -= (PAGE_SIZE - offset); | |
385 | if (dma_len) { | |
386 | dma_addr += (PAGE_SIZE - offset); | |
387 | } else { | |
388 | sg = sg_next(sg); | |
389 | dma_addr = sg_dma_address(sg); | |
390 | dma_len = sg_dma_len(sg); | |
391 | } | |
392 | ||
393 | if (length <= PAGE_SIZE) { | |
394 | cmd->prp2 = cpu_to_le64(dma_addr); | |
e025344c SMM |
395 | return prps; |
396 | } | |
397 | ||
398 | nprps = DIV_ROUND_UP(length, PAGE_SIZE); | |
0d1bc912 | 399 | npages = DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); |
b77954cb MW |
400 | prps = kmalloc(sizeof(*prps) + sizeof(__le64 *) * npages, gfp); |
401 | if (!prps) { | |
402 | cmd->prp2 = cpu_to_le64(dma_addr); | |
403 | *len = (*len - length) + PAGE_SIZE; | |
404 | return prps; | |
405 | } | |
0d1bc912 | 406 | |
99802a7a MW |
407 | if (nprps <= (256 / 8)) { |
408 | pool = dev->prp_small_pool; | |
409 | prps->npages = 0; | |
410 | } else { | |
411 | pool = dev->prp_page_pool; | |
0d1bc912 | 412 | prps->npages = 1; |
99802a7a MW |
413 | } |
414 | ||
b77954cb MW |
415 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
416 | if (!prp_list) { | |
417 | cmd->prp2 = cpu_to_le64(dma_addr); | |
418 | *len = (*len - length) + PAGE_SIZE; | |
419 | kfree(prps); | |
420 | return NULL; | |
421 | } | |
0d1bc912 | 422 | prps->list[0] = prp_list; |
e025344c SMM |
423 | prps->first_dma = prp_dma; |
424 | cmd->prp2 = cpu_to_le64(prp_dma); | |
425 | i = 0; | |
426 | for (;;) { | |
7523d834 | 427 | if (i == PAGE_SIZE / 8) { |
e025344c | 428 | __le64 *old_prp_list = prp_list; |
b77954cb MW |
429 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
430 | if (!prp_list) { | |
431 | *len = (*len - length); | |
432 | return prps; | |
433 | } | |
0d1bc912 | 434 | prps->list[prps->npages++] = prp_list; |
7523d834 MW |
435 | prp_list[0] = old_prp_list[i - 1]; |
436 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
437 | i = 1; | |
e025344c SMM |
438 | } |
439 | prp_list[i++] = cpu_to_le64(dma_addr); | |
440 | dma_len -= PAGE_SIZE; | |
441 | dma_addr += PAGE_SIZE; | |
442 | length -= PAGE_SIZE; | |
443 | if (length <= 0) | |
444 | break; | |
445 | if (dma_len > 0) | |
446 | continue; | |
447 | BUG_ON(dma_len < 0); | |
448 | sg = sg_next(sg); | |
449 | dma_addr = sg_dma_address(sg); | |
450 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
451 | } |
452 | ||
e025344c | 453 | return prps; |
ff22b54f MW |
454 | } |
455 | ||
1ad2f893 MW |
456 | /* NVMe scatterlists require no holes in the virtual address */ |
457 | #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \ | |
458 | (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE)) | |
459 | ||
d534df3c | 460 | static int nvme_map_bio(struct device *dev, struct nvme_bio *nbio, |
b60503ba MW |
461 | struct bio *bio, enum dma_data_direction dma_dir, int psegs) |
462 | { | |
76830840 MW |
463 | struct bio_vec *bvec, *bvprv = NULL; |
464 | struct scatterlist *sg = NULL; | |
1ad2f893 | 465 | int i, old_idx, length = 0, nsegs = 0; |
b60503ba | 466 | |
76830840 | 467 | sg_init_table(nbio->sg, psegs); |
1ad2f893 | 468 | old_idx = bio->bi_idx; |
b60503ba | 469 | bio_for_each_segment(bvec, bio, i) { |
76830840 MW |
470 | if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) { |
471 | sg->length += bvec->bv_len; | |
472 | } else { | |
1ad2f893 MW |
473 | if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec)) |
474 | break; | |
76830840 MW |
475 | sg = sg ? sg + 1 : nbio->sg; |
476 | sg_set_page(sg, bvec->bv_page, bvec->bv_len, | |
477 | bvec->bv_offset); | |
478 | nsegs++; | |
479 | } | |
1ad2f893 | 480 | length += bvec->bv_len; |
76830840 | 481 | bvprv = bvec; |
b60503ba | 482 | } |
1ad2f893 | 483 | bio->bi_idx = i; |
d534df3c | 484 | nbio->nents = nsegs; |
76830840 | 485 | sg_mark_end(sg); |
1ad2f893 MW |
486 | if (dma_map_sg(dev, nbio->sg, nbio->nents, dma_dir) == 0) { |
487 | bio->bi_idx = old_idx; | |
488 | return -ENOMEM; | |
489 | } | |
490 | return length; | |
b60503ba MW |
491 | } |
492 | ||
00df5cb4 MW |
493 | static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
494 | int cmdid) | |
495 | { | |
496 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
497 | ||
498 | memset(cmnd, 0, sizeof(*cmnd)); | |
499 | cmnd->common.opcode = nvme_cmd_flush; | |
500 | cmnd->common.command_id = cmdid; | |
501 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
502 | ||
503 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
504 | nvmeq->sq_tail = 0; | |
505 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
506 | ||
507 | return 0; | |
508 | } | |
509 | ||
510 | static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns) | |
511 | { | |
512 | int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH, | |
c2f5b650 | 513 | special_completion, IO_TIMEOUT); |
00df5cb4 MW |
514 | if (unlikely(cmdid < 0)) |
515 | return cmdid; | |
516 | ||
517 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
518 | } | |
519 | ||
184d2944 MW |
520 | /* |
521 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
522 | */ | |
b60503ba MW |
523 | static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
524 | struct bio *bio) | |
525 | { | |
ff22b54f | 526 | struct nvme_command *cmnd; |
d534df3c | 527 | struct nvme_bio *nbio; |
b60503ba | 528 | enum dma_data_direction dma_dir; |
1ad2f893 | 529 | int cmdid, length, result = -ENOMEM; |
b60503ba MW |
530 | u16 control; |
531 | u32 dsmgmt; | |
b60503ba MW |
532 | int psegs = bio_phys_segments(ns->queue, bio); |
533 | ||
00df5cb4 MW |
534 | if ((bio->bi_rw & REQ_FLUSH) && psegs) { |
535 | result = nvme_submit_flush_data(nvmeq, ns); | |
536 | if (result) | |
537 | return result; | |
538 | } | |
539 | ||
eeee3226 | 540 | nbio = alloc_nbio(psegs, GFP_ATOMIC); |
d534df3c | 541 | if (!nbio) |
eeee3226 | 542 | goto nomem; |
d534df3c | 543 | nbio->bio = bio; |
b60503ba | 544 | |
eeee3226 | 545 | result = -EBUSY; |
c2f5b650 | 546 | cmdid = alloc_cmdid(nvmeq, nbio, bio_completion, IO_TIMEOUT); |
b60503ba | 547 | if (unlikely(cmdid < 0)) |
d534df3c | 548 | goto free_nbio; |
b60503ba | 549 | |
00df5cb4 MW |
550 | if ((bio->bi_rw & REQ_FLUSH) && !psegs) |
551 | return nvme_submit_flush(nvmeq, ns, cmdid); | |
552 | ||
b60503ba MW |
553 | control = 0; |
554 | if (bio->bi_rw & REQ_FUA) | |
555 | control |= NVME_RW_FUA; | |
556 | if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD)) | |
557 | control |= NVME_RW_LR; | |
558 | ||
559 | dsmgmt = 0; | |
560 | if (bio->bi_rw & REQ_RAHEAD) | |
561 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; | |
562 | ||
ff22b54f | 563 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b60503ba | 564 | |
b8deb62c | 565 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 566 | if (bio_data_dir(bio)) { |
ff22b54f | 567 | cmnd->rw.opcode = nvme_cmd_write; |
b60503ba MW |
568 | dma_dir = DMA_TO_DEVICE; |
569 | } else { | |
ff22b54f | 570 | cmnd->rw.opcode = nvme_cmd_read; |
b60503ba MW |
571 | dma_dir = DMA_FROM_DEVICE; |
572 | } | |
573 | ||
1ad2f893 MW |
574 | result = nvme_map_bio(nvmeq->q_dmadev, nbio, bio, dma_dir, psegs); |
575 | if (result < 0) | |
eeee3226 | 576 | goto free_nbio; |
1ad2f893 | 577 | length = result; |
b60503ba | 578 | |
ff22b54f MW |
579 | cmnd->rw.command_id = cmdid; |
580 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); | |
d567760c | 581 | nbio->prps = nvme_setup_prps(nvmeq->dev, &cmnd->common, nbio->sg, |
b77954cb | 582 | &length, GFP_ATOMIC); |
ff22b54f | 583 | cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9)); |
1ad2f893 | 584 | cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1); |
ff22b54f MW |
585 | cmnd->rw.control = cpu_to_le16(control); |
586 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 587 | |
d8ee9d69 MW |
588 | bio->bi_sector += length >> 9; |
589 | ||
b60503ba MW |
590 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
591 | nvmeq->sq_tail = 0; | |
7547881d | 592 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 593 | |
1974b1ae MW |
594 | return 0; |
595 | ||
d534df3c MW |
596 | free_nbio: |
597 | free_nbio(nvmeq, nbio); | |
eeee3226 MW |
598 | nomem: |
599 | return result; | |
b60503ba MW |
600 | } |
601 | ||
602 | /* | |
603 | * NB: return value of non-zero would mean that we were a stacking driver. | |
604 | * make_request must always succeed. | |
605 | */ | |
606 | static int nvme_make_request(struct request_queue *q, struct bio *bio) | |
607 | { | |
608 | struct nvme_ns *ns = q->queuedata; | |
040a93b5 | 609 | struct nvme_queue *nvmeq = get_nvmeq(ns->dev); |
eeee3226 MW |
610 | int result = -EBUSY; |
611 | ||
612 | spin_lock_irq(&nvmeq->q_lock); | |
613 | if (bio_list_empty(&nvmeq->sq_cong)) | |
614 | result = nvme_submit_bio_queue(nvmeq, ns, bio); | |
615 | if (unlikely(result)) { | |
616 | if (bio_list_empty(&nvmeq->sq_cong)) | |
617 | add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait); | |
b60503ba MW |
618 | bio_list_add(&nvmeq->sq_cong, bio); |
619 | } | |
eeee3226 MW |
620 | |
621 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
622 | put_nvmeq(nvmeq); |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
b60503ba MW |
627 | static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq) |
628 | { | |
82123460 | 629 | u16 head, phase; |
b60503ba | 630 | |
b60503ba | 631 | head = nvmeq->cq_head; |
82123460 | 632 | phase = nvmeq->cq_phase; |
b60503ba MW |
633 | |
634 | for (;;) { | |
c2f5b650 MW |
635 | void *ctx; |
636 | nvme_completion_fn fn; | |
b60503ba | 637 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 638 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
639 | break; |
640 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
641 | if (++head == nvmeq->q_depth) { | |
642 | head = 0; | |
82123460 | 643 | phase = !phase; |
b60503ba MW |
644 | } |
645 | ||
c2f5b650 MW |
646 | ctx = free_cmdid(nvmeq, cqe.command_id, &fn); |
647 | fn(nvmeq, ctx, &cqe); | |
b60503ba MW |
648 | } |
649 | ||
650 | /* If the controller ignores the cq head doorbell and continuously | |
651 | * writes to the queue, it is theoretically possible to wrap around | |
652 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
653 | * requires that 0.1% of your interrupts are handled, so this isn't | |
654 | * a big problem. | |
655 | */ | |
82123460 | 656 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
b60503ba MW |
657 | return IRQ_NONE; |
658 | ||
f1938f6e | 659 | writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride)); |
b60503ba | 660 | nvmeq->cq_head = head; |
82123460 | 661 | nvmeq->cq_phase = phase; |
b60503ba MW |
662 | |
663 | return IRQ_HANDLED; | |
664 | } | |
665 | ||
666 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
667 | { |
668 | irqreturn_t result; | |
669 | struct nvme_queue *nvmeq = data; | |
670 | spin_lock(&nvmeq->q_lock); | |
671 | result = nvme_process_cq(nvmeq); | |
672 | spin_unlock(&nvmeq->q_lock); | |
673 | return result; | |
674 | } | |
675 | ||
676 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
677 | { | |
678 | struct nvme_queue *nvmeq = data; | |
679 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
680 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
681 | return IRQ_NONE; | |
682 | return IRQ_WAKE_THREAD; | |
683 | } | |
684 | ||
3c0cf138 MW |
685 | static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid) |
686 | { | |
687 | spin_lock_irq(&nvmeq->q_lock); | |
c2f5b650 | 688 | cancel_cmdid(nvmeq, cmdid, NULL); |
3c0cf138 MW |
689 | spin_unlock_irq(&nvmeq->q_lock); |
690 | } | |
691 | ||
c2f5b650 MW |
692 | struct sync_cmd_info { |
693 | struct task_struct *task; | |
694 | u32 result; | |
695 | int status; | |
696 | }; | |
697 | ||
698 | static void sync_completion(struct nvme_queue *nvmeq, void *ctx, | |
699 | struct nvme_completion *cqe) | |
700 | { | |
701 | struct sync_cmd_info *cmdinfo = ctx; | |
702 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
703 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
704 | wake_up_process(cmdinfo->task); | |
705 | } | |
706 | ||
b60503ba MW |
707 | /* |
708 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
709 | * if the result is positive, it's an NVM Express status code | |
710 | */ | |
3c0cf138 | 711 | static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq, |
e85248e5 | 712 | struct nvme_command *cmd, u32 *result, unsigned timeout) |
b60503ba MW |
713 | { |
714 | int cmdid; | |
715 | struct sync_cmd_info cmdinfo; | |
716 | ||
717 | cmdinfo.task = current; | |
718 | cmdinfo.status = -EINTR; | |
719 | ||
c2f5b650 | 720 | cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion, |
e85248e5 | 721 | timeout); |
b60503ba MW |
722 | if (cmdid < 0) |
723 | return cmdid; | |
724 | cmd->common.command_id = cmdid; | |
725 | ||
3c0cf138 MW |
726 | set_current_state(TASK_KILLABLE); |
727 | nvme_submit_cmd(nvmeq, cmd); | |
b60503ba MW |
728 | schedule(); |
729 | ||
3c0cf138 MW |
730 | if (cmdinfo.status == -EINTR) { |
731 | nvme_abort_command(nvmeq, cmdid); | |
732 | return -EINTR; | |
733 | } | |
734 | ||
b60503ba MW |
735 | if (result) |
736 | *result = cmdinfo.result; | |
737 | ||
738 | return cmdinfo.status; | |
739 | } | |
740 | ||
741 | static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd, | |
742 | u32 *result) | |
743 | { | |
e85248e5 | 744 | return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT); |
b60503ba MW |
745 | } |
746 | ||
747 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) | |
748 | { | |
749 | int status; | |
750 | struct nvme_command c; | |
751 | ||
752 | memset(&c, 0, sizeof(c)); | |
753 | c.delete_queue.opcode = opcode; | |
754 | c.delete_queue.qid = cpu_to_le16(id); | |
755 | ||
756 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
757 | if (status) | |
758 | return -EIO; | |
759 | return 0; | |
760 | } | |
761 | ||
762 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
763 | struct nvme_queue *nvmeq) | |
764 | { | |
765 | int status; | |
766 | struct nvme_command c; | |
767 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
768 | ||
769 | memset(&c, 0, sizeof(c)); | |
770 | c.create_cq.opcode = nvme_admin_create_cq; | |
771 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
772 | c.create_cq.cqid = cpu_to_le16(qid); | |
773 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
774 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
775 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
776 | ||
777 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
778 | if (status) | |
779 | return -EIO; | |
780 | return 0; | |
781 | } | |
782 | ||
783 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
784 | struct nvme_queue *nvmeq) | |
785 | { | |
786 | int status; | |
787 | struct nvme_command c; | |
788 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
789 | ||
790 | memset(&c, 0, sizeof(c)); | |
791 | c.create_sq.opcode = nvme_admin_create_sq; | |
792 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
793 | c.create_sq.sqid = cpu_to_le16(qid); | |
794 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
795 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
796 | c.create_sq.cqid = cpu_to_le16(qid); | |
797 | ||
798 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
799 | if (status) | |
800 | return -EIO; | |
801 | return 0; | |
802 | } | |
803 | ||
804 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
805 | { | |
806 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
807 | } | |
808 | ||
809 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
810 | { | |
811 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
812 | } | |
813 | ||
bc5fc7e4 MW |
814 | static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns, |
815 | dma_addr_t dma_addr) | |
816 | { | |
817 | struct nvme_command c; | |
818 | ||
819 | memset(&c, 0, sizeof(c)); | |
820 | c.identify.opcode = nvme_admin_identify; | |
821 | c.identify.nsid = cpu_to_le32(nsid); | |
822 | c.identify.prp1 = cpu_to_le64(dma_addr); | |
823 | c.identify.cns = cpu_to_le32(cns); | |
824 | ||
825 | return nvme_submit_admin_cmd(dev, &c, NULL); | |
826 | } | |
827 | ||
828 | static int nvme_get_features(struct nvme_dev *dev, unsigned fid, | |
829 | unsigned dword11, dma_addr_t dma_addr, u32 *result) | |
830 | { | |
831 | struct nvme_command c; | |
832 | ||
833 | memset(&c, 0, sizeof(c)); | |
834 | c.features.opcode = nvme_admin_get_features; | |
835 | c.features.prp1 = cpu_to_le64(dma_addr); | |
836 | c.features.fid = cpu_to_le32(fid); | |
837 | c.features.dword11 = cpu_to_le32(dword11); | |
838 | ||
839 | return nvme_submit_admin_cmd(dev, &c, result); | |
840 | } | |
841 | ||
b60503ba MW |
842 | static void nvme_free_queue(struct nvme_dev *dev, int qid) |
843 | { | |
844 | struct nvme_queue *nvmeq = dev->queues[qid]; | |
aba2080f | 845 | int vector = dev->entry[nvmeq->cq_vector].vector; |
b60503ba | 846 | |
aba2080f MW |
847 | irq_set_affinity_hint(vector, NULL); |
848 | free_irq(vector, nvmeq); | |
b60503ba MW |
849 | |
850 | /* Don't tell the adapter to delete the admin queue */ | |
851 | if (qid) { | |
852 | adapter_delete_sq(dev, qid); | |
853 | adapter_delete_cq(dev, qid); | |
854 | } | |
855 | ||
856 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
857 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
858 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
859 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
860 | kfree(nvmeq); | |
861 | } | |
862 | ||
863 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
864 | int depth, int vector) | |
865 | { | |
866 | struct device *dmadev = &dev->pci_dev->dev; | |
e85248e5 | 867 | unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info)); |
b60503ba MW |
868 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL); |
869 | if (!nvmeq) | |
870 | return NULL; | |
871 | ||
872 | nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth), | |
873 | &nvmeq->cq_dma_addr, GFP_KERNEL); | |
874 | if (!nvmeq->cqes) | |
875 | goto free_nvmeq; | |
876 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth)); | |
877 | ||
878 | nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth), | |
879 | &nvmeq->sq_dma_addr, GFP_KERNEL); | |
880 | if (!nvmeq->sq_cmds) | |
881 | goto free_cqdma; | |
882 | ||
883 | nvmeq->q_dmadev = dmadev; | |
091b6092 | 884 | nvmeq->dev = dev; |
b60503ba MW |
885 | spin_lock_init(&nvmeq->q_lock); |
886 | nvmeq->cq_head = 0; | |
82123460 | 887 | nvmeq->cq_phase = 1; |
b60503ba | 888 | init_waitqueue_head(&nvmeq->sq_full); |
1fa6aead | 889 | init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread); |
b60503ba | 890 | bio_list_init(&nvmeq->sq_cong); |
f1938f6e | 891 | nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)]; |
b60503ba MW |
892 | nvmeq->q_depth = depth; |
893 | nvmeq->cq_vector = vector; | |
894 | ||
895 | return nvmeq; | |
896 | ||
897 | free_cqdma: | |
898 | dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes, | |
899 | nvmeq->cq_dma_addr); | |
900 | free_nvmeq: | |
901 | kfree(nvmeq); | |
902 | return NULL; | |
903 | } | |
904 | ||
3001082c MW |
905 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
906 | const char *name) | |
907 | { | |
58ffacb5 MW |
908 | if (use_threaded_interrupts) |
909 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
ec6ce618 | 910 | nvme_irq_check, nvme_irq, |
58ffacb5 MW |
911 | IRQF_DISABLED | IRQF_SHARED, |
912 | name, nvmeq); | |
3001082c MW |
913 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
914 | IRQF_DISABLED | IRQF_SHARED, name, nvmeq); | |
915 | } | |
916 | ||
b60503ba MW |
917 | static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev, |
918 | int qid, int cq_size, int vector) | |
919 | { | |
920 | int result; | |
921 | struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector); | |
922 | ||
3f85d50b | 923 | if (!nvmeq) |
6f0f5449 | 924 | return ERR_PTR(-ENOMEM); |
3f85d50b | 925 | |
b60503ba MW |
926 | result = adapter_alloc_cq(dev, qid, nvmeq); |
927 | if (result < 0) | |
928 | goto free_nvmeq; | |
929 | ||
930 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
931 | if (result < 0) | |
932 | goto release_cq; | |
933 | ||
3001082c | 934 | result = queue_request_irq(dev, nvmeq, "nvme"); |
b60503ba MW |
935 | if (result < 0) |
936 | goto release_sq; | |
937 | ||
938 | return nvmeq; | |
939 | ||
940 | release_sq: | |
941 | adapter_delete_sq(dev, qid); | |
942 | release_cq: | |
943 | adapter_delete_cq(dev, qid); | |
944 | free_nvmeq: | |
945 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), | |
946 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
947 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
948 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
949 | kfree(nvmeq); | |
6f0f5449 | 950 | return ERR_PTR(result); |
b60503ba MW |
951 | } |
952 | ||
953 | static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev) | |
954 | { | |
955 | int result; | |
956 | u32 aqa; | |
22605f96 MW |
957 | u64 cap; |
958 | unsigned long timeout; | |
b60503ba MW |
959 | struct nvme_queue *nvmeq; |
960 | ||
961 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
962 | ||
963 | nvmeq = nvme_alloc_queue(dev, 0, 64, 0); | |
3f85d50b MW |
964 | if (!nvmeq) |
965 | return -ENOMEM; | |
b60503ba MW |
966 | |
967 | aqa = nvmeq->q_depth - 1; | |
968 | aqa |= aqa << 16; | |
969 | ||
970 | dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM; | |
971 | dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT; | |
972 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; | |
7f53f9d2 | 973 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba | 974 | |
5911f200 | 975 | writel(0, &dev->bar->cc); |
b60503ba MW |
976 | writel(aqa, &dev->bar->aqa); |
977 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
978 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
979 | writel(dev->ctrl_config, &dev->bar->cc); | |
980 | ||
22605f96 MW |
981 | cap = readq(&dev->bar->cap); |
982 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
f1938f6e | 983 | dev->db_stride = NVME_CAP_STRIDE(cap); |
22605f96 | 984 | |
b60503ba MW |
985 | while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) { |
986 | msleep(100); | |
987 | if (fatal_signal_pending(current)) | |
988 | return -EINTR; | |
22605f96 MW |
989 | if (time_after(jiffies, timeout)) { |
990 | dev_err(&dev->pci_dev->dev, | |
991 | "Device not ready; aborting initialisation\n"); | |
992 | return -ENODEV; | |
993 | } | |
b60503ba MW |
994 | } |
995 | ||
3001082c | 996 | result = queue_request_irq(dev, nvmeq, "nvme admin"); |
b60503ba MW |
997 | dev->queues[0] = nvmeq; |
998 | return result; | |
999 | } | |
1000 | ||
7fc3cdab MW |
1001 | static int nvme_map_user_pages(struct nvme_dev *dev, int write, |
1002 | unsigned long addr, unsigned length, | |
1003 | struct scatterlist **sgp) | |
b60503ba | 1004 | { |
36c14ed9 | 1005 | int i, err, count, nents, offset; |
7fc3cdab MW |
1006 | struct scatterlist *sg; |
1007 | struct page **pages; | |
36c14ed9 MW |
1008 | |
1009 | if (addr & 3) | |
1010 | return -EINVAL; | |
7fc3cdab MW |
1011 | if (!length) |
1012 | return -EINVAL; | |
1013 | ||
36c14ed9 | 1014 | offset = offset_in_page(addr); |
7fc3cdab MW |
1015 | count = DIV_ROUND_UP(offset + length, PAGE_SIZE); |
1016 | pages = kcalloc(count, sizeof(*pages), GFP_KERNEL); | |
36c14ed9 MW |
1017 | |
1018 | err = get_user_pages_fast(addr, count, 1, pages); | |
1019 | if (err < count) { | |
1020 | count = err; | |
1021 | err = -EFAULT; | |
1022 | goto put_pages; | |
1023 | } | |
7fc3cdab MW |
1024 | |
1025 | sg = kcalloc(count, sizeof(*sg), GFP_KERNEL); | |
36c14ed9 | 1026 | sg_init_table(sg, count); |
d0ba1e49 MW |
1027 | for (i = 0; i < count; i++) { |
1028 | sg_set_page(&sg[i], pages[i], | |
1029 | min_t(int, length, PAGE_SIZE - offset), offset); | |
1030 | length -= (PAGE_SIZE - offset); | |
1031 | offset = 0; | |
7fc3cdab MW |
1032 | } |
1033 | ||
1034 | err = -ENOMEM; | |
1035 | nents = dma_map_sg(&dev->pci_dev->dev, sg, count, | |
1036 | write ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
36c14ed9 MW |
1037 | if (!nents) |
1038 | goto put_pages; | |
b60503ba | 1039 | |
7fc3cdab MW |
1040 | kfree(pages); |
1041 | *sgp = sg; | |
1042 | return nents; | |
b60503ba | 1043 | |
7fc3cdab MW |
1044 | put_pages: |
1045 | for (i = 0; i < count; i++) | |
1046 | put_page(pages[i]); | |
1047 | kfree(pages); | |
1048 | return err; | |
1049 | } | |
b60503ba | 1050 | |
7fc3cdab | 1051 | static void nvme_unmap_user_pages(struct nvme_dev *dev, int write, |
d1a490e0 | 1052 | unsigned long addr, int length, struct scatterlist *sg) |
7fc3cdab MW |
1053 | { |
1054 | int i, count; | |
b60503ba | 1055 | |
7fc3cdab | 1056 | count = DIV_ROUND_UP(offset_in_page(addr) + length, PAGE_SIZE); |
d1a490e0 | 1057 | dma_unmap_sg(&dev->pci_dev->dev, sg, count, DMA_FROM_DEVICE); |
7fc3cdab | 1058 | |
36c14ed9 | 1059 | for (i = 0; i < count; i++) |
7fc3cdab MW |
1060 | put_page(sg_page(&sg[i])); |
1061 | } | |
b60503ba | 1062 | |
a53295b6 MW |
1063 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1064 | { | |
1065 | struct nvme_dev *dev = ns->dev; | |
1066 | struct nvme_queue *nvmeq; | |
1067 | struct nvme_user_io io; | |
1068 | struct nvme_command c; | |
1069 | unsigned length; | |
a53295b6 MW |
1070 | int nents, status; |
1071 | struct scatterlist *sg; | |
e025344c | 1072 | struct nvme_prps *prps; |
a53295b6 MW |
1073 | |
1074 | if (copy_from_user(&io, uio, sizeof(io))) | |
1075 | return -EFAULT; | |
6c7d4945 MW |
1076 | length = (io.nblocks + 1) << ns->lba_shift; |
1077 | ||
1078 | switch (io.opcode) { | |
1079 | case nvme_cmd_write: | |
1080 | case nvme_cmd_read: | |
6bbf1acd | 1081 | case nvme_cmd_compare: |
6c7d4945 MW |
1082 | nents = nvme_map_user_pages(dev, io.opcode & 1, io.addr, |
1083 | length, &sg); | |
6413214c | 1084 | break; |
6c7d4945 | 1085 | default: |
6bbf1acd | 1086 | return -EINVAL; |
6c7d4945 MW |
1087 | } |
1088 | ||
a53295b6 MW |
1089 | if (nents < 0) |
1090 | return nents; | |
1091 | ||
1092 | memset(&c, 0, sizeof(c)); | |
1093 | c.rw.opcode = io.opcode; | |
1094 | c.rw.flags = io.flags; | |
6c7d4945 | 1095 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1096 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1097 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 MW |
1098 | c.rw.control = cpu_to_le16(io.control); |
1099 | c.rw.dsmgmt = cpu_to_le16(io.dsmgmt); | |
6c7d4945 MW |
1100 | c.rw.reftag = io.reftag; |
1101 | c.rw.apptag = io.apptag; | |
1102 | c.rw.appmask = io.appmask; | |
a53295b6 | 1103 | /* XXX: metadata */ |
b77954cb | 1104 | prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL); |
a53295b6 | 1105 | |
040a93b5 | 1106 | nvmeq = get_nvmeq(dev); |
fa922821 MW |
1107 | /* |
1108 | * Since nvme_submit_sync_cmd sleeps, we can't keep preemption | |
b1ad37ef MW |
1109 | * disabled. We may be preempted at any point, and be rescheduled |
1110 | * to a different CPU. That will cause cacheline bouncing, but no | |
1111 | * additional races since q_lock already protects against other CPUs. | |
1112 | */ | |
a53295b6 | 1113 | put_nvmeq(nvmeq); |
b77954cb MW |
1114 | if (length != (io.nblocks + 1) << ns->lba_shift) |
1115 | status = -ENOMEM; | |
1116 | else | |
1117 | status = nvme_submit_sync_cmd(nvmeq, &c, NULL, IO_TIMEOUT); | |
a53295b6 | 1118 | |
d1a490e0 | 1119 | nvme_unmap_user_pages(dev, io.opcode & 1, io.addr, length, sg); |
d567760c | 1120 | nvme_free_prps(dev, prps); |
a53295b6 MW |
1121 | return status; |
1122 | } | |
1123 | ||
6bbf1acd MW |
1124 | static int nvme_user_admin_cmd(struct nvme_ns *ns, |
1125 | struct nvme_admin_cmd __user *ucmd) | |
6ee44cdc MW |
1126 | { |
1127 | struct nvme_dev *dev = ns->dev; | |
6bbf1acd | 1128 | struct nvme_admin_cmd cmd; |
6ee44cdc | 1129 | struct nvme_command c; |
6bbf1acd | 1130 | int status, length, nents = 0; |
6ee44cdc | 1131 | struct scatterlist *sg; |
6bbf1acd | 1132 | struct nvme_prps *prps = NULL; |
6ee44cdc | 1133 | |
6bbf1acd MW |
1134 | if (!capable(CAP_SYS_ADMIN)) |
1135 | return -EACCES; | |
1136 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1137 | return -EFAULT; |
6ee44cdc MW |
1138 | |
1139 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1140 | c.common.opcode = cmd.opcode; |
1141 | c.common.flags = cmd.flags; | |
1142 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1143 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1144 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1145 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1146 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1147 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1148 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1149 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1150 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1151 | ||
1152 | length = cmd.data_len; | |
1153 | if (cmd.data_len) { | |
1154 | nents = nvme_map_user_pages(dev, 1, cmd.addr, length, &sg); | |
1155 | if (nents < 0) | |
1156 | return nents; | |
1157 | prps = nvme_setup_prps(dev, &c.common, sg, &length, GFP_KERNEL); | |
1158 | } | |
1159 | ||
1160 | if (length != cmd.data_len) | |
b77954cb MW |
1161 | status = -ENOMEM; |
1162 | else | |
1163 | status = nvme_submit_admin_cmd(dev, &c, NULL); | |
6bbf1acd | 1164 | if (cmd.data_len) { |
d1a490e0 | 1165 | nvme_unmap_user_pages(dev, 0, cmd.addr, cmd.data_len, sg); |
6bbf1acd MW |
1166 | nvme_free_prps(dev, prps); |
1167 | } | |
6ee44cdc MW |
1168 | return status; |
1169 | } | |
1170 | ||
b60503ba MW |
1171 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1172 | unsigned long arg) | |
1173 | { | |
1174 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1175 | ||
1176 | switch (cmd) { | |
6bbf1acd MW |
1177 | case NVME_IOCTL_ID: |
1178 | return ns->ns_id; | |
1179 | case NVME_IOCTL_ADMIN_CMD: | |
1180 | return nvme_user_admin_cmd(ns, (void __user *)arg); | |
a53295b6 MW |
1181 | case NVME_IOCTL_SUBMIT_IO: |
1182 | return nvme_submit_io(ns, (void __user *)arg); | |
b60503ba MW |
1183 | default: |
1184 | return -ENOTTY; | |
1185 | } | |
1186 | } | |
1187 | ||
1188 | static const struct block_device_operations nvme_fops = { | |
1189 | .owner = THIS_MODULE, | |
1190 | .ioctl = nvme_ioctl, | |
49481682 | 1191 | .compat_ioctl = nvme_ioctl, |
b60503ba MW |
1192 | }; |
1193 | ||
8de05535 MW |
1194 | static void nvme_timeout_ios(struct nvme_queue *nvmeq) |
1195 | { | |
1196 | int depth = nvmeq->q_depth - 1; | |
1197 | struct nvme_cmd_info *info = nvme_cmd_info(nvmeq); | |
1198 | unsigned long now = jiffies; | |
1199 | int cmdid; | |
1200 | ||
1201 | for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) { | |
c2f5b650 MW |
1202 | void *ctx; |
1203 | nvme_completion_fn fn; | |
8de05535 MW |
1204 | static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, }; |
1205 | ||
1206 | if (!time_after(now, info[cmdid].timeout)) | |
1207 | continue; | |
1208 | dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid); | |
c2f5b650 MW |
1209 | ctx = cancel_cmdid(nvmeq, cmdid, &fn); |
1210 | fn(nvmeq, ctx, &cqe); | |
8de05535 MW |
1211 | } |
1212 | } | |
1213 | ||
1fa6aead MW |
1214 | static void nvme_resubmit_bios(struct nvme_queue *nvmeq) |
1215 | { | |
1216 | while (bio_list_peek(&nvmeq->sq_cong)) { | |
1217 | struct bio *bio = bio_list_pop(&nvmeq->sq_cong); | |
1218 | struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data; | |
1219 | if (nvme_submit_bio_queue(nvmeq, ns, bio)) { | |
1220 | bio_list_add_head(&nvmeq->sq_cong, bio); | |
1221 | break; | |
1222 | } | |
3cb967c0 MW |
1223 | if (bio_list_empty(&nvmeq->sq_cong)) |
1224 | remove_wait_queue(&nvmeq->sq_full, | |
1225 | &nvmeq->sq_cong_wait); | |
1fa6aead MW |
1226 | } |
1227 | } | |
1228 | ||
1229 | static int nvme_kthread(void *data) | |
1230 | { | |
1231 | struct nvme_dev *dev; | |
1232 | ||
1233 | while (!kthread_should_stop()) { | |
1234 | __set_current_state(TASK_RUNNING); | |
1235 | spin_lock(&dev_list_lock); | |
1236 | list_for_each_entry(dev, &dev_list, node) { | |
1237 | int i; | |
1238 | for (i = 0; i < dev->queue_count; i++) { | |
1239 | struct nvme_queue *nvmeq = dev->queues[i]; | |
740216fc MW |
1240 | if (!nvmeq) |
1241 | continue; | |
1fa6aead MW |
1242 | spin_lock_irq(&nvmeq->q_lock); |
1243 | if (nvme_process_cq(nvmeq)) | |
1244 | printk("process_cq did something\n"); | |
8de05535 | 1245 | nvme_timeout_ios(nvmeq); |
1fa6aead MW |
1246 | nvme_resubmit_bios(nvmeq); |
1247 | spin_unlock_irq(&nvmeq->q_lock); | |
1248 | } | |
1249 | } | |
1250 | spin_unlock(&dev_list_lock); | |
1251 | set_current_state(TASK_INTERRUPTIBLE); | |
1252 | schedule_timeout(HZ); | |
1253 | } | |
1254 | return 0; | |
1255 | } | |
1256 | ||
5aff9382 MW |
1257 | static DEFINE_IDA(nvme_index_ida); |
1258 | ||
1259 | static int nvme_get_ns_idx(void) | |
1260 | { | |
1261 | int index, error; | |
1262 | ||
1263 | do { | |
1264 | if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL)) | |
1265 | return -1; | |
1266 | ||
1267 | spin_lock(&dev_list_lock); | |
1268 | error = ida_get_new(&nvme_index_ida, &index); | |
1269 | spin_unlock(&dev_list_lock); | |
1270 | } while (error == -EAGAIN); | |
1271 | ||
1272 | if (error) | |
1273 | index = -1; | |
1274 | return index; | |
1275 | } | |
1276 | ||
1277 | static void nvme_put_ns_idx(int index) | |
1278 | { | |
1279 | spin_lock(&dev_list_lock); | |
1280 | ida_remove(&nvme_index_ida, index); | |
1281 | spin_unlock(&dev_list_lock); | |
1282 | } | |
1283 | ||
1284 | static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid, | |
b60503ba MW |
1285 | struct nvme_id_ns *id, struct nvme_lba_range_type *rt) |
1286 | { | |
1287 | struct nvme_ns *ns; | |
1288 | struct gendisk *disk; | |
1289 | int lbaf; | |
1290 | ||
1291 | if (rt->attributes & NVME_LBART_ATTRIB_HIDE) | |
1292 | return NULL; | |
1293 | ||
1294 | ns = kzalloc(sizeof(*ns), GFP_KERNEL); | |
1295 | if (!ns) | |
1296 | return NULL; | |
1297 | ns->queue = blk_alloc_queue(GFP_KERNEL); | |
1298 | if (!ns->queue) | |
1299 | goto out_free_ns; | |
1300 | ns->queue->queue_flags = QUEUE_FLAG_DEFAULT | QUEUE_FLAG_NOMERGES | | |
1301 | QUEUE_FLAG_NONROT | QUEUE_FLAG_DISCARD; | |
1302 | blk_queue_make_request(ns->queue, nvme_make_request); | |
1303 | ns->dev = dev; | |
1304 | ns->queue->queuedata = ns; | |
1305 | ||
1306 | disk = alloc_disk(NVME_MINORS); | |
1307 | if (!disk) | |
1308 | goto out_free_queue; | |
5aff9382 | 1309 | ns->ns_id = nsid; |
b60503ba MW |
1310 | ns->disk = disk; |
1311 | lbaf = id->flbas & 0xf; | |
1312 | ns->lba_shift = id->lbaf[lbaf].ds; | |
1313 | ||
1314 | disk->major = nvme_major; | |
1315 | disk->minors = NVME_MINORS; | |
5aff9382 | 1316 | disk->first_minor = NVME_MINORS * nvme_get_ns_idx(); |
b60503ba MW |
1317 | disk->fops = &nvme_fops; |
1318 | disk->private_data = ns; | |
1319 | disk->queue = ns->queue; | |
388f037f | 1320 | disk->driverfs_dev = &dev->pci_dev->dev; |
5aff9382 | 1321 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba MW |
1322 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); |
1323 | ||
1324 | return ns; | |
1325 | ||
1326 | out_free_queue: | |
1327 | blk_cleanup_queue(ns->queue); | |
1328 | out_free_ns: | |
1329 | kfree(ns); | |
1330 | return NULL; | |
1331 | } | |
1332 | ||
1333 | static void nvme_ns_free(struct nvme_ns *ns) | |
1334 | { | |
5aff9382 | 1335 | int index = ns->disk->first_minor / NVME_MINORS; |
b60503ba | 1336 | put_disk(ns->disk); |
5aff9382 | 1337 | nvme_put_ns_idx(index); |
b60503ba MW |
1338 | blk_cleanup_queue(ns->queue); |
1339 | kfree(ns); | |
1340 | } | |
1341 | ||
b3b06812 | 1342 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
1343 | { |
1344 | int status; | |
1345 | u32 result; | |
b3b06812 | 1346 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 1347 | |
bc5fc7e4 MW |
1348 | status = nvme_get_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
1349 | &result); | |
b60503ba MW |
1350 | if (status) |
1351 | return -EIO; | |
1352 | return min(result & 0xffff, result >> 16) + 1; | |
1353 | } | |
1354 | ||
b60503ba MW |
1355 | static int __devinit nvme_setup_io_queues(struct nvme_dev *dev) |
1356 | { | |
f1938f6e | 1357 | int result, cpu, i, nr_io_queues, db_bar_size; |
b60503ba | 1358 | |
b348b7d5 MW |
1359 | nr_io_queues = num_online_cpus(); |
1360 | result = set_queue_count(dev, nr_io_queues); | |
1b23484b MW |
1361 | if (result < 0) |
1362 | return result; | |
b348b7d5 MW |
1363 | if (result < nr_io_queues) |
1364 | nr_io_queues = result; | |
b60503ba | 1365 | |
1b23484b MW |
1366 | /* Deregister the admin queue's interrupt */ |
1367 | free_irq(dev->entry[0].vector, dev->queues[0]); | |
1368 | ||
f1938f6e MW |
1369 | db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3)); |
1370 | if (db_bar_size > 8192) { | |
1371 | iounmap(dev->bar); | |
1372 | dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0), | |
1373 | db_bar_size); | |
1374 | dev->dbs = ((void __iomem *)dev->bar) + 4096; | |
1375 | dev->queues[0]->q_db = dev->dbs; | |
1376 | } | |
1377 | ||
b348b7d5 | 1378 | for (i = 0; i < nr_io_queues; i++) |
1b23484b MW |
1379 | dev->entry[i].entry = i; |
1380 | for (;;) { | |
b348b7d5 MW |
1381 | result = pci_enable_msix(dev->pci_dev, dev->entry, |
1382 | nr_io_queues); | |
1b23484b MW |
1383 | if (result == 0) { |
1384 | break; | |
1385 | } else if (result > 0) { | |
b348b7d5 | 1386 | nr_io_queues = result; |
1b23484b MW |
1387 | continue; |
1388 | } else { | |
b348b7d5 | 1389 | nr_io_queues = 1; |
1b23484b MW |
1390 | break; |
1391 | } | |
1392 | } | |
1393 | ||
1394 | result = queue_request_irq(dev, dev->queues[0], "nvme admin"); | |
1395 | /* XXX: handle failure here */ | |
1396 | ||
1397 | cpu = cpumask_first(cpu_online_mask); | |
b348b7d5 | 1398 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1399 | irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu)); |
1400 | cpu = cpumask_next(cpu, cpu_online_mask); | |
1401 | } | |
1402 | ||
b348b7d5 | 1403 | for (i = 0; i < nr_io_queues; i++) { |
1b23484b MW |
1404 | dev->queues[i + 1] = nvme_create_queue(dev, i + 1, |
1405 | NVME_Q_DEPTH, i); | |
6f0f5449 MW |
1406 | if (IS_ERR(dev->queues[i + 1])) |
1407 | return PTR_ERR(dev->queues[i + 1]); | |
1b23484b MW |
1408 | dev->queue_count++; |
1409 | } | |
b60503ba | 1410 | |
9ecdc946 MW |
1411 | for (; i < num_possible_cpus(); i++) { |
1412 | int target = i % rounddown_pow_of_two(dev->queue_count - 1); | |
1413 | dev->queues[i + 1] = dev->queues[target + 1]; | |
1414 | } | |
1415 | ||
b60503ba MW |
1416 | return 0; |
1417 | } | |
1418 | ||
1419 | static void nvme_free_queues(struct nvme_dev *dev) | |
1420 | { | |
1421 | int i; | |
1422 | ||
1423 | for (i = dev->queue_count - 1; i >= 0; i--) | |
1424 | nvme_free_queue(dev, i); | |
1425 | } | |
1426 | ||
1427 | static int __devinit nvme_dev_add(struct nvme_dev *dev) | |
1428 | { | |
1429 | int res, nn, i; | |
1430 | struct nvme_ns *ns, *next; | |
51814232 | 1431 | struct nvme_id_ctrl *ctrl; |
bc5fc7e4 MW |
1432 | struct nvme_id_ns *id_ns; |
1433 | void *mem; | |
b60503ba | 1434 | dma_addr_t dma_addr; |
b60503ba MW |
1435 | |
1436 | res = nvme_setup_io_queues(dev); | |
1437 | if (res) | |
1438 | return res; | |
1439 | ||
bc5fc7e4 | 1440 | mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr, |
b60503ba MW |
1441 | GFP_KERNEL); |
1442 | ||
bc5fc7e4 | 1443 | res = nvme_identify(dev, 0, 1, dma_addr); |
b60503ba MW |
1444 | if (res) { |
1445 | res = -EIO; | |
1446 | goto out_free; | |
1447 | } | |
1448 | ||
bc5fc7e4 | 1449 | ctrl = mem; |
51814232 MW |
1450 | nn = le32_to_cpup(&ctrl->nn); |
1451 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); | |
1452 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
1453 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
b60503ba | 1454 | |
bc5fc7e4 | 1455 | id_ns = mem; |
2b2c1896 | 1456 | for (i = 1; i <= nn; i++) { |
bc5fc7e4 | 1457 | res = nvme_identify(dev, i, 0, dma_addr); |
b60503ba MW |
1458 | if (res) |
1459 | continue; | |
1460 | ||
bc5fc7e4 | 1461 | if (id_ns->ncap == 0) |
b60503ba MW |
1462 | continue; |
1463 | ||
bc5fc7e4 MW |
1464 | res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i, |
1465 | dma_addr + 4096, NULL); | |
b60503ba MW |
1466 | if (res) |
1467 | continue; | |
1468 | ||
bc5fc7e4 | 1469 | ns = nvme_alloc_ns(dev, i, mem, mem + 4096); |
b60503ba MW |
1470 | if (ns) |
1471 | list_add_tail(&ns->list, &dev->namespaces); | |
1472 | } | |
1473 | list_for_each_entry(ns, &dev->namespaces, list) | |
1474 | add_disk(ns->disk); | |
1475 | ||
bc5fc7e4 | 1476 | goto out; |
b60503ba MW |
1477 | |
1478 | out_free: | |
1479 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1480 | list_del(&ns->list); | |
1481 | nvme_ns_free(ns); | |
1482 | } | |
1483 | ||
bc5fc7e4 | 1484 | out: |
684f5c20 | 1485 | dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr); |
b60503ba MW |
1486 | return res; |
1487 | } | |
1488 | ||
1489 | static int nvme_dev_remove(struct nvme_dev *dev) | |
1490 | { | |
1491 | struct nvme_ns *ns, *next; | |
1492 | ||
1fa6aead MW |
1493 | spin_lock(&dev_list_lock); |
1494 | list_del(&dev->node); | |
1495 | spin_unlock(&dev_list_lock); | |
1496 | ||
b60503ba MW |
1497 | /* TODO: wait all I/O finished or cancel them */ |
1498 | ||
1499 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
1500 | list_del(&ns->list); | |
1501 | del_gendisk(ns->disk); | |
1502 | nvme_ns_free(ns); | |
1503 | } | |
1504 | ||
1505 | nvme_free_queues(dev); | |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
091b6092 MW |
1510 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
1511 | { | |
1512 | struct device *dmadev = &dev->pci_dev->dev; | |
1513 | dev->prp_page_pool = dma_pool_create("prp list page", dmadev, | |
1514 | PAGE_SIZE, PAGE_SIZE, 0); | |
1515 | if (!dev->prp_page_pool) | |
1516 | return -ENOMEM; | |
1517 | ||
99802a7a MW |
1518 | /* Optimisation for I/Os between 4k and 128k */ |
1519 | dev->prp_small_pool = dma_pool_create("prp list 256", dmadev, | |
1520 | 256, 256, 0); | |
1521 | if (!dev->prp_small_pool) { | |
1522 | dma_pool_destroy(dev->prp_page_pool); | |
1523 | return -ENOMEM; | |
1524 | } | |
091b6092 MW |
1525 | return 0; |
1526 | } | |
1527 | ||
1528 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
1529 | { | |
1530 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 1531 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
1532 | } |
1533 | ||
b60503ba MW |
1534 | /* XXX: Use an ida or something to let remove / add work correctly */ |
1535 | static void nvme_set_instance(struct nvme_dev *dev) | |
1536 | { | |
1537 | static int instance; | |
1538 | dev->instance = instance++; | |
1539 | } | |
1540 | ||
1541 | static void nvme_release_instance(struct nvme_dev *dev) | |
1542 | { | |
1543 | } | |
1544 | ||
1545 | static int __devinit nvme_probe(struct pci_dev *pdev, | |
1546 | const struct pci_device_id *id) | |
1547 | { | |
574e8b95 | 1548 | int bars, result = -ENOMEM; |
b60503ba MW |
1549 | struct nvme_dev *dev; |
1550 | ||
1551 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
1552 | if (!dev) | |
1553 | return -ENOMEM; | |
1554 | dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry), | |
1555 | GFP_KERNEL); | |
1556 | if (!dev->entry) | |
1557 | goto free; | |
1b23484b MW |
1558 | dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *), |
1559 | GFP_KERNEL); | |
b60503ba MW |
1560 | if (!dev->queues) |
1561 | goto free; | |
1562 | ||
0ee5a7d7 SMM |
1563 | if (pci_enable_device_mem(pdev)) |
1564 | goto free; | |
f64d3365 | 1565 | pci_set_master(pdev); |
574e8b95 MW |
1566 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1567 | if (pci_request_selected_regions(pdev, bars, "nvme")) | |
1568 | goto disable; | |
0ee5a7d7 | 1569 | |
b60503ba MW |
1570 | INIT_LIST_HEAD(&dev->namespaces); |
1571 | dev->pci_dev = pdev; | |
1572 | pci_set_drvdata(pdev, dev); | |
2930353f MW |
1573 | dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
1574 | dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); | |
b60503ba | 1575 | nvme_set_instance(dev); |
53c9577e | 1576 | dev->entry[0].vector = pdev->irq; |
b60503ba | 1577 | |
091b6092 MW |
1578 | result = nvme_setup_prp_pools(dev); |
1579 | if (result) | |
1580 | goto disable_msix; | |
1581 | ||
b60503ba MW |
1582 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
1583 | if (!dev->bar) { | |
1584 | result = -ENOMEM; | |
574e8b95 | 1585 | goto disable_msix; |
b60503ba MW |
1586 | } |
1587 | ||
1588 | result = nvme_configure_admin_queue(dev); | |
1589 | if (result) | |
1590 | goto unmap; | |
1591 | dev->queue_count++; | |
1592 | ||
1fa6aead MW |
1593 | spin_lock(&dev_list_lock); |
1594 | list_add(&dev->node, &dev_list); | |
1595 | spin_unlock(&dev_list_lock); | |
1596 | ||
740216fc MW |
1597 | result = nvme_dev_add(dev); |
1598 | if (result) | |
1599 | goto delete; | |
1600 | ||
b60503ba MW |
1601 | return 0; |
1602 | ||
1603 | delete: | |
740216fc MW |
1604 | spin_lock(&dev_list_lock); |
1605 | list_del(&dev->node); | |
1606 | spin_unlock(&dev_list_lock); | |
1607 | ||
b60503ba MW |
1608 | nvme_free_queues(dev); |
1609 | unmap: | |
1610 | iounmap(dev->bar); | |
574e8b95 | 1611 | disable_msix: |
b60503ba MW |
1612 | pci_disable_msix(pdev); |
1613 | nvme_release_instance(dev); | |
091b6092 | 1614 | nvme_release_prp_pools(dev); |
574e8b95 | 1615 | disable: |
0ee5a7d7 | 1616 | pci_disable_device(pdev); |
574e8b95 | 1617 | pci_release_regions(pdev); |
b60503ba MW |
1618 | free: |
1619 | kfree(dev->queues); | |
1620 | kfree(dev->entry); | |
1621 | kfree(dev); | |
1622 | return result; | |
1623 | } | |
1624 | ||
1625 | static void __devexit nvme_remove(struct pci_dev *pdev) | |
1626 | { | |
1627 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
1628 | nvme_dev_remove(dev); | |
1629 | pci_disable_msix(pdev); | |
1630 | iounmap(dev->bar); | |
1631 | nvme_release_instance(dev); | |
091b6092 | 1632 | nvme_release_prp_pools(dev); |
0ee5a7d7 | 1633 | pci_disable_device(pdev); |
574e8b95 | 1634 | pci_release_regions(pdev); |
b60503ba MW |
1635 | kfree(dev->queues); |
1636 | kfree(dev->entry); | |
1637 | kfree(dev); | |
1638 | } | |
1639 | ||
1640 | /* These functions are yet to be implemented */ | |
1641 | #define nvme_error_detected NULL | |
1642 | #define nvme_dump_registers NULL | |
1643 | #define nvme_link_reset NULL | |
1644 | #define nvme_slot_reset NULL | |
1645 | #define nvme_error_resume NULL | |
1646 | #define nvme_suspend NULL | |
1647 | #define nvme_resume NULL | |
1648 | ||
1649 | static struct pci_error_handlers nvme_err_handler = { | |
1650 | .error_detected = nvme_error_detected, | |
1651 | .mmio_enabled = nvme_dump_registers, | |
1652 | .link_reset = nvme_link_reset, | |
1653 | .slot_reset = nvme_slot_reset, | |
1654 | .resume = nvme_error_resume, | |
1655 | }; | |
1656 | ||
1657 | /* Move to pci_ids.h later */ | |
1658 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
1659 | ||
1660 | static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = { | |
1661 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, | |
1662 | { 0, } | |
1663 | }; | |
1664 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
1665 | ||
1666 | static struct pci_driver nvme_driver = { | |
1667 | .name = "nvme", | |
1668 | .id_table = nvme_id_table, | |
1669 | .probe = nvme_probe, | |
1670 | .remove = __devexit_p(nvme_remove), | |
1671 | .suspend = nvme_suspend, | |
1672 | .resume = nvme_resume, | |
1673 | .err_handler = &nvme_err_handler, | |
1674 | }; | |
1675 | ||
1676 | static int __init nvme_init(void) | |
1677 | { | |
1fa6aead MW |
1678 | int result = -EBUSY; |
1679 | ||
1680 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
1681 | if (IS_ERR(nvme_thread)) | |
1682 | return PTR_ERR(nvme_thread); | |
b60503ba MW |
1683 | |
1684 | nvme_major = register_blkdev(nvme_major, "nvme"); | |
1685 | if (nvme_major <= 0) | |
1fa6aead | 1686 | goto kill_kthread; |
b60503ba MW |
1687 | |
1688 | result = pci_register_driver(&nvme_driver); | |
1fa6aead MW |
1689 | if (result) |
1690 | goto unregister_blkdev; | |
1691 | return 0; | |
b60503ba | 1692 | |
1fa6aead | 1693 | unregister_blkdev: |
b60503ba | 1694 | unregister_blkdev(nvme_major, "nvme"); |
1fa6aead MW |
1695 | kill_kthread: |
1696 | kthread_stop(nvme_thread); | |
b60503ba MW |
1697 | return result; |
1698 | } | |
1699 | ||
1700 | static void __exit nvme_exit(void) | |
1701 | { | |
1702 | pci_unregister_driver(&nvme_driver); | |
1703 | unregister_blkdev(nvme_major, "nvme"); | |
1fa6aead | 1704 | kthread_stop(nvme_thread); |
b60503ba MW |
1705 | } |
1706 | ||
1707 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
1708 | MODULE_LICENSE("GPL"); | |
ce38c149 | 1709 | MODULE_VERSION("0.7"); |
b60503ba MW |
1710 | module_init(nvme_init); |
1711 | module_exit(nvme_exit); |