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b60503ba MW |
1 | /* |
2 | * NVM Express device driver | |
6eb0d698 | 3 | * Copyright (c) 2011-2014, Intel Corporation. |
b60503ba MW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
b60503ba MW |
13 | */ |
14 | ||
15 | #include <linux/nvme.h> | |
8de05535 | 16 | #include <linux/bitops.h> |
b60503ba | 17 | #include <linux/blkdev.h> |
a4aea562 | 18 | #include <linux/blk-mq.h> |
42f61420 | 19 | #include <linux/cpu.h> |
fd63e9ce | 20 | #include <linux/delay.h> |
b60503ba MW |
21 | #include <linux/errno.h> |
22 | #include <linux/fs.h> | |
23 | #include <linux/genhd.h> | |
4cc09e2d | 24 | #include <linux/hdreg.h> |
5aff9382 | 25 | #include <linux/idr.h> |
b60503ba MW |
26 | #include <linux/init.h> |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kdev_t.h> | |
1fa6aead | 30 | #include <linux/kthread.h> |
b60503ba | 31 | #include <linux/kernel.h> |
a5768aa8 | 32 | #include <linux/list_sort.h> |
b60503ba MW |
33 | #include <linux/mm.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/moduleparam.h> | |
36 | #include <linux/pci.h> | |
be7b6275 | 37 | #include <linux/poison.h> |
c3bfe717 | 38 | #include <linux/ptrace.h> |
b60503ba MW |
39 | #include <linux/sched.h> |
40 | #include <linux/slab.h> | |
e1e5e564 | 41 | #include <linux/t10-pi.h> |
b60503ba | 42 | #include <linux/types.h> |
5d0f6131 | 43 | #include <scsi/sg.h> |
797a796a HM |
44 | #include <asm-generic/io-64-nonatomic-lo-hi.h> |
45 | ||
b3fffdef | 46 | #define NVME_MINORS (1U << MINORBITS) |
9d43cf64 | 47 | #define NVME_Q_DEPTH 1024 |
d31af0a3 | 48 | #define NVME_AQ_DEPTH 256 |
b60503ba MW |
49 | #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) |
50 | #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) | |
9d43cf64 | 51 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
2484f407 | 52 | #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ) |
9d43cf64 KB |
53 | |
54 | static unsigned char admin_timeout = 60; | |
55 | module_param(admin_timeout, byte, 0644); | |
56 | MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); | |
b60503ba | 57 | |
bd67608a MW |
58 | unsigned char nvme_io_timeout = 30; |
59 | module_param_named(io_timeout, nvme_io_timeout, byte, 0644); | |
b355084a | 60 | MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); |
b60503ba | 61 | |
2484f407 DM |
62 | static unsigned char shutdown_timeout = 5; |
63 | module_param(shutdown_timeout, byte, 0644); | |
64 | MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); | |
65 | ||
b60503ba MW |
66 | static int nvme_major; |
67 | module_param(nvme_major, int, 0); | |
68 | ||
b3fffdef KB |
69 | static int nvme_char_major; |
70 | module_param(nvme_char_major, int, 0); | |
71 | ||
58ffacb5 MW |
72 | static int use_threaded_interrupts; |
73 | module_param(use_threaded_interrupts, int, 0); | |
74 | ||
1fa6aead MW |
75 | static DEFINE_SPINLOCK(dev_list_lock); |
76 | static LIST_HEAD(dev_list); | |
77 | static struct task_struct *nvme_thread; | |
9a6b9458 | 78 | static struct workqueue_struct *nvme_workq; |
b9afca3e | 79 | static wait_queue_head_t nvme_kthread_wait; |
1fa6aead | 80 | |
b3fffdef KB |
81 | static struct class *nvme_class; |
82 | ||
d4b4ff8e | 83 | static void nvme_reset_failed_dev(struct work_struct *ws); |
4cc06521 | 84 | static int nvme_reset(struct nvme_dev *dev); |
a4aea562 | 85 | static int nvme_process_cq(struct nvme_queue *nvmeq); |
d4b4ff8e | 86 | |
4d115420 KB |
87 | struct async_cmd_info { |
88 | struct kthread_work work; | |
89 | struct kthread_worker *worker; | |
a4aea562 | 90 | struct request *req; |
4d115420 KB |
91 | u32 result; |
92 | int status; | |
93 | void *ctx; | |
94 | }; | |
1fa6aead | 95 | |
b60503ba MW |
96 | /* |
97 | * An NVM Express queue. Each device has at least two (one for admin | |
98 | * commands and one for I/O commands). | |
99 | */ | |
100 | struct nvme_queue { | |
101 | struct device *q_dmadev; | |
091b6092 | 102 | struct nvme_dev *dev; |
3193f07b | 103 | char irqname[24]; /* nvme4294967295-65535\0 */ |
b60503ba MW |
104 | spinlock_t q_lock; |
105 | struct nvme_command *sq_cmds; | |
106 | volatile struct nvme_completion *cqes; | |
42483228 | 107 | struct blk_mq_tags **tags; |
b60503ba MW |
108 | dma_addr_t sq_dma_addr; |
109 | dma_addr_t cq_dma_addr; | |
b60503ba MW |
110 | u32 __iomem *q_db; |
111 | u16 q_depth; | |
6222d172 | 112 | s16 cq_vector; |
b60503ba MW |
113 | u16 sq_head; |
114 | u16 sq_tail; | |
115 | u16 cq_head; | |
c30341dc | 116 | u16 qid; |
e9539f47 MW |
117 | u8 cq_phase; |
118 | u8 cqe_seen; | |
4d115420 | 119 | struct async_cmd_info cmdinfo; |
b60503ba MW |
120 | }; |
121 | ||
122 | /* | |
123 | * Check we didin't inadvertently grow the command struct | |
124 | */ | |
125 | static inline void _nvme_check_size(void) | |
126 | { | |
127 | BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); | |
128 | BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); | |
129 | BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); | |
130 | BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); | |
131 | BUILD_BUG_ON(sizeof(struct nvme_features) != 64); | |
f8ebf840 | 132 | BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); |
c30341dc | 133 | BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); |
b60503ba MW |
134 | BUILD_BUG_ON(sizeof(struct nvme_command) != 64); |
135 | BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); | |
136 | BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); | |
137 | BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); | |
6ecec745 | 138 | BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); |
b60503ba MW |
139 | } |
140 | ||
edd10d33 | 141 | typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, |
c2f5b650 MW |
142 | struct nvme_completion *); |
143 | ||
e85248e5 | 144 | struct nvme_cmd_info { |
c2f5b650 MW |
145 | nvme_completion_fn fn; |
146 | void *ctx; | |
c30341dc | 147 | int aborted; |
a4aea562 | 148 | struct nvme_queue *nvmeq; |
ac3dd5bd | 149 | struct nvme_iod iod[0]; |
e85248e5 MW |
150 | }; |
151 | ||
ac3dd5bd JA |
152 | /* |
153 | * Max size of iod being embedded in the request payload | |
154 | */ | |
155 | #define NVME_INT_PAGES 2 | |
156 | #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size) | |
fda631ff | 157 | #define NVME_INT_MASK 0x01 |
ac3dd5bd JA |
158 | |
159 | /* | |
160 | * Will slightly overestimate the number of pages needed. This is OK | |
161 | * as it only leads to a small amount of wasted memory for the lifetime of | |
162 | * the I/O. | |
163 | */ | |
164 | static int nvme_npages(unsigned size, struct nvme_dev *dev) | |
165 | { | |
166 | unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size); | |
167 | return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); | |
168 | } | |
169 | ||
170 | static unsigned int nvme_cmd_size(struct nvme_dev *dev) | |
171 | { | |
172 | unsigned int ret = sizeof(struct nvme_cmd_info); | |
173 | ||
174 | ret += sizeof(struct nvme_iod); | |
175 | ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); | |
176 | ret += sizeof(struct scatterlist) * NVME_INT_PAGES; | |
177 | ||
178 | return ret; | |
179 | } | |
180 | ||
a4aea562 MB |
181 | static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
182 | unsigned int hctx_idx) | |
e85248e5 | 183 | { |
a4aea562 MB |
184 | struct nvme_dev *dev = data; |
185 | struct nvme_queue *nvmeq = dev->queues[0]; | |
186 | ||
42483228 KB |
187 | WARN_ON(hctx_idx != 0); |
188 | WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); | |
189 | WARN_ON(nvmeq->tags); | |
190 | ||
a4aea562 | 191 | hctx->driver_data = nvmeq; |
42483228 | 192 | nvmeq->tags = &dev->admin_tagset.tags[0]; |
a4aea562 | 193 | return 0; |
e85248e5 MW |
194 | } |
195 | ||
a4aea562 MB |
196 | static int nvme_admin_init_request(void *data, struct request *req, |
197 | unsigned int hctx_idx, unsigned int rq_idx, | |
198 | unsigned int numa_node) | |
22404274 | 199 | { |
a4aea562 MB |
200 | struct nvme_dev *dev = data; |
201 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
202 | struct nvme_queue *nvmeq = dev->queues[0]; | |
203 | ||
204 | BUG_ON(!nvmeq); | |
205 | cmd->nvmeq = nvmeq; | |
206 | return 0; | |
22404274 KB |
207 | } |
208 | ||
a4aea562 MB |
209 | static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, |
210 | unsigned int hctx_idx) | |
b60503ba | 211 | { |
a4aea562 | 212 | struct nvme_dev *dev = data; |
42483228 | 213 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; |
a4aea562 | 214 | |
42483228 KB |
215 | if (!nvmeq->tags) |
216 | nvmeq->tags = &dev->tagset.tags[hctx_idx]; | |
b60503ba | 217 | |
42483228 | 218 | WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); |
a4aea562 MB |
219 | hctx->driver_data = nvmeq; |
220 | return 0; | |
b60503ba MW |
221 | } |
222 | ||
a4aea562 MB |
223 | static int nvme_init_request(void *data, struct request *req, |
224 | unsigned int hctx_idx, unsigned int rq_idx, | |
225 | unsigned int numa_node) | |
b60503ba | 226 | { |
a4aea562 MB |
227 | struct nvme_dev *dev = data; |
228 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
229 | struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; | |
230 | ||
231 | BUG_ON(!nvmeq); | |
232 | cmd->nvmeq = nvmeq; | |
233 | return 0; | |
234 | } | |
235 | ||
236 | static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, | |
237 | nvme_completion_fn handler) | |
238 | { | |
239 | cmd->fn = handler; | |
240 | cmd->ctx = ctx; | |
241 | cmd->aborted = 0; | |
c917dfe5 | 242 | blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); |
b60503ba MW |
243 | } |
244 | ||
ac3dd5bd JA |
245 | static void *iod_get_private(struct nvme_iod *iod) |
246 | { | |
247 | return (void *) (iod->private & ~0x1UL); | |
248 | } | |
249 | ||
250 | /* | |
251 | * If bit 0 is set, the iod is embedded in the request payload. | |
252 | */ | |
253 | static bool iod_should_kfree(struct nvme_iod *iod) | |
254 | { | |
fda631ff | 255 | return (iod->private & NVME_INT_MASK) == 0; |
ac3dd5bd JA |
256 | } |
257 | ||
c2f5b650 MW |
258 | /* Special values must be less than 0x1000 */ |
259 | #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) | |
d2d87034 MW |
260 | #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) |
261 | #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) | |
262 | #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) | |
be7b6275 | 263 | |
edd10d33 | 264 | static void special_completion(struct nvme_queue *nvmeq, void *ctx, |
c2f5b650 MW |
265 | struct nvme_completion *cqe) |
266 | { | |
267 | if (ctx == CMD_CTX_CANCELLED) | |
268 | return; | |
c2f5b650 | 269 | if (ctx == CMD_CTX_COMPLETED) { |
edd10d33 | 270 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
271 | "completed id %d twice on queue %d\n", |
272 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
273 | return; | |
274 | } | |
275 | if (ctx == CMD_CTX_INVALID) { | |
edd10d33 | 276 | dev_warn(nvmeq->q_dmadev, |
c2f5b650 MW |
277 | "invalid id %d completed on queue %d\n", |
278 | cqe->command_id, le16_to_cpup(&cqe->sq_id)); | |
279 | return; | |
280 | } | |
edd10d33 | 281 | dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); |
c2f5b650 MW |
282 | } |
283 | ||
a4aea562 | 284 | static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) |
b60503ba | 285 | { |
c2f5b650 | 286 | void *ctx; |
b60503ba | 287 | |
859361a2 | 288 | if (fn) |
a4aea562 MB |
289 | *fn = cmd->fn; |
290 | ctx = cmd->ctx; | |
291 | cmd->fn = special_completion; | |
292 | cmd->ctx = CMD_CTX_CANCELLED; | |
c2f5b650 | 293 | return ctx; |
b60503ba MW |
294 | } |
295 | ||
a4aea562 MB |
296 | static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, |
297 | struct nvme_completion *cqe) | |
3c0cf138 | 298 | { |
a4aea562 MB |
299 | u32 result = le32_to_cpup(&cqe->result); |
300 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
301 | ||
302 | if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) | |
303 | ++nvmeq->dev->event_limit; | |
a5768aa8 KB |
304 | if (status != NVME_SC_SUCCESS) |
305 | return; | |
306 | ||
307 | switch (result & 0xff07) { | |
308 | case NVME_AER_NOTICE_NS_CHANGED: | |
309 | dev_info(nvmeq->q_dmadev, "rescanning\n"); | |
310 | schedule_work(&nvmeq->dev->scan_work); | |
311 | default: | |
312 | dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); | |
313 | } | |
b60503ba MW |
314 | } |
315 | ||
a4aea562 MB |
316 | static void abort_completion(struct nvme_queue *nvmeq, void *ctx, |
317 | struct nvme_completion *cqe) | |
5a92e700 | 318 | { |
a4aea562 MB |
319 | struct request *req = ctx; |
320 | ||
321 | u16 status = le16_to_cpup(&cqe->status) >> 1; | |
322 | u32 result = le32_to_cpup(&cqe->result); | |
a51afb54 | 323 | |
42483228 | 324 | blk_mq_free_request(req); |
a51afb54 | 325 | |
a4aea562 MB |
326 | dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); |
327 | ++nvmeq->dev->abort_limit; | |
5a92e700 KB |
328 | } |
329 | ||
a4aea562 MB |
330 | static void async_completion(struct nvme_queue *nvmeq, void *ctx, |
331 | struct nvme_completion *cqe) | |
b60503ba | 332 | { |
a4aea562 MB |
333 | struct async_cmd_info *cmdinfo = ctx; |
334 | cmdinfo->result = le32_to_cpup(&cqe->result); | |
335 | cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; | |
336 | queue_kthread_work(cmdinfo->worker, &cmdinfo->work); | |
42483228 | 337 | blk_mq_free_request(cmdinfo->req); |
b60503ba MW |
338 | } |
339 | ||
a4aea562 MB |
340 | static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, |
341 | unsigned int tag) | |
b60503ba | 342 | { |
42483228 | 343 | struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); |
a51afb54 | 344 | |
a4aea562 | 345 | return blk_mq_rq_to_pdu(req); |
4f5099af KB |
346 | } |
347 | ||
a4aea562 MB |
348 | /* |
349 | * Called with local interrupts disabled and the q_lock held. May not sleep. | |
350 | */ | |
351 | static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, | |
352 | nvme_completion_fn *fn) | |
4f5099af | 353 | { |
a4aea562 MB |
354 | struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); |
355 | void *ctx; | |
356 | if (tag >= nvmeq->q_depth) { | |
357 | *fn = special_completion; | |
358 | return CMD_CTX_INVALID; | |
359 | } | |
360 | if (fn) | |
361 | *fn = cmd->fn; | |
362 | ctx = cmd->ctx; | |
363 | cmd->fn = special_completion; | |
364 | cmd->ctx = CMD_CTX_COMPLETED; | |
365 | return ctx; | |
b60503ba MW |
366 | } |
367 | ||
368 | /** | |
714a7a22 | 369 | * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell |
b60503ba MW |
370 | * @nvmeq: The queue to use |
371 | * @cmd: The command to send | |
372 | * | |
373 | * Safe to use from interrupt context | |
374 | */ | |
a4aea562 | 375 | static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
b60503ba | 376 | { |
a4aea562 MB |
377 | u16 tail = nvmeq->sq_tail; |
378 | ||
b60503ba | 379 | memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); |
b60503ba MW |
380 | if (++tail == nvmeq->q_depth) |
381 | tail = 0; | |
7547881d | 382 | writel(tail, nvmeq->q_db); |
b60503ba | 383 | nvmeq->sq_tail = tail; |
b60503ba MW |
384 | |
385 | return 0; | |
386 | } | |
387 | ||
a4aea562 MB |
388 | static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) |
389 | { | |
390 | unsigned long flags; | |
391 | int ret; | |
392 | spin_lock_irqsave(&nvmeq->q_lock, flags); | |
393 | ret = __nvme_submit_cmd(nvmeq, cmd); | |
394 | spin_unlock_irqrestore(&nvmeq->q_lock, flags); | |
395 | return ret; | |
396 | } | |
397 | ||
eca18b23 | 398 | static __le64 **iod_list(struct nvme_iod *iod) |
e025344c | 399 | { |
eca18b23 | 400 | return ((void *)iod) + iod->offset; |
e025344c SMM |
401 | } |
402 | ||
ac3dd5bd JA |
403 | static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, |
404 | unsigned nseg, unsigned long private) | |
eca18b23 | 405 | { |
ac3dd5bd JA |
406 | iod->private = private; |
407 | iod->offset = offsetof(struct nvme_iod, sg[nseg]); | |
408 | iod->npages = -1; | |
409 | iod->length = nbytes; | |
410 | iod->nents = 0; | |
eca18b23 | 411 | } |
b60503ba | 412 | |
eca18b23 | 413 | static struct nvme_iod * |
ac3dd5bd JA |
414 | __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, |
415 | unsigned long priv, gfp_t gfp) | |
b60503ba | 416 | { |
eca18b23 | 417 | struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + |
ac3dd5bd | 418 | sizeof(__le64 *) * nvme_npages(bytes, dev) + |
eca18b23 MW |
419 | sizeof(struct scatterlist) * nseg, gfp); |
420 | ||
ac3dd5bd JA |
421 | if (iod) |
422 | iod_init(iod, bytes, nseg, priv); | |
eca18b23 MW |
423 | |
424 | return iod; | |
b60503ba MW |
425 | } |
426 | ||
ac3dd5bd JA |
427 | static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, |
428 | gfp_t gfp) | |
429 | { | |
430 | unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : | |
431 | sizeof(struct nvme_dsm_range); | |
ac3dd5bd JA |
432 | struct nvme_iod *iod; |
433 | ||
434 | if (rq->nr_phys_segments <= NVME_INT_PAGES && | |
435 | size <= NVME_INT_BYTES(dev)) { | |
436 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); | |
437 | ||
438 | iod = cmd->iod; | |
ac3dd5bd | 439 | iod_init(iod, size, rq->nr_phys_segments, |
fda631ff | 440 | (unsigned long) rq | NVME_INT_MASK); |
ac3dd5bd JA |
441 | return iod; |
442 | } | |
443 | ||
444 | return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, | |
445 | (unsigned long) rq, gfp); | |
446 | } | |
447 | ||
d29ec824 | 448 | static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) |
b60503ba | 449 | { |
1d090624 | 450 | const int last_prp = dev->page_size / 8 - 1; |
eca18b23 MW |
451 | int i; |
452 | __le64 **list = iod_list(iod); | |
453 | dma_addr_t prp_dma = iod->first_dma; | |
454 | ||
455 | if (iod->npages == 0) | |
456 | dma_pool_free(dev->prp_small_pool, list[0], prp_dma); | |
457 | for (i = 0; i < iod->npages; i++) { | |
458 | __le64 *prp_list = list[i]; | |
459 | dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); | |
460 | dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); | |
461 | prp_dma = next_prp_dma; | |
462 | } | |
ac3dd5bd JA |
463 | |
464 | if (iod_should_kfree(iod)) | |
465 | kfree(iod); | |
b60503ba MW |
466 | } |
467 | ||
b4ff9c8d KB |
468 | static int nvme_error_status(u16 status) |
469 | { | |
470 | switch (status & 0x7ff) { | |
471 | case NVME_SC_SUCCESS: | |
472 | return 0; | |
473 | case NVME_SC_CAP_EXCEEDED: | |
474 | return -ENOSPC; | |
475 | default: | |
476 | return -EIO; | |
477 | } | |
478 | } | |
479 | ||
52b68d7e | 480 | #ifdef CONFIG_BLK_DEV_INTEGRITY |
e1e5e564 KB |
481 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) |
482 | { | |
483 | if (be32_to_cpu(pi->ref_tag) == v) | |
484 | pi->ref_tag = cpu_to_be32(p); | |
485 | } | |
486 | ||
487 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
488 | { | |
489 | if (be32_to_cpu(pi->ref_tag) == p) | |
490 | pi->ref_tag = cpu_to_be32(v); | |
491 | } | |
492 | ||
493 | /** | |
494 | * nvme_dif_remap - remaps ref tags to bip seed and physical lba | |
495 | * | |
496 | * The virtual start sector is the one that was originally submitted by the | |
497 | * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical | |
498 | * start sector may be different. Remap protection information to match the | |
499 | * physical LBA on writes, and back to the original seed on reads. | |
500 | * | |
501 | * Type 0 and 3 do not have a ref tag, so no remapping required. | |
502 | */ | |
503 | static void nvme_dif_remap(struct request *req, | |
504 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
505 | { | |
506 | struct nvme_ns *ns = req->rq_disk->private_data; | |
507 | struct bio_integrity_payload *bip; | |
508 | struct t10_pi_tuple *pi; | |
509 | void *p, *pmap; | |
510 | u32 i, nlb, ts, phys, virt; | |
511 | ||
512 | if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) | |
513 | return; | |
514 | ||
515 | bip = bio_integrity(req->bio); | |
516 | if (!bip) | |
517 | return; | |
518 | ||
519 | pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; | |
e1e5e564 KB |
520 | |
521 | p = pmap; | |
522 | virt = bip_get_seed(bip); | |
523 | phys = nvme_block_nr(ns, blk_rq_pos(req)); | |
524 | nlb = (blk_rq_bytes(req) >> ns->lba_shift); | |
525 | ts = ns->disk->integrity->tuple_size; | |
526 | ||
527 | for (i = 0; i < nlb; i++, virt++, phys++) { | |
528 | pi = (struct t10_pi_tuple *)p; | |
529 | dif_swap(phys, virt, pi); | |
530 | p += ts; | |
531 | } | |
532 | kunmap_atomic(pmap); | |
533 | } | |
534 | ||
52b68d7e KB |
535 | static int nvme_noop_verify(struct blk_integrity_iter *iter) |
536 | { | |
537 | return 0; | |
538 | } | |
539 | ||
540 | static int nvme_noop_generate(struct blk_integrity_iter *iter) | |
541 | { | |
542 | return 0; | |
543 | } | |
544 | ||
545 | struct blk_integrity nvme_meta_noop = { | |
546 | .name = "NVME_META_NOOP", | |
547 | .generate_fn = nvme_noop_generate, | |
548 | .verify_fn = nvme_noop_verify, | |
549 | }; | |
550 | ||
551 | static void nvme_init_integrity(struct nvme_ns *ns) | |
552 | { | |
553 | struct blk_integrity integrity; | |
554 | ||
555 | switch (ns->pi_type) { | |
556 | case NVME_NS_DPS_PI_TYPE3: | |
557 | integrity = t10_pi_type3_crc; | |
558 | break; | |
559 | case NVME_NS_DPS_PI_TYPE1: | |
560 | case NVME_NS_DPS_PI_TYPE2: | |
561 | integrity = t10_pi_type1_crc; | |
562 | break; | |
563 | default: | |
564 | integrity = nvme_meta_noop; | |
565 | break; | |
566 | } | |
567 | integrity.tuple_size = ns->ms; | |
568 | blk_integrity_register(ns->disk, &integrity); | |
569 | blk_queue_max_integrity_segments(ns->queue, 1); | |
570 | } | |
571 | #else /* CONFIG_BLK_DEV_INTEGRITY */ | |
572 | static void nvme_dif_remap(struct request *req, | |
573 | void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) | |
574 | { | |
575 | } | |
576 | static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) | |
577 | { | |
578 | } | |
579 | static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) | |
580 | { | |
581 | } | |
582 | static void nvme_init_integrity(struct nvme_ns *ns) | |
583 | { | |
584 | } | |
585 | #endif | |
586 | ||
a4aea562 | 587 | static void req_completion(struct nvme_queue *nvmeq, void *ctx, |
b60503ba MW |
588 | struct nvme_completion *cqe) |
589 | { | |
eca18b23 | 590 | struct nvme_iod *iod = ctx; |
ac3dd5bd | 591 | struct request *req = iod_get_private(iod); |
a4aea562 MB |
592 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
593 | ||
b60503ba MW |
594 | u16 status = le16_to_cpup(&cqe->status) >> 1; |
595 | ||
edd10d33 | 596 | if (unlikely(status)) { |
a4aea562 MB |
597 | if (!(status & NVME_SC_DNR || blk_noretry_request(req)) |
598 | && (jiffies - req->start_time) < req->timeout) { | |
c9d3bf88 KB |
599 | unsigned long flags; |
600 | ||
a4aea562 | 601 | blk_mq_requeue_request(req); |
c9d3bf88 KB |
602 | spin_lock_irqsave(req->q->queue_lock, flags); |
603 | if (!blk_queue_stopped(req->q)) | |
604 | blk_mq_kick_requeue_list(req->q); | |
605 | spin_unlock_irqrestore(req->q->queue_lock, flags); | |
edd10d33 KB |
606 | return; |
607 | } | |
d29ec824 | 608 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
d29ec824 CH |
609 | req->errors = status; |
610 | } else { | |
611 | req->errors = nvme_error_status(status); | |
612 | } | |
a4aea562 MB |
613 | } else |
614 | req->errors = 0; | |
a0a931d6 KB |
615 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) { |
616 | u32 result = le32_to_cpup(&cqe->result); | |
617 | req->special = (void *)(uintptr_t)result; | |
618 | } | |
a4aea562 MB |
619 | |
620 | if (cmd_rq->aborted) | |
e75ec752 | 621 | dev_warn(nvmeq->dev->dev, |
a4aea562 MB |
622 | "completing aborted command with status:%04x\n", |
623 | status); | |
624 | ||
e1e5e564 | 625 | if (iod->nents) { |
e75ec752 | 626 | dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents, |
a4aea562 | 627 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
e1e5e564 KB |
628 | if (blk_integrity_rq(req)) { |
629 | if (!rq_data_dir(req)) | |
630 | nvme_dif_remap(req, nvme_dif_complete); | |
e75ec752 | 631 | dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1, |
e1e5e564 KB |
632 | rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); |
633 | } | |
634 | } | |
edd10d33 | 635 | nvme_free_iod(nvmeq->dev, iod); |
3291fa57 | 636 | |
a4aea562 | 637 | blk_mq_complete_request(req); |
b60503ba MW |
638 | } |
639 | ||
184d2944 | 640 | /* length is in bytes. gfp flags indicates whether we may sleep. */ |
d29ec824 CH |
641 | static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, |
642 | int total_len, gfp_t gfp) | |
ff22b54f | 643 | { |
99802a7a | 644 | struct dma_pool *pool; |
eca18b23 MW |
645 | int length = total_len; |
646 | struct scatterlist *sg = iod->sg; | |
ff22b54f MW |
647 | int dma_len = sg_dma_len(sg); |
648 | u64 dma_addr = sg_dma_address(sg); | |
f137e0f1 MI |
649 | u32 page_size = dev->page_size; |
650 | int offset = dma_addr & (page_size - 1); | |
e025344c | 651 | __le64 *prp_list; |
eca18b23 | 652 | __le64 **list = iod_list(iod); |
e025344c | 653 | dma_addr_t prp_dma; |
eca18b23 | 654 | int nprps, i; |
ff22b54f | 655 | |
1d090624 | 656 | length -= (page_size - offset); |
ff22b54f | 657 | if (length <= 0) |
eca18b23 | 658 | return total_len; |
ff22b54f | 659 | |
1d090624 | 660 | dma_len -= (page_size - offset); |
ff22b54f | 661 | if (dma_len) { |
1d090624 | 662 | dma_addr += (page_size - offset); |
ff22b54f MW |
663 | } else { |
664 | sg = sg_next(sg); | |
665 | dma_addr = sg_dma_address(sg); | |
666 | dma_len = sg_dma_len(sg); | |
667 | } | |
668 | ||
1d090624 | 669 | if (length <= page_size) { |
edd10d33 | 670 | iod->first_dma = dma_addr; |
eca18b23 | 671 | return total_len; |
e025344c SMM |
672 | } |
673 | ||
1d090624 | 674 | nprps = DIV_ROUND_UP(length, page_size); |
99802a7a MW |
675 | if (nprps <= (256 / 8)) { |
676 | pool = dev->prp_small_pool; | |
eca18b23 | 677 | iod->npages = 0; |
99802a7a MW |
678 | } else { |
679 | pool = dev->prp_page_pool; | |
eca18b23 | 680 | iod->npages = 1; |
99802a7a MW |
681 | } |
682 | ||
b77954cb MW |
683 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
684 | if (!prp_list) { | |
edd10d33 | 685 | iod->first_dma = dma_addr; |
eca18b23 | 686 | iod->npages = -1; |
1d090624 | 687 | return (total_len - length) + page_size; |
b77954cb | 688 | } |
eca18b23 MW |
689 | list[0] = prp_list; |
690 | iod->first_dma = prp_dma; | |
e025344c SMM |
691 | i = 0; |
692 | for (;;) { | |
1d090624 | 693 | if (i == page_size >> 3) { |
e025344c | 694 | __le64 *old_prp_list = prp_list; |
b77954cb | 695 | prp_list = dma_pool_alloc(pool, gfp, &prp_dma); |
eca18b23 MW |
696 | if (!prp_list) |
697 | return total_len - length; | |
698 | list[iod->npages++] = prp_list; | |
7523d834 MW |
699 | prp_list[0] = old_prp_list[i - 1]; |
700 | old_prp_list[i - 1] = cpu_to_le64(prp_dma); | |
701 | i = 1; | |
e025344c SMM |
702 | } |
703 | prp_list[i++] = cpu_to_le64(dma_addr); | |
1d090624 KB |
704 | dma_len -= page_size; |
705 | dma_addr += page_size; | |
706 | length -= page_size; | |
e025344c SMM |
707 | if (length <= 0) |
708 | break; | |
709 | if (dma_len > 0) | |
710 | continue; | |
711 | BUG_ON(dma_len < 0); | |
712 | sg = sg_next(sg); | |
713 | dma_addr = sg_dma_address(sg); | |
714 | dma_len = sg_dma_len(sg); | |
ff22b54f MW |
715 | } |
716 | ||
eca18b23 | 717 | return total_len; |
ff22b54f MW |
718 | } |
719 | ||
d29ec824 CH |
720 | static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req, |
721 | struct nvme_iod *iod) | |
722 | { | |
723 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
724 | ||
725 | memcpy(cmnd, req->cmd, sizeof(struct nvme_command)); | |
726 | cmnd->rw.command_id = req->tag; | |
727 | if (req->nr_phys_segments) { | |
728 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); | |
729 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
730 | } | |
731 | ||
732 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
733 | nvmeq->sq_tail = 0; | |
734 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
735 | } | |
736 | ||
a4aea562 MB |
737 | /* |
738 | * We reuse the small pool to allocate the 16-byte range here as it is not | |
739 | * worth having a special pool for these or additional cases to handle freeing | |
740 | * the iod. | |
741 | */ | |
742 | static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, | |
743 | struct request *req, struct nvme_iod *iod) | |
0e5e4f0e | 744 | { |
edd10d33 KB |
745 | struct nvme_dsm_range *range = |
746 | (struct nvme_dsm_range *)iod_list(iod)[0]; | |
0e5e4f0e KB |
747 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
748 | ||
0e5e4f0e | 749 | range->cattr = cpu_to_le32(0); |
a4aea562 MB |
750 | range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); |
751 | range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); | |
0e5e4f0e KB |
752 | |
753 | memset(cmnd, 0, sizeof(*cmnd)); | |
754 | cmnd->dsm.opcode = nvme_cmd_dsm; | |
a4aea562 | 755 | cmnd->dsm.command_id = req->tag; |
0e5e4f0e KB |
756 | cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); |
757 | cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); | |
758 | cmnd->dsm.nr = 0; | |
759 | cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); | |
760 | ||
761 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
762 | nvmeq->sq_tail = 0; | |
763 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
0e5e4f0e KB |
764 | } |
765 | ||
a4aea562 | 766 | static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns, |
00df5cb4 MW |
767 | int cmdid) |
768 | { | |
769 | struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; | |
770 | ||
771 | memset(cmnd, 0, sizeof(*cmnd)); | |
772 | cmnd->common.opcode = nvme_cmd_flush; | |
773 | cmnd->common.command_id = cmdid; | |
774 | cmnd->common.nsid = cpu_to_le32(ns->ns_id); | |
775 | ||
776 | if (++nvmeq->sq_tail == nvmeq->q_depth) | |
777 | nvmeq->sq_tail = 0; | |
778 | writel(nvmeq->sq_tail, nvmeq->q_db); | |
00df5cb4 MW |
779 | } |
780 | ||
a4aea562 MB |
781 | static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod, |
782 | struct nvme_ns *ns) | |
b60503ba | 783 | { |
ac3dd5bd | 784 | struct request *req = iod_get_private(iod); |
ff22b54f | 785 | struct nvme_command *cmnd; |
a4aea562 MB |
786 | u16 control = 0; |
787 | u32 dsmgmt = 0; | |
00df5cb4 | 788 | |
a4aea562 | 789 | if (req->cmd_flags & REQ_FUA) |
b60503ba | 790 | control |= NVME_RW_FUA; |
a4aea562 | 791 | if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD)) |
b60503ba MW |
792 | control |= NVME_RW_LR; |
793 | ||
a4aea562 | 794 | if (req->cmd_flags & REQ_RAHEAD) |
b60503ba MW |
795 | dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH; |
796 | ||
ff22b54f | 797 | cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail]; |
b8deb62c | 798 | memset(cmnd, 0, sizeof(*cmnd)); |
b60503ba | 799 | |
a4aea562 MB |
800 | cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read); |
801 | cmnd->rw.command_id = req->tag; | |
ff22b54f | 802 | cmnd->rw.nsid = cpu_to_le32(ns->ns_id); |
edd10d33 KB |
803 | cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); |
804 | cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); | |
a4aea562 MB |
805 | cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); |
806 | cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1); | |
e1e5e564 KB |
807 | |
808 | if (blk_integrity_rq(req)) { | |
809 | cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); | |
810 | switch (ns->pi_type) { | |
811 | case NVME_NS_DPS_PI_TYPE3: | |
812 | control |= NVME_RW_PRINFO_PRCHK_GUARD; | |
813 | break; | |
814 | case NVME_NS_DPS_PI_TYPE1: | |
815 | case NVME_NS_DPS_PI_TYPE2: | |
816 | control |= NVME_RW_PRINFO_PRCHK_GUARD | | |
817 | NVME_RW_PRINFO_PRCHK_REF; | |
818 | cmnd->rw.reftag = cpu_to_le32( | |
819 | nvme_block_nr(ns, blk_rq_pos(req))); | |
820 | break; | |
821 | } | |
822 | } else if (ns->ms) | |
823 | control |= NVME_RW_PRINFO_PRACT; | |
824 | ||
ff22b54f MW |
825 | cmnd->rw.control = cpu_to_le16(control); |
826 | cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt); | |
b60503ba | 827 | |
b60503ba MW |
828 | if (++nvmeq->sq_tail == nvmeq->q_depth) |
829 | nvmeq->sq_tail = 0; | |
7547881d | 830 | writel(nvmeq->sq_tail, nvmeq->q_db); |
b60503ba | 831 | |
1974b1ae | 832 | return 0; |
edd10d33 KB |
833 | } |
834 | ||
d29ec824 CH |
835 | /* |
836 | * NOTE: ns is NULL when called on the admin queue. | |
837 | */ | |
a4aea562 MB |
838 | static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, |
839 | const struct blk_mq_queue_data *bd) | |
edd10d33 | 840 | { |
a4aea562 MB |
841 | struct nvme_ns *ns = hctx->queue->queuedata; |
842 | struct nvme_queue *nvmeq = hctx->driver_data; | |
d29ec824 | 843 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
844 | struct request *req = bd->rq; |
845 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); | |
edd10d33 | 846 | struct nvme_iod *iod; |
a4aea562 | 847 | enum dma_data_direction dma_dir; |
edd10d33 | 848 | |
e1e5e564 KB |
849 | /* |
850 | * If formated with metadata, require the block layer provide a buffer | |
851 | * unless this namespace is formated such that the metadata can be | |
852 | * stripped/generated by the controller with PRACT=1. | |
853 | */ | |
d29ec824 | 854 | if (ns && ns->ms && !blk_integrity_rq(req)) { |
71feb364 KB |
855 | if (!(ns->pi_type && ns->ms == 8) && |
856 | req->cmd_type != REQ_TYPE_DRV_PRIV) { | |
e1e5e564 KB |
857 | req->errors = -EFAULT; |
858 | blk_mq_complete_request(req); | |
859 | return BLK_MQ_RQ_QUEUE_OK; | |
860 | } | |
861 | } | |
862 | ||
d29ec824 | 863 | iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); |
edd10d33 | 864 | if (!iod) |
fe54303e | 865 | return BLK_MQ_RQ_QUEUE_BUSY; |
a4aea562 | 866 | |
a4aea562 | 867 | if (req->cmd_flags & REQ_DISCARD) { |
edd10d33 KB |
868 | void *range; |
869 | /* | |
870 | * We reuse the small pool to allocate the 16-byte range here | |
871 | * as it is not worth having a special pool for these or | |
872 | * additional cases to handle freeing the iod. | |
873 | */ | |
d29ec824 | 874 | range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC, |
edd10d33 | 875 | &iod->first_dma); |
a4aea562 | 876 | if (!range) |
fe54303e | 877 | goto retry_cmd; |
edd10d33 KB |
878 | iod_list(iod)[0] = (__le64 *)range; |
879 | iod->npages = 0; | |
ac3dd5bd | 880 | } else if (req->nr_phys_segments) { |
a4aea562 MB |
881 | dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE; |
882 | ||
ac3dd5bd | 883 | sg_init_table(iod->sg, req->nr_phys_segments); |
a4aea562 | 884 | iod->nents = blk_rq_map_sg(req->q, req, iod->sg); |
fe54303e JA |
885 | if (!iod->nents) |
886 | goto error_cmd; | |
a4aea562 MB |
887 | |
888 | if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir)) | |
fe54303e | 889 | goto retry_cmd; |
a4aea562 | 890 | |
fe54303e | 891 | if (blk_rq_bytes(req) != |
d29ec824 CH |
892 | nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) { |
893 | dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); | |
fe54303e JA |
894 | goto retry_cmd; |
895 | } | |
e1e5e564 KB |
896 | if (blk_integrity_rq(req)) { |
897 | if (blk_rq_count_integrity_sg(req->q, req->bio) != 1) | |
898 | goto error_cmd; | |
899 | ||
900 | sg_init_table(iod->meta_sg, 1); | |
901 | if (blk_rq_map_integrity_sg( | |
902 | req->q, req->bio, iod->meta_sg) != 1) | |
903 | goto error_cmd; | |
904 | ||
905 | if (rq_data_dir(req)) | |
906 | nvme_dif_remap(req, nvme_dif_prep); | |
907 | ||
908 | if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir)) | |
909 | goto error_cmd; | |
910 | } | |
edd10d33 | 911 | } |
1974b1ae | 912 | |
9af8785a | 913 | nvme_set_info(cmd, iod, req_completion); |
a4aea562 | 914 | spin_lock_irq(&nvmeq->q_lock); |
d29ec824 CH |
915 | if (req->cmd_type == REQ_TYPE_DRV_PRIV) |
916 | nvme_submit_priv(nvmeq, req, iod); | |
917 | else if (req->cmd_flags & REQ_DISCARD) | |
a4aea562 MB |
918 | nvme_submit_discard(nvmeq, ns, req, iod); |
919 | else if (req->cmd_flags & REQ_FLUSH) | |
920 | nvme_submit_flush(nvmeq, ns, req->tag); | |
921 | else | |
922 | nvme_submit_iod(nvmeq, iod, ns); | |
923 | ||
924 | nvme_process_cq(nvmeq); | |
925 | spin_unlock_irq(&nvmeq->q_lock); | |
926 | return BLK_MQ_RQ_QUEUE_OK; | |
927 | ||
fe54303e | 928 | error_cmd: |
d29ec824 | 929 | nvme_free_iod(dev, iod); |
fe54303e JA |
930 | return BLK_MQ_RQ_QUEUE_ERROR; |
931 | retry_cmd: | |
d29ec824 | 932 | nvme_free_iod(dev, iod); |
fe54303e | 933 | return BLK_MQ_RQ_QUEUE_BUSY; |
b60503ba MW |
934 | } |
935 | ||
e9539f47 | 936 | static int nvme_process_cq(struct nvme_queue *nvmeq) |
b60503ba | 937 | { |
82123460 | 938 | u16 head, phase; |
b60503ba | 939 | |
b60503ba | 940 | head = nvmeq->cq_head; |
82123460 | 941 | phase = nvmeq->cq_phase; |
b60503ba MW |
942 | |
943 | for (;;) { | |
c2f5b650 MW |
944 | void *ctx; |
945 | nvme_completion_fn fn; | |
b60503ba | 946 | struct nvme_completion cqe = nvmeq->cqes[head]; |
82123460 | 947 | if ((le16_to_cpu(cqe.status) & 1) != phase) |
b60503ba MW |
948 | break; |
949 | nvmeq->sq_head = le16_to_cpu(cqe.sq_head); | |
950 | if (++head == nvmeq->q_depth) { | |
951 | head = 0; | |
82123460 | 952 | phase = !phase; |
b60503ba | 953 | } |
a4aea562 | 954 | ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); |
edd10d33 | 955 | fn(nvmeq, ctx, &cqe); |
b60503ba MW |
956 | } |
957 | ||
958 | /* If the controller ignores the cq head doorbell and continuously | |
959 | * writes to the queue, it is theoretically possible to wrap around | |
960 | * the queue twice and mistakenly return IRQ_NONE. Linux only | |
961 | * requires that 0.1% of your interrupts are handled, so this isn't | |
962 | * a big problem. | |
963 | */ | |
82123460 | 964 | if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) |
e9539f47 | 965 | return 0; |
b60503ba | 966 | |
b80d5ccc | 967 | writel(head, nvmeq->q_db + nvmeq->dev->db_stride); |
b60503ba | 968 | nvmeq->cq_head = head; |
82123460 | 969 | nvmeq->cq_phase = phase; |
b60503ba | 970 | |
e9539f47 MW |
971 | nvmeq->cqe_seen = 1; |
972 | return 1; | |
b60503ba MW |
973 | } |
974 | ||
975 | static irqreturn_t nvme_irq(int irq, void *data) | |
58ffacb5 MW |
976 | { |
977 | irqreturn_t result; | |
978 | struct nvme_queue *nvmeq = data; | |
979 | spin_lock(&nvmeq->q_lock); | |
e9539f47 MW |
980 | nvme_process_cq(nvmeq); |
981 | result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; | |
982 | nvmeq->cqe_seen = 0; | |
58ffacb5 MW |
983 | spin_unlock(&nvmeq->q_lock); |
984 | return result; | |
985 | } | |
986 | ||
987 | static irqreturn_t nvme_irq_check(int irq, void *data) | |
988 | { | |
989 | struct nvme_queue *nvmeq = data; | |
990 | struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; | |
991 | if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) | |
992 | return IRQ_NONE; | |
993 | return IRQ_WAKE_THREAD; | |
994 | } | |
995 | ||
b60503ba MW |
996 | /* |
997 | * Returns 0 on success. If the result is negative, it's a Linux error code; | |
998 | * if the result is positive, it's an NVM Express status code | |
999 | */ | |
d29ec824 CH |
1000 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
1001 | void *buffer, void __user *ubuffer, unsigned bufflen, | |
1002 | u32 *result, unsigned timeout) | |
b60503ba | 1003 | { |
d29ec824 CH |
1004 | bool write = cmd->common.opcode & 1; |
1005 | struct bio *bio = NULL; | |
f705f837 | 1006 | struct request *req; |
d29ec824 | 1007 | int ret; |
b60503ba | 1008 | |
d29ec824 | 1009 | req = blk_mq_alloc_request(q, write, GFP_KERNEL, false); |
f705f837 CH |
1010 | if (IS_ERR(req)) |
1011 | return PTR_ERR(req); | |
b60503ba | 1012 | |
d29ec824 | 1013 | req->cmd_type = REQ_TYPE_DRV_PRIV; |
e112af0d | 1014 | req->cmd_flags |= REQ_FAILFAST_DRIVER; |
d29ec824 CH |
1015 | req->__data_len = 0; |
1016 | req->__sector = (sector_t) -1; | |
1017 | req->bio = req->biotail = NULL; | |
b60503ba | 1018 | |
f4ff414a | 1019 | req->timeout = timeout ? timeout : ADMIN_TIMEOUT; |
a4aea562 | 1020 | |
d29ec824 CH |
1021 | req->cmd = (unsigned char *)cmd; |
1022 | req->cmd_len = sizeof(struct nvme_command); | |
a0a931d6 | 1023 | req->special = (void *)0; |
b60503ba | 1024 | |
d29ec824 CH |
1025 | if (buffer && bufflen) { |
1026 | ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT); | |
1027 | if (ret) | |
1028 | goto out; | |
1029 | } else if (ubuffer && bufflen) { | |
1030 | ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT); | |
1031 | if (ret) | |
1032 | goto out; | |
1033 | bio = req->bio; | |
1034 | } | |
3c0cf138 | 1035 | |
d29ec824 CH |
1036 | blk_execute_rq(req->q, NULL, req, 0); |
1037 | if (bio) | |
1038 | blk_rq_unmap_user(bio); | |
b60503ba | 1039 | if (result) |
a0a931d6 | 1040 | *result = (u32)(uintptr_t)req->special; |
d29ec824 CH |
1041 | ret = req->errors; |
1042 | out: | |
f705f837 | 1043 | blk_mq_free_request(req); |
d29ec824 | 1044 | return ret; |
f705f837 CH |
1045 | } |
1046 | ||
d29ec824 CH |
1047 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
1048 | void *buffer, unsigned bufflen) | |
f705f837 | 1049 | { |
d29ec824 | 1050 | return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0); |
b60503ba MW |
1051 | } |
1052 | ||
a4aea562 MB |
1053 | static int nvme_submit_async_admin_req(struct nvme_dev *dev) |
1054 | { | |
1055 | struct nvme_queue *nvmeq = dev->queues[0]; | |
1056 | struct nvme_command c; | |
1057 | struct nvme_cmd_info *cmd_info; | |
1058 | struct request *req; | |
1059 | ||
1efccc9d | 1060 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true); |
9f173b33 DC |
1061 | if (IS_ERR(req)) |
1062 | return PTR_ERR(req); | |
a4aea562 | 1063 | |
c917dfe5 | 1064 | req->cmd_flags |= REQ_NO_TIMEOUT; |
a4aea562 | 1065 | cmd_info = blk_mq_rq_to_pdu(req); |
1efccc9d | 1066 | nvme_set_info(cmd_info, NULL, async_req_completion); |
a4aea562 MB |
1067 | |
1068 | memset(&c, 0, sizeof(c)); | |
1069 | c.common.opcode = nvme_admin_async_event; | |
1070 | c.common.command_id = req->tag; | |
1071 | ||
42483228 | 1072 | blk_mq_free_request(req); |
a4aea562 MB |
1073 | return __nvme_submit_cmd(nvmeq, &c); |
1074 | } | |
1075 | ||
1076 | static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, | |
4d115420 KB |
1077 | struct nvme_command *cmd, |
1078 | struct async_cmd_info *cmdinfo, unsigned timeout) | |
1079 | { | |
a4aea562 MB |
1080 | struct nvme_queue *nvmeq = dev->queues[0]; |
1081 | struct request *req; | |
1082 | struct nvme_cmd_info *cmd_rq; | |
4d115420 | 1083 | |
a4aea562 | 1084 | req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false); |
9f173b33 DC |
1085 | if (IS_ERR(req)) |
1086 | return PTR_ERR(req); | |
a4aea562 MB |
1087 | |
1088 | req->timeout = timeout; | |
1089 | cmd_rq = blk_mq_rq_to_pdu(req); | |
1090 | cmdinfo->req = req; | |
1091 | nvme_set_info(cmd_rq, cmdinfo, async_completion); | |
4d115420 | 1092 | cmdinfo->status = -EINTR; |
a4aea562 MB |
1093 | |
1094 | cmd->common.command_id = req->tag; | |
1095 | ||
4f5099af | 1096 | return nvme_submit_cmd(nvmeq, cmd); |
4d115420 KB |
1097 | } |
1098 | ||
b60503ba MW |
1099 | static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) |
1100 | { | |
b60503ba MW |
1101 | struct nvme_command c; |
1102 | ||
1103 | memset(&c, 0, sizeof(c)); | |
1104 | c.delete_queue.opcode = opcode; | |
1105 | c.delete_queue.qid = cpu_to_le16(id); | |
1106 | ||
d29ec824 | 1107 | return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0); |
b60503ba MW |
1108 | } |
1109 | ||
1110 | static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, | |
1111 | struct nvme_queue *nvmeq) | |
1112 | { | |
b60503ba MW |
1113 | struct nvme_command c; |
1114 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; | |
1115 | ||
d29ec824 CH |
1116 | /* |
1117 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1118 | * is attached to the request. | |
1119 | */ | |
b60503ba MW |
1120 | memset(&c, 0, sizeof(c)); |
1121 | c.create_cq.opcode = nvme_admin_create_cq; | |
1122 | c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); | |
1123 | c.create_cq.cqid = cpu_to_le16(qid); | |
1124 | c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1125 | c.create_cq.cq_flags = cpu_to_le16(flags); | |
1126 | c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); | |
1127 | ||
d29ec824 | 1128 | return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0); |
b60503ba MW |
1129 | } |
1130 | ||
1131 | static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, | |
1132 | struct nvme_queue *nvmeq) | |
1133 | { | |
b60503ba MW |
1134 | struct nvme_command c; |
1135 | int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; | |
1136 | ||
d29ec824 CH |
1137 | /* |
1138 | * Note: we (ab)use the fact the the prp fields survive if no data | |
1139 | * is attached to the request. | |
1140 | */ | |
b60503ba MW |
1141 | memset(&c, 0, sizeof(c)); |
1142 | c.create_sq.opcode = nvme_admin_create_sq; | |
1143 | c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); | |
1144 | c.create_sq.sqid = cpu_to_le16(qid); | |
1145 | c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); | |
1146 | c.create_sq.sq_flags = cpu_to_le16(flags); | |
1147 | c.create_sq.cqid = cpu_to_le16(qid); | |
1148 | ||
d29ec824 | 1149 | return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0); |
b60503ba MW |
1150 | } |
1151 | ||
1152 | static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) | |
1153 | { | |
1154 | return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); | |
1155 | } | |
1156 | ||
1157 | static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) | |
1158 | { | |
1159 | return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); | |
1160 | } | |
1161 | ||
d29ec824 | 1162 | int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id) |
bc5fc7e4 | 1163 | { |
d29ec824 CH |
1164 | struct nvme_command c = { |
1165 | .identify.opcode = nvme_admin_identify, | |
1166 | .identify.cns = cpu_to_le32(1), | |
1167 | }; | |
1168 | int error; | |
bc5fc7e4 | 1169 | |
d29ec824 CH |
1170 | *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL); |
1171 | if (!*id) | |
1172 | return -ENOMEM; | |
bc5fc7e4 | 1173 | |
d29ec824 CH |
1174 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, |
1175 | sizeof(struct nvme_id_ctrl)); | |
1176 | if (error) | |
1177 | kfree(*id); | |
1178 | return error; | |
1179 | } | |
1180 | ||
1181 | int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid, | |
1182 | struct nvme_id_ns **id) | |
1183 | { | |
1184 | struct nvme_command c = { | |
1185 | .identify.opcode = nvme_admin_identify, | |
1186 | .identify.nsid = cpu_to_le32(nsid), | |
1187 | }; | |
1188 | int error; | |
bc5fc7e4 | 1189 | |
d29ec824 CH |
1190 | *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL); |
1191 | if (!*id) | |
1192 | return -ENOMEM; | |
1193 | ||
1194 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *id, | |
1195 | sizeof(struct nvme_id_ns)); | |
1196 | if (error) | |
1197 | kfree(*id); | |
1198 | return error; | |
bc5fc7e4 MW |
1199 | } |
1200 | ||
5d0f6131 | 1201 | int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid, |
08df1e05 | 1202 | dma_addr_t dma_addr, u32 *result) |
bc5fc7e4 MW |
1203 | { |
1204 | struct nvme_command c; | |
1205 | ||
1206 | memset(&c, 0, sizeof(c)); | |
1207 | c.features.opcode = nvme_admin_get_features; | |
a42cecce | 1208 | c.features.nsid = cpu_to_le32(nsid); |
bc5fc7e4 MW |
1209 | c.features.prp1 = cpu_to_le64(dma_addr); |
1210 | c.features.fid = cpu_to_le32(fid); | |
bc5fc7e4 | 1211 | |
d29ec824 CH |
1212 | return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0, |
1213 | result, 0); | |
df348139 MW |
1214 | } |
1215 | ||
5d0f6131 VV |
1216 | int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11, |
1217 | dma_addr_t dma_addr, u32 *result) | |
df348139 MW |
1218 | { |
1219 | struct nvme_command c; | |
1220 | ||
1221 | memset(&c, 0, sizeof(c)); | |
1222 | c.features.opcode = nvme_admin_set_features; | |
1223 | c.features.prp1 = cpu_to_le64(dma_addr); | |
1224 | c.features.fid = cpu_to_le32(fid); | |
1225 | c.features.dword11 = cpu_to_le32(dword11); | |
1226 | ||
d29ec824 CH |
1227 | return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0, |
1228 | result, 0); | |
1229 | } | |
1230 | ||
1231 | int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log) | |
1232 | { | |
1233 | struct nvme_command c = { | |
1234 | .common.opcode = nvme_admin_get_log_page, | |
1235 | .common.nsid = cpu_to_le32(0xFFFFFFFF), | |
1236 | .common.cdw10[0] = cpu_to_le32( | |
1237 | (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) | | |
1238 | NVME_LOG_SMART), | |
1239 | }; | |
1240 | int error; | |
1241 | ||
1242 | *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL); | |
1243 | if (!*log) | |
1244 | return -ENOMEM; | |
1245 | ||
1246 | error = nvme_submit_sync_cmd(dev->admin_q, &c, *log, | |
1247 | sizeof(struct nvme_smart_log)); | |
1248 | if (error) | |
1249 | kfree(*log); | |
1250 | return error; | |
bc5fc7e4 MW |
1251 | } |
1252 | ||
c30341dc | 1253 | /** |
a4aea562 | 1254 | * nvme_abort_req - Attempt aborting a request |
c30341dc KB |
1255 | * |
1256 | * Schedule controller reset if the command was already aborted once before and | |
1257 | * still hasn't been returned to the driver, or if this is the admin queue. | |
1258 | */ | |
a4aea562 | 1259 | static void nvme_abort_req(struct request *req) |
c30341dc | 1260 | { |
a4aea562 MB |
1261 | struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); |
1262 | struct nvme_queue *nvmeq = cmd_rq->nvmeq; | |
c30341dc | 1263 | struct nvme_dev *dev = nvmeq->dev; |
a4aea562 MB |
1264 | struct request *abort_req; |
1265 | struct nvme_cmd_info *abort_cmd; | |
1266 | struct nvme_command cmd; | |
c30341dc | 1267 | |
a4aea562 | 1268 | if (!nvmeq->qid || cmd_rq->aborted) { |
7a509a6b KB |
1269 | unsigned long flags; |
1270 | ||
1271 | spin_lock_irqsave(&dev_list_lock, flags); | |
c30341dc | 1272 | if (work_busy(&dev->reset_work)) |
7a509a6b | 1273 | goto out; |
c30341dc | 1274 | list_del_init(&dev->node); |
e75ec752 | 1275 | dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n", |
a4aea562 | 1276 | req->tag, nvmeq->qid); |
9ca97374 | 1277 | dev->reset_workfn = nvme_reset_failed_dev; |
c30341dc | 1278 | queue_work(nvme_workq, &dev->reset_work); |
7a509a6b KB |
1279 | out: |
1280 | spin_unlock_irqrestore(&dev_list_lock, flags); | |
c30341dc KB |
1281 | return; |
1282 | } | |
1283 | ||
1284 | if (!dev->abort_limit) | |
1285 | return; | |
1286 | ||
a4aea562 MB |
1287 | abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, |
1288 | false); | |
9f173b33 | 1289 | if (IS_ERR(abort_req)) |
c30341dc KB |
1290 | return; |
1291 | ||
a4aea562 MB |
1292 | abort_cmd = blk_mq_rq_to_pdu(abort_req); |
1293 | nvme_set_info(abort_cmd, abort_req, abort_completion); | |
1294 | ||
c30341dc KB |
1295 | memset(&cmd, 0, sizeof(cmd)); |
1296 | cmd.abort.opcode = nvme_admin_abort_cmd; | |
a4aea562 | 1297 | cmd.abort.cid = req->tag; |
c30341dc | 1298 | cmd.abort.sqid = cpu_to_le16(nvmeq->qid); |
a4aea562 | 1299 | cmd.abort.command_id = abort_req->tag; |
c30341dc KB |
1300 | |
1301 | --dev->abort_limit; | |
a4aea562 | 1302 | cmd_rq->aborted = 1; |
c30341dc | 1303 | |
a4aea562 | 1304 | dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, |
c30341dc | 1305 | nvmeq->qid); |
a4aea562 MB |
1306 | if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) { |
1307 | dev_warn(nvmeq->q_dmadev, | |
1308 | "Could not abort I/O %d QID %d", | |
1309 | req->tag, nvmeq->qid); | |
c87fd540 | 1310 | blk_mq_free_request(abort_req); |
a4aea562 | 1311 | } |
c30341dc KB |
1312 | } |
1313 | ||
42483228 | 1314 | static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) |
a09115b2 | 1315 | { |
a4aea562 MB |
1316 | struct nvme_queue *nvmeq = data; |
1317 | void *ctx; | |
1318 | nvme_completion_fn fn; | |
1319 | struct nvme_cmd_info *cmd; | |
cef6a948 KB |
1320 | struct nvme_completion cqe; |
1321 | ||
1322 | if (!blk_mq_request_started(req)) | |
1323 | return; | |
a09115b2 | 1324 | |
a4aea562 | 1325 | cmd = blk_mq_rq_to_pdu(req); |
a09115b2 | 1326 | |
a4aea562 MB |
1327 | if (cmd->ctx == CMD_CTX_CANCELLED) |
1328 | return; | |
1329 | ||
cef6a948 KB |
1330 | if (blk_queue_dying(req->q)) |
1331 | cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); | |
1332 | else | |
1333 | cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); | |
1334 | ||
1335 | ||
a4aea562 MB |
1336 | dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", |
1337 | req->tag, nvmeq->qid); | |
1338 | ctx = cancel_cmd_info(cmd, &fn); | |
1339 | fn(nvmeq, ctx, &cqe); | |
a09115b2 MW |
1340 | } |
1341 | ||
a4aea562 | 1342 | static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) |
9e866774 | 1343 | { |
a4aea562 MB |
1344 | struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); |
1345 | struct nvme_queue *nvmeq = cmd->nvmeq; | |
1346 | ||
1347 | dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, | |
1348 | nvmeq->qid); | |
7a509a6b | 1349 | spin_lock_irq(&nvmeq->q_lock); |
07836e65 | 1350 | nvme_abort_req(req); |
7a509a6b | 1351 | spin_unlock_irq(&nvmeq->q_lock); |
a4aea562 | 1352 | |
07836e65 KB |
1353 | /* |
1354 | * The aborted req will be completed on receiving the abort req. | |
1355 | * We enable the timer again. If hit twice, it'll cause a device reset, | |
1356 | * as the device then is in a faulty state. | |
1357 | */ | |
1358 | return BLK_EH_RESET_TIMER; | |
a4aea562 | 1359 | } |
22404274 | 1360 | |
a4aea562 MB |
1361 | static void nvme_free_queue(struct nvme_queue *nvmeq) |
1362 | { | |
9e866774 MW |
1363 | dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), |
1364 | (void *)nvmeq->cqes, nvmeq->cq_dma_addr); | |
1365 | dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), | |
1366 | nvmeq->sq_cmds, nvmeq->sq_dma_addr); | |
1367 | kfree(nvmeq); | |
1368 | } | |
1369 | ||
a1a5ef99 | 1370 | static void nvme_free_queues(struct nvme_dev *dev, int lowest) |
22404274 KB |
1371 | { |
1372 | int i; | |
1373 | ||
a1a5ef99 | 1374 | for (i = dev->queue_count - 1; i >= lowest; i--) { |
a4aea562 | 1375 | struct nvme_queue *nvmeq = dev->queues[i]; |
22404274 | 1376 | dev->queue_count--; |
a4aea562 | 1377 | dev->queues[i] = NULL; |
f435c282 | 1378 | nvme_free_queue(nvmeq); |
121c7ad4 | 1379 | } |
22404274 KB |
1380 | } |
1381 | ||
4d115420 KB |
1382 | /** |
1383 | * nvme_suspend_queue - put queue into suspended state | |
1384 | * @nvmeq - queue to suspend | |
4d115420 KB |
1385 | */ |
1386 | static int nvme_suspend_queue(struct nvme_queue *nvmeq) | |
b60503ba | 1387 | { |
2b25d981 | 1388 | int vector; |
b60503ba | 1389 | |
a09115b2 | 1390 | spin_lock_irq(&nvmeq->q_lock); |
2b25d981 KB |
1391 | if (nvmeq->cq_vector == -1) { |
1392 | spin_unlock_irq(&nvmeq->q_lock); | |
1393 | return 1; | |
1394 | } | |
1395 | vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; | |
42f61420 | 1396 | nvmeq->dev->online_queues--; |
2b25d981 | 1397 | nvmeq->cq_vector = -1; |
a09115b2 MW |
1398 | spin_unlock_irq(&nvmeq->q_lock); |
1399 | ||
6df3dbc8 KB |
1400 | if (!nvmeq->qid && nvmeq->dev->admin_q) |
1401 | blk_mq_freeze_queue_start(nvmeq->dev->admin_q); | |
1402 | ||
aba2080f MW |
1403 | irq_set_affinity_hint(vector, NULL); |
1404 | free_irq(vector, nvmeq); | |
b60503ba | 1405 | |
4d115420 KB |
1406 | return 0; |
1407 | } | |
b60503ba | 1408 | |
4d115420 KB |
1409 | static void nvme_clear_queue(struct nvme_queue *nvmeq) |
1410 | { | |
22404274 | 1411 | spin_lock_irq(&nvmeq->q_lock); |
42483228 KB |
1412 | if (nvmeq->tags && *nvmeq->tags) |
1413 | blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); | |
22404274 | 1414 | spin_unlock_irq(&nvmeq->q_lock); |
b60503ba MW |
1415 | } |
1416 | ||
4d115420 KB |
1417 | static void nvme_disable_queue(struct nvme_dev *dev, int qid) |
1418 | { | |
a4aea562 | 1419 | struct nvme_queue *nvmeq = dev->queues[qid]; |
4d115420 KB |
1420 | |
1421 | if (!nvmeq) | |
1422 | return; | |
1423 | if (nvme_suspend_queue(nvmeq)) | |
1424 | return; | |
1425 | ||
0e53d180 KB |
1426 | /* Don't tell the adapter to delete the admin queue. |
1427 | * Don't tell a removed adapter to delete IO queues. */ | |
1428 | if (qid && readl(&dev->bar->csts) != -1) { | |
b60503ba MW |
1429 | adapter_delete_sq(dev, qid); |
1430 | adapter_delete_cq(dev, qid); | |
1431 | } | |
07836e65 KB |
1432 | |
1433 | spin_lock_irq(&nvmeq->q_lock); | |
1434 | nvme_process_cq(nvmeq); | |
1435 | spin_unlock_irq(&nvmeq->q_lock); | |
b60503ba MW |
1436 | } |
1437 | ||
1438 | static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, | |
2b25d981 | 1439 | int depth) |
b60503ba | 1440 | { |
a4aea562 | 1441 | struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); |
b60503ba MW |
1442 | if (!nvmeq) |
1443 | return NULL; | |
1444 | ||
e75ec752 | 1445 | nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), |
4d51abf9 | 1446 | &nvmeq->cq_dma_addr, GFP_KERNEL); |
b60503ba MW |
1447 | if (!nvmeq->cqes) |
1448 | goto free_nvmeq; | |
b60503ba | 1449 | |
e75ec752 | 1450 | nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), |
b60503ba MW |
1451 | &nvmeq->sq_dma_addr, GFP_KERNEL); |
1452 | if (!nvmeq->sq_cmds) | |
1453 | goto free_cqdma; | |
1454 | ||
e75ec752 | 1455 | nvmeq->q_dmadev = dev->dev; |
091b6092 | 1456 | nvmeq->dev = dev; |
3193f07b MW |
1457 | snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", |
1458 | dev->instance, qid); | |
b60503ba MW |
1459 | spin_lock_init(&nvmeq->q_lock); |
1460 | nvmeq->cq_head = 0; | |
82123460 | 1461 | nvmeq->cq_phase = 1; |
b80d5ccc | 1462 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
b60503ba | 1463 | nvmeq->q_depth = depth; |
c30341dc | 1464 | nvmeq->qid = qid; |
a4aea562 | 1465 | dev->queues[qid] = nvmeq; |
b60503ba | 1466 | |
36a7e993 JD |
1467 | /* make sure queue descriptor is set before queue count, for kthread */ |
1468 | mb(); | |
1469 | dev->queue_count++; | |
1470 | ||
b60503ba MW |
1471 | return nvmeq; |
1472 | ||
1473 | free_cqdma: | |
e75ec752 | 1474 | dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, |
b60503ba MW |
1475 | nvmeq->cq_dma_addr); |
1476 | free_nvmeq: | |
1477 | kfree(nvmeq); | |
1478 | return NULL; | |
1479 | } | |
1480 | ||
3001082c MW |
1481 | static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, |
1482 | const char *name) | |
1483 | { | |
58ffacb5 MW |
1484 | if (use_threaded_interrupts) |
1485 | return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, | |
481e5bad | 1486 | nvme_irq_check, nvme_irq, IRQF_SHARED, |
58ffacb5 | 1487 | name, nvmeq); |
3001082c | 1488 | return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, |
481e5bad | 1489 | IRQF_SHARED, name, nvmeq); |
3001082c MW |
1490 | } |
1491 | ||
22404274 | 1492 | static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) |
b60503ba | 1493 | { |
22404274 | 1494 | struct nvme_dev *dev = nvmeq->dev; |
b60503ba | 1495 | |
7be50e93 | 1496 | spin_lock_irq(&nvmeq->q_lock); |
22404274 KB |
1497 | nvmeq->sq_tail = 0; |
1498 | nvmeq->cq_head = 0; | |
1499 | nvmeq->cq_phase = 1; | |
b80d5ccc | 1500 | nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; |
22404274 | 1501 | memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); |
42f61420 | 1502 | dev->online_queues++; |
7be50e93 | 1503 | spin_unlock_irq(&nvmeq->q_lock); |
22404274 KB |
1504 | } |
1505 | ||
1506 | static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) | |
1507 | { | |
1508 | struct nvme_dev *dev = nvmeq->dev; | |
1509 | int result; | |
3f85d50b | 1510 | |
2b25d981 | 1511 | nvmeq->cq_vector = qid - 1; |
b60503ba MW |
1512 | result = adapter_alloc_cq(dev, qid, nvmeq); |
1513 | if (result < 0) | |
22404274 | 1514 | return result; |
b60503ba MW |
1515 | |
1516 | result = adapter_alloc_sq(dev, qid, nvmeq); | |
1517 | if (result < 0) | |
1518 | goto release_cq; | |
1519 | ||
3193f07b | 1520 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
b60503ba MW |
1521 | if (result < 0) |
1522 | goto release_sq; | |
1523 | ||
22404274 | 1524 | nvme_init_queue(nvmeq, qid); |
22404274 | 1525 | return result; |
b60503ba MW |
1526 | |
1527 | release_sq: | |
1528 | adapter_delete_sq(dev, qid); | |
1529 | release_cq: | |
1530 | adapter_delete_cq(dev, qid); | |
22404274 | 1531 | return result; |
b60503ba MW |
1532 | } |
1533 | ||
ba47e386 MW |
1534 | static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled) |
1535 | { | |
1536 | unsigned long timeout; | |
1537 | u32 bit = enabled ? NVME_CSTS_RDY : 0; | |
1538 | ||
1539 | timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; | |
1540 | ||
1541 | while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) { | |
1542 | msleep(100); | |
1543 | if (fatal_signal_pending(current)) | |
1544 | return -EINTR; | |
1545 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1546 | dev_err(dev->dev, |
27e8166c MW |
1547 | "Device not ready; aborting %s\n", enabled ? |
1548 | "initialisation" : "reset"); | |
ba47e386 MW |
1549 | return -ENODEV; |
1550 | } | |
1551 | } | |
1552 | ||
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | /* | |
1557 | * If the device has been passed off to us in an enabled state, just clear | |
1558 | * the enabled bit. The spec says we should set the 'shutdown notification | |
1559 | * bits', but doing so may cause the device to complete commands to the | |
1560 | * admin queue ... and we don't know what memory that might be pointing at! | |
1561 | */ | |
1562 | static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap) | |
1563 | { | |
01079522 DM |
1564 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1565 | dev->ctrl_config &= ~NVME_CC_ENABLE; | |
1566 | writel(dev->ctrl_config, &dev->bar->cc); | |
44af146a | 1567 | |
ba47e386 MW |
1568 | return nvme_wait_ready(dev, cap, false); |
1569 | } | |
1570 | ||
1571 | static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap) | |
1572 | { | |
01079522 DM |
1573 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1574 | dev->ctrl_config |= NVME_CC_ENABLE; | |
1575 | writel(dev->ctrl_config, &dev->bar->cc); | |
1576 | ||
ba47e386 MW |
1577 | return nvme_wait_ready(dev, cap, true); |
1578 | } | |
1579 | ||
1894d8f1 KB |
1580 | static int nvme_shutdown_ctrl(struct nvme_dev *dev) |
1581 | { | |
1582 | unsigned long timeout; | |
1894d8f1 | 1583 | |
01079522 DM |
1584 | dev->ctrl_config &= ~NVME_CC_SHN_MASK; |
1585 | dev->ctrl_config |= NVME_CC_SHN_NORMAL; | |
1586 | ||
1587 | writel(dev->ctrl_config, &dev->bar->cc); | |
1894d8f1 | 1588 | |
2484f407 | 1589 | timeout = SHUTDOWN_TIMEOUT + jiffies; |
1894d8f1 KB |
1590 | while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) != |
1591 | NVME_CSTS_SHST_CMPLT) { | |
1592 | msleep(100); | |
1593 | if (fatal_signal_pending(current)) | |
1594 | return -EINTR; | |
1595 | if (time_after(jiffies, timeout)) { | |
e75ec752 | 1596 | dev_err(dev->dev, |
1894d8f1 KB |
1597 | "Device shutdown incomplete; abort shutdown\n"); |
1598 | return -ENODEV; | |
1599 | } | |
1600 | } | |
1601 | ||
1602 | return 0; | |
1603 | } | |
1604 | ||
a4aea562 | 1605 | static struct blk_mq_ops nvme_mq_admin_ops = { |
d29ec824 | 1606 | .queue_rq = nvme_queue_rq, |
a4aea562 MB |
1607 | .map_queue = blk_mq_map_queue, |
1608 | .init_hctx = nvme_admin_init_hctx, | |
1609 | .init_request = nvme_admin_init_request, | |
1610 | .timeout = nvme_timeout, | |
1611 | }; | |
1612 | ||
1613 | static struct blk_mq_ops nvme_mq_ops = { | |
1614 | .queue_rq = nvme_queue_rq, | |
1615 | .map_queue = blk_mq_map_queue, | |
1616 | .init_hctx = nvme_init_hctx, | |
1617 | .init_request = nvme_init_request, | |
1618 | .timeout = nvme_timeout, | |
1619 | }; | |
1620 | ||
ea191d2f KB |
1621 | static void nvme_dev_remove_admin(struct nvme_dev *dev) |
1622 | { | |
1623 | if (dev->admin_q && !blk_queue_dying(dev->admin_q)) { | |
1624 | blk_cleanup_queue(dev->admin_q); | |
1625 | blk_mq_free_tag_set(&dev->admin_tagset); | |
1626 | } | |
1627 | } | |
1628 | ||
a4aea562 MB |
1629 | static int nvme_alloc_admin_tags(struct nvme_dev *dev) |
1630 | { | |
1631 | if (!dev->admin_q) { | |
1632 | dev->admin_tagset.ops = &nvme_mq_admin_ops; | |
1633 | dev->admin_tagset.nr_hw_queues = 1; | |
1634 | dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; | |
1efccc9d | 1635 | dev->admin_tagset.reserved_tags = 1; |
a4aea562 | 1636 | dev->admin_tagset.timeout = ADMIN_TIMEOUT; |
e75ec752 | 1637 | dev->admin_tagset.numa_node = dev_to_node(dev->dev); |
ac3dd5bd | 1638 | dev->admin_tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
1639 | dev->admin_tagset.driver_data = dev; |
1640 | ||
1641 | if (blk_mq_alloc_tag_set(&dev->admin_tagset)) | |
1642 | return -ENOMEM; | |
1643 | ||
1644 | dev->admin_q = blk_mq_init_queue(&dev->admin_tagset); | |
35b489d3 | 1645 | if (IS_ERR(dev->admin_q)) { |
a4aea562 MB |
1646 | blk_mq_free_tag_set(&dev->admin_tagset); |
1647 | return -ENOMEM; | |
1648 | } | |
ea191d2f KB |
1649 | if (!blk_get_queue(dev->admin_q)) { |
1650 | nvme_dev_remove_admin(dev); | |
1651 | return -ENODEV; | |
1652 | } | |
0fb59cbc KB |
1653 | } else |
1654 | blk_mq_unfreeze_queue(dev->admin_q); | |
a4aea562 MB |
1655 | |
1656 | return 0; | |
1657 | } | |
1658 | ||
8d85fce7 | 1659 | static int nvme_configure_admin_queue(struct nvme_dev *dev) |
b60503ba | 1660 | { |
ba47e386 | 1661 | int result; |
b60503ba | 1662 | u32 aqa; |
ba47e386 | 1663 | u64 cap = readq(&dev->bar->cap); |
b60503ba | 1664 | struct nvme_queue *nvmeq; |
1d090624 KB |
1665 | unsigned page_shift = PAGE_SHIFT; |
1666 | unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12; | |
1667 | unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12; | |
1668 | ||
1669 | if (page_shift < dev_page_min) { | |
e75ec752 | 1670 | dev_err(dev->dev, |
1d090624 KB |
1671 | "Minimum device page size (%u) too large for " |
1672 | "host (%u)\n", 1 << dev_page_min, | |
1673 | 1 << page_shift); | |
1674 | return -ENODEV; | |
1675 | } | |
1676 | if (page_shift > dev_page_max) { | |
e75ec752 | 1677 | dev_info(dev->dev, |
1d090624 KB |
1678 | "Device maximum page size (%u) smaller than " |
1679 | "host (%u); enabling work-around\n", | |
1680 | 1 << dev_page_max, 1 << page_shift); | |
1681 | page_shift = dev_page_max; | |
1682 | } | |
b60503ba | 1683 | |
ba47e386 MW |
1684 | result = nvme_disable_ctrl(dev, cap); |
1685 | if (result < 0) | |
1686 | return result; | |
b60503ba | 1687 | |
a4aea562 | 1688 | nvmeq = dev->queues[0]; |
cd638946 | 1689 | if (!nvmeq) { |
2b25d981 | 1690 | nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); |
cd638946 KB |
1691 | if (!nvmeq) |
1692 | return -ENOMEM; | |
cd638946 | 1693 | } |
b60503ba MW |
1694 | |
1695 | aqa = nvmeq->q_depth - 1; | |
1696 | aqa |= aqa << 16; | |
1697 | ||
1d090624 KB |
1698 | dev->page_size = 1 << page_shift; |
1699 | ||
01079522 | 1700 | dev->ctrl_config = NVME_CC_CSS_NVM; |
1d090624 | 1701 | dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT; |
b60503ba | 1702 | dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE; |
7f53f9d2 | 1703 | dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES; |
b60503ba MW |
1704 | |
1705 | writel(aqa, &dev->bar->aqa); | |
1706 | writeq(nvmeq->sq_dma_addr, &dev->bar->asq); | |
1707 | writeq(nvmeq->cq_dma_addr, &dev->bar->acq); | |
b60503ba | 1708 | |
ba47e386 | 1709 | result = nvme_enable_ctrl(dev, cap); |
025c557a | 1710 | if (result) |
a4aea562 MB |
1711 | goto free_nvmeq; |
1712 | ||
2b25d981 | 1713 | nvmeq->cq_vector = 0; |
3193f07b | 1714 | result = queue_request_irq(dev, nvmeq, nvmeq->irqname); |
025c557a | 1715 | if (result) |
0fb59cbc | 1716 | goto free_nvmeq; |
025c557a | 1717 | |
b60503ba | 1718 | return result; |
a4aea562 | 1719 | |
a4aea562 MB |
1720 | free_nvmeq: |
1721 | nvme_free_queues(dev, 0); | |
1722 | return result; | |
b60503ba MW |
1723 | } |
1724 | ||
a53295b6 MW |
1725 | static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio) |
1726 | { | |
1727 | struct nvme_dev *dev = ns->dev; | |
a53295b6 MW |
1728 | struct nvme_user_io io; |
1729 | struct nvme_command c; | |
d29ec824 | 1730 | unsigned length, meta_len; |
a67a9513 | 1731 | int status, write; |
a67a9513 KB |
1732 | dma_addr_t meta_dma = 0; |
1733 | void *meta = NULL; | |
fec558b5 | 1734 | void __user *metadata; |
a53295b6 MW |
1735 | |
1736 | if (copy_from_user(&io, uio, sizeof(io))) | |
1737 | return -EFAULT; | |
6c7d4945 MW |
1738 | |
1739 | switch (io.opcode) { | |
1740 | case nvme_cmd_write: | |
1741 | case nvme_cmd_read: | |
6bbf1acd | 1742 | case nvme_cmd_compare: |
6413214c | 1743 | break; |
6c7d4945 | 1744 | default: |
6bbf1acd | 1745 | return -EINVAL; |
6c7d4945 MW |
1746 | } |
1747 | ||
d29ec824 CH |
1748 | length = (io.nblocks + 1) << ns->lba_shift; |
1749 | meta_len = (io.nblocks + 1) * ns->ms; | |
6a398a3e | 1750 | metadata = (void __user *)(unsigned long)io.metadata; |
d29ec824 | 1751 | write = io.opcode & 1; |
a53295b6 | 1752 | |
71feb364 KB |
1753 | if (ns->ext) { |
1754 | length += meta_len; | |
1755 | meta_len = 0; | |
a67a9513 KB |
1756 | } |
1757 | if (meta_len) { | |
d29ec824 CH |
1758 | if (((io.metadata & 3) || !io.metadata) && !ns->ext) |
1759 | return -EINVAL; | |
1760 | ||
e75ec752 | 1761 | meta = dma_alloc_coherent(dev->dev, meta_len, |
a67a9513 | 1762 | &meta_dma, GFP_KERNEL); |
fec558b5 | 1763 | |
a67a9513 KB |
1764 | if (!meta) { |
1765 | status = -ENOMEM; | |
1766 | goto unmap; | |
1767 | } | |
1768 | if (write) { | |
fec558b5 | 1769 | if (copy_from_user(meta, metadata, meta_len)) { |
a67a9513 KB |
1770 | status = -EFAULT; |
1771 | goto unmap; | |
1772 | } | |
1773 | } | |
1774 | } | |
1775 | ||
a53295b6 MW |
1776 | memset(&c, 0, sizeof(c)); |
1777 | c.rw.opcode = io.opcode; | |
1778 | c.rw.flags = io.flags; | |
6c7d4945 | 1779 | c.rw.nsid = cpu_to_le32(ns->ns_id); |
a53295b6 | 1780 | c.rw.slba = cpu_to_le64(io.slba); |
6c7d4945 | 1781 | c.rw.length = cpu_to_le16(io.nblocks); |
a53295b6 | 1782 | c.rw.control = cpu_to_le16(io.control); |
1c9b5265 MW |
1783 | c.rw.dsmgmt = cpu_to_le32(io.dsmgmt); |
1784 | c.rw.reftag = cpu_to_le32(io.reftag); | |
1785 | c.rw.apptag = cpu_to_le16(io.apptag); | |
1786 | c.rw.appmask = cpu_to_le16(io.appmask); | |
a67a9513 | 1787 | c.rw.metadata = cpu_to_le64(meta_dma); |
d29ec824 CH |
1788 | |
1789 | status = __nvme_submit_sync_cmd(ns->queue, &c, NULL, | |
1790 | (void __user *)io.addr, length, NULL, 0); | |
f410c680 | 1791 | unmap: |
a67a9513 KB |
1792 | if (meta) { |
1793 | if (status == NVME_SC_SUCCESS && !write) { | |
fec558b5 | 1794 | if (copy_to_user(metadata, meta, meta_len)) |
a67a9513 KB |
1795 | status = -EFAULT; |
1796 | } | |
e75ec752 | 1797 | dma_free_coherent(dev->dev, meta_len, meta, meta_dma); |
f410c680 | 1798 | } |
a53295b6 MW |
1799 | return status; |
1800 | } | |
1801 | ||
a4aea562 MB |
1802 | static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns, |
1803 | struct nvme_passthru_cmd __user *ucmd) | |
6ee44cdc | 1804 | { |
7963e521 | 1805 | struct nvme_passthru_cmd cmd; |
6ee44cdc | 1806 | struct nvme_command c; |
d29ec824 CH |
1807 | unsigned timeout = 0; |
1808 | int status; | |
6ee44cdc | 1809 | |
6bbf1acd MW |
1810 | if (!capable(CAP_SYS_ADMIN)) |
1811 | return -EACCES; | |
1812 | if (copy_from_user(&cmd, ucmd, sizeof(cmd))) | |
6ee44cdc | 1813 | return -EFAULT; |
6ee44cdc MW |
1814 | |
1815 | memset(&c, 0, sizeof(c)); | |
6bbf1acd MW |
1816 | c.common.opcode = cmd.opcode; |
1817 | c.common.flags = cmd.flags; | |
1818 | c.common.nsid = cpu_to_le32(cmd.nsid); | |
1819 | c.common.cdw2[0] = cpu_to_le32(cmd.cdw2); | |
1820 | c.common.cdw2[1] = cpu_to_le32(cmd.cdw3); | |
1821 | c.common.cdw10[0] = cpu_to_le32(cmd.cdw10); | |
1822 | c.common.cdw10[1] = cpu_to_le32(cmd.cdw11); | |
1823 | c.common.cdw10[2] = cpu_to_le32(cmd.cdw12); | |
1824 | c.common.cdw10[3] = cpu_to_le32(cmd.cdw13); | |
1825 | c.common.cdw10[4] = cpu_to_le32(cmd.cdw14); | |
1826 | c.common.cdw10[5] = cpu_to_le32(cmd.cdw15); | |
1827 | ||
d29ec824 CH |
1828 | if (cmd.timeout_ms) |
1829 | timeout = msecs_to_jiffies(cmd.timeout_ms); | |
eca18b23 | 1830 | |
f705f837 | 1831 | status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c, |
d29ec824 CH |
1832 | NULL, (void __user *)cmd.addr, cmd.data_len, |
1833 | &cmd.result, timeout); | |
1834 | if (status >= 0) { | |
1835 | if (put_user(cmd.result, &ucmd->result)) | |
1836 | return -EFAULT; | |
6bbf1acd | 1837 | } |
f4f117f6 | 1838 | |
6ee44cdc MW |
1839 | return status; |
1840 | } | |
1841 | ||
b60503ba MW |
1842 | static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, |
1843 | unsigned long arg) | |
1844 | { | |
1845 | struct nvme_ns *ns = bdev->bd_disk->private_data; | |
1846 | ||
1847 | switch (cmd) { | |
6bbf1acd | 1848 | case NVME_IOCTL_ID: |
c3bfe717 | 1849 | force_successful_syscall_return(); |
6bbf1acd MW |
1850 | return ns->ns_id; |
1851 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 1852 | return nvme_user_cmd(ns->dev, NULL, (void __user *)arg); |
7963e521 | 1853 | case NVME_IOCTL_IO_CMD: |
a4aea562 | 1854 | return nvme_user_cmd(ns->dev, ns, (void __user *)arg); |
a53295b6 MW |
1855 | case NVME_IOCTL_SUBMIT_IO: |
1856 | return nvme_submit_io(ns, (void __user *)arg); | |
5d0f6131 VV |
1857 | case SG_GET_VERSION_NUM: |
1858 | return nvme_sg_get_version_num((void __user *)arg); | |
1859 | case SG_IO: | |
1860 | return nvme_sg_io(ns, (void __user *)arg); | |
b60503ba MW |
1861 | default: |
1862 | return -ENOTTY; | |
1863 | } | |
1864 | } | |
1865 | ||
320a3827 KB |
1866 | #ifdef CONFIG_COMPAT |
1867 | static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode, | |
1868 | unsigned int cmd, unsigned long arg) | |
1869 | { | |
320a3827 KB |
1870 | switch (cmd) { |
1871 | case SG_IO: | |
e179729a | 1872 | return -ENOIOCTLCMD; |
320a3827 KB |
1873 | } |
1874 | return nvme_ioctl(bdev, mode, cmd, arg); | |
1875 | } | |
1876 | #else | |
1877 | #define nvme_compat_ioctl NULL | |
1878 | #endif | |
1879 | ||
9ac27090 KB |
1880 | static int nvme_open(struct block_device *bdev, fmode_t mode) |
1881 | { | |
9e60352c KB |
1882 | int ret = 0; |
1883 | struct nvme_ns *ns; | |
9ac27090 | 1884 | |
9e60352c KB |
1885 | spin_lock(&dev_list_lock); |
1886 | ns = bdev->bd_disk->private_data; | |
1887 | if (!ns) | |
1888 | ret = -ENXIO; | |
1889 | else if (!kref_get_unless_zero(&ns->dev->kref)) | |
1890 | ret = -ENXIO; | |
1891 | spin_unlock(&dev_list_lock); | |
1892 | ||
1893 | return ret; | |
9ac27090 KB |
1894 | } |
1895 | ||
1896 | static void nvme_free_dev(struct kref *kref); | |
1897 | ||
1898 | static void nvme_release(struct gendisk *disk, fmode_t mode) | |
1899 | { | |
1900 | struct nvme_ns *ns = disk->private_data; | |
1901 | struct nvme_dev *dev = ns->dev; | |
1902 | ||
1903 | kref_put(&dev->kref, nvme_free_dev); | |
1904 | } | |
1905 | ||
4cc09e2d KB |
1906 | static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo) |
1907 | { | |
1908 | /* some standard values */ | |
1909 | geo->heads = 1 << 6; | |
1910 | geo->sectors = 1 << 5; | |
1911 | geo->cylinders = get_capacity(bd->bd_disk) >> 11; | |
1912 | return 0; | |
1913 | } | |
1914 | ||
e1e5e564 KB |
1915 | static void nvme_config_discard(struct nvme_ns *ns) |
1916 | { | |
1917 | u32 logical_block_size = queue_logical_block_size(ns->queue); | |
1918 | ns->queue->limits.discard_zeroes_data = 0; | |
1919 | ns->queue->limits.discard_alignment = logical_block_size; | |
1920 | ns->queue->limits.discard_granularity = logical_block_size; | |
1921 | ns->queue->limits.max_discard_sectors = 0xffffffff; | |
1922 | queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); | |
1923 | } | |
1924 | ||
1b9dbf7f KB |
1925 | static int nvme_revalidate_disk(struct gendisk *disk) |
1926 | { | |
1927 | struct nvme_ns *ns = disk->private_data; | |
1928 | struct nvme_dev *dev = ns->dev; | |
1929 | struct nvme_id_ns *id; | |
a67a9513 KB |
1930 | u8 lbaf, pi_type; |
1931 | u16 old_ms; | |
e1e5e564 | 1932 | unsigned short bs; |
1b9dbf7f | 1933 | |
d29ec824 | 1934 | if (nvme_identify_ns(dev, ns->ns_id, &id)) { |
a5768aa8 KB |
1935 | dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__, |
1936 | dev->instance, ns->ns_id); | |
1937 | return -ENODEV; | |
1b9dbf7f | 1938 | } |
a5768aa8 KB |
1939 | if (id->ncap == 0) { |
1940 | kfree(id); | |
1941 | return -ENODEV; | |
e1e5e564 | 1942 | } |
1b9dbf7f | 1943 | |
e1e5e564 KB |
1944 | old_ms = ns->ms; |
1945 | lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK; | |
1b9dbf7f | 1946 | ns->lba_shift = id->lbaf[lbaf].ds; |
e1e5e564 | 1947 | ns->ms = le16_to_cpu(id->lbaf[lbaf].ms); |
a67a9513 | 1948 | ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT); |
e1e5e564 KB |
1949 | |
1950 | /* | |
1951 | * If identify namespace failed, use default 512 byte block size so | |
1952 | * block layer can use before failing read/write for 0 capacity. | |
1953 | */ | |
1954 | if (ns->lba_shift == 0) | |
1955 | ns->lba_shift = 9; | |
1956 | bs = 1 << ns->lba_shift; | |
1957 | ||
1958 | /* XXX: PI implementation requires metadata equal t10 pi tuple size */ | |
1959 | pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? | |
1960 | id->dps & NVME_NS_DPS_PI_MASK : 0; | |
1961 | ||
52b68d7e KB |
1962 | if (blk_get_integrity(disk) && (ns->pi_type != pi_type || |
1963 | ns->ms != old_ms || | |
e1e5e564 | 1964 | bs != queue_logical_block_size(disk->queue) || |
a67a9513 | 1965 | (ns->ms && ns->ext))) |
e1e5e564 KB |
1966 | blk_integrity_unregister(disk); |
1967 | ||
1968 | ns->pi_type = pi_type; | |
1969 | blk_queue_logical_block_size(ns->queue, bs); | |
1970 | ||
52b68d7e | 1971 | if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) && |
a67a9513 | 1972 | !ns->ext) |
e1e5e564 KB |
1973 | nvme_init_integrity(ns); |
1974 | ||
a5768aa8 | 1975 | if (ns->ms && !blk_get_integrity(disk)) |
e1e5e564 KB |
1976 | set_capacity(disk, 0); |
1977 | else | |
1978 | set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); | |
1979 | ||
1980 | if (dev->oncs & NVME_CTRL_ONCS_DSM) | |
1981 | nvme_config_discard(ns); | |
1b9dbf7f | 1982 | |
d29ec824 | 1983 | kfree(id); |
1b9dbf7f KB |
1984 | return 0; |
1985 | } | |
1986 | ||
b60503ba MW |
1987 | static const struct block_device_operations nvme_fops = { |
1988 | .owner = THIS_MODULE, | |
1989 | .ioctl = nvme_ioctl, | |
320a3827 | 1990 | .compat_ioctl = nvme_compat_ioctl, |
9ac27090 KB |
1991 | .open = nvme_open, |
1992 | .release = nvme_release, | |
4cc09e2d | 1993 | .getgeo = nvme_getgeo, |
1b9dbf7f | 1994 | .revalidate_disk= nvme_revalidate_disk, |
b60503ba MW |
1995 | }; |
1996 | ||
1fa6aead MW |
1997 | static int nvme_kthread(void *data) |
1998 | { | |
d4b4ff8e | 1999 | struct nvme_dev *dev, *next; |
1fa6aead MW |
2000 | |
2001 | while (!kthread_should_stop()) { | |
564a232c | 2002 | set_current_state(TASK_INTERRUPTIBLE); |
1fa6aead | 2003 | spin_lock(&dev_list_lock); |
d4b4ff8e | 2004 | list_for_each_entry_safe(dev, next, &dev_list, node) { |
1fa6aead | 2005 | int i; |
07836e65 | 2006 | if (readl(&dev->bar->csts) & NVME_CSTS_CFS) { |
d4b4ff8e KB |
2007 | if (work_busy(&dev->reset_work)) |
2008 | continue; | |
2009 | list_del_init(&dev->node); | |
e75ec752 | 2010 | dev_warn(dev->dev, |
a4aea562 MB |
2011 | "Failed status: %x, reset controller\n", |
2012 | readl(&dev->bar->csts)); | |
9ca97374 | 2013 | dev->reset_workfn = nvme_reset_failed_dev; |
d4b4ff8e KB |
2014 | queue_work(nvme_workq, &dev->reset_work); |
2015 | continue; | |
2016 | } | |
1fa6aead | 2017 | for (i = 0; i < dev->queue_count; i++) { |
a4aea562 | 2018 | struct nvme_queue *nvmeq = dev->queues[i]; |
740216fc MW |
2019 | if (!nvmeq) |
2020 | continue; | |
1fa6aead | 2021 | spin_lock_irq(&nvmeq->q_lock); |
bc57a0f7 | 2022 | nvme_process_cq(nvmeq); |
6fccf938 KB |
2023 | |
2024 | while ((i == 0) && (dev->event_limit > 0)) { | |
a4aea562 | 2025 | if (nvme_submit_async_admin_req(dev)) |
6fccf938 KB |
2026 | break; |
2027 | dev->event_limit--; | |
2028 | } | |
1fa6aead MW |
2029 | spin_unlock_irq(&nvmeq->q_lock); |
2030 | } | |
2031 | } | |
2032 | spin_unlock(&dev_list_lock); | |
acb7aa0d | 2033 | schedule_timeout(round_jiffies_relative(HZ)); |
1fa6aead MW |
2034 | } |
2035 | return 0; | |
2036 | } | |
2037 | ||
e1e5e564 | 2038 | static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid) |
b60503ba MW |
2039 | { |
2040 | struct nvme_ns *ns; | |
2041 | struct gendisk *disk; | |
e75ec752 | 2042 | int node = dev_to_node(dev->dev); |
b60503ba | 2043 | |
a4aea562 | 2044 | ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node); |
b60503ba | 2045 | if (!ns) |
e1e5e564 KB |
2046 | return; |
2047 | ||
a4aea562 | 2048 | ns->queue = blk_mq_init_queue(&dev->tagset); |
9f173b33 | 2049 | if (IS_ERR(ns->queue)) |
b60503ba | 2050 | goto out_free_ns; |
4eeb9215 MW |
2051 | queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue); |
2052 | queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue); | |
a4aea562 | 2053 | queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue); |
b60503ba MW |
2054 | ns->dev = dev; |
2055 | ns->queue->queuedata = ns; | |
2056 | ||
a4aea562 | 2057 | disk = alloc_disk_node(0, node); |
b60503ba MW |
2058 | if (!disk) |
2059 | goto out_free_queue; | |
a4aea562 | 2060 | |
5aff9382 | 2061 | ns->ns_id = nsid; |
b60503ba | 2062 | ns->disk = disk; |
e1e5e564 KB |
2063 | ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */ |
2064 | list_add_tail(&ns->list, &dev->namespaces); | |
2065 | ||
e9ef4636 | 2066 | blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift); |
8fc23e03 KB |
2067 | if (dev->max_hw_sectors) |
2068 | blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors); | |
a4aea562 MB |
2069 | if (dev->stripe_size) |
2070 | blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9); | |
a7d2ce28 KB |
2071 | if (dev->vwc & NVME_CTRL_VWC_PRESENT) |
2072 | blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA); | |
b60503ba MW |
2073 | |
2074 | disk->major = nvme_major; | |
469071a3 | 2075 | disk->first_minor = 0; |
b60503ba MW |
2076 | disk->fops = &nvme_fops; |
2077 | disk->private_data = ns; | |
2078 | disk->queue = ns->queue; | |
b3fffdef | 2079 | disk->driverfs_dev = dev->device; |
469071a3 | 2080 | disk->flags = GENHD_FL_EXT_DEVT; |
5aff9382 | 2081 | sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid); |
b60503ba | 2082 | |
e1e5e564 KB |
2083 | /* |
2084 | * Initialize capacity to 0 until we establish the namespace format and | |
2085 | * setup integrity extentions if necessary. The revalidate_disk after | |
2086 | * add_disk allows the driver to register with integrity if the format | |
2087 | * requires it. | |
2088 | */ | |
2089 | set_capacity(disk, 0); | |
a5768aa8 KB |
2090 | if (nvme_revalidate_disk(ns->disk)) |
2091 | goto out_free_disk; | |
2092 | ||
e1e5e564 KB |
2093 | add_disk(ns->disk); |
2094 | if (ns->ms) | |
2095 | revalidate_disk(ns->disk); | |
2096 | return; | |
a5768aa8 KB |
2097 | out_free_disk: |
2098 | kfree(disk); | |
2099 | list_del(&ns->list); | |
b60503ba MW |
2100 | out_free_queue: |
2101 | blk_cleanup_queue(ns->queue); | |
2102 | out_free_ns: | |
2103 | kfree(ns); | |
b60503ba MW |
2104 | } |
2105 | ||
42f61420 KB |
2106 | static void nvme_create_io_queues(struct nvme_dev *dev) |
2107 | { | |
a4aea562 | 2108 | unsigned i; |
42f61420 | 2109 | |
a4aea562 | 2110 | for (i = dev->queue_count; i <= dev->max_qid; i++) |
2b25d981 | 2111 | if (!nvme_alloc_queue(dev, i, dev->q_depth)) |
42f61420 KB |
2112 | break; |
2113 | ||
a4aea562 MB |
2114 | for (i = dev->online_queues; i <= dev->queue_count - 1; i++) |
2115 | if (nvme_create_queue(dev->queues[i], i)) | |
42f61420 KB |
2116 | break; |
2117 | } | |
2118 | ||
b3b06812 | 2119 | static int set_queue_count(struct nvme_dev *dev, int count) |
b60503ba MW |
2120 | { |
2121 | int status; | |
2122 | u32 result; | |
b3b06812 | 2123 | u32 q_count = (count - 1) | ((count - 1) << 16); |
b60503ba | 2124 | |
df348139 | 2125 | status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0, |
bc5fc7e4 | 2126 | &result); |
27e8166c MW |
2127 | if (status < 0) |
2128 | return status; | |
2129 | if (status > 0) { | |
e75ec752 | 2130 | dev_err(dev->dev, "Could not set queue count (%d)\n", status); |
badc34d4 | 2131 | return 0; |
27e8166c | 2132 | } |
b60503ba MW |
2133 | return min(result & 0xffff, result >> 16) + 1; |
2134 | } | |
2135 | ||
9d713c2b KB |
2136 | static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) |
2137 | { | |
b80d5ccc | 2138 | return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); |
9d713c2b KB |
2139 | } |
2140 | ||
8d85fce7 | 2141 | static int nvme_setup_io_queues(struct nvme_dev *dev) |
b60503ba | 2142 | { |
a4aea562 | 2143 | struct nvme_queue *adminq = dev->queues[0]; |
e75ec752 | 2144 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
42f61420 | 2145 | int result, i, vecs, nr_io_queues, size; |
b60503ba | 2146 | |
42f61420 | 2147 | nr_io_queues = num_possible_cpus(); |
b348b7d5 | 2148 | result = set_queue_count(dev, nr_io_queues); |
badc34d4 | 2149 | if (result <= 0) |
1b23484b | 2150 | return result; |
b348b7d5 MW |
2151 | if (result < nr_io_queues) |
2152 | nr_io_queues = result; | |
b60503ba | 2153 | |
9d713c2b KB |
2154 | size = db_bar_size(dev, nr_io_queues); |
2155 | if (size > 8192) { | |
f1938f6e | 2156 | iounmap(dev->bar); |
9d713c2b KB |
2157 | do { |
2158 | dev->bar = ioremap(pci_resource_start(pdev, 0), size); | |
2159 | if (dev->bar) | |
2160 | break; | |
2161 | if (!--nr_io_queues) | |
2162 | return -ENOMEM; | |
2163 | size = db_bar_size(dev, nr_io_queues); | |
2164 | } while (1); | |
f1938f6e | 2165 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
5a92e700 | 2166 | adminq->q_db = dev->dbs; |
f1938f6e MW |
2167 | } |
2168 | ||
9d713c2b | 2169 | /* Deregister the admin queue's interrupt */ |
3193f07b | 2170 | free_irq(dev->entry[0].vector, adminq); |
9d713c2b | 2171 | |
e32efbfc JA |
2172 | /* |
2173 | * If we enable msix early due to not intx, disable it again before | |
2174 | * setting up the full range we need. | |
2175 | */ | |
2176 | if (!pdev->irq) | |
2177 | pci_disable_msix(pdev); | |
2178 | ||
be577fab | 2179 | for (i = 0; i < nr_io_queues; i++) |
1b23484b | 2180 | dev->entry[i].entry = i; |
be577fab AG |
2181 | vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); |
2182 | if (vecs < 0) { | |
2183 | vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); | |
2184 | if (vecs < 0) { | |
2185 | vecs = 1; | |
2186 | } else { | |
2187 | for (i = 0; i < vecs; i++) | |
2188 | dev->entry[i].vector = i + pdev->irq; | |
fa08a396 RRG |
2189 | } |
2190 | } | |
2191 | ||
063a8096 MW |
2192 | /* |
2193 | * Should investigate if there's a performance win from allocating | |
2194 | * more queues than interrupt vectors; it might allow the submission | |
2195 | * path to scale better, even if the receive path is limited by the | |
2196 | * number of interrupts. | |
2197 | */ | |
2198 | nr_io_queues = vecs; | |
42f61420 | 2199 | dev->max_qid = nr_io_queues; |
063a8096 | 2200 | |
3193f07b | 2201 | result = queue_request_irq(dev, adminq, adminq->irqname); |
a4aea562 | 2202 | if (result) |
22404274 | 2203 | goto free_queues; |
1b23484b | 2204 | |
cd638946 | 2205 | /* Free previously allocated queues that are no longer usable */ |
42f61420 | 2206 | nvme_free_queues(dev, nr_io_queues + 1); |
a4aea562 | 2207 | nvme_create_io_queues(dev); |
9ecdc946 | 2208 | |
22404274 | 2209 | return 0; |
b60503ba | 2210 | |
22404274 | 2211 | free_queues: |
a1a5ef99 | 2212 | nvme_free_queues(dev, 1); |
22404274 | 2213 | return result; |
b60503ba MW |
2214 | } |
2215 | ||
a5768aa8 KB |
2216 | static void nvme_free_namespace(struct nvme_ns *ns) |
2217 | { | |
2218 | list_del(&ns->list); | |
2219 | ||
2220 | spin_lock(&dev_list_lock); | |
2221 | ns->disk->private_data = NULL; | |
2222 | spin_unlock(&dev_list_lock); | |
2223 | ||
2224 | put_disk(ns->disk); | |
2225 | kfree(ns); | |
2226 | } | |
2227 | ||
2228 | static int ns_cmp(void *priv, struct list_head *a, struct list_head *b) | |
2229 | { | |
2230 | struct nvme_ns *nsa = container_of(a, struct nvme_ns, list); | |
2231 | struct nvme_ns *nsb = container_of(b, struct nvme_ns, list); | |
2232 | ||
2233 | return nsa->ns_id - nsb->ns_id; | |
2234 | } | |
2235 | ||
2236 | static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid) | |
2237 | { | |
2238 | struct nvme_ns *ns; | |
2239 | ||
2240 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2241 | if (ns->ns_id == nsid) | |
2242 | return ns; | |
2243 | if (ns->ns_id > nsid) | |
2244 | break; | |
2245 | } | |
2246 | return NULL; | |
2247 | } | |
2248 | ||
2249 | static inline bool nvme_io_incapable(struct nvme_dev *dev) | |
2250 | { | |
2251 | return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS || | |
2252 | dev->online_queues < 2); | |
2253 | } | |
2254 | ||
2255 | static void nvme_ns_remove(struct nvme_ns *ns) | |
2256 | { | |
2257 | bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue); | |
2258 | ||
2259 | if (kill) | |
2260 | blk_set_queue_dying(ns->queue); | |
2261 | if (ns->disk->flags & GENHD_FL_UP) { | |
2262 | if (blk_get_integrity(ns->disk)) | |
2263 | blk_integrity_unregister(ns->disk); | |
2264 | del_gendisk(ns->disk); | |
2265 | } | |
2266 | if (kill || !blk_queue_dying(ns->queue)) { | |
2267 | blk_mq_abort_requeue_list(ns->queue); | |
2268 | blk_cleanup_queue(ns->queue); | |
2269 | } | |
2270 | } | |
2271 | ||
2272 | static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn) | |
2273 | { | |
2274 | struct nvme_ns *ns, *next; | |
2275 | unsigned i; | |
2276 | ||
2277 | for (i = 1; i <= nn; i++) { | |
2278 | ns = nvme_find_ns(dev, i); | |
2279 | if (ns) { | |
2280 | if (revalidate_disk(ns->disk)) { | |
2281 | nvme_ns_remove(ns); | |
2282 | nvme_free_namespace(ns); | |
2283 | } | |
2284 | } else | |
2285 | nvme_alloc_ns(dev, i); | |
2286 | } | |
2287 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) { | |
2288 | if (ns->ns_id > nn) { | |
2289 | nvme_ns_remove(ns); | |
2290 | nvme_free_namespace(ns); | |
2291 | } | |
2292 | } | |
2293 | list_sort(NULL, &dev->namespaces, ns_cmp); | |
2294 | } | |
2295 | ||
2296 | static void nvme_dev_scan(struct work_struct *work) | |
2297 | { | |
2298 | struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); | |
2299 | struct nvme_id_ctrl *ctrl; | |
2300 | ||
2301 | if (!dev->tagset.tags) | |
2302 | return; | |
2303 | if (nvme_identify_ctrl(dev, &ctrl)) | |
2304 | return; | |
2305 | nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn)); | |
2306 | kfree(ctrl); | |
2307 | } | |
2308 | ||
422ef0c7 MW |
2309 | /* |
2310 | * Return: error value if an error occurred setting up the queues or calling | |
2311 | * Identify Device. 0 if these succeeded, even if adding some of the | |
2312 | * namespaces failed. At the moment, these failures are silent. TBD which | |
2313 | * failures should be reported. | |
2314 | */ | |
8d85fce7 | 2315 | static int nvme_dev_add(struct nvme_dev *dev) |
b60503ba | 2316 | { |
e75ec752 | 2317 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
c3bfe717 | 2318 | int res; |
a5768aa8 | 2319 | unsigned nn; |
51814232 | 2320 | struct nvme_id_ctrl *ctrl; |
159b67d7 | 2321 | int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12; |
b60503ba | 2322 | |
d29ec824 | 2323 | res = nvme_identify_ctrl(dev, &ctrl); |
b60503ba | 2324 | if (res) { |
e75ec752 | 2325 | dev_err(dev->dev, "Identify Controller failed (%d)\n", res); |
e1e5e564 | 2326 | return -EIO; |
b60503ba MW |
2327 | } |
2328 | ||
51814232 | 2329 | nn = le32_to_cpup(&ctrl->nn); |
0e5e4f0e | 2330 | dev->oncs = le16_to_cpup(&ctrl->oncs); |
c30341dc | 2331 | dev->abort_limit = ctrl->acl + 1; |
a7d2ce28 | 2332 | dev->vwc = ctrl->vwc; |
51814232 MW |
2333 | memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn)); |
2334 | memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn)); | |
2335 | memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr)); | |
159b67d7 | 2336 | if (ctrl->mdts) |
8fc23e03 | 2337 | dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9); |
68608c26 | 2338 | if ((pdev->vendor == PCI_VENDOR_ID_INTEL) && |
a4aea562 MB |
2339 | (pdev->device == 0x0953) && ctrl->vs[3]) { |
2340 | unsigned int max_hw_sectors; | |
2341 | ||
159b67d7 | 2342 | dev->stripe_size = 1 << (ctrl->vs[3] + shift); |
a4aea562 MB |
2343 | max_hw_sectors = dev->stripe_size >> (shift - 9); |
2344 | if (dev->max_hw_sectors) { | |
2345 | dev->max_hw_sectors = min(max_hw_sectors, | |
2346 | dev->max_hw_sectors); | |
2347 | } else | |
2348 | dev->max_hw_sectors = max_hw_sectors; | |
2349 | } | |
d29ec824 | 2350 | kfree(ctrl); |
a4aea562 MB |
2351 | |
2352 | dev->tagset.ops = &nvme_mq_ops; | |
2353 | dev->tagset.nr_hw_queues = dev->online_queues - 1; | |
2354 | dev->tagset.timeout = NVME_IO_TIMEOUT; | |
e75ec752 | 2355 | dev->tagset.numa_node = dev_to_node(dev->dev); |
a4aea562 MB |
2356 | dev->tagset.queue_depth = |
2357 | min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; | |
ac3dd5bd | 2358 | dev->tagset.cmd_size = nvme_cmd_size(dev); |
a4aea562 MB |
2359 | dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; |
2360 | dev->tagset.driver_data = dev; | |
2361 | ||
2362 | if (blk_mq_alloc_tag_set(&dev->tagset)) | |
e1e5e564 | 2363 | return 0; |
b60503ba | 2364 | |
a5768aa8 | 2365 | schedule_work(&dev->scan_work); |
e1e5e564 | 2366 | return 0; |
b60503ba MW |
2367 | } |
2368 | ||
0877cb0d KB |
2369 | static int nvme_dev_map(struct nvme_dev *dev) |
2370 | { | |
42f61420 | 2371 | u64 cap; |
0877cb0d | 2372 | int bars, result = -ENOMEM; |
e75ec752 | 2373 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
0877cb0d KB |
2374 | |
2375 | if (pci_enable_device_mem(pdev)) | |
2376 | return result; | |
2377 | ||
2378 | dev->entry[0].vector = pdev->irq; | |
2379 | pci_set_master(pdev); | |
2380 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | |
be7837e8 JA |
2381 | if (!bars) |
2382 | goto disable_pci; | |
2383 | ||
0877cb0d KB |
2384 | if (pci_request_selected_regions(pdev, bars, "nvme")) |
2385 | goto disable_pci; | |
2386 | ||
e75ec752 CH |
2387 | if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && |
2388 | dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) | |
052d0efa | 2389 | goto disable; |
0877cb0d | 2390 | |
0877cb0d KB |
2391 | dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); |
2392 | if (!dev->bar) | |
2393 | goto disable; | |
e32efbfc | 2394 | |
0e53d180 KB |
2395 | if (readl(&dev->bar->csts) == -1) { |
2396 | result = -ENODEV; | |
2397 | goto unmap; | |
2398 | } | |
e32efbfc JA |
2399 | |
2400 | /* | |
2401 | * Some devices don't advertse INTx interrupts, pre-enable a single | |
2402 | * MSIX vec for setup. We'll adjust this later. | |
2403 | */ | |
2404 | if (!pdev->irq) { | |
2405 | result = pci_enable_msix(pdev, dev->entry, 1); | |
2406 | if (result < 0) | |
2407 | goto unmap; | |
2408 | } | |
2409 | ||
42f61420 KB |
2410 | cap = readq(&dev->bar->cap); |
2411 | dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); | |
2412 | dev->db_stride = 1 << NVME_CAP_STRIDE(cap); | |
0877cb0d KB |
2413 | dev->dbs = ((void __iomem *)dev->bar) + 4096; |
2414 | ||
2415 | return 0; | |
2416 | ||
0e53d180 KB |
2417 | unmap: |
2418 | iounmap(dev->bar); | |
2419 | dev->bar = NULL; | |
0877cb0d KB |
2420 | disable: |
2421 | pci_release_regions(pdev); | |
2422 | disable_pci: | |
2423 | pci_disable_device(pdev); | |
2424 | return result; | |
2425 | } | |
2426 | ||
2427 | static void nvme_dev_unmap(struct nvme_dev *dev) | |
2428 | { | |
e75ec752 CH |
2429 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
2430 | ||
2431 | if (pdev->msi_enabled) | |
2432 | pci_disable_msi(pdev); | |
2433 | else if (pdev->msix_enabled) | |
2434 | pci_disable_msix(pdev); | |
0877cb0d KB |
2435 | |
2436 | if (dev->bar) { | |
2437 | iounmap(dev->bar); | |
2438 | dev->bar = NULL; | |
e75ec752 | 2439 | pci_release_regions(pdev); |
0877cb0d KB |
2440 | } |
2441 | ||
e75ec752 CH |
2442 | if (pci_is_enabled(pdev)) |
2443 | pci_disable_device(pdev); | |
0877cb0d KB |
2444 | } |
2445 | ||
4d115420 KB |
2446 | struct nvme_delq_ctx { |
2447 | struct task_struct *waiter; | |
2448 | struct kthread_worker *worker; | |
2449 | atomic_t refcount; | |
2450 | }; | |
2451 | ||
2452 | static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) | |
2453 | { | |
2454 | dq->waiter = current; | |
2455 | mb(); | |
2456 | ||
2457 | for (;;) { | |
2458 | set_current_state(TASK_KILLABLE); | |
2459 | if (!atomic_read(&dq->refcount)) | |
2460 | break; | |
2461 | if (!schedule_timeout(ADMIN_TIMEOUT) || | |
2462 | fatal_signal_pending(current)) { | |
0fb59cbc KB |
2463 | /* |
2464 | * Disable the controller first since we can't trust it | |
2465 | * at this point, but leave the admin queue enabled | |
2466 | * until all queue deletion requests are flushed. | |
2467 | * FIXME: This may take a while if there are more h/w | |
2468 | * queues than admin tags. | |
2469 | */ | |
4d115420 | 2470 | set_current_state(TASK_RUNNING); |
4d115420 | 2471 | nvme_disable_ctrl(dev, readq(&dev->bar->cap)); |
0fb59cbc | 2472 | nvme_clear_queue(dev->queues[0]); |
4d115420 | 2473 | flush_kthread_worker(dq->worker); |
0fb59cbc | 2474 | nvme_disable_queue(dev, 0); |
4d115420 KB |
2475 | return; |
2476 | } | |
2477 | } | |
2478 | set_current_state(TASK_RUNNING); | |
2479 | } | |
2480 | ||
2481 | static void nvme_put_dq(struct nvme_delq_ctx *dq) | |
2482 | { | |
2483 | atomic_dec(&dq->refcount); | |
2484 | if (dq->waiter) | |
2485 | wake_up_process(dq->waiter); | |
2486 | } | |
2487 | ||
2488 | static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) | |
2489 | { | |
2490 | atomic_inc(&dq->refcount); | |
2491 | return dq; | |
2492 | } | |
2493 | ||
2494 | static void nvme_del_queue_end(struct nvme_queue *nvmeq) | |
2495 | { | |
2496 | struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; | |
4d115420 KB |
2497 | nvme_put_dq(dq); |
2498 | } | |
2499 | ||
2500 | static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, | |
2501 | kthread_work_func_t fn) | |
2502 | { | |
2503 | struct nvme_command c; | |
2504 | ||
2505 | memset(&c, 0, sizeof(c)); | |
2506 | c.delete_queue.opcode = opcode; | |
2507 | c.delete_queue.qid = cpu_to_le16(nvmeq->qid); | |
2508 | ||
2509 | init_kthread_work(&nvmeq->cmdinfo.work, fn); | |
a4aea562 MB |
2510 | return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, |
2511 | ADMIN_TIMEOUT); | |
4d115420 KB |
2512 | } |
2513 | ||
2514 | static void nvme_del_cq_work_handler(struct kthread_work *work) | |
2515 | { | |
2516 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2517 | cmdinfo.work); | |
2518 | nvme_del_queue_end(nvmeq); | |
2519 | } | |
2520 | ||
2521 | static int nvme_delete_cq(struct nvme_queue *nvmeq) | |
2522 | { | |
2523 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, | |
2524 | nvme_del_cq_work_handler); | |
2525 | } | |
2526 | ||
2527 | static void nvme_del_sq_work_handler(struct kthread_work *work) | |
2528 | { | |
2529 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2530 | cmdinfo.work); | |
2531 | int status = nvmeq->cmdinfo.status; | |
2532 | ||
2533 | if (!status) | |
2534 | status = nvme_delete_cq(nvmeq); | |
2535 | if (status) | |
2536 | nvme_del_queue_end(nvmeq); | |
2537 | } | |
2538 | ||
2539 | static int nvme_delete_sq(struct nvme_queue *nvmeq) | |
2540 | { | |
2541 | return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, | |
2542 | nvme_del_sq_work_handler); | |
2543 | } | |
2544 | ||
2545 | static void nvme_del_queue_start(struct kthread_work *work) | |
2546 | { | |
2547 | struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, | |
2548 | cmdinfo.work); | |
4d115420 KB |
2549 | if (nvme_delete_sq(nvmeq)) |
2550 | nvme_del_queue_end(nvmeq); | |
2551 | } | |
2552 | ||
2553 | static void nvme_disable_io_queues(struct nvme_dev *dev) | |
2554 | { | |
2555 | int i; | |
2556 | DEFINE_KTHREAD_WORKER_ONSTACK(worker); | |
2557 | struct nvme_delq_ctx dq; | |
2558 | struct task_struct *kworker_task = kthread_run(kthread_worker_fn, | |
2559 | &worker, "nvme%d", dev->instance); | |
2560 | ||
2561 | if (IS_ERR(kworker_task)) { | |
e75ec752 | 2562 | dev_err(dev->dev, |
4d115420 KB |
2563 | "Failed to create queue del task\n"); |
2564 | for (i = dev->queue_count - 1; i > 0; i--) | |
2565 | nvme_disable_queue(dev, i); | |
2566 | return; | |
2567 | } | |
2568 | ||
2569 | dq.waiter = NULL; | |
2570 | atomic_set(&dq.refcount, 0); | |
2571 | dq.worker = &worker; | |
2572 | for (i = dev->queue_count - 1; i > 0; i--) { | |
a4aea562 | 2573 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 KB |
2574 | |
2575 | if (nvme_suspend_queue(nvmeq)) | |
2576 | continue; | |
2577 | nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); | |
2578 | nvmeq->cmdinfo.worker = dq.worker; | |
2579 | init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); | |
2580 | queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); | |
2581 | } | |
2582 | nvme_wait_dq(&dq, dev); | |
2583 | kthread_stop(kworker_task); | |
2584 | } | |
2585 | ||
b9afca3e DM |
2586 | /* |
2587 | * Remove the node from the device list and check | |
2588 | * for whether or not we need to stop the nvme_thread. | |
2589 | */ | |
2590 | static void nvme_dev_list_remove(struct nvme_dev *dev) | |
2591 | { | |
2592 | struct task_struct *tmp = NULL; | |
2593 | ||
2594 | spin_lock(&dev_list_lock); | |
2595 | list_del_init(&dev->node); | |
2596 | if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { | |
2597 | tmp = nvme_thread; | |
2598 | nvme_thread = NULL; | |
2599 | } | |
2600 | spin_unlock(&dev_list_lock); | |
2601 | ||
2602 | if (tmp) | |
2603 | kthread_stop(tmp); | |
2604 | } | |
2605 | ||
c9d3bf88 KB |
2606 | static void nvme_freeze_queues(struct nvme_dev *dev) |
2607 | { | |
2608 | struct nvme_ns *ns; | |
2609 | ||
2610 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2611 | blk_mq_freeze_queue_start(ns->queue); | |
2612 | ||
cddcd72b | 2613 | spin_lock_irq(ns->queue->queue_lock); |
c9d3bf88 | 2614 | queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); |
cddcd72b | 2615 | spin_unlock_irq(ns->queue->queue_lock); |
c9d3bf88 KB |
2616 | |
2617 | blk_mq_cancel_requeue_work(ns->queue); | |
2618 | blk_mq_stop_hw_queues(ns->queue); | |
2619 | } | |
2620 | } | |
2621 | ||
2622 | static void nvme_unfreeze_queues(struct nvme_dev *dev) | |
2623 | { | |
2624 | struct nvme_ns *ns; | |
2625 | ||
2626 | list_for_each_entry(ns, &dev->namespaces, list) { | |
2627 | queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); | |
2628 | blk_mq_unfreeze_queue(ns->queue); | |
2629 | blk_mq_start_stopped_hw_queues(ns->queue, true); | |
2630 | blk_mq_kick_requeue_list(ns->queue); | |
2631 | } | |
2632 | } | |
2633 | ||
f0b50732 | 2634 | static void nvme_dev_shutdown(struct nvme_dev *dev) |
b60503ba | 2635 | { |
22404274 | 2636 | int i; |
7c1b2450 | 2637 | u32 csts = -1; |
22404274 | 2638 | |
b9afca3e | 2639 | nvme_dev_list_remove(dev); |
1fa6aead | 2640 | |
c9d3bf88 KB |
2641 | if (dev->bar) { |
2642 | nvme_freeze_queues(dev); | |
7c1b2450 | 2643 | csts = readl(&dev->bar->csts); |
c9d3bf88 | 2644 | } |
7c1b2450 | 2645 | if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { |
4d115420 | 2646 | for (i = dev->queue_count - 1; i >= 0; i--) { |
a4aea562 | 2647 | struct nvme_queue *nvmeq = dev->queues[i]; |
4d115420 | 2648 | nvme_suspend_queue(nvmeq); |
4d115420 KB |
2649 | } |
2650 | } else { | |
2651 | nvme_disable_io_queues(dev); | |
1894d8f1 | 2652 | nvme_shutdown_ctrl(dev); |
4d115420 KB |
2653 | nvme_disable_queue(dev, 0); |
2654 | } | |
f0b50732 | 2655 | nvme_dev_unmap(dev); |
07836e65 KB |
2656 | |
2657 | for (i = dev->queue_count - 1; i >= 0; i--) | |
2658 | nvme_clear_queue(dev->queues[i]); | |
f0b50732 KB |
2659 | } |
2660 | ||
2661 | static void nvme_dev_remove(struct nvme_dev *dev) | |
2662 | { | |
9ac27090 | 2663 | struct nvme_ns *ns; |
f0b50732 | 2664 | |
a5768aa8 KB |
2665 | list_for_each_entry(ns, &dev->namespaces, list) |
2666 | nvme_ns_remove(ns); | |
b60503ba MW |
2667 | } |
2668 | ||
091b6092 MW |
2669 | static int nvme_setup_prp_pools(struct nvme_dev *dev) |
2670 | { | |
e75ec752 | 2671 | dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, |
091b6092 MW |
2672 | PAGE_SIZE, PAGE_SIZE, 0); |
2673 | if (!dev->prp_page_pool) | |
2674 | return -ENOMEM; | |
2675 | ||
99802a7a | 2676 | /* Optimisation for I/Os between 4k and 128k */ |
e75ec752 | 2677 | dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, |
99802a7a MW |
2678 | 256, 256, 0); |
2679 | if (!dev->prp_small_pool) { | |
2680 | dma_pool_destroy(dev->prp_page_pool); | |
2681 | return -ENOMEM; | |
2682 | } | |
091b6092 MW |
2683 | return 0; |
2684 | } | |
2685 | ||
2686 | static void nvme_release_prp_pools(struct nvme_dev *dev) | |
2687 | { | |
2688 | dma_pool_destroy(dev->prp_page_pool); | |
99802a7a | 2689 | dma_pool_destroy(dev->prp_small_pool); |
091b6092 MW |
2690 | } |
2691 | ||
cd58ad7d QSA |
2692 | static DEFINE_IDA(nvme_instance_ida); |
2693 | ||
2694 | static int nvme_set_instance(struct nvme_dev *dev) | |
b60503ba | 2695 | { |
cd58ad7d QSA |
2696 | int instance, error; |
2697 | ||
2698 | do { | |
2699 | if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL)) | |
2700 | return -ENODEV; | |
2701 | ||
2702 | spin_lock(&dev_list_lock); | |
2703 | error = ida_get_new(&nvme_instance_ida, &instance); | |
2704 | spin_unlock(&dev_list_lock); | |
2705 | } while (error == -EAGAIN); | |
2706 | ||
2707 | if (error) | |
2708 | return -ENODEV; | |
2709 | ||
2710 | dev->instance = instance; | |
2711 | return 0; | |
b60503ba MW |
2712 | } |
2713 | ||
2714 | static void nvme_release_instance(struct nvme_dev *dev) | |
2715 | { | |
cd58ad7d QSA |
2716 | spin_lock(&dev_list_lock); |
2717 | ida_remove(&nvme_instance_ida, dev->instance); | |
2718 | spin_unlock(&dev_list_lock); | |
b60503ba MW |
2719 | } |
2720 | ||
9ac27090 KB |
2721 | static void nvme_free_namespaces(struct nvme_dev *dev) |
2722 | { | |
2723 | struct nvme_ns *ns, *next; | |
2724 | ||
a5768aa8 KB |
2725 | list_for_each_entry_safe(ns, next, &dev->namespaces, list) |
2726 | nvme_free_namespace(ns); | |
9ac27090 KB |
2727 | } |
2728 | ||
5e82e952 KB |
2729 | static void nvme_free_dev(struct kref *kref) |
2730 | { | |
2731 | struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref); | |
9ac27090 | 2732 | |
e75ec752 | 2733 | put_device(dev->dev); |
b3fffdef | 2734 | put_device(dev->device); |
9ac27090 | 2735 | nvme_free_namespaces(dev); |
285dffc9 | 2736 | nvme_release_instance(dev); |
a4aea562 | 2737 | blk_mq_free_tag_set(&dev->tagset); |
ea191d2f | 2738 | blk_put_queue(dev->admin_q); |
5e82e952 KB |
2739 | kfree(dev->queues); |
2740 | kfree(dev->entry); | |
2741 | kfree(dev); | |
2742 | } | |
2743 | ||
2744 | static int nvme_dev_open(struct inode *inode, struct file *f) | |
2745 | { | |
b3fffdef KB |
2746 | struct nvme_dev *dev; |
2747 | int instance = iminor(inode); | |
2748 | int ret = -ENODEV; | |
2749 | ||
2750 | spin_lock(&dev_list_lock); | |
2751 | list_for_each_entry(dev, &dev_list, node) { | |
2752 | if (dev->instance == instance) { | |
2e1d8448 KB |
2753 | if (!dev->admin_q) { |
2754 | ret = -EWOULDBLOCK; | |
2755 | break; | |
2756 | } | |
b3fffdef KB |
2757 | if (!kref_get_unless_zero(&dev->kref)) |
2758 | break; | |
2759 | f->private_data = dev; | |
2760 | ret = 0; | |
2761 | break; | |
2762 | } | |
2763 | } | |
2764 | spin_unlock(&dev_list_lock); | |
2765 | ||
2766 | return ret; | |
5e82e952 KB |
2767 | } |
2768 | ||
2769 | static int nvme_dev_release(struct inode *inode, struct file *f) | |
2770 | { | |
2771 | struct nvme_dev *dev = f->private_data; | |
2772 | kref_put(&dev->kref, nvme_free_dev); | |
2773 | return 0; | |
2774 | } | |
2775 | ||
2776 | static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg) | |
2777 | { | |
2778 | struct nvme_dev *dev = f->private_data; | |
a4aea562 MB |
2779 | struct nvme_ns *ns; |
2780 | ||
5e82e952 KB |
2781 | switch (cmd) { |
2782 | case NVME_IOCTL_ADMIN_CMD: | |
a4aea562 | 2783 | return nvme_user_cmd(dev, NULL, (void __user *)arg); |
7963e521 | 2784 | case NVME_IOCTL_IO_CMD: |
a4aea562 MB |
2785 | if (list_empty(&dev->namespaces)) |
2786 | return -ENOTTY; | |
2787 | ns = list_first_entry(&dev->namespaces, struct nvme_ns, list); | |
2788 | return nvme_user_cmd(dev, ns, (void __user *)arg); | |
4cc06521 KB |
2789 | case NVME_IOCTL_RESET: |
2790 | dev_warn(dev->dev, "resetting controller\n"); | |
2791 | return nvme_reset(dev); | |
5e82e952 KB |
2792 | default: |
2793 | return -ENOTTY; | |
2794 | } | |
2795 | } | |
2796 | ||
2797 | static const struct file_operations nvme_dev_fops = { | |
2798 | .owner = THIS_MODULE, | |
2799 | .open = nvme_dev_open, | |
2800 | .release = nvme_dev_release, | |
2801 | .unlocked_ioctl = nvme_dev_ioctl, | |
2802 | .compat_ioctl = nvme_dev_ioctl, | |
2803 | }; | |
2804 | ||
a4aea562 MB |
2805 | static void nvme_set_irq_hints(struct nvme_dev *dev) |
2806 | { | |
2807 | struct nvme_queue *nvmeq; | |
2808 | int i; | |
2809 | ||
2810 | for (i = 0; i < dev->online_queues; i++) { | |
2811 | nvmeq = dev->queues[i]; | |
2812 | ||
42483228 | 2813 | if (!nvmeq->tags || !(*nvmeq->tags)) |
a4aea562 MB |
2814 | continue; |
2815 | ||
2816 | irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, | |
42483228 | 2817 | blk_mq_tags_cpumask(*nvmeq->tags)); |
a4aea562 MB |
2818 | } |
2819 | } | |
2820 | ||
f0b50732 KB |
2821 | static int nvme_dev_start(struct nvme_dev *dev) |
2822 | { | |
2823 | int result; | |
b9afca3e | 2824 | bool start_thread = false; |
f0b50732 KB |
2825 | |
2826 | result = nvme_dev_map(dev); | |
2827 | if (result) | |
2828 | return result; | |
2829 | ||
2830 | result = nvme_configure_admin_queue(dev); | |
2831 | if (result) | |
2832 | goto unmap; | |
2833 | ||
2834 | spin_lock(&dev_list_lock); | |
b9afca3e DM |
2835 | if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { |
2836 | start_thread = true; | |
2837 | nvme_thread = NULL; | |
2838 | } | |
f0b50732 KB |
2839 | list_add(&dev->node, &dev_list); |
2840 | spin_unlock(&dev_list_lock); | |
2841 | ||
b9afca3e DM |
2842 | if (start_thread) { |
2843 | nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); | |
387caa5a | 2844 | wake_up_all(&nvme_kthread_wait); |
b9afca3e DM |
2845 | } else |
2846 | wait_event_killable(nvme_kthread_wait, nvme_thread); | |
2847 | ||
2848 | if (IS_ERR_OR_NULL(nvme_thread)) { | |
2849 | result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; | |
2850 | goto disable; | |
2851 | } | |
a4aea562 MB |
2852 | |
2853 | nvme_init_queue(dev->queues[0], 0); | |
0fb59cbc KB |
2854 | result = nvme_alloc_admin_tags(dev); |
2855 | if (result) | |
2856 | goto disable; | |
b9afca3e | 2857 | |
f0b50732 | 2858 | result = nvme_setup_io_queues(dev); |
badc34d4 | 2859 | if (result) |
0fb59cbc | 2860 | goto free_tags; |
f0b50732 | 2861 | |
a4aea562 MB |
2862 | nvme_set_irq_hints(dev); |
2863 | ||
1efccc9d | 2864 | dev->event_limit = 1; |
d82e8bfd | 2865 | return result; |
f0b50732 | 2866 | |
0fb59cbc KB |
2867 | free_tags: |
2868 | nvme_dev_remove_admin(dev); | |
f0b50732 | 2869 | disable: |
a1a5ef99 | 2870 | nvme_disable_queue(dev, 0); |
b9afca3e | 2871 | nvme_dev_list_remove(dev); |
f0b50732 KB |
2872 | unmap: |
2873 | nvme_dev_unmap(dev); | |
2874 | return result; | |
2875 | } | |
2876 | ||
9a6b9458 KB |
2877 | static int nvme_remove_dead_ctrl(void *arg) |
2878 | { | |
2879 | struct nvme_dev *dev = (struct nvme_dev *)arg; | |
e75ec752 | 2880 | struct pci_dev *pdev = to_pci_dev(dev->dev); |
9a6b9458 KB |
2881 | |
2882 | if (pci_get_drvdata(pdev)) | |
c81f4975 | 2883 | pci_stop_and_remove_bus_device_locked(pdev); |
9a6b9458 KB |
2884 | kref_put(&dev->kref, nvme_free_dev); |
2885 | return 0; | |
2886 | } | |
2887 | ||
2888 | static void nvme_remove_disks(struct work_struct *ws) | |
2889 | { | |
9a6b9458 KB |
2890 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); |
2891 | ||
5a92e700 | 2892 | nvme_free_queues(dev, 1); |
302c6727 | 2893 | nvme_dev_remove(dev); |
9a6b9458 KB |
2894 | } |
2895 | ||
2896 | static int nvme_dev_resume(struct nvme_dev *dev) | |
2897 | { | |
2898 | int ret; | |
2899 | ||
2900 | ret = nvme_dev_start(dev); | |
badc34d4 | 2901 | if (ret) |
9a6b9458 | 2902 | return ret; |
badc34d4 | 2903 | if (dev->online_queues < 2) { |
9a6b9458 | 2904 | spin_lock(&dev_list_lock); |
9ca97374 | 2905 | dev->reset_workfn = nvme_remove_disks; |
9a6b9458 KB |
2906 | queue_work(nvme_workq, &dev->reset_work); |
2907 | spin_unlock(&dev_list_lock); | |
c9d3bf88 KB |
2908 | } else { |
2909 | nvme_unfreeze_queues(dev); | |
a5768aa8 | 2910 | schedule_work(&dev->scan_work); |
c9d3bf88 | 2911 | nvme_set_irq_hints(dev); |
9a6b9458 KB |
2912 | } |
2913 | return 0; | |
2914 | } | |
2915 | ||
2916 | static void nvme_dev_reset(struct nvme_dev *dev) | |
2917 | { | |
2918 | nvme_dev_shutdown(dev); | |
2919 | if (nvme_dev_resume(dev)) { | |
e75ec752 | 2920 | dev_warn(dev->dev, "Device failed to resume\n"); |
9a6b9458 KB |
2921 | kref_get(&dev->kref); |
2922 | if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", | |
2923 | dev->instance))) { | |
e75ec752 | 2924 | dev_err(dev->dev, |
9a6b9458 KB |
2925 | "Failed to start controller remove task\n"); |
2926 | kref_put(&dev->kref, nvme_free_dev); | |
2927 | } | |
2928 | } | |
2929 | } | |
2930 | ||
2931 | static void nvme_reset_failed_dev(struct work_struct *ws) | |
2932 | { | |
2933 | struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); | |
2934 | nvme_dev_reset(dev); | |
2935 | } | |
2936 | ||
9ca97374 TH |
2937 | static void nvme_reset_workfn(struct work_struct *work) |
2938 | { | |
2939 | struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); | |
2940 | dev->reset_workfn(work); | |
2941 | } | |
2942 | ||
4cc06521 KB |
2943 | static int nvme_reset(struct nvme_dev *dev) |
2944 | { | |
2945 | int ret = -EBUSY; | |
2946 | ||
2947 | if (!dev->admin_q || blk_queue_dying(dev->admin_q)) | |
2948 | return -ENODEV; | |
2949 | ||
2950 | spin_lock(&dev_list_lock); | |
2951 | if (!work_pending(&dev->reset_work)) { | |
2952 | dev->reset_workfn = nvme_reset_failed_dev; | |
2953 | queue_work(nvme_workq, &dev->reset_work); | |
2954 | ret = 0; | |
2955 | } | |
2956 | spin_unlock(&dev_list_lock); | |
2957 | ||
2958 | if (!ret) { | |
2959 | flush_work(&dev->reset_work); | |
2960 | return 0; | |
2961 | } | |
2962 | ||
2963 | return ret; | |
2964 | } | |
2965 | ||
2966 | static ssize_t nvme_sysfs_reset(struct device *dev, | |
2967 | struct device_attribute *attr, const char *buf, | |
2968 | size_t count) | |
2969 | { | |
2970 | struct nvme_dev *ndev = dev_get_drvdata(dev); | |
2971 | int ret; | |
2972 | ||
2973 | ret = nvme_reset(ndev); | |
2974 | if (ret < 0) | |
2975 | return ret; | |
2976 | ||
2977 | return count; | |
2978 | } | |
2979 | static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset); | |
2980 | ||
2e1d8448 | 2981 | static void nvme_async_probe(struct work_struct *work); |
8d85fce7 | 2982 | static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
b60503ba | 2983 | { |
a4aea562 | 2984 | int node, result = -ENOMEM; |
b60503ba MW |
2985 | struct nvme_dev *dev; |
2986 | ||
a4aea562 MB |
2987 | node = dev_to_node(&pdev->dev); |
2988 | if (node == NUMA_NO_NODE) | |
2989 | set_dev_node(&pdev->dev, 0); | |
2990 | ||
2991 | dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); | |
b60503ba MW |
2992 | if (!dev) |
2993 | return -ENOMEM; | |
a4aea562 MB |
2994 | dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), |
2995 | GFP_KERNEL, node); | |
b60503ba MW |
2996 | if (!dev->entry) |
2997 | goto free; | |
a4aea562 MB |
2998 | dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), |
2999 | GFP_KERNEL, node); | |
b60503ba MW |
3000 | if (!dev->queues) |
3001 | goto free; | |
3002 | ||
3003 | INIT_LIST_HEAD(&dev->namespaces); | |
9ca97374 TH |
3004 | dev->reset_workfn = nvme_reset_failed_dev; |
3005 | INIT_WORK(&dev->reset_work, nvme_reset_workfn); | |
e75ec752 | 3006 | dev->dev = get_device(&pdev->dev); |
9a6b9458 | 3007 | pci_set_drvdata(pdev, dev); |
cd58ad7d QSA |
3008 | result = nvme_set_instance(dev); |
3009 | if (result) | |
a96d4f5c | 3010 | goto put_pci; |
b60503ba | 3011 | |
091b6092 MW |
3012 | result = nvme_setup_prp_pools(dev); |
3013 | if (result) | |
0877cb0d | 3014 | goto release; |
091b6092 | 3015 | |
fb35e914 | 3016 | kref_init(&dev->kref); |
b3fffdef KB |
3017 | dev->device = device_create(nvme_class, &pdev->dev, |
3018 | MKDEV(nvme_char_major, dev->instance), | |
3019 | dev, "nvme%d", dev->instance); | |
3020 | if (IS_ERR(dev->device)) { | |
3021 | result = PTR_ERR(dev->device); | |
2e1d8448 | 3022 | goto release_pools; |
b3fffdef KB |
3023 | } |
3024 | get_device(dev->device); | |
4cc06521 KB |
3025 | dev_set_drvdata(dev->device, dev); |
3026 | ||
3027 | result = device_create_file(dev->device, &dev_attr_reset_controller); | |
3028 | if (result) | |
3029 | goto put_dev; | |
740216fc | 3030 | |
e6e96d73 | 3031 | INIT_LIST_HEAD(&dev->node); |
a5768aa8 | 3032 | INIT_WORK(&dev->scan_work, nvme_dev_scan); |
2e1d8448 KB |
3033 | INIT_WORK(&dev->probe_work, nvme_async_probe); |
3034 | schedule_work(&dev->probe_work); | |
b60503ba MW |
3035 | return 0; |
3036 | ||
4cc06521 KB |
3037 | put_dev: |
3038 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance)); | |
3039 | put_device(dev->device); | |
0877cb0d | 3040 | release_pools: |
091b6092 | 3041 | nvme_release_prp_pools(dev); |
0877cb0d KB |
3042 | release: |
3043 | nvme_release_instance(dev); | |
a96d4f5c | 3044 | put_pci: |
e75ec752 | 3045 | put_device(dev->dev); |
b60503ba MW |
3046 | free: |
3047 | kfree(dev->queues); | |
3048 | kfree(dev->entry); | |
3049 | kfree(dev); | |
3050 | return result; | |
3051 | } | |
3052 | ||
2e1d8448 KB |
3053 | static void nvme_async_probe(struct work_struct *work) |
3054 | { | |
3055 | struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); | |
3056 | int result; | |
3057 | ||
3058 | result = nvme_dev_start(dev); | |
3059 | if (result) | |
3060 | goto reset; | |
3061 | ||
3062 | if (dev->online_queues > 1) | |
3063 | result = nvme_dev_add(dev); | |
3064 | if (result) | |
3065 | goto reset; | |
3066 | ||
3067 | nvme_set_irq_hints(dev); | |
2e1d8448 KB |
3068 | return; |
3069 | reset: | |
4cc06521 | 3070 | spin_lock(&dev_list_lock); |
07836e65 KB |
3071 | if (!work_busy(&dev->reset_work)) { |
3072 | dev->reset_workfn = nvme_reset_failed_dev; | |
3073 | queue_work(nvme_workq, &dev->reset_work); | |
3074 | } | |
4cc06521 | 3075 | spin_unlock(&dev_list_lock); |
2e1d8448 KB |
3076 | } |
3077 | ||
f0d54a54 KB |
3078 | static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) |
3079 | { | |
a6739479 | 3080 | struct nvme_dev *dev = pci_get_drvdata(pdev); |
f0d54a54 | 3081 | |
a6739479 KB |
3082 | if (prepare) |
3083 | nvme_dev_shutdown(dev); | |
3084 | else | |
3085 | nvme_dev_resume(dev); | |
f0d54a54 KB |
3086 | } |
3087 | ||
09ece142 KB |
3088 | static void nvme_shutdown(struct pci_dev *pdev) |
3089 | { | |
3090 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
3091 | nvme_dev_shutdown(dev); | |
3092 | } | |
3093 | ||
8d85fce7 | 3094 | static void nvme_remove(struct pci_dev *pdev) |
b60503ba MW |
3095 | { |
3096 | struct nvme_dev *dev = pci_get_drvdata(pdev); | |
9a6b9458 KB |
3097 | |
3098 | spin_lock(&dev_list_lock); | |
3099 | list_del_init(&dev->node); | |
3100 | spin_unlock(&dev_list_lock); | |
3101 | ||
3102 | pci_set_drvdata(pdev, NULL); | |
2e1d8448 | 3103 | flush_work(&dev->probe_work); |
9a6b9458 | 3104 | flush_work(&dev->reset_work); |
a5768aa8 | 3105 | flush_work(&dev->scan_work); |
4cc06521 | 3106 | device_remove_file(dev->device, &dev_attr_reset_controller); |
9a6b9458 | 3107 | nvme_dev_shutdown(dev); |
c9d3bf88 | 3108 | nvme_dev_remove(dev); |
a4aea562 | 3109 | nvme_dev_remove_admin(dev); |
b3fffdef | 3110 | device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance)); |
a1a5ef99 | 3111 | nvme_free_queues(dev, 0); |
9a6b9458 | 3112 | nvme_release_prp_pools(dev); |
5e82e952 | 3113 | kref_put(&dev->kref, nvme_free_dev); |
b60503ba MW |
3114 | } |
3115 | ||
3116 | /* These functions are yet to be implemented */ | |
3117 | #define nvme_error_detected NULL | |
3118 | #define nvme_dump_registers NULL | |
3119 | #define nvme_link_reset NULL | |
3120 | #define nvme_slot_reset NULL | |
3121 | #define nvme_error_resume NULL | |
cd638946 | 3122 | |
671a6018 | 3123 | #ifdef CONFIG_PM_SLEEP |
cd638946 KB |
3124 | static int nvme_suspend(struct device *dev) |
3125 | { | |
3126 | struct pci_dev *pdev = to_pci_dev(dev); | |
3127 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
3128 | ||
3129 | nvme_dev_shutdown(ndev); | |
3130 | return 0; | |
3131 | } | |
3132 | ||
3133 | static int nvme_resume(struct device *dev) | |
3134 | { | |
3135 | struct pci_dev *pdev = to_pci_dev(dev); | |
3136 | struct nvme_dev *ndev = pci_get_drvdata(pdev); | |
cd638946 | 3137 | |
9a6b9458 | 3138 | if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) { |
9ca97374 | 3139 | ndev->reset_workfn = nvme_reset_failed_dev; |
9a6b9458 KB |
3140 | queue_work(nvme_workq, &ndev->reset_work); |
3141 | } | |
3142 | return 0; | |
cd638946 | 3143 | } |
671a6018 | 3144 | #endif |
cd638946 KB |
3145 | |
3146 | static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); | |
b60503ba | 3147 | |
1d352035 | 3148 | static const struct pci_error_handlers nvme_err_handler = { |
b60503ba MW |
3149 | .error_detected = nvme_error_detected, |
3150 | .mmio_enabled = nvme_dump_registers, | |
3151 | .link_reset = nvme_link_reset, | |
3152 | .slot_reset = nvme_slot_reset, | |
3153 | .resume = nvme_error_resume, | |
f0d54a54 | 3154 | .reset_notify = nvme_reset_notify, |
b60503ba MW |
3155 | }; |
3156 | ||
3157 | /* Move to pci_ids.h later */ | |
3158 | #define PCI_CLASS_STORAGE_EXPRESS 0x010802 | |
3159 | ||
6eb0d698 | 3160 | static const struct pci_device_id nvme_id_table[] = { |
b60503ba MW |
3161 | { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, |
3162 | { 0, } | |
3163 | }; | |
3164 | MODULE_DEVICE_TABLE(pci, nvme_id_table); | |
3165 | ||
3166 | static struct pci_driver nvme_driver = { | |
3167 | .name = "nvme", | |
3168 | .id_table = nvme_id_table, | |
3169 | .probe = nvme_probe, | |
8d85fce7 | 3170 | .remove = nvme_remove, |
09ece142 | 3171 | .shutdown = nvme_shutdown, |
cd638946 KB |
3172 | .driver = { |
3173 | .pm = &nvme_dev_pm_ops, | |
3174 | }, | |
b60503ba MW |
3175 | .err_handler = &nvme_err_handler, |
3176 | }; | |
3177 | ||
3178 | static int __init nvme_init(void) | |
3179 | { | |
0ac13140 | 3180 | int result; |
1fa6aead | 3181 | |
b9afca3e | 3182 | init_waitqueue_head(&nvme_kthread_wait); |
b60503ba | 3183 | |
9a6b9458 KB |
3184 | nvme_workq = create_singlethread_workqueue("nvme"); |
3185 | if (!nvme_workq) | |
b9afca3e | 3186 | return -ENOMEM; |
9a6b9458 | 3187 | |
5c42ea16 KB |
3188 | result = register_blkdev(nvme_major, "nvme"); |
3189 | if (result < 0) | |
9a6b9458 | 3190 | goto kill_workq; |
5c42ea16 | 3191 | else if (result > 0) |
0ac13140 | 3192 | nvme_major = result; |
b60503ba | 3193 | |
b3fffdef KB |
3194 | result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme", |
3195 | &nvme_dev_fops); | |
3196 | if (result < 0) | |
3197 | goto unregister_blkdev; | |
3198 | else if (result > 0) | |
3199 | nvme_char_major = result; | |
3200 | ||
3201 | nvme_class = class_create(THIS_MODULE, "nvme"); | |
c727040b AK |
3202 | if (IS_ERR(nvme_class)) { |
3203 | result = PTR_ERR(nvme_class); | |
b3fffdef | 3204 | goto unregister_chrdev; |
c727040b | 3205 | } |
b3fffdef | 3206 | |
f3db22fe KB |
3207 | result = pci_register_driver(&nvme_driver); |
3208 | if (result) | |
b3fffdef | 3209 | goto destroy_class; |
1fa6aead | 3210 | return 0; |
b60503ba | 3211 | |
b3fffdef KB |
3212 | destroy_class: |
3213 | class_destroy(nvme_class); | |
3214 | unregister_chrdev: | |
3215 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
1fa6aead | 3216 | unregister_blkdev: |
b60503ba | 3217 | unregister_blkdev(nvme_major, "nvme"); |
9a6b9458 KB |
3218 | kill_workq: |
3219 | destroy_workqueue(nvme_workq); | |
b60503ba MW |
3220 | return result; |
3221 | } | |
3222 | ||
3223 | static void __exit nvme_exit(void) | |
3224 | { | |
3225 | pci_unregister_driver(&nvme_driver); | |
3226 | unregister_blkdev(nvme_major, "nvme"); | |
9a6b9458 | 3227 | destroy_workqueue(nvme_workq); |
b3fffdef KB |
3228 | class_destroy(nvme_class); |
3229 | __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme"); | |
b9afca3e | 3230 | BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); |
21bd78bc | 3231 | _nvme_check_size(); |
b60503ba MW |
3232 | } |
3233 | ||
3234 | MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); | |
3235 | MODULE_LICENSE("GPL"); | |
c78b4713 | 3236 | MODULE_VERSION("1.0"); |
b60503ba MW |
3237 | module_init(nvme_init); |
3238 | module_exit(nvme_exit); |